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arch/arm: add support for imx95 m7 core

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- Add support for i.MX95 M7 core
- Interprocessor communication by RPMSG and SCMI
- Drivers available for UART, SPI, I2C, CAN, IO and timers
This commit is contained in:
Andre Heinemans
2024-12-16 14:48:41 +01:00
committed by Xiang Xiao
parent 5db6767f6f
commit a84257c885
70 changed files with 34946 additions and 0 deletions
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arch/arm/Kconfig
+18
View File
@@ -183,6 +183,20 @@ config ARCH_CHIP_IMX6
---help---
Freescale iMX.6 architectures (Cortex-A9)
config ARCH_CHIP_IMX9_CORTEX_M
bool "NXP iMX.9 Cortex-M7"
select ARCH_CORTEXM7
select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_RAMFUNCS
select ARCH_HAVE_TICKLESS
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_SPI_CS_CONTROL
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
---help---
iMX.9 architectures (Cortex-M7)
config ARCH_CHIP_IMXRT
bool "NXP/Freescale iMX.RT"
select ARCH_CORTEXM7
@@ -1124,6 +1138,7 @@ config ARCH_CHIP
default "gd32f4" if ARCH_CHIP_GD32F4
default "imx1" if ARCH_CHIP_IMX1
default "imx6" if ARCH_CHIP_IMX6
default "imx9" if ARCH_CHIP_IMX9_CORTEX_M
default "imxrt" if ARCH_CHIP_IMXRT
default "kinetis" if ARCH_CHIP_KINETIS
default "kl" if ARCH_CHIP_KL
@@ -1536,6 +1551,9 @@ endif
if ARCH_CHIP_IMX6
source "arch/arm/src/imx6/Kconfig"
endif
if ARCH_CHIP_IMX9_CORTEX_M
source "arch/arm/src/imx9/Kconfig"
endif
if ARCH_CHIP_IMXRT
source "arch/arm/src/imxrt/Kconfig"
endif
arch/arm/include/imx9/chip.h
+52
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@@ -0,0 +1,52 @@
/****************************************************************************
* arch/arm/include/imx9/chip.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_IMX9_CHIP_H
#define __ARCH_ARM_INCLUDE_IMX9_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* NVIC priority levels *****************************************************/
/* Each priority field holds an 8-bit priority value, 0-15. The lower the
* value, the greater the priority of the corresponding interrupt. The i.MX
* RT processor implements only bits[7:4] of each field, bits[3:0] read as
* zero and ignore writes.
*/
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is min pri */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt pri used */
#define IMX9_GPIO_NPORTS 4
#endif /* __ARCH_ARM_INCLUDE_IMX9_CHIP_H */
arch/arm/include/imx9/imx95_irq.h
+420
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@@ -0,0 +1,420 @@
/****************************************************************************
* arch/arm/include/imx9/imx95_irq.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_IMX9_IMX95_IRQ_H
#define __ARCH_ARM_INCLUDE_IMX9_IMX95_IRQ_H
#define IMX9_IRQ_RESERVED16 (IMX9_IRQ_EXTINT + 0) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED17 (IMX9_IRQ_EXTINT + 1) /* DAP interrupt */
#define IMX9_IRQ_RESERVED18 (IMX9_IRQ_EXTINT + 2) /* CTI trigger outputs from CM7 platform */
#define IMX9_IRQ_RESERVED19 (IMX9_IRQ_EXTINT + 3) /* CTI trigger outputs from CM33 platform */
#define IMX9_IRQ_RESERVED20 (IMX9_IRQ_EXTINT + 4) /* CTI trigger outputs from CA55 platform */
#define IMX9_IRQ_RESERVED21 (IMX9_IRQ_EXTINT + 5) /* Performance Unit Interrupts from CA55 platform */
#define IMX9_IRQ_RESERVED22 (IMX9_IRQ_EXTINT + 6) /* ECC error from CA55 platform cache */
#define IMX9_IRQ_RESERVED23 (IMX9_IRQ_EXTINT + 7) /* 1-bit or 2-bit ECC or Parity error from CA55 platform cache */
#define IMX9_IRQ_CAN1 (IMX9_IRQ_EXTINT + 8) /* CAN1 interrupt */
#define IMX9_IRQ_CAN1_ERROR (IMX9_IRQ_EXTINT + 9) /* CAN1 error interrupt */
#define IMX9_IRQ_GPIO1_0 (IMX9_IRQ_EXTINT + 10) /* General Purpose Input/Output 1 interrupt 0 */
#define IMX9_IRQ_GPIO1_1 (IMX9_IRQ_EXTINT + 11) /* General Purpose Input/Output 1 interrupt 1 */
#define IMX9_IRQ_I3C1 (IMX9_IRQ_EXTINT + 12) /* Improved Inter-Integrated Circuit 1 interrupt */
#define IMX9_IRQ_LPI2C1 (IMX9_IRQ_EXTINT + 13) /* Low Power Inter-Integrated Circuit module 1 */
#define IMX9_IRQ_LPI2C2 (IMX9_IRQ_EXTINT + 14) /* Low Power Inter-Integrated Circuit module 2 */
#define IMX9_IRQ_LPIT1 (IMX9_IRQ_EXTINT + 15) /* Low Power Periodic Interrupt Timer 1 */
#define IMX9_IRQ_LPSPI1 (IMX9_IRQ_EXTINT + 16) /* Low Power Serial Peripheral Interface 1 */
#define IMX9_IRQ_LPSPI2 (IMX9_IRQ_EXTINT + 17) /* Low Power Serial Peripheral Interface 2 */
#define IMX9_IRQ_LPTMR1 (IMX9_IRQ_EXTINT + 18) /* Low Power Timer 1 */
#define IMX9_IRQ_LPUART1 (IMX9_IRQ_EXTINT + 19) /* Low Power UART 1 */
#define IMX9_IRQ_LPUART2 (IMX9_IRQ_EXTINT + 20) /* Low Power UART 2 */
#define IMX9_IRQ_RESERVED37 (IMX9_IRQ_EXTINT + 21) /* AONMIX Sentinel MU0 SideA interrupt */
#define IMX9_IRQ_RESERVED38 (IMX9_IRQ_EXTINT + 22) /* AONMIX Sentinel MU1 SideA interrupt */
#define IMX9_IRQ_RESERVED39 (IMX9_IRQ_EXTINT + 23) /* AONMIX Sentinel MU2 SideA interrupt */
#define IMX9_IRQ_RESERVED40 (IMX9_IRQ_EXTINT + 24) /* AONMIX Sentinel MU3 SideA interrupt */
#define IMX9_IRQ_RESERVED41 (IMX9_IRQ_EXTINT + 25) /* AONMIX Sentinel MU4 SideA interrupt */
#define IMX9_IRQ_RESERVED42 (IMX9_IRQ_EXTINT + 26) /* AONMIX Sentinel MU5 SideA interrupt */
#define IMX9_IRQ_V2X_FH_APCH0 (IMX9_IRQ_EXTINT + 27) /* V2X-FH MU APCH0 (APP0) interrupt */
#define IMX9_IRQ_V2X_FH_APHSM1 (IMX9_IRQ_EXTINT + 28) /* V2X-FH MU APHSM1 (HSM1) interrupt */
#define IMX9_IRQ_TPM1 (IMX9_IRQ_EXTINT + 29) /* Timer PWM module 1 */
#define IMX9_IRQ_TPM2 (IMX9_IRQ_EXTINT + 30) /* Timer PWM module 2 */
#define IMX9_IRQ_WDOG1 (IMX9_IRQ_EXTINT + 31) /* Watchdog 1 Interrupt */
#define IMX9_IRQ_WDOG2 (IMX9_IRQ_EXTINT + 32) /* Watchdog 2 Interrupt */
#define IMX9_IRQ_TRDC_MGR_A (IMX9_IRQ_EXTINT + 33) /* AONMIX TRDC transfer error interrupt */
#define IMX9_IRQ_SAI1 (IMX9_IRQ_EXTINT + 34) /* Serial Audio Interface 1 */
#define IMX9_IRQ_RESERVED51 (IMX9_IRQ_EXTINT + 35) /* AONMIX M33 PS Error */
#define IMX9_IRQ_RESERVED52 (IMX9_IRQ_EXTINT + 36) /* AONMIX M33 TCM Error interrupt */
#define IMX9_IRQ_RESERVED53 (IMX9_IRQ_EXTINT + 37) /* M7MIX ECC Multi-bit error */
#define IMX9_IRQ_CAN2 (IMX9_IRQ_EXTINT + 38) /* CAN2 interrupt */
#define IMX9_IRQ_CAN2_ERROR (IMX9_IRQ_EXTINT + 39) /* CAN2 error interrupt */
#define IMX9_IRQ_CAN3 (IMX9_IRQ_EXTINT + 40) /* CAN3 interrupt */
#define IMX9_IRQ_CAN3_ERROR (IMX9_IRQ_EXTINT + 41) /* CAN3 error interrupt */
#define IMX9_IRQ_CAN4 (IMX9_IRQ_EXTINT + 42) /* CAN4 interrupt */
#define IMX9_IRQ_CAN4_ERROR (IMX9_IRQ_EXTINT + 43) /* CAN4 error interrupt */
#define IMX9_IRQ_CAN5 (IMX9_IRQ_EXTINT + 44) /* CAN5 interrupt */
#define IMX9_IRQ_CAN5_ERROR (IMX9_IRQ_EXTINT + 45) /* CAN5 error interrupt */
#define IMX9_IRQ_FLEXIO1 (IMX9_IRQ_EXTINT + 46) /* Flexible IO 1 interrupt */
#define IMX9_IRQ_FLEXIO2 (IMX9_IRQ_EXTINT + 47) /* Flexible IO 2 interrupt */
#define IMX9_IRQ_FlexSPI1 (IMX9_IRQ_EXTINT + 48) /* FlexSPI controller interface interrupt 1 */
#define IMX9_IRQ_GPIO2_0 (IMX9_IRQ_EXTINT + 49) /* General Purpose Input/Output 2 interrupt 0 */
#define IMX9_IRQ_GPIO2_1 (IMX9_IRQ_EXTINT + 50) /* General Purpose Input/Output 2 interrupt 1 */
#define IMX9_IRQ_GPIO3_0 (IMX9_IRQ_EXTINT + 51) /* General Purpose Input/Output 3 interrupt 0 */
#define IMX9_IRQ_GPIO3_1 (IMX9_IRQ_EXTINT + 52) /* General Purpose Input/Output 3 interrupt 1 */
#define IMX9_IRQ_GPIO4_0 (IMX9_IRQ_EXTINT + 53) /* General Purpose Input/Output 4 interrupt 0 */
#define IMX9_IRQ_GPIO4_1 (IMX9_IRQ_EXTINT + 54) /* General Purpose Input/Output 4 interrupt 1 */
#define IMX9_IRQ_GPIO5_0 (IMX9_IRQ_EXTINT + 55) /* General Purpose Input/Output 5 interrupt 0 */
#define IMX9_IRQ_GPIO5_1 (IMX9_IRQ_EXTINT + 56) /* General Purpose Input/Output 5 interrupt 1 */
#define IMX9_IRQ_I3C2 (IMX9_IRQ_EXTINT + 57) /* Improved Inter-Integrated Circuit 2 interrupt */
#define IMX9_IRQ_LPI2C3 (IMX9_IRQ_EXTINT + 58) /* Low Power Inter-Integrated Circuit module 3 */
#define IMX9_IRQ_LPI2C4 (IMX9_IRQ_EXTINT + 59) /* Low Power Inter-Integrated Circuit module 4 */
#define IMX9_IRQ_LPIT2 (IMX9_IRQ_EXTINT + 60) /* Low Power Periodic Interrupt Timer 2 */
#define IMX9_IRQ_LPSPI3 (IMX9_IRQ_EXTINT + 61) /* Low Power Serial Peripheral Interface 3 */
#define IMX9_IRQ_LPSPI4 (IMX9_IRQ_EXTINT + 62) /* Low Power Serial Peripheral Interface 4 */
#define IMX9_IRQ_LPTMR2 (IMX9_IRQ_EXTINT + 63) /* Low Power Timer 2 */
#define IMX9_IRQ_LPUART3 (IMX9_IRQ_EXTINT + 64) /* Low Power UART 3 */
#define IMX9_IRQ_LPUART4 (IMX9_IRQ_EXTINT + 65) /* Low Power UART 4 */
#define IMX9_IRQ_LPUART5 (IMX9_IRQ_EXTINT + 66) /* Low Power UART 5 */
#define IMX9_IRQ_LPUART6 (IMX9_IRQ_EXTINT + 67) /* Low Power UART 6 */
#define IMX9_IRQ_LPUART7 (IMX9_IRQ_EXTINT + 68) /* Low Power UART 7 */
#define IMX9_IRQ_LPUART8 (IMX9_IRQ_EXTINT + 69) /* Low Power UART 8 */
#define IMX9_IRQ_RESERVED86 (IMX9_IRQ_EXTINT + 70) /* MTR Master error interrupt */
#define IMX9_IRQ_RESERVED87 (IMX9_IRQ_EXTINT + 71) /* BBNSM Non-Secure interrupt */
#define IMX9_IRQ_RESERVED88 (IMX9_IRQ_EXTINT + 72) /* System Counter compare interrupt */
#define IMX9_IRQ_TPM3 (IMX9_IRQ_EXTINT + 73) /* Timer PWM module 3 */
#define IMX9_IRQ_TPM4 (IMX9_IRQ_EXTINT + 74) /* Timer PWM module 4 */
#define IMX9_IRQ_TPM5 (IMX9_IRQ_EXTINT + 75) /* Timer PWM module 5 */
#define IMX9_IRQ_TPM6 (IMX9_IRQ_EXTINT + 76) /* Timer PWM module 6 */
#define IMX9_IRQ_WDOG3 (IMX9_IRQ_EXTINT + 77) /* Watchdog 3 Interrupt */
#define IMX9_IRQ_WDOG4 (IMX9_IRQ_EXTINT + 78) /* Watchdog 4 Interrupt */
#define IMX9_IRQ_WDOG5 (IMX9_IRQ_EXTINT + 79) /* Watchdog 5 Interrupt */
#define IMX9_IRQ_TMPSNS1_THR1 (IMX9_IRQ_EXTINT + 80) /* ANAMIX TempSensor non-secure interrupt from Threshold 1 */
#define IMX9_IRQ_TMPSNS1_THR2 (IMX9_IRQ_EXTINT + 81) /* ANAMIX TempSensor non-secure interrupt from Threshold 2 */
#define IMX9_IRQ_TMPSNS1_DRDY (IMX9_IRQ_EXTINT + 82) /* ANAMIX TempSensor non-secure data ready interrupt */
#define IMX9_IRQ_TMPSNS2_THR1 (IMX9_IRQ_EXTINT + 83) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 1 */
#define IMX9_IRQ_TMPSNS2_THR2 (IMX9_IRQ_EXTINT + 84) /* CORTEXAMIX TempSensor non-secure interrupt from Threshold 2 */
#define IMX9_IRQ_TMPSNS2_DRDY (IMX9_IRQ_EXTINT + 85) /* CORTEXAMIX TempSensor non-secure data ready interrupt */
#define IMX9_IRQ_uSDHC1 (IMX9_IRQ_EXTINT + 86) /* ultra Secure Digital Host Controller interrupt 1 */
#define IMX9_IRQ_uSDHC2 (IMX9_IRQ_EXTINT + 87) /* ultra Secure Digital Host Controller interrupt 2 */
#define IMX9_IRQ_RESERVED104 (IMX9_IRQ_EXTINT + 88) /* MEGAMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED105 (IMX9_IRQ_EXTINT + 89) /* NIC_WRAPPER TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED106 (IMX9_IRQ_EXTINT + 90) /* NOCMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED107 (IMX9_IRQ_EXTINT + 91) /* DRAM controller Performance Monitor Interrupt */
#define IMX9_IRQ_RESERVED108 (IMX9_IRQ_EXTINT + 92) /* DRAM controller Critical Interrupt */
#define IMX9_IRQ_RESERVED109 (IMX9_IRQ_EXTINT + 93) /* DRAM Phy Critical Interrupt */
#define IMX9_IRQ_RESERVED110 (IMX9_IRQ_EXTINT + 94) /* Reserved */
#define IMX9_IRQ_DMA3_ERROR (IMX9_IRQ_EXTINT + 95) /* eDMA1 error interrupt */
#define IMX9_IRQ_DMA3_0 (IMX9_IRQ_EXTINT + 96) /* eDMA1 channel 0 interrupt */
#define IMX9_IRQ_DMA3_1 (IMX9_IRQ_EXTINT + 97) /* eDMA1 channel 1 interrupt */
#define IMX9_IRQ_DMA3_2 (IMX9_IRQ_EXTINT + 98) /* eDMA1 channel 2 interrupt */
#define IMX9_IRQ_DMA3_3 (IMX9_IRQ_EXTINT + 99) /* eDMA1 channel 3 interrupt */
#define IMX9_IRQ_DMA3_4 (IMX9_IRQ_EXTINT + 100) /* eDMA1 channel 4 interrupt */
#define IMX9_IRQ_DMA3_5 (IMX9_IRQ_EXTINT + 101) /* eDMA1 channel 5 interrupt */
#define IMX9_IRQ_DMA3_6 (IMX9_IRQ_EXTINT + 102) /* eDMA1 channel 6 interrupt */
#define IMX9_IRQ_DMA3_7 (IMX9_IRQ_EXTINT + 103) /* eDMA1 channel 7 interrupt */
#define IMX9_IRQ_DMA3_8 (IMX9_IRQ_EXTINT + 104) /* eDMA1 channel 8 interrupt */
#define IMX9_IRQ_DMA3_9 (IMX9_IRQ_EXTINT + 105) /* eDMA1 channel 9 interrupt */
#define IMX9_IRQ_DMA3_10 (IMX9_IRQ_EXTINT + 106) /* eDMA1 channel 10 interrupt */
#define IMX9_IRQ_DMA3_11 (IMX9_IRQ_EXTINT + 107) /* eDMA1 channel 11 interrupt */
#define IMX9_IRQ_DMA3_12 (IMX9_IRQ_EXTINT + 108) /* eDMA1 channel 12 interrupt */
#define IMX9_IRQ_DMA3_13 (IMX9_IRQ_EXTINT + 109) /* eDMA1 channel 13 interrupt */
#define IMX9_IRQ_DMA3_14 (IMX9_IRQ_EXTINT + 110) /* eDMA1 channel 14 interrupt */
#define IMX9_IRQ_DMA3_15 (IMX9_IRQ_EXTINT + 111) /* eDMA1 channel 15 interrupt */
#define IMX9_IRQ_DMA3_16 (IMX9_IRQ_EXTINT + 112) /* eDMA1 channel 16 interrupt */
#define IMX9_IRQ_DMA3_17 (IMX9_IRQ_EXTINT + 113) /* eDMA1 channel 17 interrupt */
#define IMX9_IRQ_DMA3_18 (IMX9_IRQ_EXTINT + 114) /* eDMA1 channel 18 interrupt */
#define IMX9_IRQ_DMA3_19 (IMX9_IRQ_EXTINT + 115) /* eDMA1 channel 19 interrupt */
#define IMX9_IRQ_DMA3_20 (IMX9_IRQ_EXTINT + 116) /* eDMA1 channel 20 interrupt */
#define IMX9_IRQ_DMA3_21 (IMX9_IRQ_EXTINT + 117) /* eDMA1 channel 21 interrupt */
#define IMX9_IRQ_DMA3_22 (IMX9_IRQ_EXTINT + 118) /* eDMA1 channel 22 interrupt */
#define IMX9_IRQ_DMA3_23 (IMX9_IRQ_EXTINT + 119) /* eDMA1 channel 23 interrupt */
#define IMX9_IRQ_DMA3_24 (IMX9_IRQ_EXTINT + 120) /* eDMA1 channel 24 interrupt */
#define IMX9_IRQ_DMA3_25 (IMX9_IRQ_EXTINT + 121) /* eDMA1 channel 25 interrupt */
#define IMX9_IRQ_DMA3_26 (IMX9_IRQ_EXTINT + 122) /* eDMA1 channel 26 interrupt */
#define IMX9_IRQ_DMA3_27 (IMX9_IRQ_EXTINT + 123) /* eDMA1 channel 27 interrupt */
#define IMX9_IRQ_DMA3_28 (IMX9_IRQ_EXTINT + 124) /* eDMA1 channel 28 interrupt */
#define IMX9_IRQ_DMA3_29 (IMX9_IRQ_EXTINT + 125) /* eDMA1 channel 29 interrupt */
#define IMX9_IRQ_DMA3_30 (IMX9_IRQ_EXTINT + 126) /* eDMA1 channel 30 interrupt */
#define IMX9_IRQ_DMA5_2_ERROR (IMX9_IRQ_EXTINT + 127) /* eDMA2 error interrupt */
#define IMX9_IRQ_DMA5_2_0_1 (IMX9_IRQ_EXTINT + 128) /* eDMA2 channel 0/1 interrupt */
#define IMX9_IRQ_DMA5_2_2_3 (IMX9_IRQ_EXTINT + 129) /* eDMA2 channel 2/3 interrupt */
#define IMX9_IRQ_DMA5_2_4_5 (IMX9_IRQ_EXTINT + 130) /* eDMA2 channel 4/5 interrupt */
#define IMX9_IRQ_DMA5_2_6_7 (IMX9_IRQ_EXTINT + 131) /* eDMA2 channel 6/7 interrupt */
#define IMX9_IRQ_DMA5_2_8_9 (IMX9_IRQ_EXTINT + 132) /* eDMA2 channel 8/9 interrupt */
#define IMX9_IRQ_DMA5_2_10_11 (IMX9_IRQ_EXTINT + 133) /* eDMA2 channel 10/11 interrupt */
#define IMX9_IRQ_DMA5_2_12_13 (IMX9_IRQ_EXTINT + 134) /* eDMA2 channel 12/13 interrupt */
#define IMX9_IRQ_DMA5_2_14_15 (IMX9_IRQ_EXTINT + 135) /* eDMA2 channel 14/15 interrupt */
#define IMX9_IRQ_DMA5_2_16_17 (IMX9_IRQ_EXTINT + 136) /* eDMA2 channel 16/17 interrupt */
#define IMX9_IRQ_DMA5_2_18_19 (IMX9_IRQ_EXTINT + 137) /* eDMA2 channel 18/19 interrupt */
#define IMX9_IRQ_DMA5_2_20_21 (IMX9_IRQ_EXTINT + 138) /* eDMA2 channel 20/21 interrupt */
#define IMX9_IRQ_DMA5_2_22_23 (IMX9_IRQ_EXTINT + 139) /* eDMA2 channel 22/23 interrupt */
#define IMX9_IRQ_DMA5_2_24_25 (IMX9_IRQ_EXTINT + 140) /* eDMA2 channel 24/25 interrupt */
#define IMX9_IRQ_DMA5_2_26_27 (IMX9_IRQ_EXTINT + 141) /* eDMA2 channel 26/27 interrupt */
#define IMX9_IRQ_DMA5_2_28_29 (IMX9_IRQ_EXTINT + 142) /* eDMA2 channel 28/29 interrupt */
#define IMX9_IRQ_DMA5_2_30_31 (IMX9_IRQ_EXTINT + 143) /* eDMA2 channel 30/31 interrupt */
#define IMX9_IRQ_DMA5_2_32_33 (IMX9_IRQ_EXTINT + 144) /* eDMA2 channel 32/33 interrupt */
#define IMX9_IRQ_DMA5_2_34_35 (IMX9_IRQ_EXTINT + 145) /* eDMA2 channel 34/35 interrupt */
#define IMX9_IRQ_DMA5_2_36_37 (IMX9_IRQ_EXTINT + 146) /* eDMA2 channel 36/37 interrupt */
#define IMX9_IRQ_DMA5_2_38_39 (IMX9_IRQ_EXTINT + 147) /* eDMA2 channel 38/39 interrupt */
#define IMX9_IRQ_DMA5_2_40_41 (IMX9_IRQ_EXTINT + 148) /* eDMA2 channel 40/41 interrupt */
#define IMX9_IRQ_DMA5_2_42_43 (IMX9_IRQ_EXTINT + 149) /* eDMA2 channel 42/43 interrupt */
#define IMX9_IRQ_DMA5_2_44_45 (IMX9_IRQ_EXTINT + 150) /* eDMA2 channel 44/45 interrupt */
#define IMX9_IRQ_DMA5_2_46_47 (IMX9_IRQ_EXTINT + 151) /* eDMA2 channel 46/47 interrupt */
#define IMX9_IRQ_DMA5_2_48_49 (IMX9_IRQ_EXTINT + 152) /* eDMA2 channel 48/49 interrupt */
#define IMX9_IRQ_DMA5_2_50_51 (IMX9_IRQ_EXTINT + 153) /* eDMA2 channel 50/51 interrupt */
#define IMX9_IRQ_DMA5_2_52_53 (IMX9_IRQ_EXTINT + 154) /* eDMA2 channel 52/53 interrupt */
#define IMX9_IRQ_DMA5_2_54_55 (IMX9_IRQ_EXTINT + 155) /* eDMA2 channel 54/55 interrupt */
#define IMX9_IRQ_DMA5_2_56_57 (IMX9_IRQ_EXTINT + 156) /* eDMA2 channel 56/57 interrupt */
#define IMX9_IRQ_DMA5_2_58_59 (IMX9_IRQ_EXTINT + 157) /* eDMA2 channel 58/59 interrupt */
#define IMX9_IRQ_DMA5_2_60_61 (IMX9_IRQ_EXTINT + 158) /* eDMA2 channel 60/61 interrupt */
#define IMX9_IRQ_DMA5_2_62_63 (IMX9_IRQ_EXTINT + 159) /* eDMA2 channel 62/63 interrupt */
#define IMX9_IRQ_RESERVED176 (IMX9_IRQ_EXTINT + 160) /* Sentinel Group 1 reset source if no s500 reference clock is detected. Output synchronized to 32khz clk. */
#define IMX9_IRQ_RESERVED177 (IMX9_IRQ_EXTINT + 161) /* Sentinel Group 2 reset source s500 reference clock is not detected or too slow. Output synchronized to ref1_clk. */
#define IMX9_IRQ_RESERVED178 (IMX9_IRQ_EXTINT + 162) /* Sentinel Group 2 reset source s500 reference clock is not detected or too slow. Output synchronized to ref1_clk. */
#define IMX9_IRQ_RESERVED179 (IMX9_IRQ_EXTINT + 163) /* JTAGSW DAP MDM-AP SRC reset source */
#define IMX9_IRQ_RESERVED180 (IMX9_IRQ_EXTINT + 164) /* JTAGC SRC reset source */
#define IMX9_IRQ_RESERVED181 (IMX9_IRQ_EXTINT + 165) /* CM33 SYSREQRST SRC reset source */
#define IMX9_IRQ_RESERVED182 (IMX9_IRQ_EXTINT + 166) /* CM33 LOCKUP SRC reset source */
#define IMX9_IRQ_RESERVED183 (IMX9_IRQ_EXTINT + 167) /* CM7 SYSREQRST SRC reset source */
#define IMX9_IRQ_RESERVED184 (IMX9_IRQ_EXTINT + 168) /* CM7 LOCKUP SRC reset source */
#define IMX9_IRQ_SAI2 (IMX9_IRQ_EXTINT + 169) /* Serial Audio Interface 2 */
#define IMX9_IRQ_SAI3 (IMX9_IRQ_EXTINT + 170) /* Serial Audio Interface 3 */
#define IMX9_IRQ_SAI4 (IMX9_IRQ_EXTINT + 171) /* Serial Audio Interface 4 */
#define IMX9_IRQ_SAI5 (IMX9_IRQ_EXTINT + 172) /* Serial Audio Interface 5 */
#define IMX9_IRQ_RESERVED189 (IMX9_IRQ_EXTINT + 173) /* USB-1 Wake-up Interrupt */
#define IMX9_IRQ_RESERVED190 (IMX9_IRQ_EXTINT + 174) /* USB-2 Wake-up Interrupt */
#define IMX9_IRQ_USB1 (IMX9_IRQ_EXTINT + 175) /* USB-1 Interrupt */
#define IMX9_IRQ_USB2 (IMX9_IRQ_EXTINT + 176) /* USB-2 Interrupt */
#define IMX9_IRQ_LPSPI5 (IMX9_IRQ_EXTINT + 177) /* Low Power Serial Peripheral Interface 5 */
#define IMX9_IRQ_LPSPI6 (IMX9_IRQ_EXTINT + 178) /* Low Power Serial Peripheral Interface 6 */
#define IMX9_IRQ_LPSPI7 (IMX9_IRQ_EXTINT + 179) /* Low Power Serial Peripheral Interface 7 */
#define IMX9_IRQ_LPSPI8 (IMX9_IRQ_EXTINT + 180) /* Low Power Serial Peripheral Interface 8 */
#define IMX9_IRQ_LPI2C5 (IMX9_IRQ_EXTINT + 181) /* Low Power Inter-Integrated Circuit module 5 */
#define IMX9_IRQ_LPI2C6 (IMX9_IRQ_EXTINT + 182) /* Low Power Inter-Integrated Circuit module 6 */
#define IMX9_IRQ_LPI2C7 (IMX9_IRQ_EXTINT + 183) /* Low Power Inter-Integrated Circuit module 7 */
#define IMX9_IRQ_LPI2C8 (IMX9_IRQ_EXTINT + 184) /* Low Power Inter-Integrated Circuit module 8 */
#define IMX9_IRQ_PDM_HWVAD_ERROR (IMX9_IRQ_EXTINT + 185) /* PDM interrupt */
#define IMX9_IRQ_PDM_HWVAD_EVENT (IMX9_IRQ_EXTINT + 186) /* PDM interrupt */
#define IMX9_IRQ_PDM_ERROR (IMX9_IRQ_EXTINT + 187) /* PDM interrupt */
#define IMX9_IRQ_PDM_EVENT (IMX9_IRQ_EXTINT + 188) /* PDM interrupt */
#define IMX9_IRQ_RESERVED205 (IMX9_IRQ_EXTINT + 189) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_RESERVED206 (IMX9_IRQ_EXTINT + 190) /* AUDIO XCVR interrupt */
#define IMX9_IRQ_uSDHC3 (IMX9_IRQ_EXTINT + 191) /* ultra Secure Digital Host Controller interrupt 3 */
#define IMX9_IRQ_RESERVED208 (IMX9_IRQ_EXTINT + 192) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED209 (IMX9_IRQ_EXTINT + 193) /* OCRAM MECC interrupt */
#define IMX9_IRQ_RESERVED210 (IMX9_IRQ_EXTINT + 194) /* CM33 MCM interrupt */
#define IMX9_IRQ_RESERVED211 (IMX9_IRQ_EXTINT + 195) /* ANAMIX SFA interrupt */
#define IMX9_IRQ_RESERVED212 (IMX9_IRQ_EXTINT + 196) /* GIC700 Fault */
#define IMX9_IRQ_RESERVED213 (IMX9_IRQ_EXTINT + 197) /* GIC700 Error */
#define IMX9_IRQ_RESERVED214 (IMX9_IRQ_EXTINT + 198) /* GIC700 PMU Counter Overflow */
#define IMX9_IRQ_ADC_ER (IMX9_IRQ_EXTINT + 199) /* ADC interrupt */
#define IMX9_IRQ_ADC_WD (IMX9_IRQ_EXTINT + 200) /* ADC interrupt */
#define IMX9_IRQ_ADC_EOC (IMX9_IRQ_EXTINT + 201) /* ADC interrupt */
#define IMX9_IRQ_RESERVED218 (IMX9_IRQ_EXTINT + 202) /* s500 glue logic IRQ */
#define IMX9_IRQ_RESERVED219 (IMX9_IRQ_EXTINT + 203) /* I3C1 wakeup irq after double sync */
#define IMX9_IRQ_RESERVED220 (IMX9_IRQ_EXTINT + 204) /* I3C2 wakeup irq after double sync */
#define IMX9_IRQ_MU5_A (IMX9_IRQ_EXTINT + 205) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU6_A (IMX9_IRQ_EXTINT + 206) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU7_B (IMX9_IRQ_EXTINT + 207) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU8_B (IMX9_IRQ_EXTINT + 208) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_RESERVED225 (IMX9_IRQ_EXTINT + 209) /* WAKEUPMIX XSPI Responder */
#define IMX9_IRQ_RESERVED226 (IMX9_IRQ_EXTINT + 210) /* AONMIX FCCU Interrupt Reaction 0 */
#define IMX9_IRQ_RESERVED227 (IMX9_IRQ_EXTINT + 211) /* AONMIX FCCU Interrupt Reaction 1 */
#define IMX9_IRQ_RESERVED228 (IMX9_IRQ_EXTINT + 212) /* AONMIX FCCU Interrupt Reaction 2 */
#define IMX9_IRQ_RESERVED229 (IMX9_IRQ_EXTINT + 213) /* AONMIX STCU Selftest end Interrupt */
#define IMX9_IRQ_DISP_IRQSTEER0 (IMX9_IRQ_EXTINT + 214) /* DISPLAYMIX IRQSTEER 0 */
#define IMX9_IRQ_DISP_IRQSTEER1 (IMX9_IRQ_EXTINT + 215) /* DISPLAYMIX IRQSTEER 1 */
#define IMX9_IRQ_DISP_IRQSTEER2 (IMX9_IRQ_EXTINT + 216) /* DISPLAYMIX IRQSTEER 2 */
#define IMX9_IRQ_DISP_IRQSTEER3 (IMX9_IRQ_EXTINT + 217) /* DISPLAYMIX IRQSTEER 3 */
#define IMX9_IRQ_DISP_IRQSTEER4 (IMX9_IRQ_EXTINT + 218) /* DISPLAYMIX IRQSTEER 4 */
#define IMX9_IRQ_DISP_IRQSTEER7 (IMX9_IRQ_EXTINT + 219) /* DISPLAYMIX IRQSTEER 7 */
#define IMX9_IRQ_RESERVED236 (IMX9_IRQ_EXTINT + 220) /* CAMERAMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_ISI (IMX9_IRQ_EXTINT + 221) /* CAMERAMIX ISI interrupt Channel 0 */
#define IMX9_IRQ_RESERVED238 (IMX9_IRQ_EXTINT + 222) /* ISP Processing Interrupt - Context 0 */
#define IMX9_IRQ_RESERVED239 (IMX9_IRQ_EXTINT + 223) /* M7MIX MCM interrupt */
#define IMX9_IRQ_IRQSTEER_0 (IMX9_IRQ_EXTINT + 224) /* IRQSTEER0 interrupt */
#define IMX9_IRQ_IRQSTEER_1 (IMX9_IRQ_EXTINT + 225) /* IRQSTEER1 interrupt */
#define IMX9_IRQ_IRQSTEER_2 (IMX9_IRQ_EXTINT + 226) /* IRQSTEER2 interrupt */
#define IMX9_IRQ_IRQSTEER_3 (IMX9_IRQ_EXTINT + 227) /* IRQSTEER3 interrupt */
#define IMX9_IRQ_IRQSTEER_4 (IMX9_IRQ_EXTINT + 228) /* IRQSTEER4 interrupt */
#define IMX9_IRQ_IRQSTEER_5 (IMX9_IRQ_EXTINT + 229) /* IRQSTEER5 interrupt */
#define IMX9_IRQ_IRQSTEER_6 (IMX9_IRQ_EXTINT + 230) /* IRQSTEER6 interrupt */
#define IMX9_IRQ_IRQSTEER_7 (IMX9_IRQ_EXTINT + 231) /* IRQSTEER7 interrupt */
#define IMX9_IRQ_IRQSTEER_8 (IMX9_IRQ_EXTINT + 232) /* IRQSTEER8 interrupt */
#define IMX9_IRQ_IRQSTEER_9 (IMX9_IRQ_EXTINT + 233) /* IRQSTEER9 interrupt */
#define IMX9_IRQ_MU1_A (IMX9_IRQ_EXTINT + 234) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU1_B (IMX9_IRQ_EXTINT + 235) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU2_A (IMX9_IRQ_EXTINT + 236) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU2_B (IMX9_IRQ_EXTINT + 237) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU3_A (IMX9_IRQ_EXTINT + 238) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU3_B (IMX9_IRQ_EXTINT + 239) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU4_A (IMX9_IRQ_EXTINT + 240) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU4_B (IMX9_IRQ_EXTINT + 241) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU5_B (IMX9_IRQ_EXTINT + 242) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU6_B (IMX9_IRQ_EXTINT + 243) /* AONMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUB */
#define IMX9_IRQ_MU7_A (IMX9_IRQ_EXTINT + 244) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MU8_A (IMX9_IRQ_EXTINT + 245) /* WAKEUPMIX MU Ored of all (tx,rx,gp,core,murip) interrupt to MUA */
#define IMX9_IRQ_MSGINTR1 (IMX9_IRQ_EXTINT + 246) /* MSGINTR Instance 1, Interrupt */
#define IMX9_IRQ_MSGINTR2 (IMX9_IRQ_EXTINT + 247) /* MSGINTR Instance 2, Interrupts */
#define IMX9_IRQ_RESERVED264 (IMX9_IRQ_EXTINT + 248) /* V2X-FH MU APCH1 (APP1) interrupt */
#define IMX9_IRQ_RESERVED265 (IMX9_IRQ_EXTINT + 249) /* V2X-FH MU APHSM2 (HSM2) interrupt */
#define IMX9_IRQ_RESERVED266 (IMX9_IRQ_EXTINT + 250) /* CAMERAMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED267 (IMX9_IRQ_EXTINT + 251) /* DISPLAYMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED268 (IMX9_IRQ_EXTINT + 252) /* NETCMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED269 (IMX9_IRQ_EXTINT + 253) /* GPUMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED270 (IMX9_IRQ_EXTINT + 254) /* HSIOMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED271 (IMX9_IRQ_EXTINT + 255) /* VPUMIX TRDC transfer error interrupt */
#define IMX9_IRQ_RESERVED272 (IMX9_IRQ_EXTINT + 256) /* AONMIX ERM Single bit corrected ECC Error */
#define IMX9_IRQ_RESERVED273 (IMX9_IRQ_EXTINT + 257) /* M7MIX ERM Single bit corrected ECC Error */
#define IMX9_IRQ_RESERVED274 (IMX9_IRQ_EXTINT + 258) /* WAKEUPMIX ERM Single bit corrected ECC Error */
#define IMX9_IRQ_RESERVED275 (IMX9_IRQ_EXTINT + 259) /* NPUMIX ERM Single bit corrected ECC Error */
#define IMX9_IRQ_RESERVED276 (IMX9_IRQ_EXTINT + 260) /* WAKEUPMIX ACP EDMA error interrupt */
#define IMX9_IRQ_RESERVED277 (IMX9_IRQ_EXTINT + 261) /* OCRAM_C ECC multiple bit or address error */
#define IMX9_IRQ_RESERVED278 (IMX9_IRQ_EXTINT + 262) /* CAMERAMIX Cortex-M0+ Cache write-buffer error */
#define IMX9_IRQ_RESERVED279 (IMX9_IRQ_EXTINT + 263) /* CAMERAMIX Cortex-M0+ Cache data parity error */
#define IMX9_IRQ_RESERVED280 (IMX9_IRQ_EXTINT + 264) /* V2X-FH MU APSHE (SHE) interrupt */
#define IMX9_IRQ_RESERVED281 (IMX9_IRQ_EXTINT + 265) /* V2X-FH MU SCU/APDEBUG (DEBUG) interrupt */
#define IMX9_IRQ_DMA5_3_0_1 (IMX9_IRQ_EXTINT + 266) /* eDMA3 channel 0/1 interrupt */
#define IMX9_IRQ_DMA5_3_2_3 (IMX9_IRQ_EXTINT + 267) /* eDMA3 channel 2/3 interrupt */
#define IMX9_IRQ_DMA5_3_4_5 (IMX9_IRQ_EXTINT + 268) /* eDMA3 channel 4/5 interrupt */
#define IMX9_IRQ_DMA5_3_6_7 (IMX9_IRQ_EXTINT + 269) /* eDMA3 channel 6/7 interrupt */
#define IMX9_IRQ_DMA5_3_8_9 (IMX9_IRQ_EXTINT + 270) /* eDMA3 channel 8/9 interrupt */
#define IMX9_IRQ_DMA5_3_10_11 (IMX9_IRQ_EXTINT + 271) /* eDMA3 channel 10/11 interrupt */
#define IMX9_IRQ_DMA5_3_12_13 (IMX9_IRQ_EXTINT + 272) /* eDMA3 channel 12/13 interrupt */
#define IMX9_IRQ_DMA5_3_14_15 (IMX9_IRQ_EXTINT + 273) /* eDMA3 channel 14/15 interrupt */
#define IMX9_IRQ_DMA5_3_16_17 (IMX9_IRQ_EXTINT + 274) /* eDMA3 channel 16/17 interrupt */
#define IMX9_IRQ_DMA5_3_18_19 (IMX9_IRQ_EXTINT + 275) /* eDMA3 channel 18/19 interrupt */
#define IMX9_IRQ_DMA5_3_20_21 (IMX9_IRQ_EXTINT + 276) /* eDMA3 channel 20/21 interrupt */
#define IMX9_IRQ_DMA5_3_22_23 (IMX9_IRQ_EXTINT + 277) /* eDMA3 channel 22/23 interrupt */
#define IMX9_IRQ_DMA5_3_24_25 (IMX9_IRQ_EXTINT + 278) /* eDMA3 channel 24/25 interrupt */
#define IMX9_IRQ_DMA5_3_26_27 (IMX9_IRQ_EXTINT + 279) /* eDMA3 channel 26/27 interrupt */
#define IMX9_IRQ_DMA5_3_28_29 (IMX9_IRQ_EXTINT + 280) /* eDMA3 channel 29/29 interrupt */
#define IMX9_IRQ_DMA5_3_30_31 (IMX9_IRQ_EXTINT + 281) /* eDMA3 channel 30/31 interrupt */
#define IMX9_IRQ_DMA5_3_32_33 (IMX9_IRQ_EXTINT + 282) /* eDMA3 channel 32/33 interrupt */
#define IMX9_IRQ_DMA5_3_34_35 (IMX9_IRQ_EXTINT + 283) /* eDMA3 channel 34/35 interrupt */
#define IMX9_IRQ_DMA5_3_36_37 (IMX9_IRQ_EXTINT + 284) /* eDMA3 channel 36/37 interrupt */
#define IMX9_IRQ_DMA5_3_38_39 (IMX9_IRQ_EXTINT + 285) /* eDMA3 channel 38/39 interrupt */
#define IMX9_IRQ_DMA5_3_40_41 (IMX9_IRQ_EXTINT + 286) /* eDMA3 channel 40/41 interrupt */
#define IMX9_IRQ_DMA5_3_42_43 (IMX9_IRQ_EXTINT + 287) /* eDMA3 channel 42/43 interrupt */
#define IMX9_IRQ_DMA5_3_44_45 (IMX9_IRQ_EXTINT + 288) /* eDMA3 channel 44/45 interrupt */
#define IMX9_IRQ_DMA5_3_46_47 (IMX9_IRQ_EXTINT + 289) /* eDMA3 channel 46/47 interrupt */
#define IMX9_IRQ_DMA5_3_48_49 (IMX9_IRQ_EXTINT + 290) /* eDMA3 channel 48/49 interrupt */
#define IMX9_IRQ_DMA5_3_50_51 (IMX9_IRQ_EXTINT + 291) /* eDMA3 channel 50/51 interrupt */
#define IMX9_IRQ_DMA5_3_52_53 (IMX9_IRQ_EXTINT + 292) /* eDMA3 channel 52/53 interrupt */
#define IMX9_IRQ_DMA5_3_54_55 (IMX9_IRQ_EXTINT + 293) /* eDMA3 channel 54/55 interrupt */
#define IMX9_IRQ_DMA5_3_56_57 (IMX9_IRQ_EXTINT + 294) /* eDMA3 channel 56/57 interrupt */
#define IMX9_IRQ_DMA5_3_58_59 (IMX9_IRQ_EXTINT + 295) /* eDMA3 channel 58/59 interrupt */
#define IMX9_IRQ_DMA5_3_60_61 (IMX9_IRQ_EXTINT + 296) /* eDMA3 channel 60/61 interrupt */
#define IMX9_IRQ_DMA5_3_62_63 (IMX9_IRQ_EXTINT + 297) /* eDMA3 channel 62/63 interrupt */
#define IMX9_IRQ_RESERVED314 (IMX9_IRQ_EXTINT + 298) /* GPUMIX GPU Interrupt */
#define IMX9_IRQ_RESERVED315 (IMX9_IRQ_EXTINT + 299) /* GPUMIX Job Interrupt */
#define IMX9_IRQ_RESERVED316 (IMX9_IRQ_EXTINT + 300) /* GPUMIX MMU Interrupt */
#define IMX9_IRQ_RESERVED317 (IMX9_IRQ_EXTINT + 301) /* Reserved INTERRUPT */
#define IMX9_IRQ_RESERVED318 (IMX9_IRQ_EXTINT + 302) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED319 (IMX9_IRQ_EXTINT + 303) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED320 (IMX9_IRQ_EXTINT + 304) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED321 (IMX9_IRQ_EXTINT + 305) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED322 (IMX9_IRQ_EXTINT + 306) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED323 (IMX9_IRQ_EXTINT + 307) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED324 (IMX9_IRQ_EXTINT + 308) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED325 (IMX9_IRQ_EXTINT + 309) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED326 (IMX9_IRQ_EXTINT + 310) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED327 (IMX9_IRQ_EXTINT + 311) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED328 (IMX9_IRQ_EXTINT + 312) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED329 (IMX9_IRQ_EXTINT + 313) /* Reserved interrupt */
#define IMX9_IRQ_RESERVED330 (IMX9_IRQ_EXTINT + 314) /* NETC iEPRC PCI INT */
#define IMX9_IRQ_RESERVED331 (IMX9_IRQ_EXTINT + 315) /* NETC iEPRC PCI INT */
#define IMX9_IRQ_RESERVED332 (IMX9_IRQ_EXTINT + 316) /* PCIe Controller 1 INTA */
#define IMX9_IRQ_RESERVED333 (IMX9_IRQ_EXTINT + 317) /* PCIe Controller 1 INTB */
#define IMX9_IRQ_RESERVED334 (IMX9_IRQ_EXTINT + 318) /* PCIe Controller 1 INTC */
#define IMX9_IRQ_RESERVED335 (IMX9_IRQ_EXTINT + 319) /* PCIe Controller 1 INTD */
#define IMX9_IRQ_RESERVED336 (IMX9_IRQ_EXTINT + 320) /* PCIe interrupts */
#define IMX9_IRQ_RESERVED337 (IMX9_IRQ_EXTINT + 321) /* PCIe Controller EDMA channel interrupt */
#define IMX9_IRQ_RESERVED338 (IMX9_IRQ_EXTINT + 322) /* PCIe Controller 1 INTA */
#define IMX9_IRQ_RESERVED339 (IMX9_IRQ_EXTINT + 323) /* PCIe Controller 1 INTB */
#define IMX9_IRQ_RESERVED340 (IMX9_IRQ_EXTINT + 324) /* PCIe Controller 1 INTC */
#define IMX9_IRQ_RESERVED341 (IMX9_IRQ_EXTINT + 325) /* PCIe Controller 1 INTD */
#define IMX9_IRQ_RESERVED342 (IMX9_IRQ_EXTINT + 326) /* PCIe miscellaneous interrupts */
#define IMX9_IRQ_RESERVED343 (IMX9_IRQ_EXTINT + 327) /* PCIe Controller EDMA channel interrupt */
#define IMX9_IRQ_RESERVED344 (IMX9_IRQ_EXTINT + 328) /* Wakeup interrupt from CLKREQ#, WAKEUP#, BEACON_DET */
#define IMX9_IRQ_RESERVED345 (IMX9_IRQ_EXTINT + 329) /* NPUMIX Functional interrupt */
#define IMX9_IRQ_RESERVED346 (IMX9_IRQ_EXTINT + 330) /* DISPLAYMIX Real-time traffic TBU: Fault Handling RAS Interrupt for a contained error */
#define IMX9_IRQ_RESERVED347 (IMX9_IRQ_EXTINT + 331) /* DISPLAYMIX Real-time traffic TBU: Error Handling RAS Interrupt for an uncontained error */
#define IMX9_IRQ_RESERVED348 (IMX9_IRQ_EXTINT + 332) /* DISPLAYMIX Real-time traffic TBU: Critical Error Interrupt for an uncontainable error */
#define IMX9_IRQ_RESERVED349 (IMX9_IRQ_EXTINT + 333) /* DISPLAYMIX Real-time traffic TBU: PMU Interrupt */
#define IMX9_IRQ_RESERVED350 (IMX9_IRQ_EXTINT + 334) /* TCU Event queue, secure interrupt */
#define IMX9_IRQ_RESERVED351 (IMX9_IRQ_EXTINT + 335) /* TCU Event queue, non-secure interrupt */
#define IMX9_IRQ_RESERVED352 (IMX9_IRQ_EXTINT + 336) /* TCU SYNC complete, non-secure interrupt */
#define IMX9_IRQ_RESERVED353 (IMX9_IRQ_EXTINT + 337) /* TCU SYNC complete, secure interrupt */
#define IMX9_IRQ_RESERVED354 (IMX9_IRQ_EXTINT + 338) /* TCU global non-secure interrupt */
#define IMX9_IRQ_RESERVED355 (IMX9_IRQ_EXTINT + 339) /* TCU global secure interrupt */
#define IMX9_IRQ_RESERVED356 (IMX9_IRQ_EXTINT + 340) /* TCU fault handling RAS interrupt for a contained error */
#define IMX9_IRQ_RESERVED357 (IMX9_IRQ_EXTINT + 341) /* TCU error recovery RAS interrupt for an uncontained error */
#define IMX9_IRQ_RESERVED358 (IMX9_IRQ_EXTINT + 342) /* TCU critical error interrupt, for an uncontainable uncorrected error */
#define IMX9_IRQ_RESERVED359 (IMX9_IRQ_EXTINT + 343) /* TCU PMU interrupt */
#define IMX9_IRQ_RESERVED360 (IMX9_IRQ_EXTINT + 344) /* TCU Page Request Interface */
#define IMX9_IRQ_RESERVED361 (IMX9_IRQ_EXTINT + 345) /* SRC GPC Low Power Handshake Gasket interrupt request for system management */
#define IMX9_IRQ_RESERVED362 (IMX9_IRQ_EXTINT + 346) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED363 (IMX9_IRQ_EXTINT + 347) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED364 (IMX9_IRQ_EXTINT + 348) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED365 (IMX9_IRQ_EXTINT + 349) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED366 (IMX9_IRQ_EXTINT + 350) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED367 (IMX9_IRQ_EXTINT + 351) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED368 (IMX9_IRQ_EXTINT + 352) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED369 (IMX9_IRQ_EXTINT + 353) /* CAMERAMIX MU Ored of all */
#define IMX9_IRQ_RESERVED370 (IMX9_IRQ_EXTINT + 354) /* CAMERAMIX ISI interrupt Channel 1 */
#define IMX9_IRQ_RESERVED371 (IMX9_IRQ_EXTINT + 355) /* CAMERAMIX ISI interrupt Channel 2 */
#define IMX9_IRQ_RESERVED372 (IMX9_IRQ_EXTINT + 356) /* CAMERAMIX ISI interrupt Channel 3 */
#define IMX9_IRQ_RESERVED373 (IMX9_IRQ_EXTINT + 357) /* CAMERAMIX ISI interrupt Channel 4 */
#define IMX9_IRQ_RESERVED374 (IMX9_IRQ_EXTINT + 358) /* CAMERAMIX ISI interrupt Channel 5 */
#define IMX9_IRQ_RESERVED375 (IMX9_IRQ_EXTINT + 359) /* CAMERAMIX ISI interrupt Channel 6 */
#define IMX9_IRQ_RESERVED376 (IMX9_IRQ_EXTINT + 360) /* CAMERAMIX ISI interrupt Channel 7 */
#define IMX9_IRQ_DMA5_4_ERROR (IMX9_IRQ_EXTINT + 361) /* CAMERAMIX EDMA error interrupt */
#define IMX9_IRQ_DMA5_4_0_1 (IMX9_IRQ_EXTINT + 362) /* CAMERAMIX EDMA channel 0 interrupt */
#define IMX9_IRQ_DMA5_4_2_3 (IMX9_IRQ_EXTINT + 363) /* CAMERAMIX EDMA channel 2 interrupt */
#define IMX9_IRQ_DMA5_4_4_5 (IMX9_IRQ_EXTINT + 364) /* CAMERAMIX EDMA channel 4 interrupt */
#define IMX9_IRQ_DMA5_4_6_7 (IMX9_IRQ_EXTINT + 365) /* CAMERAMIX EDMA channel 6 interrupt */
#define IMX9_IRQ_DMA5_4_8_9 (IMX9_IRQ_EXTINT + 366) /* CAMERAMIX EDMA channel 8 interrupt */
#define IMX9_IRQ_DMA5_4_10_11 (IMX9_IRQ_EXTINT + 367) /* CAMERAMIX EDMA channel 10 interrupt */
#define IMX9_IRQ_DMA5_4_12_13 (IMX9_IRQ_EXTINT + 368) /* CAMERAMIX EDMA channel 12 interrupt */
#define IMX9_IRQ_DMA5_4_14_15 (IMX9_IRQ_EXTINT + 369) /* CAMERAMIX EDMA channel 14 interrupt */
#define IMX9_IRQ_DMA5_4_16_17 (IMX9_IRQ_EXTINT + 370) /* CAMERAMIX EDMA channel 16 interrupt */
#define IMX9_IRQ_DMA5_4_18_19 (IMX9_IRQ_EXTINT + 371) /* CAMERAMIX EDMA channel 18 interrupt */
#define IMX9_IRQ_DMA5_4_20_21 (IMX9_IRQ_EXTINT + 372) /* CAMERAMIX EDMA channel 20 interrupt */
#define IMX9_IRQ_DMA5_4_22_23 (IMX9_IRQ_EXTINT + 373) /* CAMERAMIX EDMA channel 22 interrupt */
#define IMX9_IRQ_DMA5_4_24_25 (IMX9_IRQ_EXTINT + 374) /* CAMERAMIX EDMA channel 24 interrupt */
#define IMX9_IRQ_DMA5_4_26_27 (IMX9_IRQ_EXTINT + 375) /* CAMERAMIX EDMA channel 26 interrupt */
#define IMX9_IRQ_DMA5_4_28_29 (IMX9_IRQ_EXTINT + 376) /* CAMERAMIX EDMA channel 28 interrupt */
#define IMX9_IRQ_DMA5_4_30_31 (IMX9_IRQ_EXTINT + 377) /* CAMERAMIX EDMA channel 30 interrupt */
#define IMX9_IRQ_RESERVED394 (IMX9_IRQ_EXTINT + 378) /* CAMERAMIX CSI Formatting Unit 1: Buffer overflow */
#define IMX9_IRQ_RESERVED395 (IMX9_IRQ_EXTINT + 379) /* CAMERAMIX CSI Formatting Unit 1: Interlaced Error */
#define IMX9_IRQ_RESERVED396 (IMX9_IRQ_EXTINT + 380) /* CAMERAMIX CSI Formatting Unit 1: Pixel Data Type Error */
#define IMX9_IRQ_RESERVED397 (IMX9_IRQ_EXTINT + 381) /* CAMERAMIX CSI Formatting Unit 2: Buffer overflow */
#define IMX9_IRQ_RESERVED398 (IMX9_IRQ_EXTINT + 382) /* CAMERAMIX CSI Formatting Unit 2: Interlaced Error */
#define IMX9_IRQ_RESERVED399 (IMX9_IRQ_EXTINT + 383) /* CAMERAMIX CSI Formatting Unit 2: Pixel Data Type Error */
#define IMX9_IRQ_RESERVED400 (IMX9_IRQ_EXTINT + 384) /* CAMERAMIX CSI1 */
#define IMX9_IRQ_RESERVED401 (IMX9_IRQ_EXTINT + 385) /* CAMERAMIX CSI2 */
#define IMX9_IRQ_NEXTINT (218)
/* Total amount of entries in system vector table */
#define NR_IRQS (IMX9_IRQ_EXTINT + IMX9_IRQ_NEXTINT)
#endif /* __ARCH_ARM_INCLUDE_IMX9_IMX95_IRQ_H */
arch/arm/include/imx9/irq.h
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/****************************************************************************
* arch/arm/include/imx9/irq.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_IMX9_IRQ_H
#define __ARCH_ARM_INCLUDE_IMX9_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include <arch/imx9/imx95_irq.h>
#else
# error "Unrecognized i.MX9 architecture"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* IRQ numbers. The IRQ number corresponds vector number and hence map
* directly to bits in the NVIC. This does, however, waste several words
* of memory in the IRQ to handle mapping tables.
*/
/* Common Processor Exceptions (vectors 0-15) */
#define IMX9_IRQ_RESERVED (0) /* Reserved vector .. only used with
* CONFIG_DEBUG_FEATURES */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset(not handled by IRQ) */
#define IMX9_IRQ_NMI (2) /* Vector 2: Non-Maskable Int (NMI) */
#define IMX9_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define IMX9_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define IMX9_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define IMX9_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
/* Vectors 7-10: Reserved */
#define IMX9_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define IMX9_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define IMX9_IRQ_PENDSV (14) /* Vector 14: Pendable SSR */
#define IMX9_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* Chip-Specific External interrupts */
#define IMX9_IRQ_EXTINT (16) /* Vector number of the first ext int */
#define ARMV7M_PERIPHERAL_INTERRUPTS IMX9_IRQ_NEXTINT
#endif /* __ARCH_ARM_INCLUDE_IMX9_IRQ_H */
arch/arm/src/imx9/CMakeLists.txt
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# ##############################################################################
# arch/arm/src/imx9/CMakeLists.txt
#
# SPDX-License-Identifier: Apache-2.0
#
# Licensed to the Apache Software Foundation (ASF) under one or more contributor
# license agreements. See the NOTICE file distributed with this work for
# additional information regarding copyright ownership. The ASF licenses this
# file to you under the Apache License, Version 2.0 (the "License"); you may not
# use this file except in compliance with the License. You may obtain a copy of
# the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations under
# the License.
#
# ##############################################################################
set(SRCS
imx9_allocateheap.c
imx9_start.c
imx9_clockconfig.c
imx9_gpio.c
imx9_iomuxc.c
imx9_irq.c
imx9_timerisr.c
imx9_idle.c)
if(CONFIG_IMX9_SCMI)
list(APPEND SRCS imx9_scmi.c)
# NXP SDK SCMI interface for pinctrl and clocking
endif()
if(CONFIG_RPTUN)
list(APPEND SRCS imx9_rsctable.c imx9_rptun.c)
endif()
if(CONFIG_IMX9_MU)
list(APPEND SRCS imx9_mu.c)
endif()
if(CONFIG_ARM_MPU)
list(APPEND SRCS imx9_mpuinit.c)
endif()
if(CONFIG_IMX9_FLEXCAN)
list(APPEND SRCS imx9_flexcan.c)
endif()
if(CONFIG_IMX9_LPUART)
list(APPEND SRCS imx9_lpuart.c imx9_lowputc.c)
endif()
if(CONFIG_IMX9_GPIO_IRQ)
list(APPEND SRCS imx9_gpioirq.c)
endif()
if(CONFIG_IMX9_FLEXIO_PWM)
list(APPEND SRCS imx9_flexio_pwm.c)
endif()
if(CONFIG_IMX9_TPM_PWM)
list(APPEND SRCS imx9_tpm_pwm.c)
endif()
if(CONFIG_IMX9_USBDEV)
list(APPEND SRCS imx9_usbdev.c)
endif()
if(CONFIG_IMX9_LPI2C)
list(APPEND SRCS imx9_lpi2c.c)
endif()
if(CONFIG_IMX9_LPSPI)
list(APPEND SRCS imx9_lpspi.c)
endif()
if(CONFIG_IMX9_EDMA)
list(APPEND SRCS imx9_edma.c)
endif()
target_sources(arch PRIVATE ${SRCS})
arch/arm/src/imx9/Kconfig
+877
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arch/arm/src/imx9/Make.defs
+81
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############################################################################
# arch/arm/src/imx9/Make.defs
#
# SPDX-License-Identifier: Apache-2.0
# SPDX-FileCopyrightText: 2024 NXP
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include armv7-m/Make.defs
# i.MX9-specific C source files
CHIP_CSRCS = imx9_allocateheap.c imx9_start.c imx9_clockconfig.c imx9_gpio.c imx9_iomuxc.c imx9_irq.c imx9_timerisr.c imx9_idle.c
ifeq ($(CONFIG_IMX9_SCMI),y)
CHIP_CSRCS += imx9_scmi.c
# NXP SDK SCMI interface for pinctrl and clocking
endif
ifeq ($(CONFIG_RPTUN),y)
CHIP_CSRCS += imx9_rsctable.c imx9_rptun.c
endif
ifeq ($(CONFIG_IMX9_MU),y)
CHIP_CSRCS += imx9_mu.c
endif
ifeq ($(CONFIG_ARM_MPU),y)
CHIP_CSRCS += imx9_mpuinit.c
endif
ifeq ($(CONFIG_IMX9_FLEXCAN),y)
CHIP_CSRCS += imx9_flexcan.c
endif
ifeq ($(CONFIG_IMX9_LPUART),y)
CHIP_CSRCS += imx9_lpuart.c imx9_lowputc.c
endif
ifeq ($(CONFIG_IMX9_GPIO_IRQ),y)
CHIP_CSRCS += imx9_gpioirq.c
endif
ifeq ($(CONFIG_IMX9_FLEXIO_PWM),y)
CHIP_CSRCS += imx9_flexio_pwm.c
endif
ifeq ($(CONFIG_IMX9_TPM_PWM),y)
CHIP_CSRCS += imx9_tpm_pwm.c
endif
ifeq ($(CONFIG_IMX9_USBDEV),y)
CHIP_CSRCS += imx9_usbdev.c
endif
ifeq ($(CONFIG_IMX9_LPI2C),y)
CHIP_CSRCS += imx9_lpi2c.c
endif
ifeq ($(CONFIG_IMX9_LPSPI), y)
CHIP_CSRCS += imx9_lpspi.c
endif
ifeq ($(CONFIG_IMX9_EDMA), y)
CHIP_CSRCS += imx9_edma.c
endif
arch/arm/src/imx9/chip.h
+52
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/****************************************************************************
* arch/arm/src/imx9/chip.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_CHIP_H
#define __ARCH_ARM_SRC_IMX9_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <nuttx/arch.h>
# include <arch/irq.h>
# include <arch/imx9/chip.h>
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Cache line sizes (in bytes) for the i.MX 9 M7 Core */
#define ARMV7M_DCACHE_LINESIZE 32 /* 32 bytes (8 words) */
#define ARMV7M_ICACHE_LINESIZE 32 /* 32 bytes (8 words) */
/****************************************************************************
* Macro Definitions
****************************************************************************/
#endif /* __ARCH_ARM_SRC_IMX9_CHIP_H */
arch/arm/src/imx9/hardware/imx95/imx95_clock.h
+827
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arch/arm/src/imx9/hardware/imx95/imx95_dmamux.h
+212
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx95/imx95_dmamux.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_DMAMUX_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_DMAMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "imx95_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Identify channel MUX from 9th bit */
#define EDMA3_MUX_ID 0x0000
#define EDMA4_MUX_ID 0x0100
#define EDMA_MUX_ID_MASK 0xff00
#define EDMA_MUX_MASK 0x00ff
/* eDMA3 MUXs */
#define DMA_REQUEST_DISABLED (0 | EDMA3_MUX_ID) /**< DSisabled*/
#define DMA_REQUEST_MUXCAN1 (1 | EDMA3_MUX_ID) /**< CAN1 */
#define DMA_REQUEST_MUXLPTMR1REQUEST (2 | EDMA3_MUX_ID) /**< LPTMR1 Request */
#define DMA_REQUEST_MUXELEREQUEST (3 | EDMA3_MUX_ID) /**< ELE Request */
#define DMA_REQUEST_MUXTPM1OVERFLOWREQUEST (4 | EDMA3_MUX_ID) /**< TPM1 Overflow Request */
#define DMA_REQUEST_MUXTPM2OVERFLOWREQUEST (5 | EDMA3_MUX_ID) /**< TPM2 Overflow Request */
#define DMA_REQUEST_MUXPDMREQUEST (6 | EDMA3_MUX_ID) /**< PDM */
#define DMA_REQUEST_MUXADC1REQUEST (7 | EDMA3_MUX_ID) /**< ADC1 */
#define DMA_REQUEST_MUXGPIO1REQUEST0 (8 | EDMA3_MUX_ID) /**< GPIO1 channel 0 */
#define DMA_REQUEST_MUXGPIO1REQUEST1 (9 | EDMA3_MUX_ID) /**< GPIO1 channel 1 */
#define DMA_REQUEST_MUXI3C1TOBUSREQUEST (10 | EDMA3_MUX_ID) /**< I3C1 To-bus Request */
#define DMA_REQUEST_MUXI3C1FROMBUSREQUEST (11 | EDMA3_MUX_ID) /**< I3C1 From-bus Request */
#define DMA_REQUEST_MUXLPI2C1TX (12 | EDMA3_MUX_ID) /**< LPI2C1 */
#define DMA_REQUEST_MUXLPI2C1RX (13 | EDMA3_MUX_ID) /**< LPI2C1 */
#define DMA_REQUEST_MUXLPI2C2TX (14 | EDMA3_MUX_ID) /**< LPI2C2 */
#define DMA_REQUEST_MUXLPI2C2RX (15 | EDMA3_MUX_ID) /**< LPI2C2 */
#define DMA_REQUEST_MUXLPSPI1TX (16 | EDMA3_MUX_ID) /**< LPSPI1 Transmit */
#define DMA_REQUEST_MUXLPSPI1RX (17 | EDMA3_MUX_ID) /**< LPSPI1 Receive */
#define DMA_REQUEST_MUXLPSPI2TX (18 | EDMA3_MUX_ID) /**< LPSPI2 Transmit */
#define DMA_REQUEST_MUXLPSPI2RX (19 | EDMA3_MUX_ID) /**< LPSPI2 Receive */
#define DMA_REQUEST_MUXLPUART1TX (20 | EDMA3_MUX_ID) /**< LPUART1 Transmit */
#define DMA_REQUEST_MUXLPUART1RX (21 | EDMA3_MUX_ID) /**< LPUART1 Receive */
#define DMA_REQUEST_MUXLPUART2TX (22 | EDMA3_MUX_ID) /**< LPUART2 Transmit */
#define DMA_REQUEST_MUXLPUART2RX (23 | EDMA3_MUX_ID) /**< LPUART2 Receive */
#define DMA_REQUEST_MUXSAI1TX (24 | EDMA3_MUX_ID) /**< SAI1 Transmit */
#define DMA_REQUEST_MUXSAI1RX (25 | EDMA3_MUX_ID) /**< SAI1 Receive */
#define DMA_REQUEST_MUXTPM1REQUEST0REQUEST2 (26 | EDMA3_MUX_ID) /**< TPM1 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM1REQUEST1REQUEST3 (27 | EDMA3_MUX_ID) /**< TPM1 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM2REQUEST0REQUEST2 (28 | EDMA3_MUX_ID) /**< TPM2 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM2REQUEST1REQUEST3 (29 | EDMA3_MUX_ID) /**< TPM2 request 1 and request 3 */
#define DMA3_REQUEST_MUX_COUNT (30)
/* eDMA4 MUXs */
#define DMA_REQUEST_MUXCAN2 (1U | EDMA4_MUX_ID) /**< CAN2 */
#define DMA_REQUEST_MUXGPIO2REQUEST0 (2U | EDMA4_MUX_ID) /**< GPIO2 channel 0 */
#define DMA_REQUEST_MUXGPIO2REQUEST1 (3U | EDMA4_MUX_ID) /**< GPIO2 channel 1 */
#define DMA_REQUEST_MUXGPIO3REQUEST0 (4U | EDMA4_MUX_ID) /**< GPIO3 channel 0 */
#define DMA_REQUEST_MUXGPIO3REQUEST1 (5U | EDMA4_MUX_ID) /**< GPIO3 channel 1 */
#define DMA_REQUEST_MUXI3C2TOBUSREQUEST (6U | EDMA4_MUX_ID) /**< I3C2 To-bus Request */
#define DMA_REQUEST_MUXI3C2FROMBUSREQUEST (7U | EDMA4_MUX_ID) /**< I3C2 From-bus Request */
#define DMA_REQUEST_MUXLPI2C3TX (8U | EDMA4_MUX_ID) /**< LPI2C3 */
#define DMA_REQUEST_MUXLPI2C3RX (9U | EDMA4_MUX_ID) /**< LPI2C3 */
#define DMA_REQUEST_MUXLPI2C4TX (10U | EDMA4_MUX_ID) /**< LPI2C4 */
#define DMA_REQUEST_MUXLPI2C4RX (11U | EDMA4_MUX_ID) /**< LPI2C2 */
#define DMA_REQUEST_MUXLPSPI3TX (12U | EDMA4_MUX_ID) /**< LPSPI3 Transmit */
#define DMA_REQUEST_MUXLPSPI3RX (13U | EDMA4_MUX_ID) /**< LPSPI3 Receive */
#define DMA_REQUEST_MUXLPSPI4TX (14U | EDMA4_MUX_ID) /**< LPSPI4 Transmit */
#define DMA_REQUEST_MUXLPSPI4RX (15U | EDMA4_MUX_ID) /**< LPSPI4 Receive */
#define DMA_REQUEST_MUXLPTMR2REQUEST (16U | EDMA4_MUX_ID) /**< LPTMR2 Request */
#define DMA_REQUEST_MUXLPUART3TX (17U | EDMA4_MUX_ID) /**< LPUART3 Transmit */
#define DMA_REQUEST_MUXLPUART3RX (18U | EDMA4_MUX_ID) /**< LPUART3 Receive */
#define DMA_REQUEST_MUXLPUART4TX (19U | EDMA4_MUX_ID) /**< LPUART4 Transmit */
#define DMA_REQUEST_MUXLPUART4RX (20U | EDMA4_MUX_ID) /**< LPUART4 Receive */
#define DMA_REQUEST_MUXLPUART5TX (21U | EDMA4_MUX_ID) /**< LPUART5 Transmit */
#define DMA_REQUEST_MUXLPUART5RX (22U | EDMA4_MUX_ID) /**< LPUART5 Receive */
#define DMA_REQUEST_MUXLPUART6TX (23U | EDMA4_MUX_ID) /**< LPUART6 Transmit */
#define DMA_REQUEST_MUXLPUART6RX (24U | EDMA4_MUX_ID) /**< LPUART6 Receive */
#define DMA_REQUEST_MUXTPM3REQUEST0REQUEST2 (25U | EDMA4_MUX_ID) /**< TPM3 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM3REQUEST1REQUEST3 (26U | EDMA4_MUX_ID) /**< TPM3 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM3OVERFLOWREQUEST (27U | EDMA4_MUX_ID) /**< TPM3 Overflow request */
#define DMA_REQUEST_MUXTPM4REQUEST0REQUEST2 (28U | EDMA4_MUX_ID) /**< TPM4 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM4REQUEST1REQUEST3 (29U | EDMA4_MUX_ID) /**< TPM4 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM4OVERFLOWREQUEST (30U | EDMA4_MUX_ID) /**< TPM4 Overflow request */
#define DMA_REQUEST_MUXTPM5REQUEST0REQUEST2 (31U | EDMA4_MUX_ID) /**< TPM5 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM5REQUEST1REQUEST3 (32U | EDMA4_MUX_ID) /**< TPM5 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM5OVERFLOWREQUEST (33U | EDMA4_MUX_ID) /**< TPM5 Overflow request */
#define DMA_REQUEST_MUXTPM6REQUEST0REQUEST2 (34U | EDMA4_MUX_ID) /**< TPM6 request 0 and request 2 */
#define DMA_REQUEST_MUXTPM6REQUEST1REQUEST3 (35U | EDMA4_MUX_ID) /**< TPM6 request 1 and request 3 */
#define DMA_REQUEST_MUXTPM6OVERFLOWREQUEST (36U | EDMA4_MUX_ID) /**< TPM6 Overflow request */
#define DMA_REQUEST_MUXFLEXIO1REQUEST0 (37U | EDMA4_MUX_ID) /**< FlexIO1 Request0 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST1 (38U | EDMA4_MUX_ID) /**< FlexIO1 Request1 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST2 (39U | EDMA4_MUX_ID) /**< FlexIO1 Request2 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST3 (40U | EDMA4_MUX_ID) /**< FlexIO1 Request3 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST4 (41U | EDMA4_MUX_ID) /**< FlexIO1 Request4 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST5 (42U | EDMA4_MUX_ID) /**< FlexIO1 Request5 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST6 (43U | EDMA4_MUX_ID) /**< FlexIO1 Request6 */
#define DMA_REQUEST_MUXFLEXIO1REQUEST7 (44U | EDMA4_MUX_ID) /**< FlexIO1 Request7 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST0 (45U | EDMA4_MUX_ID) /**< FlexIO2 Request0 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST1 (46U | EDMA4_MUX_ID) /**< FlexIO2 Request1 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST2 (47U | EDMA4_MUX_ID) /**< FlexIO2 Request2 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST3 (48U | EDMA4_MUX_ID) /**< FlexIO2 Request3 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST4 (49U | EDMA4_MUX_ID) /**< FlexIO2 Request4 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST5 (50U | EDMA4_MUX_ID) /**< FlexIO2 Request5 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST6 (51U | EDMA4_MUX_ID) /**< FlexIO2 Request6 */
#define DMA_REQUEST_MUXFLEXIO2REQUEST7 (52U | EDMA4_MUX_ID) /**< FlexIO2 Request7 */
#define DMA_REQUEST_MUXFLEXSPI1TX (53U | EDMA4_MUX_ID) /**< FlexSPI1 Transmit */
#define DMA_REQUEST_MUXFLEXSPI1RX (54U | EDMA4_MUX_ID) /**< FlexSPI1 Receive */
#define DMA_REQUEST_MUXGPIO5REQUEST0 (53U | EDMA4_MUX_ID) /**< GPIO5 Request0 */
#define DMA_REQUEST_MUXGPIO5REQUEST1 (54U | EDMA4_MUX_ID) /**< GPIO5 Request1 */
#define DMA_REQUEST_MUXCAN3 (57U | EDMA4_MUX_ID) /**< CAN3 */
#define DMA_REQUEST_MUXSAI2TX (58U | EDMA4_MUX_ID) /**< SAI2 Transmit */
#define DMA_REQUEST_MUXSAI2RX (59U | EDMA4_MUX_ID) /**< SAI2 Receive */
#define DMA_REQUEST_MUXSAI3TX (60U | EDMA4_MUX_ID) /**< SAI3 Transmit */
#define DMA_REQUEST_MUXSAI3RX (61U | EDMA4_MUX_ID) /**< SAI3 Receive */
#define DMA_REQUEST_MUXGPIO4REQUEST0 (62U | EDMA4_MUX_ID) /**< GPIO4 Request0 */
#define DMA_REQUEST_MUXGPIO4REQUEST1 (63U | EDMA4_MUX_ID) /**< GPIO4 Request1 */
#define DMA_REQUEST_MUXEARCREQUEST0 (65U | EDMA4_MUX_ID) /**< eARC enhanced Audio Return Channel */
#define DMA_REQUEST_MUXEARCREQUEST1 (66U | EDMA4_MUX_ID) /**< eARC enhanced Audio Return Channel */
#define DMA_REQUEST_MUXSAI4TX (67U | EDMA4_MUX_ID) /**< SAI4 Transmit */
#define DMA_REQUEST_MUXSAI4RX (68U | EDMA4_MUX_ID) /**< SAI4 Receive */
#define DMA_REQUEST_MUXSAI5TX (69U | EDMA4_MUX_ID) /**< SAI5 Transmit */
#define DMA_REQUEST_MUXSAI5RX (70U | EDMA4_MUX_ID) /**< SAI5 Receive */
#define DMA_REQUEST_MUXLPI2C5TX (71U | EDMA4_MUX_ID) /**< LPI2C5 */
#define DMA_REQUEST_MUXLPI2C5RX (72U | EDMA4_MUX_ID) /**< LPI2C5 */
#define DMA_REQUEST_MUXLPI2C6TX (73U | EDMA4_MUX_ID) /**< LPI2C6 */
#define DMA_REQUEST_MUXLPI2C6RX (74U | EDMA4_MUX_ID) /**< LPI2C6 */
#define DMA_REQUEST_MUXLPI2C7TX (75U | EDMA4_MUX_ID) /**< LPI2C7 */
#define DMA_REQUEST_MUXLPI2C7RX (76U | EDMA4_MUX_ID) /**< LPI2C7 */
#define DMA_REQUEST_MUXLPI2C8TX (77U | EDMA4_MUX_ID) /**< LPI2C8 */
#define DMA_REQUEST_MUXLPI2C8RX (78U | EDMA4_MUX_ID) /**< LPI2C8 */
#define DMA_REQUEST_MUXLPSPI5TX (79U | EDMA4_MUX_ID) /**< LPSPI5 Transmit */
#define DMA_REQUEST_MUXLPSPI5RX (80U | EDMA4_MUX_ID) /**< LPSPI5 Receive */
#define DMA_REQUEST_MUXLPSPI6TX (81U | EDMA4_MUX_ID) /**< LPSPI6 Transmit */
#define DMA_REQUEST_MUXLPSPI6RX (82U | EDMA4_MUX_ID) /**< LPSPI6 Receive */
#define DMA_REQUEST_MUXLPSPI7TX (83U | EDMA4_MUX_ID) /**< LPSPI7 Transmit */
#define DMA_REQUEST_MUXLPSPI7RX (84U | EDMA4_MUX_ID) /**< LPSPI7 Receive */
#define DMA_REQUEST_MUXLPSPI8TX (85U | EDMA4_MUX_ID) /**< LPSPI8 Transmit */
#define DMA_REQUEST_MUXLPSPI8RX (86U | EDMA4_MUX_ID) /**< LPSPI8 Receive */
#define DMA_REQUEST_MUXLPUART7TX (87U | EDMA4_MUX_ID) /**< LPUART7 Transmit */
#define DMA_REQUEST_MUXLPUART7RX (88U | EDMA4_MUX_ID) /**< LPUART7 Receive */
#define DMA_REQUEST_MUXLPUART8TX (89U | EDMA4_MUX_ID) /**< LPUART8 Transmit */
#define DMA_REQUEST_MUXLPUART8RX (90U | EDMA4_MUX_ID) /**< LPUART8 Receive */
#define DMA_REQUEST_MUXCAN4 (91U | EDMA4_MUX_ID) /**< CAN4 */
#define DMA_REQUEST_MUXCAN5 (92U | EDMA4_MUX_ID) /**< CAN5 */
#define DMA4_REQUEST_MUX_COUNT (95)
/* Combined MUX count (eDMA3 and eDMA4) */
#define DMA_REQUEST_MUX_COUNT (DMA3_REQUEST_MUX_COUNT + DMA4_REQUEST_MUX_COUNT)
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_dmamux_get_dmabase
*
* Description:
* Get DMA engine base address from MUX identifier.
*
* Input Parameters:
* dmamux - The DMA MUX identifier.
*
* Returned Value:
* Base address of the associated DMA engine.
*
****************************************************************************/
static inline uintptr_t imx9_dmamux_get_dmabase(uint16_t dmamux)
{
if ((dmamux & EDMA_MUX_ID_MASK) == EDMA3_MUX_ID)
{
return IMX9_DMA3_BASE;
}
else
{
return IMX9_EDMA5_2_BASE;
}
}
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_DMAMUX_H */
arch/arm/src/imx9/hardware/imx95/imx95_edma.h
+445
View File
@@ -0,0 +1,445 @@
/****************************************************************************
* arch/arm/src/imx9/hardware/imx95/imx95_edma.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_EDMA_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_EDMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdint.h>
#include "imx95_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* eDMA3 / eDMA4 Register Offsets */
#define IMX9_EDMA_CSR_OFFSET (0x000000) /* Management Page Control Register (CSR) */
#define IMX9_EDMA_ES_OFFSET (0x000004) /* Management Page Error Status Register (ES) */
#define IMX9_EDMA_CH_GRPRI_OFFSET(n) (0x000100 + ((n) << 2)) /* Channel n Arbitration Group Register (CHn_GRPRI) */
/* eDMA3 only */
#define IMX9_EDMA_INT_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT) */
#define IMX9_EDMA_HRS_OFFSET (0x00000c) /* Management Page Hardware Request Status Register (HRS) */
/* eDMA4 only */
#define IMX9_EDMA_INT_LOW_OFFSET (0x000008) /* Management Page Interrupt Request Status Register (INT_LOW) */
#define IMX9_EDMA_INT_HIGH_OFFSET (0x00000c) /* Management Page Interrupt Request Status Register (INT_HIGH) */
#define IMX9_EDMA_HRS_LOW_OFFSET (0x000010) /* Management Page Hardware Request Status Register (HRS_LOW) */
#define IMX9_EDMA_HRS_HIGH_OFFSET (0x000014) /* Management Page Hardware Request Status Register (HRS_HIGH) */
/* eDNA5 only */
#define IMX9_EDMA_MP_CH_MUX_OFFSET(n) (0x000200 + ((n) << 2)) /* Channel Multiplexor Configuration (CH_MUX) */
/* eDMA3 / eDMA4 Register Addresses */
#define IMX9_EDMA_CSR(n) ((n) + IMX9_EDMA_CSR_OFFSET)
#define IMX9_EDMA_ES(n) ((n) + IMX9_EDMA_ES_OFFSET)
#define IMX9_EDMA_CH_GRPRI(n,c) ((n) + IMX9_EDMA_CH_GRPRI_OFFSET(n))
/* eDMA3 only */
#define IMX9_EDMA_INT (IMX9_DMA3_BASE + IMX9_EDMA_INT_OFFSET)
#define IMX9_EDMA_HRS (IMX9_DMA3_BASE + IMX9_EDMA_HRS_OFFSET)
/* eDMA5 only */
#define IMX9_EDMA_INT_LOW (IMX9_EDMA5_2_BASE + IMX9_EDMA_INT_LOW_OFFSET)
#define IMX9_EDMA_INT_HIGH (IMX9_EDMA5_2_BASE + IMX9_EDMA_INT_HIGH_OFFSET)
#define IMX9_EDMA_HRS_LOW (IMX9_EDMA5_2_BASE + IMX9_EDMA_HRS_LOW_OFFSET)
#define IMX9_EDMA_HRS_HIGH (IMX9_EDMA5_2_BASE + IMX9_EDMA_HRS_HIGH_OFFSET)
/* eDMA Transfer Control Descriptor (TCD) Register Offsets */
#define IMX9_EDMA_CH_CSR_OFFSET (0x000000) /* Channel Control and Status Register (CH0_CSR) */
#define IMX9_EDMA_CH_ES_OFFSET (0x000004) /* Channel Error Status Register (CH0_ES) */
#define IMX9_EDMA_CH_INT_OFFSET (0x000008) /* Channel Interrupt Status Register (CH0_INT) */
#define IMX9_EDMA_CH_SBR_OFFSET (0x00000c) /* Channel System Bus Register (CH0_SBR) */
#define IMX9_EDMA_CH_PRI_OFFSET (0x000010) /* Channel Priority Register (CH0_PRI) */
#define IMX9_EDMA_CH_MUX_OFFSET (0x000014) /* Channel Multiplexor Configuration (CH0_MUX) (eDMA4 only) */
#define IMX9_EDMA_CH_MATTR_OFFSET (0x000018) /* Memory Attributes Register (CH0_MATTR) (eDMA4 only) */
#define IMX9_EDMA_TCD_SADDR_OFFSET (0x000020) /* TCD Source Address Register (TCD0_SADDR) */
#define IMX9_EDMA_TCD_SOFF_OFFSET (0x000024) /* TCD Signed Source Address Offset Register (TCD0_SOFF) */
#define IMX9_EDMA_TCD_ATTR_OFFSET (0x000026) /* TCD Transfer Attributes (TCD0_ATTR) */
#define IMX9_EDMA_TCD_NBYTES_OFFSET (0x000028) /* TCD Transfer Size (TCD0_NBYTES) */
#define IMX9_EDMA_TCD_SLAST_SDA_OFFSET (0x00002c) /* TCD Last Source Address Adjustment / Store DADDR Address Register (TCD0_SLAST_SDA) */
#define IMX9_EDMA_TCD_DADDR_OFFSET (0x000030) /* TCD Destination Address Register (TCD0_DADDR) */
#define IMX9_EDMA_TCD_DOFF_OFFSET (0x000034) /* TCD Signed Destination Address Offset Register (TCD0_DOFF) */
#define IMX9_EDMA_TCD_CITER_OFFSET (0x000036) /* TCD Current Major Loop Count Register (TCD0_CITER) */
#define IMX9_EDMA_TCD_DLAST_SGA_OFFSET (0x000038) /* TCD Last Destination Address Adjustment / Scatter Gather Address Register (TCD0_DLAST_SGA)*/
#define IMX9_EDMA_TCD_CSR_OFFSET (0x00003c) /* TCD Control and Status Register (TCD0_CSR) */
#define IMX9_EDMA_TCD_BITER_OFFSET (0x00003e) /* TCD Beginning Major Loop Count Register (TCD0_BITER) */
/* eDMA 3 and eDMA 4 have TCD instance offsets, but same base offset */
#define IMX9_EDMA_TCD_BASE_OFFSET (0x10000) /* Offset to TCD for both eDMA3/4 */
#define IMX9_EDMA3_TCD_INST_OFFSET (0x10000) /* Per instance TCD offset for eDMA3 */
#define IMX9_EDMA4_TCD_INST_OFFSET (0x8000) /* Per instance TCD offset for eDMA4 */
#define IMX9_EDMA_TCD_BASE(n) ((n) + IMX9_EDMA_TCD_BASE_OFFSET)
#define IMX9_EDMA_TCD_INST_OFFSET(n) ((n) == IMX9_DMA3_BASE ? IMX9_EDMA3_TCD_INST_OFFSET : IMX9_EDMA4_TCD_INST_OFFSET)
#define IMX9_EDMA_TCD(n,t) (IMX9_EDMA_TCD_BASE(n) + (t) * IMX9_EDMA_TCD_INST_OFFSET(n))
/* eDMA Transfer Control Descriptor (TCD) Register Addresses ****************/
#define IMX9_EDMA_CH_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_CSR_OFFSET)
#define IMX9_EDMA_CH_ES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_ES_OFFSET)
#define IMX9_EDMA_CH_INT(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_INT_OFFSET)
#define IMX9_EDMA_CH_SBR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_SBR_OFFSET)
#define IMX9_EDMA_CH_PRI(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_PRI_OFFSET)
#define IMX9_EDMA_CH_MUX(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_CH_MUX_OFFSET)
#define IMX9_EDMA_TCD_SADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SADDR_OFFSET)
#define IMX9_EDMA_TCD_SOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SOFF_OFFSET)
#define IMX9_EDMA_TCD_ATTR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_ATTR_OFFSET)
#define IMX9_EDMA_TCD_NBYTES(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_NBYTES_OFFSET)
#define IMX9_EDMA_TCD_SLAST_SDA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_SLAST_SDA_OFFSET)
#define IMX9_EDMA_TCD_DADDR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DADDR_OFFSET)
#define IMX9_EDMA_TCD_DOFF(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DOFF_OFFSET)
#define IMX9_EDMA_TCD_CITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CITER_OFFSET)
#define IMX9_EDMA_TCD_DLAST_SGA(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_DLAST_SGA_OFFSET)
#define IMX9_EDMA_TCD_CSR(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_CSR_OFFSET)
#define IMX9_EDMA_TCD_BITER(n,t) (IMX9_EDMA_TCD(n,t) + IMX9_EDMA_TCD_BITER_OFFSET)
/* eDMA Register Bitfield Definitions ***************************************/
/* Management Page Control Register (CSR) */
/* Bit 0: Reserved */
#define EDMA_CSR_EDBG (1 << 1) /* Bit 1: Enable Debug (EDBG) */
#define EDMA_CSR_ERCA (1 << 2) /* Bit 2: Enable Round Robin Channel Arbitration (ERCA) */
/* Bit 3: Reserved */
#define EDMA_CSR_HAE (1 << 4) /* Bit 4: Halt After Error (HAE) */
#define EDMA_CSR_HALT (1 << 5) /* Bit 5: Halt DMA Operations (HALT) */
#define EDMA_CSR_GCLC (1 << 6) /* Bit 6: Global Channel Linking Control (GCLC) */
#define EDMA_CSR_GMRC (1 << 7) /* Bit 7: Global Master ID Replication Control (GMRC) */
#define EDMA_CSR_ECX (1 << 8) /* Bit 8: Cancel Transfer With Error (ECX) */
#define EDMA_CSR_CX (1 << 9) /* Bit 9: Cancel Transfer (CX) */
/* Bits 10-23: Reserved */
#define EDMA_CSR_ACTIVE_ID_SHIFT (24) /* Bits 24-28: Active Channel ID (ACTIVE_ID) */
#define EDMA_CSR_ACTIVE_ID_MASK (0x1f << EDMA_CSR_ACTIVE_ID_SHIFT)
/* Bits 29-30: Reserved */
#define EDMA_CSR_ACTIVE (1 << 31) /* Bit 31: DMA Active Status (ACTIVE) */
/* Management Page Error Status Register (ES) */
#define EDMA_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
#define EDMA_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
#define EDMA_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
#define EDMA_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
#define EDMA_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
#define EDMA_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
#define EDMA_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
#define EDMA_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
#define EDMA_ES_ECX (1 << 8) /* Bit 8: Transfer Canceled (ECX) */
/* Bits 9-23: Reserved */
#define EDMA_ES_ERRCHN_SHIFT (24) /* Bits 24-28: Error Channel Number or Canceled Channel Number (ERRCHN) */
#define EDMA_ES_ERRCHN_MASK (0x1f << EDMA_ES_ERRCHN_SHIFT)
/* Bits 29-30: Reserved */
#define EDMA_ES_VLD (1 << 31) /* Bit 31: Logical OR of all ERR status fields (VALID) */
/* Management Page Interrupt Request Status Register (INT) */
#define EDMA_INT(n) (1 << (n)) /* Bit n: Interrupt Request Status (INT) */
/* Management Page Hardware Request Status Register (HRS) */
#define EDMA_HRS(n) (1 << (n)) /* Bit n: Hardware Request Status (HRS) */
/* Channel n Arbitration Group Register (CHn_GRPRI) */
#define EDMA_CH_GRPRI_SHIFT (0) /* Bits 0-4: Arbitration Group For Channel n (GRPRI) */
#define EDMA_CH_GRPRI_MASK (0x1f << EDMA_CH_GRPRI_SHIFT)
/* Bits 5-31: Reserved */
/* eDMA Transfer Control Descriptor (TCD) Bitfield Definitions **************/
/* Channel n Control and Status Register (CHn_CSR) */
#define EDMA_CH_CSR_ERQ (1 << 0) /* Bit 0: Enable DMA Request (ERQ) */
#define EDMA_CH_CSR_EARQ (1 << 1) /* Bit 1: Enable Asynchronous DMA Request in Stop Mode for Channel (EARQ) */
#define EDMA_CH_CSR_EEI (1 << 2) /* Bit 2: Enable Error Interrupt (EEI) */
#define EDMA_CH_CSR_EBW (1 << 3) /* Bit 3: Enable Buffered Writes (EBW) */
/* Bit 4-29: Reserved */
#define EDMA_CH_CSR_DONE (1 << 30) /* Bit 30: Channel Done (DONE) */
#define EDMA_CH_CSR_ACTIVE (1 << 31) /* Bit 31: CHannel Active (ACTIVE) */
/* Channel n Error Status Register (CHn_ES) */
#define EDMA_CH_ES_DBE (1 << 0) /* Bit 0: Destination Bus Error (DBE) */
#define EDMA_CH_ES_SBE (1 << 1) /* Bit 1: Source Bus Error (SBE) */
#define EDMA_CH_ES_SGE (1 << 2) /* Bit 2: Scatter/Gather Configuration Error (SGE) */
#define EDMA_CH_ES_NCE (1 << 3) /* Bit 3: NBYTES/CITER Configuration Error (NCE) */
#define EDMA_CH_ES_DOE (1 << 4) /* Bit 4: Destination Offset Error (DOE) */
#define EDMA_CH_ES_DAE (1 << 5) /* Bit 5: Destination Address Error (DAE) */
#define EDMA_CH_ES_SOE (1 << 6) /* Bit 6: Source Offset Error (SOE) */
#define EDMA_CH_ES_SAE (1 << 7) /* Bit 7: Source Address Error (SAE) */
/* Bit 8-30: Reserved */
#define EDMA_CH_ES_ERR (1 << 31) /* Bit 31: Error in this channel (ERR) */
/* Channel n Interrupt Status Register (CHn_INT) */
#define EDMA_CH_INT (1 << 0) /* Bit 0: Interrupt Request (INT) */
/* Bits 1-31: Reserved */
/* Channel n System Bus Register (CHn_SBR) */
#define EDMA_CH_SBR_MID_SHIFT (0) /* Bits 0-3: Master ID (MID) */
#define EDMA_CH_SBR_MID_MASK (0x0f << EDMA_CH_SBR_MID_SHIFT)
/* Bits 4-13: Reserved */
#define EDMA_CH_SBR_SEC (1 << 14) /* Bit 14: Security Level (SEC) */
#define EDMA_CH_SBR_PAL (1 << 15) /* Bit 15: Privileged Access Level (PAL) */
#define EDMA_CH_SBR_EMI (1 << 16) /* Bit 16: Enable Master ID Replication (EMI) */
#define EDMA_CH_SBR_ATTR_SHIFT (17) /* Bits 17-19: Attribute Output (ATTR) */
#define EDMA_CH_SBR_ATTR_MASK (0x07 << EDMA_CH_SBR_ATTR_SHIFT)
/* Bits 20-31: Reserved */
/* Channel n Priority Register (CHn_PRI) */
#define EDMA_CH_PRI_APL_SHIFT (0) /* Bits 0-2: Arbitration Priority Level (APL) */
#define EDMA_CH_PRI_APL_MASK (0x07 << EDMA_CH_PRI_APL_SHIFT)
/* Bits 3-29: Reserved */
#define EDMA_CH_PRI_DPA (1 << 30) /* Bit 30: Disable Preempt Ability (DPA) */
#define EDMA_CH_PRI_ECP (1 << 31) /* Bit 31: Enable Channel Preemption (ECP) */
/* Channel Multiplexor Configuration (CHn_MUX) */
#define EDMA_CH_SRC_SHIFT (0) /* Bits 0-6: Service Request Source */
#define EDMA_CH_SRC_MASK (0x7f << EDMA_CH_SRC_SHIFT)
/* TCDn Source Address Register (TCDn_SADDR) */
#define EDMA_TCD_SADDR_SHIFT (0) /* Bits 0-31: Source Address (SADDR) */
#define EDMA_TCD_SADDR_MASK (0xffffffff << EDMA_TCD_SADDR_SHIFT)
/* TCDn Signed Source Address Offset Register (TCDn_SOFF) */
#define EDMA_TCD_SOFF_SHIFT (0) /* Bits 0-31: Source Address Signed Offset (SOFF) */
#define EDMA_TCD_SOFF_MASK (0xffffffff << EDMA_TCD_SOFF_SHIFT)
/* TCDn Transfer Attributes (TCDn_ATTR) */
#define EDMA_TCD_ATTR_DSIZE_SHIFT (0) /* Bits 0-2: Destination Data Transfer Size (DSIZE) */
#define EDMA_TCD_ATTR_DSIZE_MASK (0x07 << EDMA_TCD_ATTR_DSIZE_SHIFT)
#define EDMA_TCD_ATTR_DSIZE(n) (((n) << EDMA_TCD_ATTR_DSIZE_SHIFT) & EDMA_TCD_ATTR_DSIZE_MASK)
#define EDMA_TCD_ATTR_DMOD_SHIFT (3) /* Bits 3-7: Destination Address Modulo (DMOD) */
#define EDMA_TCD_ATTR_DMOD_MASK (0x1f << EDMA_TCD_ATTR_DMOD_SHIFT)
#define EDMA_TCD_ATTR_DMOD(n) (((n) << EDMA_TCD_ATTR_DMOD_SHIFT) & EDMA_TCD_ATTR_DMOD_MASK)
#define EDMA_TCD_ATTR_SSIZE_SHIFT (8) /* Bits 8-10: Source Data Transfer Size (SSIZE) */
#define EDMA_TCD_ATTR_SSIZE_MASK (0x07 << EDMA_TCD_ATTR_SSIZE_SHIFT)
#define EDMA_TCD_ATTR_SSIZE(n) (((n) << EDMA_TCD_ATTR_SSIZE_SHIFT) & EDMA_TCD_ATTR_SSIZE_MASK)
# define EDMA_TCD_ATTR_SSIZE_8BIT (0x00 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 8-bit */
# define EDMA_TCD_ATTR_SSIZE_16BIT (0x01 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-bit */
# define EDMA_TCD_ATTR_SSIZE_32BIT (0x02 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-bit */
# define EDMA_TCD_ATTR_SSIZE_64BIT (0x03 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-bit */
# define EDMA_TCD_ATTR_SSIZE_16BYTE (0x04 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 16-byte */
# define EDMA_TCD_ATTR_SSIZE_32BYTE (0x05 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 32-byte */
# define EDMA_TCD_ATTR_SSIZE_64BYTE (0x06 << EDMA_TCD_ATTR_SSIZE_SHIFT) /* 64-byte */
#define EDMA_TCD_ATTR_SMOD_SHIFT (11) /* Bits 11-15: Source Address Modulo (SMOD) */
#define EDMA_TCD_ATTR_SMOD_MASK (0x1f << EDMA_TCD_ATTR_SMOD_SHIFT)
#define EDMA_TCD_ATTR_SMOD(n) (((n) << EDMA_TCD_ATTR_SMOD_SHIFT) & EDMA_TCD_ATTR_SMOD_MASK)
/* TCDn Transfer Size (TCDn_NBYTES) */
#define EDMA_TCD_NBYTES_SHIFT (0) /* Bits 0-29: Number of Bytes to Transfer per Service Request (NBYTES) */
#define EDMA_TCD_NBYTES_MASK (0x3fffffff << EDMA_TCD_NBYTES_SHIFT)
#define EDMA_TCD_NBYTES_MASK_MLOFF (0x03ff << EDMA_TCD_NBYTES_SHIFT)
#define EDMA_TCD_NBYTES_MLOFF_SHIFT (10) /* Bits 10-29: Minor Loop Offset (MLOFF) */
#define EDMA_TCD_NBYTES_MLOFF_MASK (0x0fffff << EDMA_TCD_NBYTES_MLOFF_SHIFT)
#define EDMA_TCD_NBYTES_DMLOE (1 << 30) /* Bit 30: Destination Minor Loop Offset Enable (DMLOE) */
#define EDMA_TCD_NBYTES_SMLOE (1 << 31) /* Bit 31: Source Minor Loop Offset Enable (SMLOE) */
/* TCDn Last Source Address Adjustment / Store DADDR Address Register
* (TCDn_SLAST_SDA)
*/
#define EDMA_TCD_SLAST_SDA_SHIFT (0) /* Bits 0-31: Last Source Address Adjustment / Store DADDR Address (SLAST_SDA) */
#define EDMA_TCD_SLAST_SDA_MASK (0xffffffff << EDMA_TCD_SLAST_SDA_SHIFT)
/* TCDn Destination Address Register (TCDn_DADDR) */
#define EDMA_TCD_DADDR_SHIFT (0) /* Bits 0-31: Destination Address (DADDR) */
#define EDMA_TCD_DADDR_MASK (0xffffffff << EDMA_TCD_DADDR_SHIFT)
/* TCDn Signed Destination Address Offset Register (TCDn_DOFF) */
#define EDMA_TCD_DOFF_SHIFT (0) /* Bits 0-15: Destination Address Signed Offset (DOFF) */
#define EDMA_TCD_DOFF_MASK (0xffff << EDMA_TCD_DOFF_SHIFT)
/* TCDn Current Major Loop Count Register (TCDn_CITER) */
#define EDMA_TCD_CITER_SHIFT (0) /* Bits 0-14: Current Major Iteration Count (CITER) */
#define EDMA_TCD_CITER_MASK (0x7fff << EDMA_TCD_CITER_SHIFT)
#define EDMA_TCD_CITER_MASK_ELINK (0x01ff << EDMA_TCD_CITER_SHIFT)
#define EDMA_TCD_CITER_LINKCH_SHIFT (9) /* Bits 9-13: Minor Loop Link Channel Number (LINKCH) */
#define EDMA_TCD_CITER_LINKCH_MASK (0x1f << EDMA_TCD_CITER_LINKCH_SHIFT)
#define EDMA_TCD_CITER_LINKCH(n) (((n) << EDMA_TCD_CITER_LINKCH_SHIFT) & EDMA_TCD_CITER_LINKCH_SHIFT)
#define EDMA_TCD_CITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
/* TCDn Last Destination Address Adjustment / Scatter Gather Address Register
* (TCDn_DLAST_SGA)
*/
#define EDMA_TCD_DLAST_SGA_SHIFT (0) /* Bits 0-31: Last Destination Address Adjustment / Scatter Gather Address (DLAST_SGA) */
#define EDMA_TCD_DLAST_SGA_MASK (0xffffffff << EDMA_TCD_DLAST_SGA_SHIFT)
/* TCDn Control and Status Register (TCDn_CSR) */
#define EDMA_TCD_CSR_START (1 << 0) /* Bit 0: Channel Start (START) */
#define EDMA_TCD_CSR_INTMAJOR (1 << 1) /* Bit 1: Enable Interrupt if Major count complete (INTMAJOR) */
#define EDMA_TCD_CSR_INTHALF (1 << 2) /* Bit 2: Enable Interrupt if Major Count Half-complete (INTHALF) */
#define EDMA_TCD_CSR_DREQ (1 << 3) /* Bit 3: Disable Request (DREQ) */
#define EDMA_TCD_CSR_ESG (1 << 4) /* Bit 4: Enable Scatter/Gather Processing (ESG) */
#define EDMA_TCD_CSR_MAJORELINK (1 << 5) /* Bit 5: Enable Link When Major Loop Complete (MAJORELINK) */
#define EDMA_TCD_CSR_EEOP (1 << 6) /* Bit 6: Enable End-Of-Packet Processing (EEOP) */
#define EDMA_TCD_CSR_ESDA (1 << 7) /* Bit 7: Enable Store Destination Address (ESDA) */
#define EDMA_TCD_CSR_MAJORLINKCH_SHIFT (8) /* Bits 8-12: Major Loop Link Channel Number (MAJORLINKCH) */
#define EDMA_TCD_CSR_MAJORLINKCH_MASK (0x1f << EDMA_TCD_CSR_MAJORLINKCH_SHIFT)
#define EDMA_TCD_CSR_MAJORLINKCH(n) (((n) << EDMA_TCD_CSR_MAJORLINKCH_SHIFT) & EDMA_TCD_CSR_MAJORLINKCH_MASK)
/* Bit 13: Reserved */
#define EDMA_TCD_CSR_BWC_SHIFT (14) /* Bits 14-15: Bandwidth Control (BWC) */
#define EDMA_TCD_CSR_BWC_MASK (0x03 << EDMA_TCD_CSR_BWC_SHIFT)
# define EDMA_TCD_CSR_BWC_NOSTALL (0x00 << EDMA_TCD_CSR_BWC_SHIFT) /* No eDMA engine stalls */
# define EDMA_TCD_CSR_BWC_HPE (0x01 << EDMA_TCD_CSR_BWC_SHIFT) /* Enable eDMA master high-priority elevation (HPE) mode */
# define EDMA_TCD_CSR_BWC_4CYCLES (0x02 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 4 cycles after each R/W */
# define EDMA_TCD_CSR_BWC_8CYCLES (0x03 << EDMA_TCD_CSR_BWC_SHIFT) /* eDMA engine stalls for 8 cycles after each R/W */
/* TCDn Beginning Major Loop Count Register (TCDn_BITER) */
#define EDMA_TCD_BITER_SHIFT (0) /* Bits 0-14: Starting Major Iteration Count (BITER) */
#define EDMA_TCD_BITER_MASK (0x7fff << EDMA_TCD_BITER_SHIFT)
#define EDMA_TCD_BITER_MASK_ELINK (0x01ff << EDMA_TCD_BITER_SHIFT)
#define EDMA_TCD_BITER_LINKCH_SHIFT (9) /* Bits 9-13: Link Channel Number (LINKCH) */
#define EDMA_TCD_BITER_LINKCH_MASK (0x1f << EDMA_TCD_BITER_LINKCH_SHIFT)
#define EDMA_TCD_BITER_LINKCH(n) (((n) << EDMA_TCD_BITER_LINKCH_SHIFT) & EDMA_TCD_BITER_LINKCH_MASK)
#define EDMA_TCD_BITER_ELINK (1 << 15) /* Bit 15: Enable Link (ELINK) */
/* Amount of channels */
#define DMA3_CHANNEL_COUNT (31)
#define DMA4_CHANNEL_COUNT (64)
#define IMX9_EDMA_NCHANNELS (DMA3_CHANNEL_COUNT + DMA4_CHANNEL_COUNT)
/* Amount of interrupt sources */
#ifdef CONFIG_ARCH_CHIP_IMX95_M7
#define DMA3_IRQ_COUNT (31) /* Error interrupt not counted */
#else
#define DMA3_IRQ_COUNT (32) /* Error interrupt not counted */
#endif
#define DMA4_IRQ_COUNT (32) /* Error interrupt not counted */
/****************************************************************************
* Public Types
****************************************************************************/
/* In-memory representation of the 32-byte Transfer Control Descriptor
* (TCD)
*/
struct imx9_edmatcd_s
{
uint32_t saddr; /* Offset: 0x0000 TCD Source Address */
uint16_t soff; /* Offset: 0x0004 TCD Signed Source Address Offset */
uint16_t attr; /* Offset: 0x0006 TCD Transfer Attributes */
uint32_t nbytes; /* Offset: 0x0008 TCD Signed Minor Loop Offset / Byte Count */
uint32_t slast; /* Offset: 0x000c TCD Last Source Address Adjustment */
uint32_t daddr; /* Offset: 0x0010 TCD Destination Address */
uint16_t doff; /* Offset: 0x0014 TCD Signed Destination Address Offset */
uint16_t citer; /* Offset: 0x0016 TCD Current Minor Loop Link, Major Loop Count */
uint32_t dlastsga; /* Offset: 0x0018 TCD Last Destination Address Adjustment/Scatter Gather Address */
uint16_t csr; /* Offset: 0x001c TCD Control and Status */
uint16_t biter; /* Offset: 0x001e TCD Beginning Minor Loop Link, Major Loop Count */
};
/****************************************************************************
* Inline Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_edma_tcdhasmux
*
* Description:
* Check if DMA TCD has TCD.MUX register.
*
* Input Parameters:
* dmabase - The eDMA base.
*
* Returned Value:
* true if TCD.MUX exists; false if not.
*
****************************************************************************/
static inline bool imx9_edma_tcdhasmux(uintptr_t dmabase)
{
/* Only eDMA5 has TCD.MUX register */
return dmabase == IMX9_EDMA5_2_BASE ? true : false;
}
/****************************************************************************
* Name: imx9_edma_choffset
*
* Description:
* Channel offset in global channel list for dma base.
*
* Input Parameters:
* base - The eDMA base.
*
* Returned Value:
* Channel offset.
*
****************************************************************************/
static inline uint32_t imx9_edma_choffset(uintptr_t base)
{
return base == IMX9_DMA3_BASE ? 0 : DMA3_CHANNEL_COUNT;
}
/****************************************************************************
* Name: imx9_edma_chmax
*
* Description:
* Max channel in global channel list for dma base.
*
* Input Parameters:
* base - The eDMA base.
*
* Returned Value:
* Channel max.
*
****************************************************************************/
static inline uint32_t imx9_edma_chmax(uintptr_t base)
{
return base == IMX9_DMA3_BASE ? DMA3_CHANNEL_COUNT : IMX9_EDMA_NCHANNELS;
}
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_EDMA_H */
arch/arm/src/imx9/hardware/imx95/imx95_gpio.h
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx95/imx95_gpio.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_GPIO_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "imx95_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IMX9_GPIO_VERID_OFFSET (0x0000) /* Version ID */
#define IMX9_GPIO_PARAM_OFFSET (0x0004) /* Parameter */
#define IMX9_GPIO_LOCK_OFFSET (0x000c) /* Lock */
#define IMX9_GPIO_PCNS_OFFSET (0x0010) /* Pin Control Nonsecure */
#define IMX9_GPIO_ICNS_OFFSET (0x0014) /* Interrupt Control Nonsecure */
#define IMX9_GPIO_PCNP_OFFSET (0x0018) /* Pin Control Nonprivilege */
#define IMX9_GPIO_ICNP_OFFSET (0x001c) /* Interrupt Control Nonprivilege */
#define IMX9_GPIO_PDOR_OFFSET (0x0040) /* Port Data Output */
#define IMX9_GPIO_PSOR_OFFSET (0x0044) /* Port Set Output */
#define IMX9_GPIO_PCOR_OFFSET (0x0048) /* Port Clear Output */
#define IMX9_GPIO_PTOR_OFFSET (0x004c) /* Port Toggle Output */
#define IMX9_GPIO_PDIR_OFFSET (0x0050) /* Port Data Input */
#define IMX9_GPIO_PDDR_OFFSET (0x0054) /* Port Data Direction */
#define IMX9_GPIO_PIDR_OFFSET (0x0058) /* Port Input Disable */
#define IMX9_GPIO_P0DR_OFFSET (0x0060) /* Pin Data (0-31 at offsets of n * 4h) */
#define IMX9_GPIO_ICR0_OFFSET (0x0080) /* Interrupt Control (0-31 at offsets of n * 4h) */
#define IMX9_GPIO_GICLR_OFFSET (0x0100) /* Global Interrupt Control Low */
#define IMX9_GPIO_GICHR_OFFSET (0x0104) /* Global Interrupt Control High */
#define IMX9_GPIO_ISFR0_OFFSET (0x0120) /* Interrupt Status Flag */
#define IMX9_GPIO_ISFR1_OFFSET (0x0124) /* Interrupt Status Flag */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX95_IMX95_GPIO_H */
arch/arm/src/imx9/hardware/imx95/imx95_iomuxc.h
+810
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arch/arm/src/imx9/hardware/imx95/imx95_memorymap.h
+765
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arch/arm/src/imx9/hardware/imx95/imx95_pinmux.h
+748
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arch/arm/src/imx9/hardware/imx9_clock.h
+40
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_clock.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx9_memorymap.h"
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_clock.h"
#else
# error Unrecognized i.MX9 architecture
#endif
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_CCM_H_ */
arch/arm/src/imx9/hardware/imx9_dmamux.h
+39
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_dmamux.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_dmamux.h"
#else
# error Unrecognized i.MX9 architecture
#endif
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_DMAMUX_H */
arch/arm/src/imx9/hardware/imx9_edma.h
+39
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_edma.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_EDMA_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_EDMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_edma.h"
#else
# error Unrecognized i.MX9 architecture
#endif
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_EDMA_H */
arch/arm/src/imx9/hardware/imx9_flexcan.h
+7703
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arch/arm/src/imx9/hardware/imx9_gpc.h
+434
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_gpc.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPC_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPC_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_OFFSET 0x0004 /* CMC Authentication Control */
#define IMX9_GPC_CTRL_CMC_MISC_OFFSET 0x000c /* Miscellaneous */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_OFFSET 0x0010 /* CPU mode control */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_OFFSET 0x0014 /* CPU mode Status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_OFFSET 0x0018 /* CMC pin Status */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_1_OFFSET 0x0100 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_2_OFFSET 0x0104 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_3_OFFSET 0x0108 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_4_OFFSET 0x010c /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_5_OFFSET 0x0110 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_6_OFFSET 0x0114 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_7_OFFSET 0x0118 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_8_OFFSET 0x011c /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_9_OFFSET 0x0120 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_10_OFFSET 0x0124 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_11_OFFSET 0x0128 /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_12_OFFSET 0x012c /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_OFFSET 0x0140 /* CMC non-IRQ wakeup mask */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_1_OFFSET 0x0150 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_2_OFFSET 0x0154 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_3_OFFSET 0x0158 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_4_OFFSET 0x015c /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_5_OFFSET 0x0160 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_6_OFFSET 0x0164 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_7_OFFSET 0x0168 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_8_OFFSET 0x016c /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_9_OFFSET 0x0170 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_10_OFFSET 0x0174 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_11_OFFSET 0x0178 /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_12_OFFSET 0x017c /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_OFFSET 0x0190 /* CMC non-IRQ wakeup status */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_OFFSET 0x0200 /* CMC sleep A55_HDSK control */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_OFFSET 0x0204 /* CMC sleep A55_HDSK status */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_OFFSET 0x0208 /* CMC sleep SSAR control */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_OFFSET 0x020c /* CMC sleep SSAR status */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_OFFSET 0x0230 /* CMC sleep reset control */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_OFFSET 0x0234 /* CMC sleep reset status */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_OFFSET 0x0248 /* CMC sleep Sysman control */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_OFFSET 0x024c /* CMC Sleep Sysman status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_OFFSET 0x0290 /* CMC wakeup power control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_OFFSET 0x0294 /* CMC wakeup power status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_OFFSET 0x02c8 /* CMC wakeup SSAR control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_OFFSET 0x02cc /* CMC wakeup SSAR status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_OFFSET 0x02d0 /* CMC wakeup A55_HDSK control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_OFFSET 0x02d4 /* CMC wakeup A55_HDSK status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_OFFSET 0x02d8 /* CMC wakeup Sysman control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_OFFSET 0x02dc /* CMC wakeup Sysman status */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_OFFSET 0x0380 /* CMC system sleep control */
#define IMX9_GPC_CTRL_CMC_DEBUG_OFFSET 0x0390 /* CMC debug */
/* Register macros */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_OFFSET) /* CMC Authentication Control */
#define IMX9_GPC_CTRL_CMC_MISC(n) ((n) + IMX9_GPC_CTRL_CMC_MISC_OFFSET) /* Miscellaneous */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_MODE_CTRL_OFFSET) /* CPU mode control */
#define IMX9_GPC_CTRL_CMC_MODE_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_MODE_STAT_OFFSET) /* CPU mode Status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_PIN_STAT_OFFSET) /* CMC pin Status */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_1(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_1_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_2(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_2_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_3(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_3_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_4(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_4_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_5(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_5_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_6(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_6_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_7(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_7_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_8(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_8_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_9(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_9_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_10(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_10_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_11(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_11_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_12(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK_12_OFFSET) /* IRQ wake-up mask register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK(n) ((n) + IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_OFFSET) /* CMC non-IRQ wakeup mask */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_1(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_1_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_2(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_2_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_3(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_3_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_4(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_4_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_5(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_5_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_6(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_6_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_7(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_7_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_8(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_8_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_9(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_9_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_10(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_10_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_11(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_11_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_12(n) ((n) + IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT_12_OFFSET) /* IRQ status register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_OFFSET) /* CMC non-IRQ wakeup status */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_OFFSET) /* CMC sleep A55_HDSK control */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_OFFSET) /* CMC sleep A55_HDSK status */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_OFFSET) /* CMC sleep SSAR control */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_OFFSET) /* CMC sleep SSAR status */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_OFFSET) /* CMC sleep reset control */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_OFFSET) /* CMC sleep reset status */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_OFFSET) /* CMC sleep Sysman control */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_OFFSET) /* CMC Sleep Sysman status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_OFFSET) /* CMC wakeup power control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_OFFSET) /* CMC wakeup power status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_OFFSET) /* CMC wakeup SSAR control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_OFFSET) /* CMC wakeup SSAR status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_OFFSET) /* CMC wakeup A55_HDSK control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_OFFSET) /* CMC wakeup A55_HDSK status */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_OFFSET) /* CMC wakeup Sysman control */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT(n) ((n) + IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_OFFSET) /* CMC wakeup Sysman status */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL(n) ((n) + IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_OFFSET) /* CMC system sleep control */
#define IMX9_GPC_CTRL_CMC_DEBUG(n) ((n) + IMX9_GPC_CTRL_CMC_DEBUG_OFFSET) /* CMC debug */
/* Field definitions */
/* CMC_AUTHEN_CTRL register */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_CFG_SHIFT 7 /* Configuration lock */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_CFG_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_CFG_SHIFT) /* Configuration lock */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_USER_SHIFT 8 /* Allow user mode access */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_USER_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_USER_SHIFT) /* Allow user mode access */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_NONSECURE_SHIFT 9 /* Allow non-secure mode access */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_NONSECURE_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_NONSECURE_SHIFT) /* Allow non-secure mode access */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_SETTING_SHIFT 11 /* Lock NONSECURE and USER */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_SETTING_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_SETTING_SHIFT) /* Lock NONSECURE and USER */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_LIST_SHIFT 15 /* White list lock */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_LIST_FLAG (1 << IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_LOCK_LIST_SHIFT) /* White list lock */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_WHITE_LIST_SHIFT 16 /* Domain ID white list */
#define IMX9_GPC_CTRL_CMC_AUTHEN_CTRL_WHITE_LIST_MASK 0xffff /* Domain ID white list */
/* CMC_MISC register */
#define IMX9_GPC_CTRL_CMC_MISC_NMI_STAT_SHIFT 0 /* Non-masked interrupt status */
#define IMX9_GPC_CTRL_CMC_MISC_NMI_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_NMI_STAT_SHIFT) /* Non-masked interrupt status */
#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_SHIFT 1 /* Allow cpu_sleep_hold_req assert during CPU low power status */
#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_SHIFT) /* Allow cpu_sleep_hold_req assert during CPU low power status */
#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_STAT_SHIFT 2 /* Status of cpu_sleep_hold_ack_b */
#define IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_STAT_SHIFT) /* Status of cpu_sleep_hold_ack_b */
#define IMX9_GPC_CTRL_CMC_MISC_GIC_WAKEUP_STAT_SHIFT 4 /* GIC wakeup request status */
#define IMX9_GPC_CTRL_CMC_MISC_GIC_WAKEUP_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_GIC_WAKEUP_STAT_SHIFT) /* GIC wakeup request status */
#define IMX9_GPC_CTRL_CMC_MISC_IRQ_MUX_SHIFT 5 /* IRQ select */
#define IMX9_GPC_CTRL_CMC_MISC_IRQ_MUX_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_IRQ_MUX_SHIFT) /* IRQ select */
#define IMX9_GPC_CTRL_CMC_MISC_SW_WAKEUP_SHIFT 6 /* Software wakeup. Used for CPU hotplug. */
#define IMX9_GPC_CTRL_CMC_MISC_SW_WAKEUP_FLAG (1 << IMX9_GPC_CTRL_CMC_MISC_SW_WAKEUP_SHIFT) /* Software wakeup. Used for CPU hotplug. */
/* CMC_MODE_CTRL register */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_SHIFT 0 /* The CPU mode the CPU platform should transit to on next sleep event */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_MASK 0x3 /* The CPU mode the CPU platform should transit to on next sleep event */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_STAY_IN_RUN_MODE 0
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_TRANSIT_TO_WAIT 1
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_TRANSIT_TO_STOP 2
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_TRANSIT_TO_SUSPEND 3
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET(n) (n << IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_SHIFT)
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_WFE_EN_SHIFT 4 /* WFE assertion can be sleep event */
#define IMX9_GPC_CTRL_CMC_MODE_CTRL_WFE_EN_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_CTRL_WFE_EN_SHIFT) /* WFE assertion can be sleep event */
/* CMC_MODE_STAT register */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_CURRENT_SHIFT 0 /* Current CPU mode */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_CURRENT_MASK 0x3 /* Current CPU mode */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT 2 /* Previous CPU mode */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_CPU_MODE_PREVIOUS_MASK 0x3 /* Previous CPU mode */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT 8 /* Busy on CPU mode transition of sleep, not include set point trans busy. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_TRANS_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_TRANS_BUSY_SHIFT) /* Busy on CPU mode transition of sleep, not include set point trans busy. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT 9 /* Busy on CPU mode transition of wakeup, not include set point trans busy. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_TRANS_BUSY_SHIFT) /* Busy on CPU mode transition of wakeup, not include set point trans busy. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEPING_IDLE_SHIFT 10 /* Completed CPU mode and set point transition of sleep sequence, in a sleeping_idle state. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEPING_IDLE_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEPING_IDLE_SHIFT) /* Completed CPU mode and set point transition of sleep sequence, in a sleeping_idle state. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_REQUEST_SHIFT 16 /* Status of sleep_request input port */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_REQUEST_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_SLEEP_REQUEST_SHIFT) /* Status of sleep_request input port */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WFE_REQUEST_SHIFT 17 /* Status of standby_wfe input port */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WFE_REQUEST_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_WFE_REQUEST_SHIFT) /* Status of standby_wfe input port */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_REQUEST_SHIFT 18 /* "ORed" of all unmasked IRQ */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_REQUEST_FLAG (1 << IMX9_GPC_CTRL_CMC_MODE_STAT_WAKEUP_REQUEST_SHIFT) /* "ORed" of all unmasked IRQ */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_FSM_STATE_SHIFT 24 /* CPU mode trans FSM state. */
#define IMX9_GPC_CTRL_CMC_MODE_STAT_FSM_STATE_MASK 0x1f /* CPU mode trans FSM state. */
/* CMC_PIN_STAT register */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT 0 /* cpu_mode_trans_a55_hdsk_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_REQUEST_STAT_SHIFT) /* cpu_mode_trans_a55_hdsk_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_REQUEST_STAT_SHIFT 1 /* cpu_mode_trans_ssar_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_REQUEST_STAT_SHIFT) /* cpu_mode_trans_ssar_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_REQUEST_STAT_SHIFT 6 /* cpu_mode_trans_reset_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_REQUEST_STAT_SHIFT) /* cpu_mode_trans_reset_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_REQUEST_STAT_SHIFT 7 /* cpu_mode_trans_power_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_REQUEST_STAT_SHIFT) /* cpu_mode_trans_power_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_SHIFT 9 /* cpu_mode_trans_sysman_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_REQUEST_STAT_SHIFT) /* cpu_mode_trans_sysman_request pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT 16 /* cpu_mode_trans_a55_hdsk_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_A55_HDSK_DONE_STAT_SHIFT) /* cpu_mode_trans_a55_hdsk_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_DONE_STAT_SHIFT 17 /* cpu_mode_trans_ssar_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SSAR_DONE_STAT_SHIFT) /* cpu_mode_trans_ssar_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_DONE_STAT_SHIFT 22 /* cpu_mode_trans_reset_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_RESET_DONE_STAT_SHIFT) /* cpu_mode_trans_reset_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_DONE_STAT_SHIFT 23 /* cpu_mode_trans_power_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_POWER_DONE_STAT_SHIFT) /* cpu_mode_trans_power_done pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_DONE_STAT_SHIFT 25 /* cpu_mode_trans_sysman_done pin status. */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_DONE_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_SYSMAN_DONE_STAT_SHIFT) /* cpu_mode_trans_sysman_done pin status. */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_CPU_MODE_STAT_SHIFT 29 /* cpu_power_mode pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_CPU_MODE_STAT_MASK 0x3 /* cpu_power_mode pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT 31 /* Debug wakeup acknowledge pin status */
#define IMX9_GPC_CTRL_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_PIN_STAT_DEBUG_WAKEUP_ACK_STAT_SHIFT) /* Debug wakeup acknowledge pin status */
/* CMC_NON_IRQ_WAKEUP_MASK register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT 0 /* "1" means the event cannot wakeup CPU platform */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT) /* "1" means the event cannot wakeup CPU platform */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT 1 /* "1" means the debug_wakeup_request cannot wakeup CPU platform */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT) /* "1" means the debug_wakeup_request cannot wakeup CPU platform */
/* CMC_NON_IRQ_WAKEUP_STAT register */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT 0 /* Event wakeup status */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT) /* Event wakeup status */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT 1 /* Debug wakeup status */
#define IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_FLAG (1 << IMX9_GPC_CTRL_CMC_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT) /* Debug wakeup status */
/* CMC_SLEEP_A55_HDSK_CTRL register */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_SLEEP_A55_HDSK_STAT register */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_SLEEP_A55_HDSK_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_SLEEP_SSAR_CTRL register */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_SSAR_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_SLEEP_SSAR_STAT register */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_SLEEP_SSAR_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_SLEEP_RESET_CTRL register */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_RESET_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_SLEEP_RESET_STAT register */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_SLEEP_RESET_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_SLEEP_SYSMAN_CTRL register */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE. */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_SLEEP_SYSMAN_STAT register */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_SLEEP_SYSMAN_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_WAKEUP_POWER_CTRL register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_POWER_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_WAKEUP_POWER_STAT register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_WAKEUP_POWER_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_WAKEUP_SSAR_CTRL register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_WAKEUP_SSAR_STAT register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SSAR_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_WAKEUP_A55_HDSK_CTRL register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_WAKEUP_A55_HDSK_STAT register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_WAKEUP_A55_HDSK_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_WAKEUP_SYSMAN_CTRL register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_STEP_CNT_SHIFT 0 /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_STEP_CNT_MASK 0xffffff /* (invalid when CNT_MODE==0 and invisible on customer RM)Step count, usage depends on CNT_MODE */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_CNT_MODE_SHIFT 28 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_CNT_MODE_MASK 0x3 /* (keep==0 and invisible on customer RM)Count mode */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_SHIFT 31 /* Disable this step */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_FLAG (1 << IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_CTRL_DISABLE_SHIFT) /* Disable this step */
/* CMC_WAKEUP_SYSMAN_STAT register */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_RSP_CNT_SHIFT 0 /* Response count, record the delay from step start to step_done received */
#define IMX9_GPC_CTRL_CMC_WAKEUP_SYSMAN_STAT_RSP_CNT_MASK 0xffffff /* Response count, record the delay from step start to step_done received */
/* CMC_SYS_SLEEP_CTRL register */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_WAIT_SHIFT 0 /* Request system sleep when CPU is in WAIT mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_WAIT_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_WAIT_SHIFT) /* Request system sleep when CPU is in WAIT mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_STOP_SHIFT 1 /* Request system sleep when CPU is in STOP mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_STOP_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_STOP_SHIFT) /* Request system sleep when CPU is in STOP mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT 2 /* Request system sleep when CPU is in SUSPEND mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SS_SUSPEND_SHIFT) /* Request system sleep when CPU is in SUSPEND mode */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT 16 /* Indicates the CPU is busy entering system sleep mode. */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_SLEEP_BUSY_SHIFT) /* Indicates the CPU is busy entering system sleep mode. */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT 17 /* Indicates the CPU is busy exiting system sleep mode. */
#define IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_FLAG (1 << IMX9_GPC_CTRL_CMC_SYS_SLEEP_CTRL_SYS_WAKEUP_BUSY_SHIFT) /* Indicates the CPU is busy exiting system sleep mode. */
/* CMC_DEBUG register */
#define IMX9_GPC_CTRL_CMC_DEBUG_PRETEND_SLEEP_SHIFT 0 /* Write 1 to force CMC into sleep. Used to debug GPC status. Locked by LOCK_CFG field. */
#define IMX9_GPC_CTRL_CMC_DEBUG_PRETEND_SLEEP_FLAG (1 << IMX9_GPC_CTRL_CMC_DEBUG_PRETEND_SLEEP_SHIFT) /* Write 1 to force CMC into sleep. Used to debug GPC status. Locked by LOCK_CFG field. */
/* Register array dimensions */
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_MASK__REGARRAY_SIZE 12
#define IMX9_GPC_CTRL_CMC_IRQ_WAKEUP_STAT__REGARRAY_SIZE 12
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPC_H */
arch/arm/src/imx9/hardware/imx9_gpio.h
+109
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_gpio.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_gpio.h"
#else
# error Unrecognized i.MX9 architecture
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define GPIO1 0 /* Port 1 index */
#define GPIO2 1 /* Port 2 index */
#define GPIO3 2 /* Port 3 index */
#define GPIO4 3 /* Port 4 index */
#define GPIO5 4 /* Port 5 index */
#define GPIO6 5 /* Port 6 index */
#define GPIO7 6 /* Port 7 index */
#define GPIO8 7 /* Port 8 index */
#define GPIO9 8 /* Port 9 index */
#define GPIO10 9 /* Port 10 index */
#define GPIO11 10 /* Port 11 index */
#define GPIO12 11 /* Port 12 index */
#define GPIO13 12 /* Port 13 index */
#define IMX9_GPIO_NPINS 32 /* Up to 32 pins per port */
/* Register bit definitions *************************************************/
/* Most registers are laid out simply with one bit per pin */
#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-31 */
/* ICRN Register */
#define IMX9_GPIO_ICRN_ISF (1 << 24) /* Bit 24: Interrupt Status Flag */
#define IMX9_GPIO_ICRN_LK (1 << 23) /* Bit 23: Lock Register */
#define IMX9_GPIO_ICRN_IRQS (1 << 20) /* Bit 20: Configures the selected interrupt, or DMA request. */
#define IMX9_GPIO_ICRN_SHIFT (16) /* Bits 16-19: Interrupt Configuration */
#define IMX9_GPIO_ICRN_MASK (0xf << IMX9_GPIO_ICRN_SHIFT)
# define IMX9_GPIO_ICRN_DISABLED (0 << IMX9_GPIO_ICRN_SHIFT) /* Interrupt Status Flag (ISF) is disabled */
# define IMX9_GPIO_ICRN_DMARISING (1 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on rising edge */
# define IMX9_GPIO_ICRN_DMAFALLING (2 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on falling edge */
# define IMX9_GPIO_ICRN_DMABOTH (3 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and DMA request on either edge */
# define IMX9_GPIO_ICRN_ISFRISING (5 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on rising edge */
# define IMX9_GPIO_ICRN_ISFFALLING (6 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on falling edge */
# define IMX9_GPIO_ICRN_ISFBOTH (7 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag sets on either edge */
# define IMX9_GPIO_ICRN_ZERO (8 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt when logic 0 */
# define IMX9_GPIO_ICRN_RISING (9 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on rising-edge */
# define IMX9_GPIO_ICRN_FALLING (10 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on falling-edge */
# define IMX9_GPIO_ICRN_BOTH (11 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt on either edge */
# define IMX9_GPIO_ICRN_ONE (12 << IMX9_GPIO_ICRN_SHIFT) /* ISF flag and Interrupt when logic 1 */
/* Global Interrupt Control Low Register */
#define IMX9_GPIO_GICLR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */
#define IMX9_GPIO_GICLR_GIWD_MASK (0xffff << IMX9_GPIO_GICLR_GIWD_SHIFT)
# define IMX9_GPIO_GICLR_GIWD_PIN(n) ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWD_SHIFT) /* Pin n=0..15 */
#define IMX9_GPIO_GICLR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */
#define IMX9_GPIO_GICLR_GIWE_MASK (0xffff << IMX9_GPIO_GICLR_GIWE_SHIFT)
# define IMX9_GPIO_GICLR_GIWE_PIN(n) ((uint32_t)(n) << IMX9_GPIO_GICLR_GIWE_SHIFT) /* Pin n=0..15 */
/* Global Interrupt Control High Register */
#define IMX9_GPIO_GICHR_GIWD_SHIFT (0) /* Bits 0-15: Global Interrupt Write Data */
#define IMX9_GPIO_GICHR_GIWD_MASK (0xffff << IMX9_GPIO_GICHR_GIWD_SHIFT)
# define IMX9_GPIO_GICHR_GIWD_PIN(n) ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWD_SHIFT) /* Pin n=16..31 */
#define IMX9_GPIO_GICHR_GIWE_SHIFT (16) /* Bits 16-31: Global Interrupt Write Enable */
#define IMX9_GPIO_GICHR_GIWE_MASK (0xffff << IMX9_GPIO_GICHR_GIWE_SHIFT)
# define IMX9_GPIO_GICHR_GIWE_PIN(n) ((uint32_t)((n) - 16) << IMX9_GPIO_GICHR_GIWE_SHIFT) /* Pin n=16..31 */
/* Interrupt Status Flag Register */
#define IMX9_GPIO_ISFR(n) (1 << (n)) /* Interrupt Status Flag, n=0-31 */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_GPIO_H */
arch/arm/src/imx9/hardware/imx9_iomuxc.h
+107
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_iomuxc.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_iomuxc.h"
#else
# error Unrecognized i.MX9 architecture
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Pad muxing */
#define IOMUXC_MUX_MODE_SHIFT (0) /* MODE: pin alternate function */
#define IOMUXC_MUX_MODE_MASK (0x03 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT0 (0 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT1 (1 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT2 (2 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT3 (3 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT4 (4 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT5 (5 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_MODE_ALT6 (6 << IOMUXC_MUX_MODE_SHIFT)
#define IOMUXC_MUX_SION_SHIFT (4) /* SION: Force input path */
#define IPMUXC_MUX_SION_MASK (0x01 << IOMUXC_MUX_SION_SHIFT)
#define IOMUXC_MUX_SION_OFF (0 << IOMUXC_MUX_SION_SHIFT)
#define IOMUXC_MUX_SION_ON (1 << IOMUXC_MUX_SION_SHIFT)
/* Pad control */
#define IOMUXC_PAD_DSE_SHIFT (1) /* DSE: Drive strength */
#define IOMUXC_PAD_DSE_MASK (0x3f << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X0 (0x00 << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X1 (0x01 << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X2 (0x03 << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X3 (0x07 << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X4 (0x0f << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X5 (0x1f << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_DSE_X6 (0x3f << IOMUXC_PAD_DSE_SHIFT)
#define IOMUXC_PAD_FSEL_SHIFT (7) /* FSEL: Slew rate control */
#define IOMUXC_PAD_FSEL_MASK (0x02 << IOMUXC_PAD_FSEL_SHIFT)
#define IOMUXC_PAD_FSEL_SLOW (0 << IOMUXC_PAD_FSEL_SHIFT)
#define IOMUXC_PAD_FSEL_SSLOW (1 << IOMUXC_PAD_FSEL_SHIFT) /* Slightly slow */
#define IOMUXC_PAD_FSEL_SFAST (2 << IOMUXC_PAD_FSEL_SHIFT) /* Slightly fast */
#define IOMUXC_PAD_FSEL_FAST (3 << IOMUXC_PAD_FSEL_SHIFT)
#define IOMUXC_PAD_PU_SHIFT (9) /* PU: Pull-up */
#define IOMUXC_PAD_PU_MASK (0x01 << IOMUXC_PAD_PU_SHIFT)
#define IOMUXC_PAD_PU_OFF (0 << IOMUXC_PAD_PU_SHIFT)
#define IOMUXC_PAD_PU_ON (1 << IOMUXC_PAD_PU_SHIFT)
#define IOMUXC_PAD_PD_SHIFT (10) /* PD: Pull-down */
#define IOMUXC_PAD_PD_MASK (0x01 << IOMUXC_PAD_PD_SHIFT)
#define IOMUXC_PAD_PD_OFF (0 << IOMUXC_PAD_PD_SHIFT)
#define IOMUXC_PAD_PD_ON (1 << IOMUXC_PAD_PD_SHIFT)
#define IOMUXC_PAD_OD_SHIFT (11) /* OD: Open-drain */
#define IOMUXC_PAD_OD_MASK (0x01 << IOMUXC_PAD_OD_SHIFT)
#define IOMUXC_PAD_OD_DISABE (0 << IOMUXC_PAD_OD_SHIFT)
#define IOMUXC_PAD_OD_ENABLE (1 << IOMUXC_PAD_OD_SHIFT)
#define IOMUXC_PAD_HYS_SHIFT (12) /* HYS: Enable schmitt-trigger on input */
#define IOMUXC_PAD_HYS_MASK (0x01 << IOMUXC_PAD_HYS_SHIFT)
#define IOMUXC_PAD_HYS_ST_OFF (0 << IOMUXC_PAD_HYS_SHIFT) /* Schmitt-trigger off */
#define IOMUXC_PAD_HYS_ST_ON (1 << IOMUXC_PAD_HYS_SHIFT) /* Schmitt-trigger on */
#define IOMUXC_PAD_APC_SHIFT (24) /* APC: Access control */
#define IOMUXC_PAD_APC_MASK (0xff << IOMUXC_PAD_APC_SHIFT)
/* Daisy chain control, 2 bits seems to be enough */
#define IOMUXC_DSY_SHIFT (0)
#define IOMUXC_DSY_MASK (0x03 << IOMUXC_DSY_SHIFT)
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_IOMUXC_H */
arch/arm/src/imx9/hardware/imx9_lpi2c.h
+628
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arch/arm/src/imx9/hardware/imx9_lpit.h
+128
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_lpit.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPIT_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPIT_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define IMX9_LPIT_VERID_OFFSET 0x0000 /* Version ID */
#define IMX9_LPIT_PARAM_OFFSET 0x0004 /* Parameter */
#define IMX9_LPIT_MCR_OFFSET 0x0008 /* Module Control */
#define IMX9_LPIT_MSR_OFFSET 0x000c /* Module Status Register */
#define IMX9_LPIT_MIER_OFFSET 0x0010 /* Moduel Interrupt Enable */
#define IMX9_LPIT_SETTEN_OFFSET 0x0014 /* Set Timer Enable */
#define IMX9_LPIT_CLRTEN_OFFSET 0x0018 /* Clear Timer Enable */
#define IMX9_LPIT_TVAL0_OFFSET 0x0020 /* Timer Channel 0 Value */
#define IMX9_LPIT_CVAL0_OFFSET 0x0024 /* Current Timer Channel 0 Value */
#define IMX9_LPIT_TCTRL0_OFFSET 0x0028 /* Timer Channel 0 Control */
#define IMX9_LPIT_TVAL1_OFFSET 0x0030 /* Timer Channel 1 Value */
#define IMX9_LPIT_CVAL1_OFFSET 0x0034 /* Current Timer Channel 1 Value */
#define IMX9_LPIT_TCTRL1_OFFSET 0x0048 /* Timer Channel 1 Control */
#define IMX9_LPIT_TVAL2_OFFSET 0x0040 /* Timer Channel 2 Value */
#define IMX9_LPIT_CVAL2_OFFSET 0x0044 /* Current Timer Channel 2 Value */
#define IMX9_LPIT_TCTRL2_OFFSET 0x0048 /* Timer Channel 2 Control */
#define IMX9_LPIT_TVAL3_OFFSET 0x0050 /* Timer Channel 3 Value */
#define IMX9_LPIT_CVAL3_OFFSET 0x0054 /* Current Timer Channel 3 Value */
#define IMX9_LPIT_TCTRL3_OFFSET 0x0058 /* Timer Channel 3 Control */
/* Register access */
#define LPIT_VERID(n) ((n) + IMX9_LPIT_VERID_OFFSET)
#define LPIT_PARAM(n) ((n) + IMX9_LPIT_PARAM_OFFSET)
#define LPIT_MCR(n) ((n) + IMX9_LPIT_MCR_OFFSET)
#define LPIT_MSR(n) ((n) + IMX9_LPIT_MSR_OFFSET)
#define LPIT_MIER(n) ((n) + IMX9_LPIT_MIER_OFFSET)
#define LPIT_SETTEN(n) ((n) + IMX9_LPIT_SETTEN_OFFSET)
#define LPIT_CLRTEN(n) ((n) + IMX9_LPIT_CLRTEN_OFFSET)
#define LPIT_TVAL0(n) ((n) + IMX9_LPIT_TVAL0_OFFSET)
#define LPIT_CVAL0(n) ((n) + IMX9_LPIT_CVAL0_OFFSET)
#define LPIT_TCTRL0(n) ((n) + IMX9_LPIT_TCTRL0_OFFSET)
#define LPIT_TVAL1(n) ((n) + IMX9_LPIT_TVAL1_OFFSET)
#define LPIT_CVAL1(n) ((n) + IMX9_LPIT_CVAL1_OFFSET)
#define LPIT_TCTRL1(n) ((n) + IMX9_LPIT_TCTRL1_OFFSET)
#define LPIT_TVAL2(n) ((n) + IMX9_LPIT_TVAL2_OFFSET)
#define LPIT_CVAL2(n) ((n) + IMX9_LPIT_CVAL2_OFFSET)
#define LPIT_TCTRL2(n) ((n) + IMX9_LPIT_TCTRL2_OFFSET)
#define LPIT_TVAL3(n) ((n) + IMX9_LPIT_TVAL3_OFFSET)
#define LPIT_CVAL3(n) ((n) + IMX9_LPIT_CVAL3_OFFSET)
#define LPIT_TCTRL3(n) ((n) + IMX9_LPIT_TCTRL3_OFFSET)
/* Register Bitfield Definitions ********************************************/
#define LPIT_PARAM_EXT_TRIG_SHIFT (8) /* Bit[15:8]: Number of External Trigger Inputs */
#define LPIT_PARAM_EXT_TRIG_MASK (0xff << LPIT_PARAM_EXT_TRIG_SHIFT)
#define LPIT_PARAM_CHANNEL_SHIFT (0) /* Bit[7:0]: Number of Timer Channels */
#define LPIT_PARAM_CHANNEL_MASK (0xff << LPIT_PARAM_CHANNEL_SHIFT)
#define LPIT_MCR_DBG_EN (1 << 3) /* Stop Timer when in Debug Mode */
#define LPIT_MCR_DOZE_EN (1 << 2) /* DOZE Mode Enable */
#define LPIT_MCR_SW_RST (1 << 1) /* Software Reset Bit */
#define LPIT_MCR_M_CEN (1 << 0) /* Module Clock Enable */
#define LPIT_MSR_TIF3 (1 << 3) /* Channel 3 Timer Interrupt Flag */
#define LPIT_MSR_TIF2 (1 << 2) /* Channel 2 Timer Interrupt Flag */
#define LPIT_MSR_TIF1 (1 << 1) /* Channel 1 Timer Interrupt Flag */
#define LPIT_MSR_TIF0 (1 << 0) /* Channel 0 Timer Interrupt Flag */
#define LPIT_MIER_TIE3 (1 << 3) /* Channel 3 Timer Interrupt Enable */
#define LPIT_MIER_TIE2 (1 << 2) /* Channel 2 Timer Interrupt Enable */
#define LPIT_MIER_TIE1 (1 << 1) /* Channel 1 Timer Interrupt Enable */
#define LPIT_MIER_TIE0 (1 << 0) /* Channel 0 Timer Interrupt Enable */
#define LPIT_TCTRL_TRG_SEL_SHIFT (27) /* Bit[27:24]: Trigger Select */
#define LPIT_TCTRL_TRG_SEL_MASK (0xf << LPIT_TCTRL_TRG_SEL_SHIFT)
#define LPIT_TCTRL_TRG_SEL_CHAN0 (0 << LPIT_TCTRL_TRG_SEL_SHIFT)
#define LPIT_TCTRL_TRG_SEL_CHAN1 (1 << LPIT_TCTRL_TRG_SEL_SHIFT)
#define LPIT_TCTRL_TRG_SEL_CHAN2 (2 << LPIT_TCTRL_TRG_SEL_SHIFT)
#define LPIT_TCTRL_TRG_SEL_CHAN3 (3 << LPIT_TCTRL_TRG_SEL_SHIFT)
#define LPIT_TCTRL_TRG_SRC_SHIFT (23) /* Bit23: Trigger Source */
#define LPIT_TCTRL_TRG_SRC_MASK (1 << LPIT_TCTRL_TRG_SRC_SHIFT)
#define LPIT_TCTRL_TRG_SRC_EXTER (0 << LPIT_TCTRL_TRG_SRC_SHIFT) /* external */
#define LPIT_TCTRL_TRG_SRC_INTER (1 << LPIT_TCTRL_TRG_SRC_SHIFT) /* internal */
#define LPIT_TCTRL_TROT (1 << 18) /* Timer Reload On Trigger */
#define LPIT_TCTRL_TSOI (1 << 17) /* Timer Stop On Interrupt */
#define LPIT_TCTRL_TSOT (1 << 16) /* Timer Start On Trigger */
#define LPIT_TCTRL_MODE_SHIFT (2)
#define LPIT_TCTRL_MODE_MASK (3 << LPIT_TCTRL_MODE_SHIFT)
#define LPIT_TCTRL_MODE_32PC (0 << LPIT_TCTRL_MODE_SHIFT) /* 32 Bit periodic Counter */
#define LPIT_TCTRL_MODE_D16PC (1 << LPIT_TCTRL_MODE_SHIFT) /* Dual 16-bit periodic Counter */
#define LPIT_TCTRL_MODE_32TA (2 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Accumulator */
#define LPIT_TCTRL_MODE_32TIC (3 << LPIT_TCTRL_MODE_SHIFT) /* 32 bit Trigger Input Capture */
#define LPIT_TCTRL_CHAIN (1 << 1) /* Chain Channel */
#define LPIT_TCTRL_T_EN (1 << 0) /* Timer Enable */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPIT_H */
arch/arm/src/imx9/hardware/imx9_lpspi.h
+355
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_lpspi.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets *********************************************************/
#define IMX9_LPSPI_VERID_OFFSET (0x0000) /* Version ID Register (VERID) */
#define IMX9_LPSPI_PARAM_OFFSET (0x0004) /* Parameter Register (PARAM) */
#define IMX9_LPSPI_CR_OFFSET (0x0010) /* Control Register (CR) */
#define IMX9_LPSPI_SR_OFFSET (0x0014) /* Status Register (SR) */
#define IMX9_LPSPI_IER_OFFSET (0x0018) /* Interrupt Enable Register (IER) */
#define IMX9_LPSPI_DER_OFFSET (0x001c) /* DMA Enable Register (DER) */
#define IMX9_LPSPI_CFGR0_OFFSET (0x0020) /* Configuration Register 0 (CFGR0) */
#define IMX9_LPSPI_CFGR1_OFFSET (0x0024) /* Configuration Register 1 (CFGR1) */
#define IMX9_LPSPI_DMR0_OFFSET (0x0030) /* Data Match Register 0 (DMR0) */
#define IMX9_LPSPI_DMR1_OFFSET (0x0034) /* Data Match Register 1 (DMR1) */
#define IMX9_LPSPI_CCR_OFFSET (0x0040) /* Clock Configuration Register (CCR) */
#define IMX9_LPSPI_CCR1_OFFSET (0x0044) /* Clock Configuration Register 1 (CCR1) */
#define IMX9_LPSPI_FCR_OFFSET (0x0058) /* FIFO Control Register (FCR) */
#define IMX9_LPSPI_FSR_OFFSET (0x005c) /* FIFO Status Register (FSR) */
#define IMX9_LPSPI_TCR_OFFSET (0x0060) /* Transmit Command Register (TCR) */
#define IMX9_LPSPI_TDR_OFFSET (0x0064) /* Transmit Data Register (TDR) */
#define IMX9_LPSPI_RSR_OFFSET (0x0070) /* Receive Status Register (RSR) */
#define IMX9_LPSPI_RDR_OFFSET (0x0074) /* Receive Data Register (RDR) */
#define IMX9_LPSPI_RDROR_OFFSET (0x0078) /* Receive Data Read Only Register (RDROR) */
#define IMX9_LPSPI_TCBR_OFFSET (0x03fc) /* Transmit Command Burst Register (TCBR) */
#define IMX9_LPSPI_TDBR_OFFSET(n) (0x0400 + ((n) << 2)) /* Transmit Data Burst Register n=0..127 (TDBRn) */
#define IMX9_LPSPI_RDBR_OFFSET(n) (0x0600 + ((n) << 2)) /* Receive Data Burst Register n=0..127 (RDBRn) */
/* Register addresses *******************************************************/
#define IMX9_LPSPI0_VERID(n) ((n) + IMX9_LPSPI_VERID_OFFSET)
#define IMX9_LPSPI0_PARAM(n) ((n) + IMX9_LPSPI_PARAM_OFFSET)
#define IMX9_LPSPI0_CR(n) ((n) + IMX9_LPSPI_CR_OFFSET)
#define IMX9_LPSPI0_SR(n) ((n) + IMX9_LPSPI_SR_OFFSET)
#define IMX9_LPSPI0_IER(n) ((n) + IMX9_LPSPI_IER_OFFSET)
#define IMX9_LPSPI0_DER(n) ((n) + IMX9_LPSPI_DER_OFFSET)
#define IMX9_LPSPI0_CFGR0(n) ((n) + IMX9_LPSPI_CFGR0_OFFSET)
#define IMX9_LPSPI0_CFGR1(n) ((n) + IMX9_LPSPI_CFGR1_OFFSET)
#define IMX9_LPSPI0_DMR0(n) ((n) + IMX9_LPSPI_DMR0_OFFSET)
#define IMX9_LPSPI0_DMR1(n) ((n) + IMX9_LPSPI_DMR1_OFFSET)
#define IMX9_LPSPI0_CCR(n) ((n) + IMX9_LPSPI_CCR_OFFSET)
#define IMX9_LPSPI0_CCR1(n) ((n) + IMX9_LPSPI_CCR1_OFFSET)
#define IMX9_LPSPI0_FCR(n) ((n) + IMX9_LPSPI_FCR_OFFSET)
#define IMX9_LPSPI0_FSR(n) ((n) + IMX9_LPSPI_FSR_OFFSET)
#define IMX9_LPSPI0_TCR(n) ((n) + IMX9_LPSPI_TCR_OFFSET)
#define IMX9_LPSPI0_TDR(n) ((n) + IMX9_LPSPI_TDR_OFFSET)
#define IMX9_LPSPI0_RSR(n) ((n) + IMX9_LPSPI_RSR_OFFSET)
#define IMX9_LPSPI0_RDR(n) ((n) + IMX9_LPSPI_RDR_OFFSET)
#define IMX9_LPSPI0_RDROR(n) ((n) + IMX9_LPSPI_RDROR_OFFSET)
#define IMX9_LPSPI0_TCBR(n) ((n) + IMX9_LPSPI_TCBR_OFFSET)
#define IMX9_LPSPI0_TDBR(n,v) ((n) + IMX9_LPSPI_TDBR_OFFSET(v))
#define IMX9_LPSPI0_RDBR(n,v) ((n) + IMX9_LPSPI_RDBR_OFFSET(v))
/* Register bit definitions *************************************************/
/* Version ID Register (VERID) */
#define LPSPI_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Module Identification Number (FEATURE) */
#define LPSPI_VERID_FEATURE_MASK (0xffff << LPSPI_VERID_FEATURE_SHIFT)
#define LPSPI_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */
#define LPSPI_VERID_MINOR_MASK (0xff << LPSPI_VERID_MINOR_SHIFT)
#define LPSPI_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */
#define LPSPI_VERID_MAJOR_MASK (0xff << LPSPI_VERID_MAJOR_SHIFT)
/* Parameter Register (PARAM) */
#define LPSPI_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size (TXFIFO) */
#define LPSPI_PARAM_TXFIFO_MASK (0xff << LPSPI_PARAM_TXFIFO_SHIFT)
#define LPSPI_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size (RXFIFO) */
#define LPSPI_PARAM_RXFIFO_MASK (0xff << LPSPI_PARAM_RXFIFO_SHIFT)
#define LPSPI_PARAM_PCSNUM_SHIFT (16) /* Bits 16-23: PCS Number (PCSNUM) */
#define LPSPI_PARAM_PCSNUM_MASK (0xff << LPSPI_PARAM_PCSNUM_SHIFT)
/* Bits 24-31: Reserved */
/* Control Register (CR) */
#define LPSPI_CR_MEN (1 << 0) /* Bit 0: Module Enable (MEN) */
#define LPSPI_CR_RST (1 << 1) /* Bit 1: Software Reset (RST) */
/* Bit 2: Reserved */
#define LPSPI_CR_DBGEN (1 << 3) /* Bit 3: Debug Enable (DBGEN) */
/* Bits 4-7: Reserved */
#define LPSPI_CR_RTF (1 << 8) /* Bit 8: Reset Transmit FIFO (RTF) */
#define LPSPI_CR_RRF (1 << 9) /* Bit 9: Reset Receive FIFO (RRF) */
/* Bits 10-31: Reserved */
/* Status Register (SR) */
#define LPSPI_SR_TDF (1 << 0) /* Bit 0: Transmit Data Flag (TDF) */
#define LPSPI_SR_RDF (1 << 1) /* Bit 1: Receive Data Flag (RDF) */
/* Bits 2-7: Reserved */
#define LPSPI_SR_WCF (1 << 8) /* Bit 8: Word Complete Flag (WCF) */
#define LPSPI_SR_FCF (1 << 9) /* Bit 9: Frame Complete Flag (FCF) */
#define LPSPI_SR_TCF (1 << 10) /* Bit 10: Transfer Complete Flag (TCF) */
#define LPSPI_SR_TEF (1 << 11) /* Bit 11: Transmit Error Flag (TEF) */
#define LPSPI_SR_REF (1 << 12) /* Bit 12: Receive Error Flag (REF) */
#define LPSPI_SR_DMF (1 << 13) /* Bit 13: Data Match Flag (DMF) */
/* Bits 14-23: Reserved */
#define LPSPI_SR_MBF (1 << 24) /* Bit 24: Module Busy Flag (MBF) */
/* Bits 25-31: Reserved */
/* Interrupt Enable Register (IER) */
#define LPSPI_IER_TDIE (1 << 0) /* Bit 0: Transmit Data Interrupt Enable (TDIE) */
#define LPSPI_IER_RDIE (1 << 1) /* Bit 1: Receive Data Interrupt Enable (RDIE) */
/* Bits 2-7: Reserved */
#define LPSPI_IER_WCIE (1 << 8) /* Bit 8: Word Complete Interrupt Enable (WCIE) */
#define LPSPI_IER_FCIE (1 << 9) /* Bit 9: Frame Complete Interrupt Enable (FCIE) */
#define LPSPI_IER_TCIE (1 << 10) /* Bit 10: Transfer Complete Interrupt Enable (TCIE) */
#define LPSPI_IER_TEIE (1 << 11) /* Bit 11: Transmit Error Interrupt Enable (TEIE) */
#define LPSPI_IER_REIE (1 << 12) /* Bit 12: Receive Error Interrupt Enable (REIE) */
#define LPSPI_IER_DMIE (1 << 13) /* Bit 13: Data Match Interrupt Enable (DMIE) */
/* Bits 14-31: Reserved */
/* DMA Enable Register (DER) */
#define LPSPI_DER_TDDE (1 << 0) /* Bit 0: Transmit Data DMA Enable (TDDE) */
#define LPSPI_DER_RDDE (1 << 1) /* Bit 1: Receive Data DMA Enable (RDDE) */
/* Bits 2-31: Reserved */
/* Configuration Register 0 (CFGR0) */
#define LPSPI_CFGR0_HREN (1 << 0) /* Bit 0: Host Request Enable (HREN) */
#define LPSPI_CFGR0_HRPOL (1 << 1) /* Bit 1: Host Request Polarity (HRPOL) */
# define LPSPI_CFGR0_HRPOL_HIGH (0 << 1) /* HREQ pin or input trigger is active high */
# define LPSPI_CFGR0_HRPOL_LOW (1 << 1) /* HREQ pin or input trigger is active low */
#define LPSPI_CFGR0_HRSEL (1 << 2) /* Bit 2: Host Request Select (HRSEL) */
# define LPSPI_CFGR0_HRSEL_HREQ (0 << 2) /* Host request input is the LPSPI_HREQ pin */
# define LPSPI_CFGR0_HRSEL_INTR (1 << 2) /* Host request input is the input trigger */
#define LPSPI_CFGR0_HRDIR (1 << 3) /* Bit 3: Host Request Direction (HRDIR) */
# define LPSPI_CFGR0_HRDIR_INPUT (0 << 3) /* HREQ pin is configured as input */
# define LPSPI_CFGR0_HRDIR_OUTPUT (1 << 3) /* HREQ pin is configured as output */
/* Bits 4-7: Reserved */
#define LPSPI_CFGR0_CIRFIFO (1 << 8) /* Bit 8: Circular FIFO Enable (CIRCFIFO) */
#define LPSPI_CFGR0_RDMO (1 << 9) /* Bit 9: Receive Data Match Only (RDMO) */
# define LPSPI_CFGR0_RDMO_FIFO (0 << 9) /* Received data is stored in the receive FIFO as in normal operations */
# define LPSPI_CFGR0_RDMO_DMF (1 << 9) /* Received data is discarded unless the Data Match Flag (DMF) is set */
/* Bits 10-31: Reserved */
/* Configuration Register 1 (CFGR1) */
#define LPSPI_CFGR1_MASTER (1 << 0) /* Bit 0: Master Mode (MASTER) */
#define LPSPI_CFGR1_SAMPLE (1 << 1) /* Bit 1: Sample Point (SAMPLE) */
# define LPSPI_CFGR1_SAMPLE_SCK (0 << 1) /* Input data is sampled on SCK edge */
# define LPSPI_CFGR1_SAMPLE_DELAY (1 << 1) /* Input data is sampled on delayed SCK edge */
#define LPSPI_CFGR1_AUTOPCS (1 << 2) /* Bit 2: Automatic PCS (AUTOPCS) */
#define LPSPI_CFGR1_NOSTALL (1 << 3) /* Bit 3: No Stall (NOSTALL) */
#define LPSPI_CFGR1_PARTIAL (1 << 4) /* Bit 4: Partial Enable (PARTIAL) */
/* Bits 5-7: Reserved */
#define LPSPI_CFGR1_PCSPOL_SHIFT (8) /* Bits 8-15: Peripheral Chip Select Polarity (PCSPOL) */
#define LPSPI_CFGR1_PCSPOL_MASK (0xff << LPSPI_CFGR1_PCSPOL_SHIFT)
# define LPSPI_CFGR1_PCSPOL_LOW(n) (0 << (LPSPI_CFGR1_PCSPOL_SHIFT + (n))) /* The Peripheral Chip Select PCS[n] pin is active low */
# define LPSPI_CFGR1_PCSPOL_HIGH(n) (1 << (LPSPI_CFGR1_PCSPOL_SHIFT + (n))) /* The Peripheral Chip Select PCS[n] pin is active high */
#define LPSPI_CFGR1_MATCFG_SHIFT (16) /* Bits 16-18: Match Configuration (MATCFG) */
#define LPSPI_CFGR1_MATCFG_MASK (0x07 << LPSPI_CFGR1_MATCFG_SHIFT)
#define LPSPI_CFGR1_MATCFG_DIS (0x00 << LPSPI_CFGR1_MATCFG_SHIFT) /* Match is disabled */
/* Bits 19-23: Reserved */
#define LPSPI_CFGR1_PINCFG_SHIFT (24) /* Bits 24-25: Pin Configuration (PINCFG) */
#define LPSPI_CFGR1_PINCFG_MASK (0x03 << LPSPI_CFGR1_PINCFG_SHIFT)
# define LPSPI_CFGR1_PINCFG_SIN_SOUT (0x00 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for input data and SOUT is used for output data */
# define LPSPI_CFGR1_PINCFG_SIN_SIN (0x01 << LPSPI_CFGR1_PINCFG_SHIFT) /* SIN is used for both input and output data */
# define LPSPI_CFGR1_PINCFG_SOUT_SOUT (0x02 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for both input and output data */
# define LPSPI_CFGR1_PINCFG_SOUT_SIN (0x03 << LPSPI_CFGR1_PINCFG_SHIFT) /* SOUT is used for input data and SIN is used for output data */
# define LPSPI_CFGR1_PINCFG(n) ((n) << LPSPI_CFGR1_PINCFG_SHIFT)
#define LPSPI_CFGR1_OUTCFG (1 << 26) /* Bit 26: Output Config (OUTCFG) */
# define LPSPI_CFGR1_OUTCFG_RETAIN (0 << 26) /* Output data retains last value when chip select is negated */
# define LPSPI_CFGR1_OUTCFG_TRISTATE (1 << 26) /* Output data is tristated when chip select is negated */
#define LPSPI_CFGR1_PCSCFG_SHIFT (27) /* Bits 27-28: Peripheral Chip Select Configuration (PCSCFG) */
#define LPSPI_CFGR1_PCSCFG_MASK (0x03 << LPSPI_CFGR1_PCSCFG_SHIFT)
# define LPSPI_CFGR1_PCSCFG_PCS (0x00 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:7] are configured for chip select function */
# define LPSPI_CFGR1_PCSCFG_4BIT (0x01 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:3] are configured for half-duplex 4-bit transfers */
# define LPSPI_CFGR1_PCSCFG_8BIT (0x03 << LPSPI_CFGR1_PCSCFG_SHIFT) /* PCS[2:7] are configured for half-duplex 4-bit and 8-bit transfers */
/* Bits 29-31: Reserved */
/* Data Match Register 0 (DMR0) */
#define LPSPI_DMR0_MATCH0_SHIFT (0) /* Bits 0-31: Match 0 Value (MATCH0) */
#define LPSPI_DMR0_MATCH0_MASK (0xffffffff << LPSPI_DMR0_MATCH0_SHIFT)
/* Data Match Register 0 (DMR1) */
#define LPSPI_DMR1_MATCH1_SHIFT (0) /* Bits 0-31: Match 1 Value (MATCH1) */
#define LPSPI_DMR1_MATCH1_MASK (0xffffffff << LPSPI_DMR1_MATCH1_SHIFT)
/* Clock Configuration Register (CCR) */
#define LPSPI_CCR_SCKDIV_SHIFT (0) /* Bits 0-7: SCK Divider (SCKDIV) */
#define LPSPI_CCR_SCKDIV_MASK (0xff << LPSPI_CCR_SCKDIV_SHIFT)
# define LPSPI_CCR_SCKDIV(n) (((uint32_t)(n) << LPSPI_CCR_SCKDIV_SHIFT) & LPSPI_CCR_SCKDIV_MASK)
#define LPSPI_CCR_DBT_SHIFT (8) /* Bits 8-15: Delay Between Transfers (DBT) */
#define LPSPI_CCR_DBT_MASK (0xff << LPSPI_CCR_DBT_SHIFT)
# define LPSPI_CCR_DBT(n) (((uint32_t)(n) << LPSPI_CCR_DBT_SHIFT) & LPSPI_CCR_DBT_MASK)
#define LPSPI_CCR_PCSSCK_SHIFT (16) /* Bits 16-23: PCS-to-SCK Delay (PCSSCK) */
#define LPSPI_CCR_PCSSCK_MASK (0xff << LPSPI_CCR_PCSSCK_SHIFT)
# define LPSPI_CCR_PCSSCK(n) (((uint32_t)(n) << LPSPI_CCR_PCSSCK_SHIFT) & LPSPI_CCR_PCSSCK_MASK)
#define LPSPI_CCR_SCKPCS_SHIFT (24) /* Bits 24-31: SCK-to-PCS Delay (SCKPCS) */
#define LPSPI_CCR_SCKPCS_MASK (0xff << LPSPI_CCR_SCKPCS_SHIFT)
# define LPSPI_CCR_SCKPCS(n) (((uint32_t)(n) << LPSPI_CCR_SCKPCS_SHIFT) & LPSPI_CCR_SCKPCS_MASK)
/* Clock Configuration Register 1 (CCR1) */
#define LPSPI_CCR1_SCKSET_SHIFT (0) /* Bits 0-7: SCK Setup (SCKSET) */
#define LPSPI_CCR1_SCKSET_MASK (0xff << LPSPI_CCR1_SCKSET_SHIFT)
#define LPSPI_CCR1_SCKHLD_SHIFT (8) /* Bits 8-15: SCK Hold (SCKHLD) */
#define LPSPI_CCR1_SCKHLD_MASK (0xff << LPSPI_CCR1_SCKHLD_SHIFT)
#define LPSPI_CCR1_PCSPCS_SHIFT (16) /* Bits 16-23: PCS to PCS Delay (PCSPCS) */
#define LPSPI_CCR1_PCSPCS_MASK (0xff << LPSPI_CCR1_PCSPCS_SHIFT)
#define LPSPI_CCR1_SCKSCK_SHIFT (24) /* Bits 24-31: SCK Inter-Frame Delay (SCKSCK) */
#define LPSPI_CCR1_SCKSCK_MASK (0xff << LPSPI_CCR1_SCKSCK_SHIFT)
/* FIFO Control Register (FCR) */
#define LPSPI_FCR_TXWATER_SHIFT (0) /* Bits 0-1: Transmit FIFO Watermark (TXWATER) */
#define LPSPI_FCR_TXWATER_MASK (0x03 << LPSPI_FCR_TXWATER_SHIFT)
# define LPSPI_FCR_TXWATER(n) ((uint32_t)(n) << LPSPI_FCR_TXWATER_SHIFT)
/* Bits 2-15: Reserved */
#define LPSPI_FCR_RXWATER_SHIFT (16) /* Bits 16-17: Receive FIFO Watermark (RXWATER) */
#define LPSPI_FCR_RXWATER_MASK (0x03 << LPSPI_FCR_RXWATER_SHIFT)
# define LPSPI_FCR_RXWATER(n) ((uint32_t)(n) << LPSPI_FCR_RXWATER_SHIFT)
/* Bits 18-31: Reserved */
/* FIFO Status Register (FSR) */
#define LPSPI_FSR_TXCOUNT_SHIFT (0) /* Bits 0-2: Transmit FIFO Count (TXCOUNT) */
#define LPSPI_FSR_TXCOUNT_MASK (0x07 << LPSPI_FSR_TXCOUNT_SHIFT)
/* Bits 3-15: Reserved */
#define LPSPI_FSR_RXCOUNT_SHIFT (16) /* Bits 16-18: Receive FIFO Count (RXCOUNT) */
#define LPSPI_FSR_RXCOUNT_MASK (0x07 << LPSPI_FSR_RXCOUNT_SHIFT)
/* Bits 19-31: Reserved */
/* Transmit Command Register (TCR) */
#define LPSPI_TCR_FRAMESZ_SHIFT (0) /* Bits 0-11: Frame Size (FRAMESZ) */
#define LPSPI_TCR_FRAMESZ_MASK (0x0fff << LPSPI_TCR_FRAMESZ_SHIFT)
# define LPSPI_TCR_FRAMESZ(n) ((uint32_t)(n) << LPSPI_TCR_FRAMESZ_SHIFT)
/* Bits 12-15: Reserved */
#define LPSPI_TCR_WIDTH_SHIFT (16) /* Bits 16-17: Transfer Width (WIDTH) */
#define LPSPI_TCR_WIDTH_MASK (0x03 << LPSPI_TCR_WIDTH_SHIFT)
# define LPSPI_TCR_WIDTH_1BIT (0x00 << LPSPI_TCR_WIDTH_SHIFT) /* 1 bit transfer */
# define LPSPI_TCR_WIDTH_2BIT (0x01 << LPSPI_TCR_WIDTH_SHIFT) /* 2 bit transfer */
# define LPSPI_TCR_WIDTH_4BIT (0x02 << LPSPI_TCR_WIDTH_SHIFT) /* 4 bit transfer */
# define LPSPI_TCR_WIDTH_8BIT (0x03 << LPSPI_TCR_WIDTH_SHIFT) /* 8 bit transfer */
#define LPSPI_TCR_TXMSK (1 << 18) /* Bit 18: Transmit Data Mask (TXMSK) */
#define LPSPI_TCR_RXMSK (1 << 19) /* Bit 19: Receive Data Mask (RXMSK) */
#define LPSPI_TCR_CONTC (1 << 20) /* Bit 20: Continuing Command (CONTC) */
#define LPSPI_TCR_CONT (1 << 21) /* Bit 21: Continuous Transfer (CONT) */
#define LPSPI_TCR_BYSW (1 << 22) /* Bit 22: Byte Swap (BYSW) */
#define LPSPI_TCR_LSBF (1 << 23) /* Bit 23: LSB First (LSBF) */
# define LPSPI_TCR_MSBF (0 << 23) /* MSB First */
#define LPSPI_TCR_PCS_SHIFT (24) /* Bits 24-26: Peripheral Chip Select (PCS) */
#define LPSPI_TCR_PCS_MASK (0x07 << LPSPI_TCR_PCS_SHIFT)
# define LPSPI_TCR_PCS_0 (0x00 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[0] */
# define LPSPI_TCR_PCS_1 (0x01 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[1] */
# define LPSPI_TCR_PCS_2 (0x02 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[2] */
# define LPSPI_TCR_PCS_3 (0x03 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[3] */
# define LPSPI_TCR_PCS_4 (0x04 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[4] */
# define LPSPI_TCR_PCS_5 (0x05 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[5] */
# define LPSPI_TCR_PCS_6 (0x06 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[6] */
# define LPSPI_TCR_PCS_7 (0x07 << LPSPI_TCR_PCS_SHIFT) /* Transfer using PCS[7] */
# define LPSPI_TCR_PCS(n) (((n) << LPSPI_TCR_PCS_SHIFT) & LPSPI_TCR_PCS_MASK)
#define LPSPI_TCR_PRESCALE_SHIFT (27) /* Bits 27-29: Prescaler Value (PRESCALE) */
#define LPSPI_TCR_PRESCALE_MASK (0x07 << LPSPI_TCR_PRESCALE_SHIFT)
# define LPSPI_TCR_PRESCALE_DIV1 (0x00 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 1 */
# define LPSPI_TCR_PRESCALE_DIV2 (0x01 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 2 */
# define LPSPI_TCR_PRESCALE_DIV4 (0x02 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 4 */
# define LPSPI_TCR_PRESCALE_DIV8 (0x03 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 8 */
# define LPSPI_TCR_PRESCALE_DIV16 (0x04 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 16 */
# define LPSPI_TCR_PRESCALE_DIV32 (0x05 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 32 */
# define LPSPI_TCR_PRESCALE_DIV64 (0x06 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 64 */
# define LPSPI_TCR_PRESCALE_DIV128 (0x07 << LPSPI_TCR_PRESCALE_SHIFT) /* Divide by 128 */
# define LPSPI_TCR_PRESCALE(n) ((n) << LPSPI_TCR_PRESCALE_SHIFT)
#define LPSPI_TCR_CPHA (1 << 30) /* Bit 30: Clock Phase (CPHA) */
# define LPSPI_TCR_CPHA_CAPTURED (0 << 30) /* Data is captured on the leading edge of SCK and changed on the following edge of SCK */
# define LPSPI_TCR_CPHA_CHANGED (1 << 30) /* Data is changed on the leading edge of SCK and captured on the following edge of SCK */
#define LPSPI_TCR_CPOL (1 << 31) /* Bit 31: Clock Polarity (CPOL) */
# define LPSPI_TCR_CPOL_LOW (0 << 31) /* The inactive state value of SCK is low */
# define LPSPI_TCR_CPOL_HIGH (1 << 31) /* The inactive state value of SCK is high */
/* Transmit Data Register (TDR) */
#define LPSPI_TDR_DATA_SHIFT (0) /* Bits 0-31: Transmit Data (DATA) */
#define LPSPI_TDR_DATA_MASK (0xffffffff << LPSPI_TDR_DATA_SHIFT)
/* Receive Status Register (RSR) */
#define LPSPI_RSR_SOF (1 << 0) /* Bit 0: Start Of Frame (SOF) */
#define LPSPI_RSR_RXEMPTY (1 << 1) /* Bit 1: RX FIFO Empty (RXEMPTY) */
/* Bits 2-31: Reserved */
/* Receive Data Register (RDR) */
#define LPSPI_RDR_DATA_SHIFT (0) /* Bits 0-31: Receive Data (DATA) */
#define LPSPI_RDR_DATA_MASK (0xffffffff << LPSPI_RDR_DATA_SHIFT)
/* Receive Data Read Only Register (RDROR) */
#define LPSPI_RDROR_DATA_SHIFT (0) /* Bits 0-31: Receive Data (DATA) */
#define LPSPI_RDROR_DATA_MASK (0xffffffff << LPSPI_RDROR_DATA_SHIFT)
/* Transmit Command Burst Register (TCBR) */
#define LPSPI_TCBR_DATA_SHIFT (0) /* Bits 0-31: Command Data (DATA) */
#define LPSPI_TCBR_DATA_MASK (0xffffffff << LPSPI_TCBR_DATA_SHIFT)
/* Transmit Data Burst Register (TDBR) */
#define LPSPI_TDBR_DATA_SHIFT (0) /* Bits 0-31: Data (DATA) */
#define LPSPI_TDBR_DATA_MASK (0xffffffff << LPSPI_TDBR_DATA_SHIFT)
/* Receive Data Burst Register (RDBR) */
#define LPSPI_RDBR_DATA_SHIFT (0) /* Bits 0-31: Data (DATA) */
#define LPSPI_RDBR_DATA_MASK (0xffffffff << LPSPI_RDBR_DATA_SHIFT)
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPSPI_H_ */
arch/arm/src/imx9/hardware/imx9_lptmr.h
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@@ -0,0 +1,103 @@
/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_lptmr.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define IMX9_LPTMR_CSR_OFFSET 0x0000 /* Control Status */
#define IMX9_LPTMR_PSR_OFFSET 0x0004 /* Prescale */
#define IMX9_LPTMR_CMR_OFFSET 0x0008 /* Compare */
#define IMX9_LPTMR_CNR_OFFSET 0x000c /* Counter */
/* Register Address *********************************************************/
#define LPTMR_CSR(n) ((n) + IMX9_LPTMR_CSR_OFFSET)
#define LPTMR_PSR(n) ((n) + IMX9_LPTMR_PSR_OFFSET)
#define LPTMR_CMR(n) ((n) + IMX9_LPTMR_CMR_OFFSET)
#define LPTMR_CNR(n) ((n) + IMX9_LPTMR_CNR_OFFSET)
/* Register Bitfield Definitions ********************************************/
#define LPTMR_CSR_TDRE (1 << 8) /* Timer DMA Request Enable */
#define LPTMR_CSR_TCF (1 << 7) /* Timer Compare Flag */
#define LPTMR_CSR_TIE (1 << 6) /* Timer Interrupt Enable */
#define LPTMR_CSR_TPS_SHIFT (4) /* Bit[5:4]: Timer Pin Select */
#define LPTMR_CSR_TPS_MASK (3 << LPTMR_CSR_TPS_SHIFT)
#define LPTMR_CSR_TPS0 (0 << LPTMR_CSR_TPS_SHIFT)
#define LPTMR_CSR_TPS1 (1 << LPTMR_CSR_TPS_SHIFT)
#define LPTMR_CSR_TPS2 (2 << LPTMR_CSR_TPS_SHIFT)
#define LPTMR_CSR_TPS3 (3 << LPTMR_CSR_TPS_SHIFT)
#define LPTMR_CSR_TPP (1 << 3) /* Timer Pin Polarity */
#define LPTMR_CSR_TFC (1 << 2) /* Timer Free-Running Counter */
#define LPTMR_CSR_TMS (1 << 1) /* Timer Mode Select */
#define LPTMR_CSR_TEN (1 << 0) /* Timer Enable */
#define LPTMR_PSR_PRESCALE_SHIFT (3) /* Bit[6:3]: Prescale Value */
#define LPTMR_PSR_PRESCALE_MASK (0xf << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV2 (0 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV4 (1 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV8 (2 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV16 (3 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV32 (4 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV64 (5 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV128 (6 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV256 (7 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV512 (8 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV1024 (9 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV2048 (10 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV4096 (11 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV8192 (12 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV16384 (13 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV32768 (14 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PRESCALE_DIV65536 (15 << LPTMR_PSR_PRESCALE_SHIFT)
#define LPTMR_PSR_PBYP (1 << 2) /* Prescaler Bypass */
/* Clock sources (module clock / root clock)
* ipg_clk_irclk -> lptmrx_clk_root
* ipg_clk_1khz -> 32k_clk_root
* ipg_clk_32khz -> 32k_clk_root
* ipg_clk_ercl -> 32k_clk_root
*/
#define LPTMR_PSR_PCS_SHIFT (0) /* Bit[1:0]: Prescaler Clock Select */
#define LPTMR_PSR_PCS_MASK (3 << LPTMR_PSR_PCS_SHIFT)
#define LPTMR_PSR_PCS_REF_INT (0 << LPTMR_PSR_PCS_SHIFT) /* Internal reference clock */
#define LPTMR_PSR_PCS_LPO (1 << LPTMR_PSR_PCS_SHIFT) /* LPO 1K Hz */
#define LPTMR_PSR_PCS_RTC (2 << LPTMR_PSR_PCS_SHIFT) /* RTC 32768 Hz */
#define LPTMR_PSR_PCS_REF_EXT (3 << LPTMR_PSR_PCS_SHIFT) /* External reference clock */
# define LPTMR_PSR_PCS_SOSC LPTMR_PSR_PCS_RFOSC
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPTMR_H_ */
arch/arm/src/imx9/hardware/imx9_lpuart.h
+316
View File
@@ -0,0 +1,316 @@
/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_lpuart.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPUART_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPUART_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <hardware/imx9_memorymap.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* LPUART Register Offsets **************************************************/
#define IMX9_LPUART_VERID_OFFSET (0x00) /* Version ID Register (VERID) */
#define IMX9_LPUART_PARAM_OFFSET (0x04) /* Parameter Register (PARAM) */
#define IMX9_LPUART_GLOBAL_OFFSET (0x08) /* LPUART Global Register (GLOBAL) */
#define IMX9_LPUART_PINCFG_OFFSET (0x0c) /* LPUART Pin Configuration Register (PINCFG) */
#define IMX9_LPUART_BAUD_OFFSET (0x10) /* LPUART Baud Rate Register (BAUD) */
#define IMX9_LPUART_STAT_OFFSET (0x14) /* LPUART Status Register (STAT) */
#define IMX9_LPUART_CTRL_OFFSET (0x18) /* LPUART Control Register (CTRL) */
#define IMX9_LPUART_DATA_OFFSET (0x1c) /* LPUART Data Register (DATA) */
#define IMX9_LPUART_MATCH_OFFSET (0x20) /* LPUART Match Address Register (MATCH) */
#define IMX9_LPUART_MODIR_OFFSET (0x24) /* LPUART Modem IrDA Register (MODIR) */
#define IMX9_LPUART_FIFO_OFFSET (0x28) /* LPUART FIFO Register (FIFO) */
#define IMX9_LPUART_WATER_OFFSET (0x2c) /* LPUART Watermark Register (WATER) */
#define IMX9_LPUART_DATARO_OFFSET (0x30) /* Data read-only Register (DATARO) */
/* Register bit definitions *************************************************/
/* Version ID Register (VERID) */
#define LPUART_VERID_FEATURE_SHIFT (0) /* Bits 0-15: Feature Identification Number (FEATURE) */
#define LPUART_VERID_FEATURE_MASK (0xffff << LPUART_VERID_FEATURE_SHIFT)
# define LPUART_VERID_FEATURE_STD (1 << LPUART_VERID_FEATURE_SHIFT) /* Standard feature set */
# define LPUART_VERID_FEATURE_MODEM (3 << LPUART_VERID_FEATURE_SHIFT) /* MODEM/IrDA support */
#define LPUART_VERID_MINOR_SHIFT (16) /* Bits 16-23: Minor Version Number (MINOR) */
#define LPUART_VERID_MINOR_MASK (0xff << LPUART_VERID_MINOR_SHIFT)
#define LPUART_VERID_MAJOR_SHIFT (24) /* Bits 24-31: Major Version Number (MAJOR) */
#define LPUART_VERID_MAJOR_MASK (0xff << LPUART_VERID_MAJOR_SHIFT)
/* Parameter Register (PARAM) */
#define LPUART_PARAM_TXFIFO_SHIFT (0) /* Bits 0-7: Transmit FIFO Size (TXFIFO) */
#define LPUART_PARAM_TXFIFO_MASK (0xff << LPUART_PARAM_TXFIFO_SHIFT)
#define LPUART_PARAM_RXFIFO_SHIFT (8) /* Bits 8-15: Receive FIFO Size (RXFIFO) */
#define LPUART_PARAM_RXFIFO_MASK (0xff << LPUART_PARAM_RXFIFO_SHIFT)
/* Bits 16-31: Reserved */
/* LPUART Global Register (GLOBAL) */
/* Bit 0: Reserved */
#define LPUART_GLOBAL_RST (1 << 1) /* Bit 1: Software Reset (RST) */
/* Bits 2-31: Reserved */
/* LPUART Pin Configuration Register (PINCFG) */
#define LPUART_PINCFG_TRGSEL_SHIFT (0) /* Bits 0-1: Trigger Select (TRGSEL) */
#define LPUART_PINCFG_TRGSEL_MASK (0x03 << LPUART_PINCFG_TRGSEL_SHIFT)
# define LPUART_PINCFG_TRGSEL_DISABLE (0 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger disabled */
# define LPUART_PINCFG_TRGSEL_RXD (1 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of RXD pin */
# define LPUART_PINCFG_TRGSEL_CTSB (2 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used instead of CTS_B pin */
# define LPUART_PINCFG_TRGSEL_TXDMOD (3 << LPUART_PINCFG_TRGSEL_SHIFT) /* Trigger used to modulate the TXD output */
/* Bits 2-31: Reserved */
/* LPUART Baud Rate Register (BAUD) */
#define LPUART_BAUD_SBR_SHIFT (0) /* Bits 0-12: Baud Rate Modulo Divisor (SBR) */
#define LPUART_BAUD_SBR_MASK (0x1fff << LPUART_BAUD_SBR_SHIFT)
# define LPUART_BAUD_SBR(n) ((n) << LPUART_BAUD_SBR_SHIFT)
#define LPUART_BAUD_SBNS (1 << 13) /* Bit 13: Stop Bit Number Select (SBNS) */
#define LPUART_BAUD_RXEDGIE (1 << 14) /* Bit 14: RX Input Active Edge Interrupt Enable (RXEDGIE) */
#define LPUART_BAUD_LBKDIE (1 << 15) /* Bit 15: LIN Break Detect Interrupt Enable (LBKDIE) */
#define LPUART_BAUD_RESYNCDIS (1 << 16) /* Bit 16: Resynchronization Disable (RESYNCDIS) */
#define LPUART_BAUD_BOTHEDGE (1 << 17) /* Bit 17: Both Edge Sampling (BOTHEDGE) */
#define LPUART_BAUD_MATCFG_SHIFT (18) /* Bits 18-19: Match Configuration (MATCFG) */
#define LPUART_BAUD_MATCFG_MASK (0x03 << LPUART_BAUD_MATCFG_SHIFT)
# define LPUART_BAUD_MATCFG_ADDR (0 << LPUART_BAUD_MATCFG_SHIFT) /* Address Match Wakeup */
# define LPUART_BAUD_MATCFG_IDLE (1 << LPUART_BAUD_MATCFG_SHIFT) /* Idle Match Wakeup */
# define LPUART_BAUD_MATCFG_ONOFF (2 << LPUART_BAUD_MATCFG_SHIFT) /* Match On and Match Off */
# define LPUART_BAUD_MATCFG_RWUENAB (3 << LPUART_BAUD_MATCFG_SHIFT) /* Enables RWU on Data Match and Match On/Off for transmitter CTS input */
/* Bit 20: Reserved */
#define LPUART_BAUD_RDMAE (1 << 21) /* Bit 21: Receiver Full DMA Enable (RDMAE) */
/* Bit 22: Reserved */
#define LPUART_BAUD_TDMAE (1 << 23) /* Bit 23: Transmitter DMA Enable (TDMAE) */
#define LPUART_BAUD_OSR_SHIFT (24) /* Bits 24-29: Oversampling Ratio (OSR) */
#define LPUART_BAUD_OSR_MASK (0x1f << LPUART_BAUD_OSR_SHIFT)
# define LPUART_BAUD_OSR(n) (((n) - 1) << LPUART_BAUD_OSR_SHIFT) /* n=4..32 */
#define LPUART_BAUD_M10 (1 << 29) /* Bit 29: 10-bit Mode Select (M10) */
#define LPUART_BAUD_MAEN2 (1 << 30) /* Bit 30: Match Address Mode Enable 2 (MAEN2) */
#define LPUART_BAUD_MAEN1 (1 << 31) /* Bit 31: Match Address Mode Enable 1 (MAEN1) */
/* LPUART Status Register (STAT) */
#define LPUART_STAT_LBKFE (1 << 0) /* Bit 0: LIN Break Flag Enable (LBKFE) */
#define LPUART_STAT_AME (1 << 1) /* Bit 1: Address Mark Enable (AME) */
/* Bits 2-13: Reserved */
#define LPUART_STAT_MA2F (1 << 14) /* Bit 14: Match 2 Flag (MA2F) */
#define LPUART_STAT_MA1F (1 << 15) /* Bit 15: Match 1 Flag (MA1F) */
#define LPUART_STAT_PF (1 << 16) /* Bit 16: Parity Error Flag (PF) */
#define LPUART_STAT_FE (1 << 17) /* Bit 17: Framing Error Flag (FE) */
#define LPUART_STAT_NF (1 << 18) /* Bit 18: Noise Flag (NF) */
#define LPUART_STAT_OR (1 << 19) /* Bit 19: Receiver Overrun Flag (OR) */
#define LPUART_STAT_IDLE (1 << 20) /* Bit 20: Idle Line Flag (IDLE) */
#define LPUART_STAT_RDRF (1 << 21) /* Bit 21: Receive Data Register Full Flag (RDRF) */
#define LPUART_STAT_TC (1 << 22) /* Bit 22: Transmission Complete Flag (TC) */
#define LPUART_STAT_TDRE (1 << 23) /* Bit 23: Transmit Data Register Empty Flag (TDRE) */
#define LPUART_STAT_RAF (1 << 24) /* Bit 24: Receiver Active Flag (RAF) */
#define LPUART_STAT_LBKDE (1 << 25) /* Bit 25: LIN Break Detection Enable (LBKDE) */
#define LPUART_STAT_BRK13 (1 << 26) /* Bit 26: Break Character Generation Length (BRK13) */
#define LPUART_STAT_RWUID (1 << 27) /* Bit 27: Receive Wake Up Idle Detect (RWUID) */
#define LPUART_STAT_RXINV (1 << 28) /* Bit 28: Receive Data Inversion (RXINV) */
#define LPUART_STAT_MSBF (1 << 29) /* Bit 29: MSB First (MSBF) */
#define LPUART_STAT_RXEDGIF (1 << 30) /* Bit 30: RXD Pin Active Edge Interrupt Flag (RXEDGIF) */
#define LPUART_STAT_LBKDIF (1 << 31) /* Bit 31: LIN Break Detect Interrupt Flag (LBKDIF) */
/* LPUART Control Register (CTRL) */
#define LPUART_CTRL_PT (1 << 0) /* Bit 0: Parity Type */
# define LPUART_CTRL_PT_EVEN (0 << 0) /* Even parity */
# define LPUART_CTRL_PT_ODD (1 << 0) /* Odd parity */
#define LPUART_CTRL_PE (1 << 1) /* Bit 1: Parity Enable */
#define LPUART_CTRL_ILT (1 << 2) /* Bit 2: Idle Line Type Select */
#define LPUART_CTRL_WAKE (1 << 3) /* Bit 3: Receiver Wakeup Method Select */
#define LPUART_CTRL_M (1 << 4) /* Bit 4: 9-Bit or 8-Bit Mode Select */
#define LPUART_CTRL_RSRC (1 << 5) /* Bit 5: Receiver Source Select */
#define LPUART_CTRL_DOZEEN (1 << 6) /* Bit 6: Doze Enable */
#define LPUART_CTRL_LOOPS (1 << 7) /* Bit 7: Loop Mode Select */
#define LPUART_CTRL_IDLECFG_SHIFT (8) /* Bits 8-10: Idle Configuration */
#define LPUART_CTRL_IDLECFG_MASK (0x07 << LPUART_CTRL_IDLECFG_SHIFT)
# define LPUART_CTRL_IDLECFG_1 (0 << LPUART_CTRL_IDLECFG_SHIFT) /* 1 idle character */
# define LPUART_CTRL_IDLECFG_2 (1 << LPUART_CTRL_IDLECFG_SHIFT) /* 2 idle characters */
# define LPUART_CTRL_IDLECFG_4 (2 << LPUART_CTRL_IDLECFG_SHIFT) /* 4 idle characters */
# define LPUART_CTRL_IDLECFG_8 (3 << LPUART_CTRL_IDLECFG_SHIFT) /* 8 idle characters */
# define LPUART_CTRL_IDLECFG_16 (4 << LPUART_CTRL_IDLECFG_SHIFT) /* 6 idle characters */
# define LPUART_CTRL_IDLECFG_32 (5 << LPUART_CTRL_IDLECFG_SHIFT) /* 32 idle characters */
# define LPUART_CTRL_IDLECFG_64 (6 << LPUART_CTRL_IDLECFG_SHIFT) /* 64 idle characters */
# define LPUART_CTRL_IDLECFG_128 (7 << LPUART_CTRL_IDLECFG_SHIFT) /* 128 idle characters */
#define LPUART_CTRL_M7 (1 << 11) /* Bit 11: 7-Bit Mode Select (M7) */
/* Bits 12-13: Reserved */
#define LPUART_CTRL_MA2IE (1 << 14) /* Bit 14: Match 2 Interrupt Enable (MA2IE) */
#define LPUART_CTRL_MA1IE (1 << 15) /* Bit 15: Match 1 Interrupt Enable (MA1IE) */
#define LPUART_CTRL_SBK (1 << 16) /* Bit 16: Send Break (SBK) */
#define LPUART_CTRL_RWU (1 << 17) /* Bit 17: Receiver Wakeup Control (RWU) */
#define LPUART_CTRL_RE (1 << 18) /* Bit 18: Receiver Enable (RE) */
#define LPUART_CTRL_TE (1 << 19) /* Bit 19: Transmitter Enable (TE) */
#define LPUART_CTRL_ILIE (1 << 20) /* Bit 20: Idle Line Interrupt Enable (ILIE) */
#define LPUART_CTRL_RIE (1 << 21) /* Bit 21: Receiver Interrupt Enable (RIE) */
#define LPUART_CTRL_TCIE (1 << 22) /* Bit 22: Transmission Complete Interrupt Enable (TCIE) */
#define LPUART_CTRL_TIE (1 << 23) /* Bit 23: Transmit Interrupt Enable (TIE) */
#define LPUART_CTRL_PEIE (1 << 24) /* Bit 24: Parity Error Interrupt Enable (PEIE) */
#define LPUART_CTRL_FEIE (1 << 25) /* Bit 25: Framing Error Interrupt Enable (FEIE) */
#define LPUART_CTRL_NEIE (1 << 26) /* Bit 26: Noise Error Interrupt Enable (NEIE) */
#define LPUART_CTRL_ORIE (1 << 27) /* Bit 27: Overrun Interrupt Enable (ORIE) */
#define LPUART_CTRL_TXINV (1 << 28) /* Bit 28: Transmit Data Inversion (TXINV) */
#define LPUART_CTRL_TXDIR (1 << 29) /* Bit 29: TXD Pin Direction in Single-Wire Mode (TXDIR) */
#define LPUART_CTRL_R9T8 (1 << 30) /* Bit 30: Receive Bit 9 / Transmit Bit 8 (R9T8) */
#define LPUART_CTRL_R8T9 (1 << 31) /* Bit 31: Receive Bit 8 / Transmit Bit 9 (R8T9) */
#define LPUART_ALL_INTS (LPUART_CTRL_ORIE | LPUART_CTRL_NEIE | LPUART_CTRL_FEIE | \
LPUART_CTRL_PEIE | LPUART_CTRL_TIE | LPUART_CTRL_TCIE | \
LPUART_CTRL_RIE | LPUART_CTRL_ILIE | LPUART_CTRL_MA1IE | \
LPUART_CTRL_MA2IE)
/* LPUART Data Register (DATA) */
#define LPUART_DATA_SHIFT (0) /* Bits 0-9: Data bits 0-9 (DATA)*/
#define LPUART_DATA_MASK (0x03ff << LPUART_DATA_SHIFT)
#define LPUART_DATA_LINBRK (1 << 10) /* Bit 10: LIN Break (LINBRK) */
#define LPUART_DATA_STATUS_SHIFT (11) /* Bits 11-15: Status */
#define LPUART_DATA_IDLINE (1 << 11) /* Bit 11: Idle Line (IDLINE) */
#define LPUART_DATA_RXEMPT (1 << 12) /* Bit 12: Receive Buffer Empty (RXEMPT) */
#define LPUART_DATA_FRETSC (1 << 13) /* Bit 13: Frame Error / Transmit Special Character (FRETSC) */
#define LPUART_DATA_PARITYE (1 << 14) /* Bit 14: Parity Error (PARITYE) */
#define LPUART_DATA_NOISY (1 << 15) /* Bit 15: Noisy Data Received (NOISY) */
/* Bits 16-31: Reserved */
/* LPUART Match Address Register (MATCH) */
#define LPUART_MATCH_MA1_SHIFT (0) /* Bits 0-9: Match Address 1 (MA1) */
#define LPUART_MATCH_MA1_MASK (0x03ff << LPUART_MATCH_MA1_SHIFT)
# define LPUART_MATCH_MA1(n) ((n) << LPUART_MATCH_MA1_SHIFT)
/* Bits 10-15: Reserved */
#define LPUART_MATCH_MA2_SHIFT (16) /* Bits 16-25: Match Address 2 (MA2) */
#define LPUART_MATCH_MA2_MASK (0x03ff << LPUART_MATCH_MA2_SHIFT)
# define LPUART_MATCH_MA2(n) ((n) << LPUART_MATCH_MA2_SHIFT)
/* Bits 26-31: Reserved */
/* LPUART Modem IrDA Register (MODIR) */
#define LPUART_MODIR_TXCTSE (1 << 0) /* Bit 0: Transmitter clear-to-send enable (TXCTSE) */
#define LPUART_MODIR_TXRTSE (1 << 1) /* Bit 1: Transmitter request-to-send enable (TXRTSE) */
#define LPUART_MODIR_TXRTSPOL (1 << 2) /* Bit 2: Transmitter request-to-send polarity (TXRTSPOL) */
#define LPUART_MODIR_RXRTSE (1 << 3) /* Bit 3: Receiver request-to-send enable (RXRTSE) */
#define LPUART_MODIR_TXCTSC (1 << 4) /* Bit 4: Transmit CTS Configuration (TXCTSC) */
# define LPUART_MODIR_TXCTSC_START (0 << 4) /* CTS sampled at start of character */
# define LPUART_MODIR_TXCTSC_IDLE (1 << 4) /* CTS sampled when transmitter idle */
#define LPUART_MODIR_TXCTSSRC (1 << 5) /* Bit 5: Transmit CTS Source (TXCTSSRC) */
# define LPUART_MODIR_TXCTSSRC_CTSB (0 << 5) /* CTS input is CTS_B pin */
# define LPUART_MODIR_TXCTSSRC_RXMAT (1 << 5) /* CTS input is receiver address match result */
/* Bits 6-7: Reserved */
#define LPUART_MODIR_RTSWATER_SHIFT (8) /* Bits 8-9: Receive RTS Configuration (RTSWATER) */
#define LPUART_MODIR_RTSWATER_MASK (0x03 << LPUART_MODIR_RTSWATER_SHIFT)
# define LPUART_MODIR_RTSWATER(n) ((n) << LPUART_MODIR_RTSWATER_SHIFT)
/* Bits 10-15: Reserved */
#define LPUART_MODIR_TNP_SHIFT (16) /* Bits 16-17: Transmitter narrow pulse (TNP) */
#define LPUART_MODIR_TNP_MASK (0x03 << LPUART_MODIR_TNP_SHIFT)
# define LPUART_MODIR_TNP(n) (((n) - 1) << LPUART_MODIR_TNP_SHIFT) /* n/OSR */
#define LPUART_MODIR_IREN (1 << 18) /* Bit 18: Infrared enable (IREN) */
/* Bits 19-31: Reserved */
/* LPUART FIFO Register (FIFO) */
#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0) /* Bits 0-2: Receive FIFO Buffer Depth (RXFIFOSIZE) */
#define LPUART_FIFO_RXFIFOSIZE_MASK (0x07 << LPUART_FIFO_RXFIFOSIZE_SHIFT)
# define LPUART_FIFO_RXFIFOSIZE_1 (0 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 1 dataword */
# define LPUART_FIFO_RXFIFOSIZE_4 (1 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 4 datawords */
# define LPUART_FIFO_RXFIFOSIZE_8 (2 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 8 datawords */
# define LPUART_FIFO_RXFIFOSIZE_16 (3 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 16 datawords */
# define LPUART_FIFO_RXFIFOSIZE_32 (4 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 32 datawords */
# define LPUART_FIFO_RXFIFOSIZE_64 (5 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 64 datawords */
# define LPUART_FIFO_RXFIFOSIZE_128 (6 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 128 datawords */
# define LPUART_FIFO_RXFIFOSIZE_256 (7 << LPUART_FIFO_RXFIFOSIZE_SHIFT) /* 256 datawords */
#define LPUART_FIFO_RXFE (1 << 3) /* Bit 3: Receive FIFO Enable (RXFE) */
#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4) /* Bits 4-6: Transmit FIFO Buffer Depth (TXFIFOSIZE) */
#define LPUART_FIFO_TXFIFOSIZE_MASK (0x07 << LPUART_FIFO_TXFIFOSIZE_SHIFT)
# define LPUART_FIFO_TXFIFOSIZE_1 (0 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 1 dataword */
# define LPUART_FIFO_TXFIFOSIZE_4 (1 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 4 datawords */
# define LPUART_FIFO_TXFIFOSIZE_8 (2 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 8 datawords */
# define LPUART_FIFO_TXFIFOSIZE_16 (3 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 16 datawords */
# define LPUART_FIFO_TXFIFOSIZE_32 (4 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 32 datawords */
# define LPUART_FIFO_TXFIFOSIZE_64 (5 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 64 datawords */
# define LPUART_FIFO_TXFIFOSIZE_128 (6 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 128 datawords */
# define LPUART_FIFO_TXFIFOSIZE_256 (7 << LPUART_FIFO_TXFIFOSIZE_SHIFT) /* 256 datawords */
#define LPUART_FIFO_TXFE (1 << 7) /* Bit 7: Transmit FIFO Enable (TXFE) */
#define LPUART_FIFO_RXUFE (1 << 8) /* Bit 8: Receive FIFO Underflow Interrupt Enable (RXUFE) */
#define LPUART_FIFO_TXOFE (1 << 9) /* Bit 9: Transmit FIFO Overflow Interrupt Enable (TXOFE) */
#define LPUART_FIFO_RXIDEN_SHIFT (10) /* Bits 10-12: Receiver Idle Empty Enable (RXIDEN) */
#define LPUART_FIFO_RXIDEN_MASK (0x07 << LPUART_FIFO_RXIDEN_SHIFT)
# define LPUART_FIFO_RXIDEN_DISABLE (0 << LPUART_FIFO_RXIDEN_SHIFT) /* Disable RDRF assertion when receiver is idle */
# define LPUART_FIFO_RXIDEN_1 (1 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 1 character */
# define LPUART_FIFO_RXIDEN_2 (2 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 2 characters */
# define LPUART_FIFO_RXIDEN_4 (3 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 4 characters */
# define LPUART_FIFO_RXIDEN_8 (4 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 8 characters */
# define LPUART_FIFO_RXIDEN_16 (5 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 16 characters */
# define LPUART_FIFO_RXIDEN_32 (6 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 32 characters */
# define LPUART_FIFO_RXIDEN_64 (7 << LPUART_FIFO_RXIDEN_SHIFT) /* Enable RDRF assertion when receiver idle for 64 characters */
/* Bit 13: Reserved */
#define LPUART_FIFO_RXFLUSH (1 << 14) /* Bit 14: Receive FIFO Flush (RXFLUSH) */
#define LPUART_FIFO_TXFLUSH (1 << 15) /* Bit 15: Transmit FIFO Flush (TXFLUSH) */
#define LPUART_FIFO_RXUF (1 << 16) /* Bit 16: Receiver FIFO Underflow Flag (RXUF) */
#define LPUART_FIFO_TXOF (1 << 17) /* Bit 17: Transmitter FIFO Overflow Flag (TXOF) */
/* Bits 18-21: Reserved */
#define LPUART_FIFO_RXEMPT (1 << 22) /* Bit 22: Receive Buffer/FIFO Empty (RXEMPT) */
#define LPUART_FIFO_TXEMPT (1 << 23) /* Bit 23: Transmit Buffer/FIFO Empty (TXEMPT) */
/* Bits 24-31: Reserved */
/* LPUART Watermark Register (WATER) */
#define LPUART_WATER_TXWATER_SHIFT (0) /* Bits 0-3: Transmit Watermark (TXWATER) */
#define LPUART_WATER_TXWATER_MASK (0x0f << LPUART_WATER_TXWATER_SHIFT)
# define LPUART_WATER_TXWATER(n) ((n) << LPUART_WATER_TXWATER_SHIFT)
/* Bits 4-7: Reserved */
#define LPUART_WATER_TXCOUNT_SHIFT (8) /* Bits 8-12: Transmit Counter (TXCOUNT) */
#define LPUART_WATER_TXCOUNT_MASK (0x1f << LPUART_WATER_TXCOUNT_SHIFT)
# define LPUART_WATER_TXCOUNT(n) ((n) << LPUART_WATER_TXCOUNT_SHIFT)
/* Bits 13-15: Reserved */
#define LPUART_WATER_RXWATER_SHIFT (16) /* Bits 16-19: Receive Watermark (RXWATER) */
#define LPUART_WATER_RXWATER_MASK (0x0f << LPUART_WATER_RXWATER_SHIFT)
# define LPUART_WATER_RXWATER(n) ((n) << LPUART_WATER_RXWATER_SHIFT)
/* Bits 20-23: Reserved */
#define LPUART_WATER_RXCOUNT_SHIFT (24) /* Bits 24-28: Receive Counter (RXCOUNT) */
#define LPUART_WATER_RXCOUNT_MASK (0x1f << LPUART_WATER_RXCOUNT_SHIFT)
# define LPUART_WATER_RXCOUNT(n) ((n) << LPUART_WATER_RXCOUNT_SHIFT)
/* Bits 29-31: Reserved */
/* Data read-only Register (DATARO) */
#define LPUART_DATARO_DATA_SHIFT (0) /* Bits 0-15: Receive Data (DATA) */
#define LPUART_DATARO_DATA_MASK (0xffff << LPUART_DATARO_DATA_SHIFT)
/* Bits 16-31: Reserved */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_LPUART_H */
arch/arm/src/imx9/hardware/imx9_memorymap.h
+39
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_memorymap.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_memorymap.h"
#else
# error Unrecognized i.MX9 architecture
#endif
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_MEMORYMAP_H */
arch/arm/src/imx9/hardware/imx9_mu.h
+257
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_mu.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets */
#define IMX9_MU_VER_OFFSET 0x0000 /* Version ID */
#define IMX9_MU_PAR_OFFSET 0x0004 /* Parameter */
#define IMX9_MU_CR_OFFSET 0x0008 /* Control */
#define IMX9_MU_SR_OFFSET 0x000c /* Status */
#define IMX9_MU_FCR_OFFSET 0x0100 /* Flag Control */
#define IMX9_MU_FSR_OFFSET 0x0104 /* Flag Status */
#define IMX9_MU_GIER_OFFSET 0x0110 /* General-Purpose Interrupt Enable */
#define IMX9_MU_GCR_OFFSET 0x0114 /* General-Purpose Control */
#define IMX9_MU_GSR_OFFSET 0x0118 /* General-purpose Status */
#define IMX9_MU_TCR_OFFSET 0x0120 /* Transmit Control */
#define IMX9_MU_TSR_OFFSET 0x0124 /* Transmit Status */
#define IMX9_MU_RCR_OFFSET 0x0128 /* Receive Control */
#define IMX9_MU_RSR_OFFSET 0x012c /* Receive Status */
#define IMX9_MU_TR1_OFFSET 0x0200 /* Transmit */
#define IMX9_MU_TR2_OFFSET 0x0200 /* Transmit */
#define IMX9_MU_TR3_OFFSET 0x0200 /* Transmit */
#define IMX9_MU_TR4_OFFSET 0x0200 /* Transmit */
#define IMX9_MU_RR1_OFFSET 0x0280 /* Receive */
#define IMX9_MU_RR2_OFFSET 0x0280 /* Receive */
#define IMX9_MU_RR3_OFFSET 0x0280 /* Receive */
#define IMX9_MU_RR4_OFFSET 0x0280 /* Receive */
/* Register macros */
#define IMX9_MU_VER(n) ((n) + IMX9_MU_VER_OFFSET) /* Version ID */
#define IMX9_MU_PAR(n) ((n) + IMX9_MU_PAR_OFFSET) /* Parameter */
#define IMX9_MU_CR(n) ((n) + IMX9_MU_CR_OFFSET) /* Control */
#define IMX9_MU_SR(n) ((n) + IMX9_MU_SR_OFFSET) /* Status */
#define IMX9_MU_FCR(n) ((n) + IMX9_MU_FCR_OFFSET) /* Flag Control */
#define IMX9_MU_FSR(n) ((n) + IMX9_MU_FSR_OFFSET) /* Flag Status */
#define IMX9_MU_GIER(n) ((n) + IMX9_MU_GIER_OFFSET) /* General-Purpose Interrupt Enable */
#define IMX9_MU_GCR(n) ((n) + IMX9_MU_GCR_OFFSET) /* General-Purpose Control */
#define IMX9_MU_GSR(n) ((n) + IMX9_MU_GSR_OFFSET) /* General-purpose Status */
#define IMX9_MU_TCR(n) ((n) + IMX9_MU_TCR_OFFSET) /* Transmit Control */
#define IMX9_MU_TSR(n) ((n) + IMX9_MU_TSR_OFFSET) /* Transmit Status */
#define IMX9_MU_RCR(n) ((n) + IMX9_MU_RCR_OFFSET) /* Receive Control */
#define IMX9_MU_RSR(n) ((n) + IMX9_MU_RSR_OFFSET) /* Receive Status */
#define IMX9_MU_TR1(n) ((n) + IMX9_MU_TR1_OFFSET) /* Transmit */
#define IMX9_MU_TR2(n) ((n) + IMX9_MU_TR2_OFFSET) /* Transmit */
#define IMX9_MU_TR3(n) ((n) + IMX9_MU_TR3_OFFSET) /* Transmit */
#define IMX9_MU_TR4(n) ((n) + IMX9_MU_TR4_OFFSET) /* Transmit */
#define IMX9_MU_RR1(n) ((n) + IMX9_MU_RR1_OFFSET) /* Receive */
#define IMX9_MU_RR2(n) ((n) + IMX9_MU_RR2_OFFSET) /* Receive */
#define IMX9_MU_RR3(n) ((n) + IMX9_MU_RR3_OFFSET) /* Receive */
#define IMX9_MU_RR4(n) ((n) + IMX9_MU_RR4_OFFSET) /* Receive */
/* Field definitions */
/* VER register */
#define IMX9_MU_VER_FEATURE_SHIFT 0 /* Feature Set Number */
#define IMX9_MU_VER_FEATURE_MASK 0xffff /* Feature Set Number */
#define IMX9_MU_VER_MINOR_SHIFT 16 /* Minor Version Number */
#define IMX9_MU_VER_MINOR_MASK 0xff /* Minor Version Number */
#define IMX9_MU_VER_MAJOR_SHIFT 24 /* Major Version Number */
#define IMX9_MU_VER_MAJOR_MASK 0xff /* Major Version Number */
/* PAR register */
#define IMX9_MU_PAR_TR_NUM_SHIFT 0 /* Transmit Register Number */
#define IMX9_MU_PAR_TR_NUM_MASK 0xff /* Transmit Register Number */
#define IMX9_MU_PAR_RR_NUM_SHIFT 8 /* Receive Register Number */
#define IMX9_MU_PAR_RR_NUM_MASK 0xff /* Receive Register Number */
#define IMX9_MU_PAR_GIR_NUM_SHIFT 16 /* General-Purpose Interrupt Request Number */
#define IMX9_MU_PAR_GIR_NUM_MASK 0xff /* General-Purpose Interrupt Request Number */
#define IMX9_MU_PAR_FLAG_WIDTH_SHIFT 24 /* Flag Width */
#define IMX9_MU_PAR_FLAG_WIDTH_MASK 0xff /* Flag Width */
/* CR register */
#define IMX9_MU_CR_MUR_SHIFT 0 /* MU Reset */
#define IMX9_MU_CR_MUR_FLAG (1 << IMX9_MU_CR_MUR_SHIFT) /* MU Reset */
#define IMX9_MU_CR_MURIE_SHIFT 1 /* MUA Reset Interrupt Enable */
#define IMX9_MU_CR_MURIE_FLAG (1 << IMX9_MU_CR_MURIE_SHIFT) /* MUA Reset Interrupt Enable */
/* SR register */
#define IMX9_MU_SR_MURS_SHIFT 0 /* MUA and MUB Reset State */
#define IMX9_MU_SR_MURS_FLAG (1 << IMX9_MU_SR_MURS_SHIFT) /* MUA and MUB Reset State */
#define IMX9_MU_SR_MURIP_SHIFT 1 /* MU Reset Interrupt Pending Flag */
#define IMX9_MU_SR_MURIP_FLAG (1 << IMX9_MU_SR_MURIP_SHIFT) /* MU Reset Interrupt Pending Flag */
#define IMX9_MU_SR_EP_SHIFT 2 /* MUA Side Event Pending */
#define IMX9_MU_SR_EP_FLAG (1 << IMX9_MU_SR_EP_SHIFT) /* MUA Side Event Pending */
#define IMX9_MU_SR_FUP_SHIFT 3 /* MUA Flag Update Pending */
#define IMX9_MU_SR_FUP_FLAG (1 << IMX9_MU_SR_FUP_SHIFT) /* MUA Flag Update Pending */
#define IMX9_MU_SR_GIRP_SHIFT 4 /* MUA General-Purpose Interrupt Pending */
#define IMX9_MU_SR_GIRP_FLAG (1 << IMX9_MU_SR_GIRP_SHIFT) /* MUA General-Purpose Interrupt Pending */
#define IMX9_MU_SR_TEP_SHIFT 5 /* MUA Transmit Empty Pending */
#define IMX9_MU_SR_TEP_FLAG (1 << IMX9_MU_SR_TEP_SHIFT) /* MUA Transmit Empty Pending */
#define IMX9_MU_SR_RFP_SHIFT 6 /* MUA Receive Full Pending */
#define IMX9_MU_SR_RFP_FLAG (1 << IMX9_MU_SR_RFP_SHIFT) /* MUA Receive Full Pending */
/* FCR register */
#define IMX9_MU_FCR_F0_SHIFT 0 /* MUA to MUB Flag */
#define IMX9_MU_FCR_F0_FLAG (1 << IMX9_MU_FCR_F0_SHIFT) /* MUA to MUB Flag */
#define IMX9_MU_FCR_F1_SHIFT 1 /* MUA to MUB Flag */
#define IMX9_MU_FCR_F1_FLAG (1 << IMX9_MU_FCR_F1_SHIFT) /* MUA to MUB Flag */
#define IMX9_MU_FCR_F2_SHIFT 2 /* MUA to MUB Flag */
#define IMX9_MU_FCR_F2_FLAG (1 << IMX9_MU_FCR_F2_SHIFT) /* MUA to MUB Flag */
/* FSR register */
#define IMX9_MU_FSR_F0_SHIFT 0 /* MUB to MUA-Side Flag */
#define IMX9_MU_FSR_F0_FLAG (1 << IMX9_MU_FSR_F0_SHIFT) /* MUB to MUA-Side Flag */
#define IMX9_MU_FSR_F1_SHIFT 1 /* MUB to MUA-Side Flag */
#define IMX9_MU_FSR_F1_FLAG (1 << IMX9_MU_FSR_F1_SHIFT) /* MUB to MUA-Side Flag */
#define IMX9_MU_FSR_F2_SHIFT 2 /* MUB to MUA-Side Flag */
#define IMX9_MU_FSR_F2_FLAG (1 << IMX9_MU_FSR_F2_SHIFT) /* MUB to MUA-Side Flag */
/* GIER register */
#define IMX9_MU_GIER_GIE0_SHIFT 0 /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE0_FLAG (1 << IMX9_MU_GIER_GIE0_SHIFT) /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE1_SHIFT 1 /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE1_FLAG (1 << IMX9_MU_GIER_GIE1_SHIFT) /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE2_SHIFT 2 /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE2_FLAG (1 << IMX9_MU_GIER_GIE2_SHIFT) /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE3_SHIFT 3 /* MUA General-purpose Interrupt Enable */
#define IMX9_MU_GIER_GIE3_FLAG (1 << IMX9_MU_GIER_GIE3_SHIFT) /* MUA General-purpose Interrupt Enable */
/* GCR register */
#define IMX9_MU_GCR_GIR0_SHIFT 0 /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR0_FLAG (1 << IMX9_MU_GCR_GIR0_SHIFT) /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR1_SHIFT 1 /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR1_FLAG (1 << IMX9_MU_GCR_GIR1_SHIFT) /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR2_SHIFT 2 /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR2_FLAG (1 << IMX9_MU_GCR_GIR2_SHIFT) /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR3_SHIFT 3 /* MUA General-Purpose Interrupt Request */
#define IMX9_MU_GCR_GIR3_FLAG (1 << IMX9_MU_GCR_GIR3_SHIFT) /* MUA General-Purpose Interrupt Request */
/* GSR register */
#define IMX9_MU_GSR_GIP0_SHIFT 0 /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP0_FLAG (1 << IMX9_MU_GSR_GIP0_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP1_SHIFT 1 /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP1_FLAG (1 << IMX9_MU_GSR_GIP1_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP2_SHIFT 2 /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP2_FLAG (1 << IMX9_MU_GSR_GIP2_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP3_SHIFT 3 /* MUA General-Purpose Interrupt Request Pending */
#define IMX9_MU_GSR_GIP3_FLAG (1 << IMX9_MU_GSR_GIP3_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
/* TCR register */
#define IMX9_MU_TCR_TIE0_SHIFT 0 /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE0_FLAG (1 << IMX9_MU_TCR_TIE0_SHIFT) /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE1_SHIFT 1 /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE1_FLAG (1 << IMX9_MU_TCR_TIE1_SHIFT) /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE2_SHIFT 2 /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE2_FLAG (1 << IMX9_MU_TCR_TIE2_SHIFT) /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE3_SHIFT 3 /* MUA Transmit Interrupt Enable */
#define IMX9_MU_TCR_TIE3_FLAG (1 << IMX9_MU_TCR_TIE3_SHIFT) /* MUA Transmit Interrupt Enable */
/* TSR register */
#define IMX9_MU_TSR_TE0_SHIFT 0 /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE0_FLAG (1 << IMX9_MU_TSR_TE0_SHIFT) /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE1_SHIFT 1 /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE1_FLAG (1 << IMX9_MU_TSR_TE1_SHIFT) /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE2_SHIFT 2 /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE2_FLAG (1 << IMX9_MU_TSR_TE2_SHIFT) /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE3_SHIFT 3 /* MUA Transmit Empty */
#define IMX9_MU_TSR_TE3_FLAG (1 << IMX9_MU_TSR_TE3_SHIFT) /* MUA Transmit Empty */
/* RCR register */
#define IMX9_MU_RCR_RIE0_SHIFT 0 /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE0_FLAG (1 << IMX9_MU_RCR_RIE0_SHIFT) /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE1_SHIFT 1 /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE1_FLAG (1 << IMX9_MU_RCR_RIE1_SHIFT) /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE2_SHIFT 2 /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE2_FLAG (1 << IMX9_MU_RCR_RIE2_SHIFT) /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE3_SHIFT 3 /* MUA Receive Interrupt Enable */
#define IMX9_MU_RCR_RIE3_FLAG (1 << IMX9_MU_RCR_RIE3_SHIFT) /* MUA Receive Interrupt Enable */
/* RSR register */
#define IMX9_MU_RSR_RF0_SHIFT 0 /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF0_FLAG (1 << IMX9_MU_RSR_RF0_SHIFT) /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF1_SHIFT 1 /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF1_FLAG (1 << IMX9_MU_RSR_RF1_SHIFT) /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF2_SHIFT 2 /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF2_FLAG (1 << IMX9_MU_RSR_RF2_SHIFT) /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF3_SHIFT 3 /* MUA Receive Register Full */
#define IMX9_MU_RSR_RF3_FLAG (1 << IMX9_MU_RSR_RF3_SHIFT) /* MUA Receive Register Full */
/* Register array dimensions */
#define IMX9_MU_TR_REGARRAY_SIZE 4
#define IMX9_MU_RR_REGARRAY_SIZE 4
arch/arm/src/imx9/hardware/imx9_pinmux.h
+39
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@@ -0,0 +1,39 @@
/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_pinmux.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_PINMUX_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_PINMUX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#if defined(CONFIG_ARCH_CHIP_IMX95_M7)
# include "hardware/imx95/imx95_pinmux.h"
#else
# error Unrecognized i.MX9 architecture
#endif
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_PINMUX_H */
arch/arm/src/imx9/hardware/imx9_tpm.h
+216
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_tpm.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TPM_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TPM_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define IMX9_TPM_VERID_OFFSET 0x0000 /* Version ID */
#define IMX9_TPM_PARAM_OFFSET 0x0004 /* Parameter */
#define IMX9_TPM_GLOBAL_OFFSET 0x0008 /* TPM Global */
#define IMX9_TPM_SC_OFFSET 0x0010 /* Status and Control */
#define IMX9_TPM_CNT_OFFSET 0x0014 /* Counter */
#define IMX9_TPM_MOD_OFFSET 0x0018 /* Modulo */
#define IMX9_TPM_STATUS_OFFSET 0x001c /* Capture and Compare Status */
#define IMX9_TPM_CXSC_OFFSET(ch) (0x0020 + (ch) * 8) /* Channel Status and Control */
#define IMX9_TPM_CXV_OFFSET(ch) (0x0024 + (ch) * 8) /* Channel Value */
#define IMX9_TPM_C1SC_OFFSET 0x0028 /* Channel n Status and Control */
#define IMX9_TPM_C1V_OFFSET 0x002c /* Channel n Value */
#define IMX9_TPM_C2SC_OFFSET 0x0030 /* Channel n Status and Control */
#define IMX9_TPM_C2V_OFFSET 0x0034 /* Channel n Value */
#define IMX9_TPM_C3SC_OFFSET 0x0038 /* Channel n Status and Control */
#define IMX9_TPM_C3V_OFFSET 0x003c /* Channel n Value */
#define IMX9_TPM_COMBINE_OFFSET 0x0064 /* Combine Channel */
#define IMX9_TPM_TRIG_OFFSET 0x006c /* Channel Trigger */
#define IMX9_TPM_POL_OFFSET 0x0070 /* Channel Polarity */
#define IMX9_TPM_FILTER_OFFSET 0x0078 /* Filter Control */
#define IMX9_TPM_QDCTRL_OFFSET 0x0080 /* Quadrature Decoder Control and Status */
#define IMX9_TPM_CONF_OFFSET 0x0084 /* Configuration */
/* Register Bitfield Definitions ********************************************/
/* PARAM */
#define TPM_PARAM_WIDTH_SHIFT (16) /* Bit[23:16]: Width of the counter and timer channels */
#define TPM_PARAM_WIDTH_MASK (0xff << TPM_PARAM_WIDTH_SHIFT)
#define TPM_PARAM_TRIG_SHIFT (8) /* Bit[15:8]: Number of triggers that TPM implements */
#define TPM_PARAM_TRIG_MASK (0xff << LPIT_PARAM_TRIG_SHIFT)
#define TPM_PARAM_CHAN_SHIFT (0) /* Bit[7:0]: Number of timer channels */
#define TPM_PARAM_CHAN_MASK (0xff << TPM_PARAM_CHAN_SHIFT)
/* GLOBAL */
#define TPM_GLOBAL_RST_SHIFT (1) /* Bit[1]: Software Reset */
#define TPM_GLOBAL_RST_MASK (0x1 << TPM_GLOBAL_RST_SHIFT)
#define TPM_GLOBAL_NOUPDATE_SHIFT (0) /* Bit[0]: Block updates to internal registers */
#define TPM_GLOBAL_NOUPDATE_MASK (0x1 << TPM_GLOBAL_NOUPDATE_SHIFT)
/* SC */
#define TPM_SC_DMA_SHIFT (8) /* Bit[8]: DMA Enable */
#define TPM_SC_DMA_MASK (0x1 << TPM_SC_DMA_SHIFT)
#define TPM_SC_TOF_SHIFT (7) /* Bit[7]: Timer Overflow Flag */
#define TPM_SC_TOF_MASK (0x1 << TPM_SC_TOF_SHIFT)
#define TPM_SC_TOIE_SHIFT (6) /* Bit[6]: Timer Overflow Interrupt Enable */
#define TPM_SC_TOIE_MASK (0x1 << TPM_SC_TOIE_SHIFT)
#define TPM_SC_CPWMS_SHIFT (5) /* Bit[5]: Center-Aligned PWM Select */
#define TPM_SC_CPWMS_MASK (0x1 << TPM_SC_CPWMS_SHIFT)
#define TPM_SC_CMOD_SHIFT (3) /* Bit[4:3]: Clock Mode Selection */
#define TPM_SC_CMOD_MASK (0x3 << TPM_SC_CMOD_SHIFT)
#define TPM_SC_CMOD_VALUE_DISABLE 0
#define TPM_SC_CMOD_VALUE_COUNTER 1
#define TPM_SC_CMOD_VALUE_EXTCLK 2
#define TPM_SC_CMOD_VALUE_TRIG 3
#define TPM_SC_CMOD(n) ((n << TPM_SC_CMOD_SHIFT) & TPM_SC_CMOD_MASK)
#define TPM_SC_PS_SHIFT (0) /* Bit[2:0]: Prescale Factor Selection */
#define TPM_SC_PS_MASK (0x7 << TPM_SC_PS_SHIFT)
/* STATUS */
#define TPM_STATUS_TOF_SHIFT (8) /* Bit[8]: Timer Overflow Flag */
#define TPM_STATUS_TOF_MASK (0x1 << TPM_STATUS_TOF_SHIFT)
#define TPM_STATUS_CH3F_SHIFT (3) /* Bit[3]: Channel 3 Flag */
#define TPM_STATUS_CH3F_MASK (0x1 << TPM_STATUS_CH3F_SHIFT)
#define TPM_STATUS_CH2F_SHIFT (2) /* Bit[2]: Channel 2 Flag */
#define TPM_STATUS_CH2F_MASK (0x1 << TPM_STATUS_CH2F_SHIFT)
#define TPM_STATUS_CH1F_SHIFT (1) /* Bit[1]: Channel 1 Flag */
#define TPM_STATUS_CH1F_MASK (0x1 << TPM_STATUS_CH1F_SHIFT)
#define TPM_STATUS_CH0F_SHIFT (0) /* Bit[0]: Channel 0 Flag */
#define TPM_STATUS_CH0F_MASK (0x1 << TPM_STATUS_CH0F_SHIFT)
/* C0SC - C3SC */
#define TPM_CXSC_CHF_SHIFT (7) /* Bit[7]: Channel Flag */
#define TPM_CXSC_CHF_MASK (0x1 << TPM_CXSC_CHF_SHIFT)
#define TPM_CXSC_CHIE_SHIFT (6) /* Bit[6]: Channel Interrupt Enable */
#define TPM_CXSC_CHIE_MASK (0x1 << TPM_CXSC_CHIE_SHIFT)
#define TPM_CXSC_MSB_SHIFT (5) /* Bit[5]: Channel Mode Select B */
#define TPM_CXSC_MSB_MASK (0x1 << TPM_CXSC_MSB_SHIFT)
#define TPM_CXSC_MSA_SHIFT (4) /* Bit[4]: Channel Mode Select A */
#define TPM_CXSC_MSA_MASK (0x1 << TPM_CXSC_MSA_SHIFT)
#define TPM_CXSC_ELSB_SHIFT (3) /* Bit[3]: Edge or Level Select B */
#define TPM_CXSC_ELSB_MASK (0x1 << TPM_CXSC_ELSB_SHIFT)
#define TPM_CXSC_ELSA_SHIFT (2) /* Bit[2]: Edge or Level Select A */
#define TPM_CXSC_ELSA_MASK (0x1 << TPM_CXSC_ELSA_SHIFT)
#define TPM_CXSC_DMA_SHIFT (0) /* Bit[0]: DMA Enable */
#define TPM_CXSC_DMA_MASK (0x1 << TPM_CXSC_DMA_SHIFT)
/* COMBINE */
#define TPM_COMBINE_COMSWAP1_SHIFT (9) /* Bit[9]: Combine Channels 2 and 3 Swap */
#define TPM_COMBINE_COMSWAP1_MASK (0x1 << TPM_COMBINE_COMSWAP1_SHIFT)
#define TPM_COMBINE_COMBINE1_SHIFT (8) /* Bit[8]: Combine Channels 2 and 3 */
#define TPM_COMBINE_COMBINE1_MASK (0x1 << TPM_COMBINE_COMBINE1_SHIFT)
#define TPM_COMBINE_COMSWAP0_SHIFT (1) /* Bit[1]: Combine Channel 0 and 1 Swap */
#define TPM_COMBINE_COMSWAP0_MASK (0x1 << TPM_COMBINE_COMSWAP0_SHIFT)
#define TPM_COMBINE_COMBINE0_SHIFT (0) /* Bit[0]: Combine Channels 0 and 1 */
#define TPM_COMBINE_COMBINE0_MASK (0x1 << TPM_COMBINE_COMBINE0_SHIFT)
/* TRIG */
#define TPM_TRIG_TRIGX_MASK(ch) (0x1 << (ch)) /* Channel trigger configure */
/* POL */
#define TPM_POL_POLX_MASK(ch) (0x1 < (ch)) /* Channel polarity active low */
/* FILTER */
#define TPM_FILTER_CHXFVAL_SHIFT(ch) ((ch) * 4) /* Channel filter value */
#define TPM_FILTER_CHXFVAL_MASK(ch) (0xf << TPM_FILTER_CHXFVAL_SHIFT(ch))
/* QDCTRL */
#define TPM_QDCTRL_QUADMODE_SHIFT (3) /* Bit[3]: Quadrature Decoder Mode */
#define TPM_QDCTRL_QUADMODE_MASK (0x1 << TPM_QDCTRL_QUADMODE_SHIFT)
#define TPM_QDCTRL_QUADIR_SHIFT (2) /* Bit[2]: Counter Direction */
#define TPM_QDCTRL_QUADIR_MASK (0x1 << TPM_QDCTRL_QUADIR_SHIFT)
#define TPM_QDCTRL_TOFDIR_SHIFT (1) /* Bit[1]: Timer Overflow Direction */
#define TPM_QDCTRL_TOFDIR_MASK (0x1 << TPM_QDCTRL_TOFDIR_SHIFT)
#define TPM_QDCTRL_QUADEN_SHIFT (0) /* Bit[0]: Quadrature Decoder Enable */
#define TPM_QDCTRL_QUADEN_MASK (0x1 << TPM_QDCTRL_QUADEN_SHIFT)
/* CONF */
#define TPM_CONF_TRGSEL_SHIFT (24) /* Bit[25:24]: Trigger Select */
#define TPM_CONF_TRGSEL_MASK (0x3 << TPM_CONF_TRGSEL_SHIFT)
#define TPM_CONF_TRGSRC_SHIFT (23) /* Bit[23]: Trigger Source select */
#define TPM_CONF_TRGSRC_MASK (0x1 << TPM_CONF_TRGSRC_SHIFT)
#define TPM_CONF_TRGPOL_SHIFT (22) /* Bit[22]: Trigger Polarity */
#define TPM_CONF_TRGPOL_MASK (0x1 << TPM_CONF_TRGPOL_SHIFT)
#define TPM_CONF_CPOT_SHIFT (19) /* Bit[19]: Counter Pause on Trigger */
#define TPM_CONF_CPOT_MASK (0x1 << TPM_CONF_CPOT_SHIFT)
#define TPM_CONF_CROT_SHIFT (18) /* Bit[18]: Counter Reload on Trigger */
#define TPM_CONF_CROT_MASK (0x1 << TPM_CONF_CROT_SHIFT)
#define TPM_CONF_CSOO_SHIFT (17) /* Bit[17]: Counter Stop on Overflow */
#define TPM_CONF_CSOO_MASK (0x1 << TPM_CONF_CSOO_SHIFT)
#define TPM_CONF_CSOT_SHIFT (16) /* Bit[16]: Counter Start on Trigger */
#define TPM_CONF_CSOT_MASK (0x1 << TPM_CONF_CSOT_SHIFT)
#define TPM_CONF_DBGMODE_SHIFT (6) /* Bit[7:6]: Debug Mode */
#define TPM_CONF_DBGMODE_MASK (0x3 << TPM_CONF_DBGMODE_SHIFT)
#define TPM_CONF_DOZEEN_SHIFT (5) /* Bit[5]: Doze Enable */
#define TPM_CONF_DOZEEN_MASK (0x1 << TPM_CONF_DOZEEN_SHIFT)
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TPM_H */
arch/arm/src/imx9/hardware/imx9_tstmr.h
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/****************************************************************************
* arch/arm/src/imx9/hardware/imx9_tstmr.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TSTMR_H
#define __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TSTMR_H
/****************************************************************************
* Included Files
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register offsets */
#define IMX9_TSTMR_LOW_OFFSET 0x0000 /* Timestamp Timer Low */
#define IMX9_TSTMR_HIGH_OFFSET 0x0004 /* Timestamp Timer High */
/* Register macros */
#define IMX9_TSTMR_LOW(n) ((n) + IMX9_TSTMR_LOW_OFFSET) /* Timestamp Timer Low */
#define IMX9_TSTMR_HIGH(n) ((n) + IMX9_TSTMR_HIGH_OFFSET) /* Timestamp Timer High */
/* Field definitions */
/* HIGH register */
#define IMX9_TSTMR_HIGH_VALUE_SHIFT 0 /* Timestamp Timer High */
#define IMX9_TSTMR_HIGH_VALUE_MASK 0xffffff /* Timestamp Timer High */
#endif /* __ARCH_ARM_SRC_IMX9_HARDWARE_IMX9_TSTMR_H */
arch/arm/src/imx9/imx9_allocateheap.c
+314
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/****************************************************************************
* arch/arm/src/imx9/imx9_allocateheap.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <assert.h>
#include <debug.h>
#include <stdint.h>
#include <sys/types.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/kmalloc.h>
#include <nuttx/userspace.h>
#include <arch/imx9/chip.h>
#include "arm_internal.h"
#include "hardware/imx9_memorymap.h"
#include "imx9_mpuinit.h"
#include "mpu.h"
#include <arch/board/board.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Primary RAM: The Linker script positions the system BLOB's .data and
* .bss in some RAM. We refer to that RAM as the primary RAM. It also
* holds the IDLE threads stack and any remaining portion of the primary
* OCRAM is automatically added to the heap. The linker provided address,
* ... .sbss, .ebss, .sdat, etc. ... are expected to lie in the the region
* defined by the OCRAM configuration settings.
*
* Other RAM regions must be selected use configuration options and the
* start and end of those RAM regions must also be provided in the
* configuration. CONFIG_MM_REGIONS must also be set to determined the
* number of regions to be added to the heap.
*
*
* IMX9_ITCM_BASE 0x00000000 256KB M7 ITCM
* IMX9_DTCM_BASE 0x20000000 256KB M7 DTCM
* IMX9_OCRAM_BASE 0x20480000 352KB OCRAM
*/
/* There there then several memory configurations with a one primary memory
* region and up to two additional memory regions which may be OCRAM, DTCM
* external DDR.
*/
#undef IMX9_OCRAM_ASSIGNED
#undef IMX9_DCTM_ASSIGNED
#define _IMX9_OCRAM_BASE IMX9_OCRAM_BASE
/* See linker script */
extern const uint32_t _ram_start[];
extern const uint32_t _ram_size[];
extern const uint32_t _ocram_start[];
extern const uint32_t _ocram_size[];
/* by default DTCM size is 256k
* Can be configured by AON__BLK_CTRL_Secure_AON.M7_CFG (0x444f0124)
*/
#define PRIMARY_RAM_START (uint32_t) _ram_start
#define PRIMARY_RAM_SIZE (uint32_t) _ram_size
#define PRIMARY_RAM_END ((uint32_t)_ram_start + (uint32_t)_ram_size)
#define OCRAM_START (uint32_t) _ocram_start
#define OCRAM_SIZE (uint32_t) _ocram_size
#if CONFIG_MM_REGIONS > 1
/* Pick the first region to add to the heap could be any one of OCRAM, DTCM,
* SDRAM, or SRAM depending upon which are enabled and which has not
* already been assigned as the primary RAM.
*/
#if defined(CONFIG_IMX9_OCRAM_HEAP) && !defined(IMX9_OCRAM_ASSIGNED)
#define REGION1_RAM_START OCRAM_START
#define REGION1_RAM_SIZE OCRAM_SIZE
#define IMX9_OCRAM_ASSIGNED 1
#else
#warning CONFIG_MM_REGIONS > 1 but no available memory region
#endif
#define REGION1_RAM_END (REGION1_RAM_START + REGION1_RAM_SIZE)
#endif
#if CONFIG_MM_REGIONS > 2
#warning CONFIG_MM_REGIONS > 2 but no available memory region
#endif
#if CONFIG_MM_REGIONS > 3
#warning CONFIG_MM_REGIONS > 3 but no available memory region
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* _sbss is the start of the BSS region (see the linker script) _ebss is the
* end of the BSS regions (see the linker script). The idle task stack starts
* at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE. The IDLE
* thread is the thread that the system boots on and, eventually, becomes the
* idle, do nothing task that runs only when there is nothing else to run.
* The heap continues from there until the configured end of memory.
* g_idle_topstack is the beginning of this heap region (not necessarily
* aligned).
*/
const uintptr_t g_idle_topstack
= (uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE;
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap/up_allocate_kheap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* - For the normal "flat" build, this function returns the size of the
* single heap.
* - For the protected build (CONFIG_BUILD_PROTECTED=y) with both kernel-
* and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function
* provides the size of the unprotected, user-space heap.
* - For the kernel build (CONFIG_BUILD_KERNEL=y), this function provides
* the size of the protected, kernel-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated by an analogous up_allocate_kheap(). A custom version of this
* file is needed if memory protection of the kernel heap is required.
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region. Size determined at link time.
* Kernel .bss region Size determined at link time.
* Kernel IDLE thread stack. (size determined by
* CONFIG_IDLETHREAD_STACKSIZE).
* Padding for alignment
* User .data region. Size determined at link time.
* User .bss region Size determined at link time.
* Kernel heap. Size determined by CONFIG_MM_KERNEL_HEAPSIZE.
* User heap. Extends to the end of SRAM.
*
****************************************************************************/
#ifdef CONFIG_BUILD_KERNEL
void up_allocate_kheap(void **heap_start, size_t *heap_size)
#else
void up_allocate_heap(void **heap_start, size_t *heap_size)
#endif
{
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase
= (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = PRIMARY_RAM_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the PRIMARY_RAM_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
DEBUGASSERT((PRIMARY_RAM_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = PRIMARY_RAM_END - usize;
/* Return the user-space heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)ubase;
*heap_size = usize;
/* Allow user-mode access to the user heap memory */
imx9_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)g_idle_topstack;
*heap_size = PRIMARY_RAM_END - g_idle_topstack;
#endif
}
/****************************************************************************
* Name: up_allocate_kheap
*
* Description:
* For the kernel build (CONFIG_BUILD_PROTECTED/KERNEL=y) with both kernel-
* and user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
* the kernel-space heap. A custom version of this function is needed if
* memory protection of the kernel heap is required.
*
****************************************************************************/
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
void up_allocate_kheap(void **heap_start, size_t *heap_size)
{
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase
= (uintptr_t)USERSPACE->us_bssend + CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = PRIMARY_RAM_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)PRIMARY_RAM_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the CONFIG_RAM_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
DEBUGASSERT((PRIMARY_RAM_END & ((1 << log2) - 1)) == 0);
usize = (1 << log2);
ubase = PRIMARY_RAM_END - usize;
/* Return the kernel heap settings (i.e., the part of the heap region
* that was not dedicated to the user heap).
*/
*heap_start = (void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif
/****************************************************************************
* Name: arm_addregion
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
/* Add region 1 to the user heap */
kumm_addregion((void *)REGION1_RAM_START, REGION1_RAM_SIZE);
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to region 1 */
imx9_mpu_uheap((uintptr_t)REGION1_RAM_START, REGION1_RAM_SIZE);
#endif
#if CONFIG_MM_REGIONS > 2
/* Add region 2 to the user heap */
kumm_addregion((void *)REGION2_RAM_START, REGION2_RAM_SIZE);
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to region 2 */
imx9_mpu_uheap((uintptr_t)REGION2_RAM_START, REGION2_RAM_SIZE);
#endif
#endif /* CONFIG_MM_REGIONS > 2 */
}
#endif /* CONFIG_MM_REGIONS > 1 */
arch/arm/src/imx9/imx9_clockconfig.c
+267
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/****************************************************************************
* arch/arm/src/imx9/imx9_clockconfig.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdint.h>
#include <sys/param.h>
#include <sys/types.h>
#include <arch/board/board.h>
#include "barriers.h"
#include "arm_internal.h"
#include "hardware/imx9_gpc.h"
#include "imx9_clockconfig.h"
#include "imx9_scmi.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The base oscillator frequency is 24MHz */
#define XTAL_FREQ 24000000u
#define ROOT_CLOCK_OFFSET 41
/* Common barrier */
#define mb() \
do \
{ \
ARM_DSB(); \
ARM_ISB(); \
} \
while (0)
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_clockconfig
*
* Description:
* Called to initialize the i.IMX9. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void imx9_clockconfig(void)
{
/* Keep the system clock running so SYSTICK can wake up the system from
* wfi.
*/
modifyreg32(
IMX9_GPC_CTRL_CMC_MODE_CTRL(IMX9_GPC_CTRL_CM7_BASE),
IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_MASK,
IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET(
IMX9_GPC_CTRL_CMC_MODE_CTRL_CPU_MODE_TARGET_STAY_IN_RUN_MODE));
modifyreg32(IMX9_GPC_CTRL_CMC_MISC(IMX9_GPC_CTRL_CM7_BASE),
IMX9_GPC_CTRL_CMC_MISC_SLEEP_HOLD_EN_FLAG, 0);
/* Cortex-M33 with SM does PLL initalization */
}
#ifdef CONFIG_IMX9_CLK_OVER_SCMI
int imx9_sm_setrootclock(sm_clock_t *sm_clk)
{
scmi_clock_rate_t rate = /* clang-format off */
{
0, 0
}; /* clang-format on */
uint32_t channel = sm_clk->channel;
uint32_t clock_id = sm_clk->clk_id;
uint32_t pclk_id = sm_clk->pclk_id;
uint32_t div = sm_clk->div;
uint32_t attributes = sm_clk->attributes;
uint32_t oem_config_val = sm_clk->oem_config_val;
uint32_t flags = sm_clk->flags;
uint32_t old_pclk_id = 0; /* parent clock id */
uint64_t src_rate, root_rate;
int32_t status = -1;
if (div == 0)
{
return -EINVAL;
}
status = imx9_scmi_clockparentget(channel, clock_id, &old_pclk_id);
if (status != 0)
{
return status;
}
if (old_pclk_id != pclk_id)
{
status = imx9_scmi_clockparentset(channel, clock_id, pclk_id);
if (status != 0)
{
return status;
}
}
status = imx9_scmi_clockrateget(channel, pclk_id, &rate);
if (status != 0)
{
return status;
}
src_rate = rate.upper;
src_rate = (src_rate << 32);
src_rate |= rate.lower;
root_rate = src_rate / div;
rate.lower = root_rate & SM_CLOCK_RATE_MASK;
rate.upper = (root_rate >> 32) & SM_CLOCK_RATE_MASK;
status = imx9_scmi_clockrateset(channel, clock_id, flags, rate);
if (status != 0)
{
return status;
}
status = imx9_scmi_clockconfigset(channel, clock_id, attributes,
oem_config_val);
if (status != 0)
{
return status;
}
return OK;
}
int imx9_sm_getipfreq(sm_clock_t *sm_clk)
{
scmi_clock_rate_t rate = /* clang-format off */
{
0, 0
}; /* clang-format on */
uint32_t channel = sm_clk->channel;
uint32_t clock_id = sm_clk->clk_id;
uint32_t pclk_id = sm_clk->pclk_id;
int status = 0;
status = imx9_scmi_clockparentget(channel, clock_id, &pclk_id);
if (status < 0)
{
return status;
}
status = imx9_scmi_clockrateget(channel, clock_id, &rate);
if (status < 0)
{
return status;
}
return rate.lower;
}
#endif
int imx9_configure_clock(clock_config_t clk_config, bool enabled)
{
sm_clock_t sm_clk = /* clang-format off */
{
0
}; /* clang-format on */
sm_clk.clk_id = GET_CLOCK_ROOT(clk_config) + ROOT_CLOCK_OFFSET;
sm_clk.pclk_id = GET_CLOCK_ID(clk_config);
sm_clk.channel = SM_PLATFORM_A2P;
sm_clk.div = GET_CLOCK_DIV(clk_config);
if (sm_clk.div == 0)
{
/* Make sure div is always 1 */
sm_clk.div = 1;
}
sm_clk.attributes = SCMI_CLOCK_CONFIG_SET_ENABLE(enabled);
sm_clk.flags = SCMI_CLOCK_RATE_FLAGS_ROUND(SCMI_CLOCK_ROUND_AUTO);
return imx9_sm_setrootclock(&sm_clk);
}
/****************************************************************************
* Name: imx9_get_rootclock
*
* Description:
* This function returns the clock frequency of the specified root
* functional clock.
*
* Input Parameters:
* clkroot - Identifies the peripheral clock of interest
* frequency - The location where the peripheral clock frequency will be
* returned
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure. -ENODEV is returned if the clock is not enabled or is not
* being clocked.
*
****************************************************************************/
int imx9_get_rootclock(int clkroot, uint32_t *frequency)
{
if (clkroot <= CCM_CR_COUNT)
{
uint32_t ret = 0;
sm_clock_t sm_clk = /* clang-format off */
{
0
}; /* clang-format on */
sm_clk.clk_id = (uint32_t)(clkroot + ROOT_CLOCK_OFFSET);
sm_clk.channel = SM_PLATFORM_A2P;
ret = imx9_sm_getipfreq(&sm_clk);
if (ret < 0)
{
return -ENODEV;
}
else
{
*frequency = ret;
return OK;
}
}
return -ENODEV;
}
arch/arm/src/imx9/imx9_clockconfig.h
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/****************************************************************************
* arch/arm/src/imx9/imx9_clockconfig.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_CLOCKCONFIG_H
#define __ARCH_ARM_SRC_IMX9_IMX9_CLOCKCONFIG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include "hardware/imx9_clock.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_clockconfig
*
* Description:
* Called to initialize the i.IMX9. This does whatever setup is needed to
* put the SoC in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void imx9_clockconfig(void);
int imx9_configure_clock(clock_config_t clk_config, bool enabled);
/****************************************************************************
* Name: imx9_get_rootclock
*
* Description:
* This function returns the clock frequency of the specified root
* functional clock.
*
* Input Parameters:
* clkroot - Identifies the peripheral clock of interest
* frequency - The location where the peripheral clock frequency will be
* returned
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure. -ENODEV is returned if the clock is not enabled or is not
* being clocked.
*
****************************************************************************/
int imx9_get_rootclock(int clkroot, uint32_t *frequency);
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_CLOCKCONFIG_H */
arch/arm/src/imx9/imx9_edma.c
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arch/arm/src/imx9/imx9_edma.h
+478
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/****************************************************************************
* arch/arm/src/imx9/imx9_edma.h
*
* SPDX-License-Identifier: BSD-3-Clause
* SPDX-FileCopyrightText: 2024 NXP
* SPDX-FileCopyrightText: 2019, 2021, 2023 Gregory Nutt.
* SPDX-FileCopyrightText: 2022 NXP
* SPDX-FileCopyrightText: 2016-2017 NXP
* SPDX-FileCopyrightText: 2015, Freescale Semiconductor, Inc.
* SPDX-FileContributor: Gregory Nutt <gnutt@nuttx.org>
* SPDX-FileContributor: David Sidrane <david.sidrane@nscdg.com>
* SPDX-FileContributor: Peter van der Perk <peter.vanderperk@nxp.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_EDMA_H
#define __ARCH_ARM_SRC_IMX9_IMX9_EDMA_H
/* General Usage:
*
* 1. Allocate a DMA channel
*
* DMACH_HANDLE handle;
* handle = edma_dmach_alloc(dmamux, dchpri);
*
* Where 'dmamux' is the channel DMAMUX configuration register setting and
* 'dchpri' is the channel DCHPRIO priority register setting.
*
* 2. Create the transfer configuration:
*
* struct imx9_edma_xfrconfig_s config;
* config.saddr = ..;
* config.daddr = ..;
* etc.
*
* 3. Setup the transfer in hardware:
*
* int ret;
* ret = imx9_dmach_xfrsetup(handle, &config);
*
* 4. If you are setting up a scatter gather DMA
* (with CONFIG_IMX9_EDMA_NTCD > 0), then repeat steps 2 and 3 for
* each segment of the transfer.
*
* 5. Start the DMA:
*
* ret = imx9_dmach_start(handle, my_callback_func, priv);
*
* Where my_callback_func() is called when the DMA completes or an error
* occurs. 'priv' represents some internal driver state that will be
* provided with the callback.
*
* 6. If you need to stop the DMA and free resources (such as if a timeout
* occurs), then:
*
* i mxrt_dmach_stop(handle);
*
* 7. The callback will be received when the DMA completes (or an error
* occurs). After that, you may free the DMA channel, or re-use it on
* subsequent DMAs.
*
* imx9_dmach_free(handle);
*
* Almost non-invasive debug instrumentation is available. You may call
* imx9_dmasample() to save the current state of the eDMA registers at
* any given point in time. At some later, postmortem analysis, you can
* dump the content of the buffered registers with imx9_dmadump().
* imx9_dmasample() is also available for monitoring DMA progress.
*/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration flags.
*
* REVISIT: Many missing options that should be represented as flags:
* 1. Bandwidth
* 2. Source/Destination modulo
*/
#define EDMA_CONFIG_LINKTYPE_SHIFT (0) /* Bits 0-1: Link type */
#define EDMA_CONFIG_LINKTYPE_MASK (3 << EDMA_CONFIG_LINKTYPE_SHIFT)
# define EDMA_CONFIG_LINKTYPE_LINKNONE (0 << EDMA_CONFIG_LINKTYPE_SHIFT) /* No channel link */
# define EDMA_CONFIG_LINKTYPE_MINORLINK (1 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link after each minor loop */
# define EDMA_CONFIG_LINKTYPE_MAJORLINK (2 << EDMA_CONFIG_LINKTYPE_SHIFT) /* Channel link when major loop count exhausted */
#define EDMA_CONFIG_LOOP_SHIFT (2) /* Bits 2: Loop type */
#define EDMA_CONFIG_LOOP_MASK (3 << EDMA_CONFIG_LOOP_SHIFT)
# define EDMA_CONFIG_LOOPNONE (0 << EDMA_CONFIG_LOOP_SHIFT) /* No looping */
# define EDMA_CONFIG_LOOPSRC (1 << EDMA_CONFIG_LOOP_SHIFT) /* Source looping */
# define EDMA_CONFIG_LOOPDEST (2 << EDMA_CONFIG_LOOP_SHIFT) /* Dest looping */
#define EDMA_CONFIG_INTHALF (1 << 4) /* Bits 4: Int on HALF */
#define EDMA_CONFIG_INTMAJOR (1 << 5) /* Bits 5: Int on all Major completion
* Default is only on last completion
* if using scatter gather
*/
/****************************************************************************
* Public Types
****************************************************************************/
typedef void *DMACH_HANDLE;
typedef void (*edma_callback_t)(DMACH_HANDLE handle,
void *arg, bool done, int result);
/* eDMA transfer type */
enum imx9_edma_xfrtype_e
{
EDMA_MEM2MEM = 0, /* Transfer from memory to memory */
EDMA_PERIPH2MEM, /* Transfer from peripheral to memory */
EDMA_MEM2PERIPH, /* Transfer from memory to peripheral */
};
/* eDMA transfer sises */
enum imx9_edma_sizes_e
{
EDMA_8BIT = 0, /* Transfer data size 8 */
EDMA_16BIT = 1, /* Transfer data size 16 */
EDMA_32BIT = 2, /* Transfer data size 32 */
EDMA_64BIT = 3, /* Transfer data size 64 */
EDMA_16BYTE = 4, /* Transfer data size 16-byte */
EDMA_32BYTE = 5, /* Transfer data size 32-byte */
EDMA_64BYTE = 6, /* Transfer data size 64-byte */
};
/* This structure holds the source/destination transfer attribute
* configuration.
*/
struct imx9_edma_xfrconfig_s
{
uintptr_t saddr; /* Source data address. */
uintptr_t daddr; /* Destination data address. */
int16_t soff; /* Sign-extended offset for current source address. */
int16_t doff; /* Sign-extended offset for current destination address. */
uint16_t iter; /* Major loop iteration count. */
uint8_t flags; /* See EDMA_CONFIG_* definitions */
uint8_t ssize; /* Source data transfer size (see TCD_ATTR_SIZE_* definitions in rdware/. */
uint8_t dsize; /* Destination data transfer size. */
#ifdef CONFIG_IMX9_EDMA_EMLIM
uint16_t nbytes; /* Bytes to transfer in a minor loop */
#else
uint32_t nbytes; /* Bytes to transfer in a minor loop */
#endif
#ifdef CONFIG_IMX9_EDMA_MOD
uint8_t smod;
uint8_t dmod;
#endif
#ifdef CONFIG_IMX9_EDMA_BWC
uint8_t bwc;
#endif
#ifdef CONFIG_IMX9_EDMA_ELINK
DMACH_HANDLE linkch; /* Link channel (With EDMA_CONFIG_LINKTYPE_* flags) */
#endif
};
/* The following is used for sampling DMA registers when CONFIG DEBUG_DMA
* is selected
*/
#ifdef CONFIG_DEBUG_DMA
struct imx9_dmaregs_s
{
uint8_t chan; /* Sampled channel */
/* eDMA Global Registers */
uint32_t cr; /* Control */
uint32_t es; /* Error Status */
uint32_t req; /* Interrupt Request */
uint32_t hrs; /* Hardware Request Status */
/* eDMA Channel registers */
uint8_t dchpri; /* Channel priority */
/* eDMA TCD */
uint32_t saddr; /* TCD Source Address */
uint16_t soff; /* TCD Signed Source Address Offset */
uint16_t attr; /* TCD Transfer Attributes */
uint32_t nbml; /* TCD Signed Minor Loop Offset / Byte Count */
uint32_t slast; /* TCD Last Source Address Adjustment */
uint32_t daddr; /* TCD Destination Address */
uint16_t doff; /* TCD Signed Destination Address Offset */
uint16_t citer; /* TCD Current Minor Loop Link, Major Loop Count */
uint32_t dlastsga; /* TCD Last Destination Address Adjustment/Scatter Gather Address */
uint16_t csr; /* TCD Control and Status */
uint16_t biter; /* TCD Beginning Minor Loop Link, Major Loop Count */
/* DMAMUX registers */
uint32_t dmamux; /* Channel configuration */
};
#endif /* CONFIG_DEBUG_DMA */
/****************************************************************************
* Inline Functions
****************************************************************************/
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_dmach_alloc
*
* Allocate a DMA channel. This function sets aside a DMA channel,
* initializes the DMAMUX for the channel, then gives the caller exclusive
* access to the DMA channel.
*
* Input Parameters:
* dmamux - DMAMUX configuration see DMAMUX channel configuration register
* bit-field definitions in hardware/imx9_dmamux.h.
* Settings include:
*
* DMAMUX_CHCFG_SOURCE Chip-specific DMA source (required)
* DMAMUX_CHCFG_TRIG DMA Channel Trigger Enable (optional)
* DMAMUX_CHCFG_ENBL DMA Mux Channel Enable (required)
*
* A value of zero will disable the DMAMUX channel.
* dchpri - DCHPRI channel priority configuration. See DCHPRI channel
* configuration register bit-field definitions in
* hardware/imx9_edma.h. Meaningful settings include:
*
* EDMA_DCHPRI_CHPRI Channel Arbitration Priority
* DCHPRI_DPA Disable Preempt Ability
* DCHPRI_ECP Enable Channel Preemption
*
* The power-on default, 0x05, is a reasonable choice.
*
* Returned Value:
* If a DMA channel is available, this function returns a non-NULL, void*
* DMA channel handle. NULL is returned on any failure.
*
****************************************************************************/
DMACH_HANDLE imx9_dmach_alloc(uint16_t dmamux, uint8_t dchpri);
/****************************************************************************
* Name: imx9_dmach_free
*
* Description:
* Release a DMA channel.
* NOTE: The 'handle' used in this argument must NEVER be used again
* until imx9_dmach_alloc() is called again to re-gain a valid handle.
*
* Returned Value:
* None
*
****************************************************************************/
void imx9_dmach_free(DMACH_HANDLE handle);
/****************************************************************************
* Name: imx9_dmach_xfrsetup
*
* Description:
* This function adds the eDMA transfer to the DMA sequence. The request
* is setup according to the content of the transfer configuration
* structure. For "normal" DMA, imx9_dmach_xfrsetup is called only
* once.
* Scatter/gather DMA is accomplished by calling this function repeatedly,
* once for each transfer in the sequence. Scatter/gather DMA processing
* is enabled automatically when the second transfer configuration is
* received.
*
* This function may be called multiple times to handle multiple,
* discontinuous transfers (scatter-gather)
*
* Input Parameters:
* handle - DMA channel handle created by imx9_dmach_alloc()
* config - A DMA transfer configuration instance, populated by the
* The content of 'config' describes the transfer
*
* Returned Value
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure.
*
****************************************************************************/
int imx9_dmach_xfrsetup(DMACH_HANDLE handle,
const struct imx9_edma_xfrconfig_s *config);
/****************************************************************************
* Name: imx9_dmach_start
*
* Description:
* Start the DMA transfer by enabling the channel DMA request.
* This function should be called after the final call to
* imx9_dmasetup() in order to avoid race conditions.
*
* At the conclusion of each major DMA loop, a callback to the
* user-provided function is made: |For "normal" DMAs, this will
* correspond to the DMA DONE interrupt; for scatter gather DMAs, multiple
* interrupts will be generated with the final being the DONE interrupt.
*
* At the conclusion of the DMA, the DMA channel is reset, all TCDs are
* freed, and the callback function is called with the the success/fail
* result of the DMA.
*
* NOTE:
* On Rx DMAs (peripheral-to-memory or memory-to-memory), it is necessary
* to invalidate the destination memory. That is not done automatically
* by the DMA module. Invalidation of the destination memory regions is
* the responsibility of the caller.
*
* Input Parameters:
* handle - DMA channel handle created by imx9_dmach_alloc()
* callback - The callback to be invoked when the DMA is completes or is
* aborted.
* arg - An argument that accompanies the callback
*
* Returned Value:
* Zero (OK) is returned on success; a negated errno value is returned on
* any failure.
*
****************************************************************************/
int imx9_dmach_start(DMACH_HANDLE handle, edma_callback_t callback,
void *arg);
/****************************************************************************
* Name: imx9_dmach_stop
*
* Description:
* Cancel the DMA. After imx9_dmach_stop() is called, the DMA channel
* is reset, all TCDs are freed, and imx9_dmarx/txsetup() must be called
* before imx9_dmach_start() can be called again
*
* Input Parameters:
* handle - DMA channel handle created by imx9_dmach_alloc()
*
* Returned Value:
* None.
*
****************************************************************************/
void imx9_dmach_stop(DMACH_HANDLE handle);
/****************************************************************************
* Name: imx9_dmach_getcount
*
* Description:
* This function checks the TCD (Task Control Descriptor) status for a
* specified eDMA channel and returns the the number of major loop counts
* that have not finished.
*
* NOTES:
* 1. This function can only be used to get unfinished major loop count of
* transfer without the next TCD, or it might be inaccuracy.
* 2. The unfinished/remaining transfer bytes cannot be obtained directly
* from registers while the channel is running.
*
* Because to calculate the remaining bytes, the initial NBYTES configured
* in DMA_TCDn_NBYTES_MLNO register is needed while the eDMA IP does not
* support getting it while a channel is active. In another words, the
* NBYTES value reading is always the actual (decrementing) NBYTES value
* the dma_engine is working with while a channel is running.
* Consequently, to get the remaining transfer bytes, a software-saved
* initial value of NBYTES (for example copied before enabling the channel)
* is needed. The formula to calculate it is shown below:
*
* RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
*
* Input Parameters:
* handle - DMA channel handle created by imx9_dmach_alloc()
*
* Returned Value:
* Major loop count which has not been transferred yet for the current TCD.
*
****************************************************************************/
unsigned int imx9_dmach_getcount(DMACH_HANDLE handle);
/****************************************************************************
* Name: imx9_dmach_idle
*
* Description:
* This function checks if the dma is idle
*
* Returned Value:
* 0 - if idle
* !0 - not
*
****************************************************************************/
unsigned int imx9_dmach_idle(DMACH_HANDLE handle);
/****************************************************************************
* Name: imx9_dmasample
*
* Description:
* Sample DMA register contents
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA
void imx9_dmasample(DMACH_HANDLE handle, struct imx9_dmaregs_s *regs);
#else
# define imx9_dmasample(handle,regs)
#endif
/****************************************************************************
* Name: imx9_dmadump
*
* Description:
* Dump previously sampled DMA register contents
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA
void imx9_dmadump(const struct imx9_dmaregs_s *regs, const char *msg);
#else
# define imx9_dmadump(handle,regs,msg)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_EDMA_H */
arch/arm/src/imx9/imx9_flexcan.c
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arch/arm/src/imx9/imx9_flexcan.h
+87
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/****************************************************************************
* arch/arm/src/imx9/imx9_flexcan.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H
#define __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "hardware/imx9_flexcan.h"
#ifdef CONFIG_IMX9_FLEXCAN
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Function: arm_caninitialize
*
* Description:
* Initialize the enabled CAN device interfaces. If there are more
* different network devices in the chip, then board-specific logic will
* have to provide this function to determine which, if any, network
* devices should be initialized.
*
* Input Parameters:
* None
*
* Returned Value:
* OK on success; Negated errno on failure.
*
* Assumptions:
* Called very early in the initialization sequence.
*
****************************************************************************/
#ifdef CONFIG_NETDEV_LATEINIT
int imx9_caninitialize(int intf);
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* CONFIG_IMX9_FLEXCAN */
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_FLEXCAN_H */
arch/arm/src/imx9/imx9_gpio.c
+281
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/****************************************************************************
* arch/arm/src/imx9/imx9_gpio.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <assert.h>
#include <errno.h>
#include <nuttx/irq.h>
#include <imx9_gpiobase.c>
#include "chip.h"
#include "arm_internal.h"
#include "imx9_iomuxc.h"
#include "imx9_gpio.h"
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_gpio_dirout
****************************************************************************/
static inline void imx9_gpio_dirout(uint32_t port, uint32_t pin)
{
uint32_t regval = getreg32(IMX9_GPIO_PDDR(port));
regval |= GPIO_PIN(pin);
putreg32(regval, IMX9_GPIO_PDDR(port));
}
/****************************************************************************
* Name: imx9_gpio_dirin
****************************************************************************/
static inline void imx9_gpio_dirin(uint32_t port, uint32_t pin)
{
uint32_t regval = getreg32(IMX9_GPIO_PDDR(port));
regval &= ~GPIO_PIN(pin);
putreg32(regval, IMX9_GPIO_PDDR(port));
}
/****************************************************************************
* Name: imx9_gpio_setoutput
****************************************************************************/
static void imx9_gpio_setoutput(uint32_t port, uint32_t pin, bool value)
{
uintptr_t regaddr = IMX9_GPIO_PDOR(port);
uint32_t regval;
regval = getreg32(regaddr);
if (value)
{
regval |= GPIO_PIN(pin);
}
else
{
regval &= ~GPIO_PIN(pin);
}
putreg32(regval, regaddr);
}
/****************************************************************************
* Name: imx9_gpio_getpin_status
****************************************************************************/
static inline bool imx9_gpio_get_pinstatus(uint32_t port, uint32_t pin)
{
uintptr_t regaddr = IMX9_GPIO_PSOR(port);
uint32_t regval;
regval = getreg32(regaddr);
return ((regval & GPIO_PIN(pin)) != 0);
}
/****************************************************************************
* Name: imx9_gpio_getinput
****************************************************************************/
static inline bool imx9_gpio_getinput(uint32_t port, uint32_t pin)
{
uintptr_t regaddr = IMX9_GPIO_PDIR(port);
uint32_t regval;
regval = getreg32(regaddr);
return ((regval & GPIO_PIN(pin)) != 0);
}
/****************************************************************************
* Name: imx9_gpio_configinput
****************************************************************************/
static int imx9_gpio_configinput(gpio_pinset_t pinset)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS);
/* Configure pin as in input */
imx9_gpio_dirin(port, pin);
return OK;
}
/****************************************************************************
* Name: imx9_gpio_configoutput
****************************************************************************/
static inline int imx9_gpio_configoutput(gpio_pinset_t pinset)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
bool value = ((pinset & GPIO_OUTPUT_ONE) != 0);
DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS);
/* Set the output value */
imx9_gpio_setoutput(port, pin, value);
/* Convert the configured input GPIO to an output */
imx9_gpio_dirout(port, pin);
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_config_gpio
*
* Description:
* Configure a GPIO pin based on pin-encoded description of the pin.
*
****************************************************************************/
int imx9_config_gpio(gpio_pinset_t pinset)
{
irqstate_t flags;
int ret;
/* Configure the pin as an input initially to avoid any spurious outputs */
flags = enter_critical_section();
/* Configure based upon the pin mode */
switch (pinset & GPIO_MODE_MASK)
{
case GPIO_INPUT:
{
/* Configure the pin as a GPIO input */
ret = imx9_gpio_configinput(pinset);
}
break;
case GPIO_OUTPUT:
{
/* First configure the pin as a GPIO input to avoid output
* glitches.
*/
ret = imx9_gpio_configinput(pinset);
if (ret >= 0)
{
/* Convert the input to an output */
ret = imx9_gpio_configoutput(pinset);
}
}
break;
#ifdef CONFIG_IMX9_GPIO_IRQ
case GPIO_INTERRUPT:
{
/* Configure the pin as a GPIO input */
ret = imx9_gpio_configinput(pinset);
if (ret == OK)
{
ret = imx9_gpioirq_configure(pinset);
}
}
break;
#endif
default:
ret = -EINVAL;
break;
}
leave_critical_section(flags);
return ret;
}
/****************************************************************************
* Name: imx9_gpio_write
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void imx9_gpio_write(gpio_pinset_t pinset, bool value)
{
irqstate_t flags;
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS);
flags = enter_critical_section();
imx9_gpio_setoutput(port, pin, value);
leave_critical_section(flags);
}
/****************************************************************************
* Name: imx9_gpio_read
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool imx9_gpio_read(gpio_pinset_t pinset)
{
irqstate_t flags;
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
bool value;
DEBUGASSERT((unsigned int)port < IMX9_GPIO_NPORTS);
flags = enter_critical_section();
if ((pinset & (GPIO_OUTPUT)) == (GPIO_OUTPUT))
{
value = imx9_gpio_get_pinstatus(port, pin);
}
else
{
value = imx9_gpio_getinput(port, pin);
}
leave_critical_section(flags);
return value;
}
arch/arm/src/imx9/imx9_gpio.h
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/****************************************************************************
* arch/arm/src/imx9/imx9_gpio.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_GPIO_H
#define __ARCH_ARM_SRC_IMX9_IMX9_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/imx9_gpio.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GPIO pinset is a 16-bit word used to configure the GPIO settings. The
* encoding is as follows...
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* ENCODING MMVX BEEG GGGP PPPP
* GPIO INPUT 00.. BEEG GGGP PPPP
* INT INPUT 11.. BEEG GGGP PPPP
* GPIO OUTPUT 01V. ...G GGGP PPPP
*/
/* Input/Output Selection:
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* ENCODING MM.. .... .... ....
*/
#define GPIO_MODE_SHIFT (14) /* Bits 14-15: Pin mode */
#define GPIO_MODE_MASK (0x3 << GPIO_MODE_SHIFT)
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* GPIO input */
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* GPIO output */
# define GPIO_INTERRUPT (2 << GPIO_MODE_SHIFT) /* Interrupt input */
/* Initial Output Value:
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* GPIO OUTPUT 01V. .... .... ....
*/
#define GPIO_OUTPUT_SHIFT (13) /* Bit 13: Initial output */
#define GPIO_OUTPUT_MASK (0x1 << GPIO_OUTPUT_SHIFT)
# define GPIO_OUTPUT_ZERO (0 << GPIO_OUTPUT_SHIFT) /* Bit 29: 0=Initial output is low */
# define GPIO_OUTPUT_ONE (1 << GPIO_OUTPUT_SHIFT) /* Bit 29: 1=Initial output is high */
/* Interrupt on both edges configuration
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* INT INPUT 11.. B... .... ....
*/
#define GPIO_INTBOTHCFG_SHIFT (11) /* Bit 11: Interrupt both edges configuration */
#define GPIO_INTBOTHCFG_MASK (1 << GPIO_INTBOTHCFG_SHIFT)
# define GPIO_INTBOTH_EDGES (1 << GPIO_INTBOTHCFG_SHIFT)
/* Interrupt edge/level configuration
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* INT INPUT 11.. .EE. .... ....
*/
#define GPIO_INTCFG_SHIFT (9) /* Bits 9-10: Interrupt edge/level configuration */
#define GPIO_INTCFG_MASK (0x3 << GPIO_INTCFG_SHIFT)
# define GPIO_INT_LOWLEVEL (0 << GPIO_INTCFG_SHIFT)
# define GPIO_INT_HIGHLEVEL (1 << GPIO_INTCFG_SHIFT)
# define GPIO_INT_RISINGEDGE (2 << GPIO_INTCFG_SHIFT)
# define GPIO_INT_FALLINGEDGE (3 << GPIO_INTCFG_SHIFT)
/* GPIO Port Number
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* GPIO IN/OUT .... ...G GGG. ....
*/
#define GPIO_PORT_SHIFT (5) /* Bits 5-8: GPIO port index */
#define GPIO_PORT_MASK (0xf << GPIO_PORT_SHIFT)
# define GPIO_PORT1 (GPIO1 << GPIO_PORT_SHIFT) /* GPIO1 */
# define GPIO_PORT2 (GPIO2 << GPIO_PORT_SHIFT) /* GPIO2 */
# define GPIO_PORT3 (GPIO3 << GPIO_PORT_SHIFT) /* GPIO3 */
# define GPIO_PORT4 (GPIO4 << GPIO_PORT_SHIFT) /* GPIO4 */
# define GPIO_PORT5 (GPIO5 << GPIO_PORT_SHIFT) /* GPIO5 */
# define GPIO_PORT6 (GPIO6 << GPIO_PORT_SHIFT) /* GPIO6 */
# define GPIO_PORT7 (GPIO7 << GPIO_PORT_SHIFT) /* GPIO7 */
# define GPIO_PORT8 (GPIO8 << GPIO_PORT_SHIFT) /* GPIO8 */
# define GPIO_PORT9 (GPIO9 << GPIO_PORT_SHIFT) /* GPIO9 */
# define GPIO_PORT10 (GPIO10 << GPIO_PORT_SHIFT) /* GPIO10 */
# define GPIO_PORT11 (GPIO11 << GPIO_PORT_SHIFT) /* GPIO11 */
# define GPIO_PORT12 (GPIO12 << GPIO_PORT_SHIFT) /* GPIO12 */
# define GPIO_PORT13 (GPIO13 << GPIO_PORT_SHIFT) /* GPIO13 */
/* GPIO Pin Number:
*
* 1111 1100 0000 0000
* 5432 1098 7654 3210
* GPIO IN/OUT .... .... ...P PPPP
*/
#define GPIO_PIN_SHIFT (0) /* Bits 0-4: GPIO pin number */
#define GPIO_PIN_MASK (0x1f << GPIO_PIN_SHIFT)
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT) /* Pin 0 */
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT) /* Pin 1 */
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT) /* Pin 2 */
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT) /* Pin 3 */
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT) /* Pin 4 */
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT) /* Pin 5 */
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT) /* Pin 6 */
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT) /* Pin 7 */
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT) /* Pin 8 */
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT) /* Pin 9 */
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT) /* Pin 10 */
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT) /* Pin 11 */
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT) /* Pin 12 */
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT) /* Pin 13 */
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT) /* Pin 14 */
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT) /* Pin 15 */
# define GPIO_PIN16 (16 << GPIO_PIN_SHIFT) /* Pin 16 */
# define GPIO_PIN17 (17 << GPIO_PIN_SHIFT) /* Pin 17 */
# define GPIO_PIN18 (18 << GPIO_PIN_SHIFT) /* Pin 18 */
# define GPIO_PIN19 (19 << GPIO_PIN_SHIFT) /* Pin 19 */
# define GPIO_PIN20 (20 << GPIO_PIN_SHIFT) /* Pin 20 */
# define GPIO_PIN21 (21 << GPIO_PIN_SHIFT) /* Pin 21 */
# define GPIO_PIN22 (22 << GPIO_PIN_SHIFT) /* Pin 22 */
# define GPIO_PIN23 (23 << GPIO_PIN_SHIFT) /* Pin 23 */
# define GPIO_PIN24 (24 << GPIO_PIN_SHIFT) /* Pin 24 */
# define GPIO_PIN25 (25 << GPIO_PIN_SHIFT) /* Pin 25 */
# define GPIO_PIN26 (26 << GPIO_PIN_SHIFT) /* Pin 26 */
# define GPIO_PIN27 (27 << GPIO_PIN_SHIFT) /* Pin 27 */
# define GPIO_PIN28 (28 << GPIO_PIN_SHIFT) /* Pin 28 */
# define GPIO_PIN29 (29 << GPIO_PIN_SHIFT) /* Pin 29 */
# define GPIO_PIN30 (30 << GPIO_PIN_SHIFT) /* Pin 30 */
# define GPIO_PIN31 (31 << GPIO_PIN_SHIFT) /* Pin 31 */
/* Port access via global LUT */
#define IMX9_GPIO_BASE(n) g_gpio_base[n] /* Use GPIO1..GPIOn macros as indices */
#define IMX9_GPIO_VERID(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_VERID_OFFSET)
#define IMX9_GPIO_PARAM(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PARAM_OFFSET)
#define IMX9_GPIO_LOCK(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_LOCK_OFFSET)
#define IMX9_GPIO_PCNS(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCNS_OFFSET)
#define IMX9_GPIO_ICNS(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICNS_OFFSET)
#define IMX9_GPIO_PCNP(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCNP_OFFSET)
#define IMX9_GPIO_ICNP(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICNP_OFFSET)
#define IMX9_GPIO_PDOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDOR_OFFSET)
#define IMX9_GPIO_PSOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PSOR_OFFSET)
#define IMX9_GPIO_PCOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PCOR_OFFSET)
#define IMX9_GPIO_PTOR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PTOR_OFFSET)
#define IMX9_GPIO_PDIR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDIR_OFFSET)
#define IMX9_GPIO_PDDR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PDDR_OFFSET)
#define IMX9_GPIO_PIDR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_PIDR_OFFSET)
#define IMX9_GPIO_GICLR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_GICLR_OFFSET)
#define IMX9_GPIO_GICHR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_GICHR_OFFSET)
/* Interrupt status flags, these have two channels. Channel is selected by
* setting / clearing ICRN.IRQS bit.
*/
#define IMX9_GPIO_ISFR0(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ISFR0_OFFSET)
#define IMX9_GPIO_ISFR1(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ISFR1_OFFSET)
/* GPIO PIN[0...31] and ICR[0...31] */
#define IMX9_GPIO_P0DR(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_P0DR_OFFSET)
#define IMX9_GPIO_PNDR(n, p) (IMX9_GPIO_P0DR(n) + ((p) * 0x4))
#define IMX9_GPIO_ICR0(n) (IMX9_GPIO_BASE(n) + IMX9_GPIO_ICR0_OFFSET)
#define IMX9_GPIO_ICRN(n, p) (IMX9_GPIO_ICR0(n) + ((p) * 0x4))
/****************************************************************************
* Public Types
****************************************************************************/
/* The smallest integer type that can hold the GPIO encoding */
typedef uint16_t gpio_pinset_t;
/****************************************************************************
* Public Data
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* Look-up table that maps GPIO1..GPIOn indexes into GPIO register base
* addresses
*/
EXTERN const uintptr_t g_gpio_base[];
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: imx9_gpioirq_initialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
#ifdef CONFIG_IMX9_GPIO_IRQ
void imx9_gpioirq_initialize(void);
#else
# define imx9_gpioirq_initialize()
#endif
/****************************************************************************
* Name: imx9_config_gpio
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
****************************************************************************/
int imx9_config_gpio(gpio_pinset_t pinset);
/****************************************************************************
* Name: imx9_gpio_write
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void imx9_gpio_write(gpio_pinset_t pinset, bool value);
/****************************************************************************
* Name: imx9_gpio_read
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool imx9_gpio_read(gpio_pinset_t pinset);
/****************************************************************************
* Name: imx9_gpioirq_attach
*
* Description:
* Attach a pin interrupt handler.
*
****************************************************************************/
#ifdef CONFIG_IMX9_GPIO_IRQ
int imx9_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg);
#else
#define imx9_gpioirq_attach(pinset, isr, arg) 0
#endif
/****************************************************************************
* Name: imx9_gpioirq_configure
*
* Description:
* Configure an interrupt for the specified GPIO pin.
*
****************************************************************************/
#ifdef CONFIG_IMX9_GPIO_IRQ
int imx9_gpioirq_configure(gpio_pinset_t pinset);
#else
# define imx9_gpioirq_configure(pinset) 0
#endif
/****************************************************************************
* Name: imx9_gpioirq_enable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_IMX9_GPIO_IRQ
int imx9_gpioirq_enable(gpio_pinset_t pinset);
#else
# define imx9_gpioirq_enable(pinset) 0
#endif
/****************************************************************************
* Name: imx9_gpioirq_disable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
****************************************************************************/
#ifdef CONFIG_IMX9_GPIO_IRQ
int imx9_gpioirq_disable(gpio_pinset_t pinset);
#else
# define imx9_gpioirq_disable(pinset) 0
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_GPIO_H */
arch/arm/src/imx9/imx9_gpiobase.c
+62
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@@ -0,0 +1,62 @@
/****************************************************************************
* arch/arm/src/imx9/imx9_gpiobase.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "imx9_gpio.h"
/****************************************************************************
* Public Data
****************************************************************************/
#if defined(CONFIG_ARCH_CHIP_IMX93)
/* Base address for the GPIO memory mapped registers */
const uintptr_t g_gpio_base[] =
{
IMX9_GPIO1_BASE,
IMX9_GPIO2_BASE,
IMX9_GPIO3_BASE,
IMX9_GPIO4_BASE,
};
#elif defined(CONFIG_ARCH_CHIP_IMX9_CORTEX_M)
/* Base address for the GPIO memory mapped registers */
const uintptr_t g_gpio_base[] =
{
IMX9_GPIO1_BASE,
IMX9_GPIO2_BASE,
IMX9_GPIO3_BASE,
IMX9_GPIO4_BASE,
};
#else
# error Unrecognized i.MX9 architecture
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
arch/arm/src/imx9/imx9_gpioirq.c
+309
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@@ -0,0 +1,309 @@
/****************************************************************************
* arch/arm/src/imx9/imx9_gpioirq.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h>
#include "arm_internal.h"
#include "imx9_gpio.h"
#ifdef CONFIG_IMX9_GPIO_IRQ
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/****************************************************************************
* Private Types
****************************************************************************/
struct imx9_portisr_s
{
struct
{
xcpt_t isr; /* The interrupt service routine */
void *arg; /* Argument passed to it */
}
pins[IMX9_GPIO_NPINS];
};
/****************************************************************************
* Private Data
****************************************************************************/
static struct imx9_portisr_s g_isrtab[IMX9_GPIO_NPORTS];
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_gpio_interrupt
*
* Description:
* GPIO interrupt handlers. iMX9 has two interrupt sources for each pin,
* the NuttX driver uses source 0.
*
****************************************************************************/
static int imx9_gpio_interrupt(int irq, void *context, void *arg)
{
uint32_t port = (uint32_t)((uintptr_t)arg) >> GPIO_PORT_SHIFT;
uint32_t status;
uint32_t pin;
uint32_t regaddr;
/* Get the pending interrupt indications */
regaddr = IMX9_GPIO_ISFR0(port);
status = getreg32(regaddr);
/* Decode the pending interrupts */
for (pin = 0; pin < 32 && status != 0; pin++)
{
/* Is the IRQ associated with this pin pending? */
uint32_t mask = (1 << pin);
if ((status & mask) != 0)
{
struct imx9_portisr_s *isrtab;
/* Yes, clear the status bit and dispatch the interrupt */
putreg32(mask, regaddr);
status &= ~mask;
/* Get the interrupt table for this port */
isrtab = &g_isrtab[port];
if (isrtab->pins[pin].isr != NULL)
{
/* Run the user handler with the user's argument */
isrtab->pins[pin].isr(irq, context, isrtab->pins[pin].arg);
}
}
}
return OK;
}
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_gpioirq_initialize
*
* Description:
* Initialize logic to support a second level of interrupt decoding for
* GPIO pins.
*
****************************************************************************/
void imx9_gpioirq_initialize(void)
{
/* Do not loop over all GPIOs on IMX95 because some IOs may not be
* accessible depending on the system managers configuration
*/
#ifndef CONFIG_ARCH_CHIP_IMX95_M7
uint32_t port;
uint32_t pin;
/* Disable all GPIO interrupts at the source */
for (port = 0; port < IMX9_GPIO_NPORTS; port++)
{
for (pin = 0; pin < IMX9_GPIO_NPINS; pin++)
{
/* Reset the interrupt configuration, disabling the interrupt */
putreg32(0, IMX9_GPIO_ICRN(port, pin));
}
}
#endif /* CONFIG_ARCH_CHIP_IMX95_M7 */
/* Disable all GPIO interrupts */
up_disable_irq(IMX9_IRQ_GPIO1_0);
up_disable_irq(IMX9_IRQ_GPIO1_1);
up_disable_irq(IMX9_IRQ_GPIO2_0);
up_disable_irq(IMX9_IRQ_GPIO2_1);
up_disable_irq(IMX9_IRQ_GPIO3_0);
up_disable_irq(IMX9_IRQ_GPIO3_1);
up_disable_irq(IMX9_IRQ_GPIO4_0);
up_disable_irq(IMX9_IRQ_GPIO4_1);
/* Attach the common GPIO interrupt handler and enable the interrupt */
DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO1_0,
imx9_gpio_interrupt, (void *)GPIO_PORT1));
up_enable_irq(IMX9_IRQ_GPIO1_0);
DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO2_0,
imx9_gpio_interrupt, (void *)GPIO_PORT2));
up_enable_irq(IMX9_IRQ_GPIO2_0);
DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO3_0,
imx9_gpio_interrupt, (void *)GPIO_PORT3));
up_enable_irq(IMX9_IRQ_GPIO3_0);
DEBUGVERIFY(irq_attach(IMX9_IRQ_GPIO4_0,
imx9_gpio_interrupt, (void *)GPIO_PORT4));
up_enable_irq(IMX9_IRQ_GPIO4_0);
}
/****************************************************************************
* Name: imx9_gpioirq_attach
*
* Description:
* Attach a pin interrupt handler.
*
****************************************************************************/
int imx9_gpioirq_attach(gpio_pinset_t pinset, xcpt_t isr, void *arg)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Atomically change the handler */
irqstate_t flags = enter_critical_section();
g_isrtab[port].pins[pin].isr = isr;
g_isrtab[port].pins[pin].arg = arg;
leave_critical_section(flags);
return OK;
}
/****************************************************************************
* Name: imx9_gpioirq_configure
*
* Description:
* Configure an interrupt for the specified GPIO pin.
*
****************************************************************************/
int imx9_gpioirq_configure(gpio_pinset_t pinset)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
/* Nothing much to do here, just reset the IRQ config */
putreg32(0, IMX9_GPIO_ICRN(port, pin));
return OK;
}
/****************************************************************************
* Name: imx9_gpioirq_enable
*
* Description:
* Enable the interrupt for specified GPIO IRQ
*
****************************************************************************/
int imx9_gpioirq_enable(gpio_pinset_t pinset)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
uint32_t both = (pinset & GPIO_INTBOTHCFG_MASK) >> GPIO_INTBOTHCFG_SHIFT;
uint32_t icr = (pinset & GPIO_INTCFG_MASK);
uint32_t regval;
uintptr_t regaddr;
/* Perform RMW to the specific pin */
regaddr = IMX9_GPIO_ICRN(port, pin);
regval = getreg32(regaddr);
regval &= ~IMX9_GPIO_ICRN_MASK;
if (both)
{
regval |= IMX9_GPIO_ICRN_BOTH;
}
else if (icr == GPIO_INT_LOWLEVEL)
{
regval |= IMX9_GPIO_ICRN_ZERO;
}
else if (icr == GPIO_INT_HIGHLEVEL)
{
regval |= IMX9_GPIO_ICRN_ONE;
}
else if (icr == GPIO_INT_RISINGEDGE)
{
regval |= IMX9_GPIO_ICRN_RISING;
}
else /* GPIO_INT_FALLINGEDGE */
{
regval |= IMX9_GPIO_ICRN_FALLING;
}
putreg32(regval, regaddr);
return OK;
}
/****************************************************************************
* Name: imx9_gpioirq_disable
*
* Description:
* Disable the interrupt for specified GPIO IRQ
*
****************************************************************************/
int imx9_gpioirq_disable(gpio_pinset_t pinset)
{
uint32_t port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
uint32_t pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
uint32_t regval;
uintptr_t regaddr;
/* Perform RMW to the specific pin */
regaddr = IMX9_GPIO_ICRN(port, pin);
regval = getreg32(regaddr);
regval &= ~IMX9_GPIO_ICRN_MASK;
putreg32(regval, regaddr);
return OK;
}
#endif /* CONFIG_IMX9_GPIO_IRQ */
arch/arm/src/imx9/imx9_idle.c
+174
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/****************************************************************************
* arch/arm/src/imx9/imx9_idle.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/power/pm.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_idlepm
*
* Description:
* Perform IDLE state power management.
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_idlepm(void)
{
static enum pm_state_e oldstate = PM_NORMAL;
enum pm_state_e newstate;
irqstate_t flags;
int ret;
/* Decide, which power saving level can be obtained */
newstate = pm_checkstate(PM_IDLE_DOMAIN);
/* Check for state changes */
if (newstate != oldstate)
{
flags = enter_critical_section();
/* Perform board-specific, state-dependent logic here */
pwrinfo("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
if (ret < 0)
{
/* The new state change failed, revert to the preceding state */
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
/* Save the new state */
oldstate = newstate;
}
/* MCU-specific power management logic */
switch (newstate)
{
case PM_NORMAL:
break;
case PM_IDLE:
break;
case PM_STANDBY:
imx9_pmstop(true);
break;
case PM_SLEEP:
imx9_pmstandby();
break;
default:
break;
}
leave_critical_section(flags);
}
}
#else
# define up_idlepm()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when there is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
/* Sleep until an interrupt occurs to save power. */
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
}
arch/arm/src/imx9/imx9_iomuxc.c
+207
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/****************************************************************************
* arch/arm/src/imx9/imx9_iomuxc.c
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include <stdint.h>
#include "arm_internal.h"
#include "hardware/imx9_memorymap.h"
#include "imx9_iomuxc.h"
#ifdef CONFIG_IMX9_IOMUX_OVER_SCMI
#include "imx9_scmi.h"
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: imx9_iomux_configure
*
* Description:
* This function writes the encoded pad configuration to the Pad Control
* register.
*
* Input Parameters:
* cfg - The IOMUX configuration
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
#ifdef CONFIG_IMX9_IOMUX_OVER_SCMI
/* Sets the IOMUXC pin mux mode.
*/
void imx9_sm_iomucx_configure(sm_pinctrl_t *sm_pinctrl)
{
scmi_pin_config_t configs[4];
uint32_t num_configs = 0;
uint32_t channel = sm_pinctrl->channel;
uint32_t mux_register = sm_pinctrl->mux_register;
uint32_t mux_mode = sm_pinctrl->mux_mode;
uint32_t input_register = sm_pinctrl->input_register;
uint32_t input_daisy = sm_pinctrl->input_daisy;
uint32_t input_on_field = sm_pinctrl->input_on_field;
uint32_t config_register = sm_pinctrl->config_register;
uint32_t config_value = sm_pinctrl->config_value;
if (mux_register)
{
configs[num_configs].type = SCMI_PINCTRL_TYPE_MUX;
configs[num_configs].value = SM_PLATFORM_PINCTRL_MUX_MODE(mux_mode)
| SM_PLATFORM_PINCTRL_SION(
input_on_field);
num_configs++;
}
if (input_register & 0xffff)
{
configs[num_configs].type = SCMI_PINCTRL_TYPE_DAISY_ID;
configs[num_configs].value =
(input_register - SM_PLATFORM_PINCTRL_DAISYREG_OFF) / 4;
num_configs++;
configs[num_configs].type = SCMI_PINCTRL_TYPE_DAISY_CFG;
configs[num_configs].value = input_daisy;
num_configs++;
}
if (config_register)
{
configs[num_configs].type = SCMI_PINCTRL_TYPE_CONFIG;
configs[num_configs].value = config_value;
num_configs++;
}
if (mux_register || input_register)
{
uint32_t attributes = SCMI_PINCTRL_SET_ATTR_SELECTOR(
SCMI_PINCTRL_SEL_PIN)
| SCMI_PINCTRL_SET_ATTR_NUM_CONFIGS(
num_configs);
imx9_scmi_pinctrlconfigset(
channel, (mux_register - SM_PLATFORM_PINCTRL_MUXREG_OFF) / 4,
attributes, configs);
}
}
#endif
int imx9_iomux_configure(iomux_cfg_t cfg)
{
#ifdef CONFIG_IMX9_IOMUX_OVER_SCMI
sm_pinctrl_t sm_pinctrl =
{
0
};
sm_pinctrl.channel = SM_PLATFORM_A2P;
sm_pinctrl.mux_register = IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff;
sm_pinctrl.mux_mode = cfg.padcfg.mode;
sm_pinctrl.input_register = IMX9_IOMUXC_BASE + cfg.padcfg.dsyregoff;
sm_pinctrl.input_daisy = cfg.padcfg.dsy;
sm_pinctrl.config_register = IMX9_IOMUXC_BASE + cfg.padcfg.padregoff;
sm_pinctrl.config_value = cfg.pad;
sm_pinctrl.input_on_field = cfg.sion;
imx9_sm_iomucx_configure(&sm_pinctrl);
#else
if (!cfg.padcfg.ctlregoff)
{
return -EINVAL;
}
putreg32(cfg.padcfg.mode | (cfg.sion << IOMUXC_MUX_SION_SHIFT),
IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff);
if (cfg.padcfg.dsyregoff)
{
putreg32(cfg.padcfg.dsy, IMX9_IOMUXC_BASE + cfg.padcfg.dsyregoff);
}
if (cfg.padcfg.padregoff)
{
putreg32(cfg.pad << IOMUXC_PAD_CONFIG_SHIFT,
IMX9_IOMUXC_BASE + cfg.padcfg.padregoff);
}
return OK;
#endif
}
/****************************************************************************
* Name: imx9_iomux_configure
*
* Description:
* This can be used to forcibly set a pad to GPIO mode. This overrides and
* disconnects any peripheral using the pin.
*
* Input Parameters:
* cfg - The IOMUX configuration.
* sion - if true; sets SION, otherwise clears it.
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
int imx9_iomux_gpio(iomux_cfg_t cfg, bool sion)
{
uint32_t reg_sion;
if (!cfg.padcfg.ctlregoff)
{
return -EINVAL;
}
/* Set sion if requested to do so */
reg_sion = sion ? IOMUXC_MUX_SION_ON : 0;
/* Based on pad number, either ALT0/ALT5 sets the pad as GPIO */
if ((cfg.padcfg.ctlregoff >= IOMUXC_MUX_CTL_GPIO_IO00_OFFSET)
&& (cfg.padcfg.ctlregoff <= IOMUXC_MUX_CTL_GPIO_IO37_OFFSET))
{
putreg32(IOMUXC_MUX_MODE_ALT0 | reg_sion,
IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff);
}
else
{
putreg32(IOMUXC_MUX_MODE_ALT5 | reg_sion,
IMX9_IOMUXC_BASE + cfg.padcfg.ctlregoff);
}
return OK;
}
arch/arm/src/imx9/imx9_iomuxc.h
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/****************************************************************************
* arch/arm/src/imx9/imx9_iomuxc.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_IOMUXC_H
#define __ARCH_ARM_SRC_IMX9_IMX9_IOMUXC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <stdbool.h>
#include "hardware/imx9_iomuxc.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define IOMUXC_PAD_CONFIG_SHIFT 1
#define IOMUX_PADCFG(_ctlregoff, _mode, _dsyregoff, _dsy, _padregoff) \
{ \
.ctlregoff = (_ctlregoff), \
.padregoff = (_padregoff), \
.dsyregoff = (_dsyregoff), \
.mode = (_mode), \
.dsy = (_dsy), \
}
#define IOMUX_CFG(_padcfg, _pad, _sion) \
(iomux_cfg_t) \
{ \
.padcfg = _padcfg, \
.pad = (_pad) >> IOMUXC_PAD_CONFIG_SHIFT, \
.sion = (_sion) >> IOMUXC_MUX_SION_SHIFT, \
}
/****************************************************************************
* Public Types
****************************************************************************/
/* Information for the pad alternate function */
struct iomux_padcfg_s
{
/* Register offsets for PAD
* ALT(mode) configuration for ctlreg
* input daisy(dsy) configuration for dsyreg
*/
uint16_t mode : 3;
uint16_t ctlregoff : 13;
uint16_t padregoff : 16;
uint16_t dsy : 3;
uint16_t dsyregoff : 13;
};
struct iomux_cfg_s
{
struct iomux_padcfg_s padcfg;
/* Register values */
uint32_t pad :31;
uint32_t sion : 1;
};
typedef struct iomux_cfg_s iomux_cfg_t;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: imx9_iomux_configure
*
* Description:
* This function writes the encoded pad configuration to the Pad Control
* register.
*
* Input Parameters:
* cfg - The IOMUX configuration
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
int imx9_iomux_configure(iomux_cfg_t cfg);
/****************************************************************************
* Name: imx9_iomux_configure
*
* Description:
* This can be used to forcibly set a pad to GPIO mode. This overrides and
* disconnects any peripheral using the pin.
*
* Input Parameters:
* cfg - The IOMUX configuration.
* sion - if true; sets SION, otherwise clears it.
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
****************************************************************************/
int imx9_iomux_gpio(iomux_cfg_t cfg, bool sion);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_IOMUXC_H */
arch/arm/src/imx9/imx9_irq.c
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arch/arm/src/imx9/imx9_lowputc.c
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arch/arm/src/imx9/imx9_lowputc.h
+96
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/****************************************************************************
* arch/arm/src/imx9/imx9_lowputc.h
*
* SPDX-License-Identifier: Apache-2.0
* SPDX-FileCopyrightText: 2024 NXP
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H
#define __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/compiler.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
/****************************************************************************
* Public Types
****************************************************************************/
/* This structure describes the configuration of an UART */
struct uart_config_s
{
uint32_t baud; /* Configured baud */
uint8_t parity; /* 0=none, 1=odd, 2=even */
uint8_t bits; /* Number of bits (5-9) */
bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */
bool userts; /* True: Assert RTS when there are data to be sent */
bool invrts; /* True: Invert sense of RTS pin (true=active high) */
bool usects; /* True: Condition transmission on CTS asserted */
bool users485; /* True: Assert RTS while transmission progresses */
};
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifdef __cplusplus
extern "C"
{
#endif
/****************************************************************************
* Name: imx9_lowsetup
*
* Description:
* Called at the very beginning of _start. Performs low level
* initialization including setup of the console UART. This UART done
* early so that the serial console is available for debugging very early
* in the boot sequence.
*
****************************************************************************/
void imx9_lowsetup(void);
/****************************************************************************
* Name: imx9_lpuart_configure
*
* Description:
* Configure a UART for non-interrupt driven operation
*
****************************************************************************/
int imx9_lpuart_configure(uint32_t base,
int uartnum,
const struct uart_config_s *config);
#ifdef __cplusplus
}
#endif
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_LOWPUTC_H */
arch/arm/src/imx9/imx9_lpi2c.c
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