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Add circular DMA support to STM32 and STM32 serial driver; Add initial configuration for the Mikroelektronika PIC32MX7 MMB board
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4640 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_uart.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -1,7 +1,7 @@
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/****************************************************************************
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* arch/arm/src/stm32/stm32_dma.c
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -251,6 +251,19 @@ EXTERN void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback,
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EXTERN void stm32_dmastop(DMA_HANDLE handle);
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/****************************************************************************
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* Name: stm32_dmaresidual
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*
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* Description:
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* Returns the number of bytes remaining to be transferred
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*
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* Assumptions:
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* - DMA handle allocated by stm32_dmachannel()
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*
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****************************************************************************/
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EXTERN size_t stm32_dmaresidual(DMA_HANDLE handle);
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/****************************************************************************
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* Name: stm32_dmasample
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*
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@@ -56,89 +56,6 @@
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/**************************************************************************
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* Private Definitions
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**************************************************************************/
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/* Configuration **********************************************************/
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/* Make sure that we have not enabled more U[S]ARTs than are support by
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* the device.
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*/
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#if STM32_NUSART < 6
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# undef CONFIG_STM32_USART6
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#endif
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#if STM32_NUSART < 5
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# undef CONFIG_STM32_UART5
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#endif
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#if STM32_NUSART < 4
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# undef CONFIG_STM32_UART4
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#endif
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#if STM32_NUSART < 3
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# undef CONFIG_STM32_USART3
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#endif
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#if STM32_NUSART < 2
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# undef CONFIG_STM32_USART2
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#endif
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#if STM32_NUSART < 1
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# undef CONFIG_STM32_USART1
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#endif
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#if defined(CONFIG_STM32_USART1) || defined (CONFIG_STM32_USART2) || defined(CONFIG_STM32_USART3) || \
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defined(CONFIG_STM32_UART4) || defined (CONFIG_STM32_UART5) || defined(CONFIG_STM32_USART6)
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# define HAVE_UART
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#endif
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/* Is there a serial console? */
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#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1)
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_UART5_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# define HAVE_CONSOLE 1
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#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2)
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_USART4_SERIAL_CONSOLE
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# undef CONFIG_USART5_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# define HAVE_CONSOLE 1
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#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3)
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_UART5_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# define HAVE_CONSOLE 1
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#elif defined(CONFIG_UART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4)
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_UART5_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# define HAVE_CONSOLE 1
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#elif defined(CONFIG_UART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5)
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# define HAVE_CONSOLE 1
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#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6)
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_UART5_SERIAL_CONSOLE
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# define HAVE_CONSOLE 1
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#else
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_UART5_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# undef HAVE_CONSOLE
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#endif
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/* Select USART parameters for the selected console */
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#if defined(CONFIG_USART1_SERIAL_CONSOLE)
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File diff suppressed because it is too large
Load Diff
@@ -532,6 +532,9 @@ static inline void spi_dmarxwakeup(FAR struct stm32_spidev_s *priv)
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static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
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{
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FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg;
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/* Wake-up the SPI driver */
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priv->rxresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */
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spi_dmarxwakeup(priv);
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}
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@@ -549,6 +552,9 @@ static void spi_dmarxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
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static void spi_dmatxcallback(DMA_HANDLE handle, uint8_t isr, void *arg)
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{
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FAR struct stm32_spidev_s *priv = (FAR struct stm32_spidev_s *)arg;
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/* Wake-up the SPI driver */
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priv->txresult = isr | 0x080; /* OR'ed with 0x80 to assure non-zero */
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spi_dmatxwakeup(priv);
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}
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@@ -1,7 +1,7 @@
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/************************************************************************************
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* arch/arm/src/stm32/stm32_uart.h
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Copyright (C) 2009, 2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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@@ -48,6 +48,163 @@
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Make sure that we have not enabled more U[S]ARTs than are support by
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* the device.
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*/
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#if STM32_NUSART < 6
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# undef CONFIG_STM32_USART6
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#endif
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#if STM32_NUSART < 5
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# undef CONFIG_STM32_UART5
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#endif
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#if STM32_NUSART < 4
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# undef CONFIG_STM32_UART4
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#endif
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#if STM32_NUSART < 3
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# undef CONFIG_STM32_USART3
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#endif
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#if STM32_NUSART < 2
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# undef CONFIG_STM32_USART2
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#endif
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#if STM32_NUSART < 1
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# undef CONFIG_STM32_USART1
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#endif
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/* Is there a USART enabled? */
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#if defined(CONFIG_STM32_USART1) || defined(CONFIG_STM32_USART2) || \
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defined(CONFIG_STM32_USART3) || defined(CONFIG_STM32_UART4) || \
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defined(CONFIG_STM32_UART5) || defined(CONFIG_STM32_USART6)
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# define HAVE_UART 1
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#endif
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/* Is there a serial console? */
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#if defined(CONFIG_USART1_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART1)
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_UART5_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# define CONSOLE_UART 1
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# define HAVE_CONSOLE 1
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#elif defined(CONFIG_USART2_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART2)
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_USART4_SERIAL_CONSOLE
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# undef CONFIG_USART5_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# define CONSOLE_UART 2
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# define HAVE_CONSOLE 1
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#elif defined(CONFIG_USART3_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART3)
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_UART5_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# define CONSOLE_UART 3
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# define HAVE_CONSOLE 1
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#elif defined(CONFIG_USART4_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART4)
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_UART5_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# define CONSOLE_UART 4
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# define HAVE_CONSOLE 1
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#elif defined(CONFIG_USART5_SERIAL_CONSOLE) && defined(CONFIG_STM32_UART5)
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# define CONSOLE_UART 5
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# define HAVE_CONSOLE 1
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#elif defined(CONFIG_USART6_SERIAL_CONSOLE) && defined(CONFIG_STM32_USART6)
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_UART5_SERIAL_CONSOLE
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# define CONSOLE_UART 6
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# define HAVE_CONSOLE 1
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#else
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# undef CONFIG_USART1_SERIAL_CONSOLE
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# undef CONFIG_USART2_SERIAL_CONSOLE
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# undef CONFIG_USART3_SERIAL_CONSOLE
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# undef CONFIG_UART4_SERIAL_CONSOLE
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# undef CONFIG_UART5_SERIAL_CONSOLE
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# undef CONFIG_USART6_SERIAL_CONSOLE
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# define CONSOLE_UART 0
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# undef HAVE_CONSOLE
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#endif
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/* DMA support is only provided if CONFIG_ARCH_DMA is in the NuttX configuration.
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* Furthermore, DMA support is currently only implemented for the F4 (but could be
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* extended to the F1 and F2 with a little effort in the DMA code.
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*/
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#if !defined(HAVE_UART) || !defined(CONFIG_ARCH_DMA) || !defined(CONFIG_STM32_STM32F40XX)
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# undef CONFIG_USART1_RXDMA
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# undef CONFIG_USART2_RXDMA
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# undef CONFIG_USART3_RXDMA
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# undef CONFIG_USART4_RXDMA
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# undef CONFIG_USART5_RXDMA
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# undef CONFIG_USART6_RXDMA
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#endif
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/* Disable the DMA configuration on all unused USARTs */
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#ifndef CONFIG_STM32_USART1
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# undef CONFIG_USART1_RXDMA
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#endif
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#ifndef CONFIG_STM32_USART2
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# undef CONFIG_USART2_RXDMA
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#endif
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#ifndef CONFIG_STM32_USART3
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# undef CONFIG_USART3_RXDMA
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#endif
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#ifndef CONFIG_STM32_USART4
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# undef CONFIG_USART4_RXDMA
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#endif
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#ifndef CONFIG_STM32_USART5
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# undef CONFIG_USART5_RXDMA
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#endif
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#ifndef CONFIG_STM32_USART6
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# undef CONFIG_USART6_RXDMA
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#endif
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/* Is DMA available on any (enabled) USART? */
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#undef SERIAL_HAVE_DMA
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#if defined(CONFIG_USART1_RXDMA) || defined(CONFIG_USART2_RXDMA) || \
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defined(CONFIG_USART3_RXDMA) || defined(CONFIG_USART4_RXDMA) || \
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defined(CONFIG_USART5_RXDMA) || defined(CONFIG_USART6_RXDMA)
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# define SERIAL_HAVE_DMA 1
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#endif
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/* Is DMA used on all (enabled) USARTs */
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#define SERIAL_HAVE_ONLY_DMA 1
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#if defined(CONFIG_STM32_USART1) && !defined(CONFIG_USART1_RXDMA)
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# undef SERIAL_HAVE_ONLY_DMA
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#elif defined(CONFIG_STM32_USART2) && !defined(CONFIG_USART2_RXDMA)
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# undef SERIAL_HAVE_ONLY_DMA
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#elif defined(CONFIG_STM32_USART3) && !defined(CONFIG_USART3_RXDMA)
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# undef SERIAL_HAVE_ONLY_DMA
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#elif defined(CONFIG_STM32_UART4) && !defined(CONFIG_USART4_RXDMA)
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# undef SERIAL_HAVE_ONLY_DMA
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#elif defined(CONFIG_STM32_UART5) && !defined(CONFIG_USART5_RXDMA)
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# undef SERIAL_HAVE_ONLY_DMA
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#elif defined(CONFIG_STM32_USART6) && !defined(CONFIG_USART6_RXDMA)
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# undef SERIAL_HAVE_ONLY_DMA
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#endif
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/************************************************************************************
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* Public Types
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@@ -57,8 +214,41 @@
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* Public Data
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************************************************************************************/
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#ifndef __ASSEMBLY__
|
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#undef EXTERN
|
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#if defined(__cplusplus)
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#define EXTERN extern "C"
|
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extern "C" {
|
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#else
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#define EXTERN extern
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#endif
|
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/************************************************************************************
|
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* Public Functions
|
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************************************************************************************/
|
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/****************************************************************************
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* Name: stm32_serial_dma_poll
|
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*
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* Description:
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* Must be called periodically if any STM32 UART is configured for DMA.
|
||||
* The DMA callback is triggered for each fifo size/2 bytes, but this can
|
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* result in some bytes being transferred but not collected if the incoming
|
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* data is not a whole multiple of half the FIFO size.
|
||||
*
|
||||
* May be safely called from either interrupt or thread context.
|
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*
|
||||
****************************************************************************/
|
||||
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#ifdef SERIAL_HAVE_DMA
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EXTERN void stm32_serial_dma_poll(void);
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#endif
|
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|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
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#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_STC_STM32_STM32_UART_H */
|
||||
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@@ -94,6 +94,7 @@ struct stm32_dma_s
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uint8_t irq; /* DMA stream IRQ number */
|
||||
uint8_t shift; /* ISR/IFCR bit shift value */
|
||||
uint8_t channel; /* DMA channel number (0-7) */
|
||||
bool nonstop; /* Stream is configured in a non-stopping mode. */
|
||||
sem_t sem; /* Used to wait for DMA channel to become available */
|
||||
uint32_t base; /* DMA register channel base address */
|
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dma_callback_t callback; /* Callback invoked when the DMA completes */
|
||||
@@ -429,9 +430,20 @@ static int stm32_dmainterrupt(int irq, void *context)
|
||||
|
||||
status = (dmabase_getreg(dmast, regoffset) >> dmast->shift) & DMA_STREAM_MASK;
|
||||
|
||||
/* Disable the DMA stream */
|
||||
/* Clear fetched stream interrupts by setting bits in the upper or lower IFCR
|
||||
* register
|
||||
*/
|
||||
|
||||
stm32_dmastreamdisable(dmast);
|
||||
if (stream < 4)
|
||||
{
|
||||
regoffset = STM32_DMA_LIFCR_OFFSET;
|
||||
}
|
||||
else
|
||||
{
|
||||
regoffset = STM32_DMA_HIFCR_OFFSET;
|
||||
}
|
||||
|
||||
dmabase_putreg(dmast, regoffset, (status << dmast->shift));
|
||||
|
||||
/* Invoke the callback */
|
||||
|
||||
@@ -636,11 +648,15 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
||||
/* "Set the memory address in the DMA_SM0ARx ... register. The data will be
|
||||
* written to or read from this memory after the peripheral event."
|
||||
*
|
||||
* Note that only single-buffer mode is currently supported so SM1ARx
|
||||
* is not used."
|
||||
* Note that in double-buffered mode it is explicitly assumed that the second
|
||||
* buffer immediately follows the first.
|
||||
*/
|
||||
|
||||
dmast_putreg(dmast, STM32_DMA_SM0AR_OFFSET, maddr);
|
||||
if (scr & DMA_SCR_DBM)
|
||||
{
|
||||
dmast_putreg(dmast, STM32_DMA_SM1AR_OFFSET, maddr + ntransfers);
|
||||
}
|
||||
|
||||
/* "Configure the total number of data items to be transferred in the
|
||||
* DMA_SNDTRx register. After each peripheral event, this value will be
|
||||
@@ -677,28 +693,42 @@ void stm32_dmasetup(DMA_HANDLE handle, uint32_t paddr, uint32_t maddr,
|
||||
* generated when the stream is enabled, then the stream will be automatically
|
||||
* disabled."
|
||||
*
|
||||
* The FIFO is disabled in circular mode when transferring data from a
|
||||
* peripheral to memory, as in this case it is usually desirable to know that
|
||||
* every byte from the peripheral is transferred immediately to memory. It is
|
||||
* not practical to flush the DMA FIFO, as this requires disabling the channel
|
||||
* which triggers the transfer-complete interrupt.
|
||||
*
|
||||
* NOTE: The FEIFx error interrupt is not enabled because the FEIFx seems to
|
||||
* be reported spuriously causing good transfers to be marked as failures.
|
||||
*/
|
||||
|
||||
regval = dmast_getreg(dmast, STM32_DMA_SFCR_OFFSET);
|
||||
regval &= ~(DMA_SFCR_FTH_MASK | DMA_SFCR_FS_MASK | DMA_SFCR_FEIE);
|
||||
regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS);
|
||||
if (!((scr & (DMA_SCR_CIRC | DMA_SCR_DIR_MASK)) == (DMA_SCR_CIRC | DMA_SCR_DIR_P2M)))
|
||||
{
|
||||
regval |= (DMA_SFCR_FTH_FULL | DMA_SFCR_DMDIS);
|
||||
}
|
||||
dmast_putreg(dmast, STM32_DMA_SFCR_OFFSET, regval);
|
||||
|
||||
/* "Configure data transfer direction, circular mode, peripheral & memory
|
||||
* incremented mode, peripheral & memory data size, and interrupt after
|
||||
* half and/or full transfer in the DMA_CCRx register."
|
||||
*
|
||||
* Note: The CT bit is always reset.
|
||||
*/
|
||||
|
||||
regval = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
|
||||
regval &= ~(DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
|
||||
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
|
||||
DMA_SCR_CIRC|DMA_SCR_DBM|DMA_SCR_CT|
|
||||
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
|
||||
scr &= (DMA_SCR_PFCTRL|DMA_SCR_DIR_MASK|DMA_SCR_PINC|DMA_SCR_MINC|
|
||||
DMA_SCR_PSIZE_MASK|DMA_SCR_MSIZE_MASK|DMA_SCR_PINCOS|
|
||||
DMA_SCR_DBM|DMA_SCR_CIRC|
|
||||
DMA_SCR_PBURST_MASK|DMA_SCR_MBURST_MASK);
|
||||
regval |= scr;
|
||||
dmast->nonstop = (scr & (DMA_SCR_DBM|DMA_SCR_CIRC)) != 0;
|
||||
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, regval);
|
||||
}
|
||||
|
||||
@@ -734,14 +764,28 @@ void stm32_dmastart(DMA_HANDLE handle, dma_callback_t callback, void *arg, bool
|
||||
scr = dmast_getreg(dmast, STM32_DMA_SCR_OFFSET);
|
||||
scr |= DMA_SCR_EN;
|
||||
|
||||
/* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
|
||||
* set and an interrupt is generated if the Half-Transfer Interrupt Enable
|
||||
* bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag
|
||||
* (TCIF) is set and an interrupt is generated if the Transfer Complete
|
||||
* Interrupt Enable bit (TCIE) is set.
|
||||
*/
|
||||
if (!dmast->nonstop)
|
||||
{
|
||||
/* Once half of the bytes are transferred, the half-transfer flag (HTIF) is
|
||||
* set and an interrupt is generated if the Half-Transfer Interrupt Enable
|
||||
* bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag
|
||||
* (TCIF) is set and an interrupt is generated if the Transfer Complete
|
||||
* Interrupt Enable bit (TCIE) is set.
|
||||
*/
|
||||
|
||||
scr |= (half ? (DMA_SCR_HTIE|DMA_SCR_TEIE) : (DMA_SCR_TCIE|DMA_SCR_TEIE));
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In nonstop mode, when the transfer completes it immediately resets
|
||||
* and starts again. The transfer-complete interrupt is thus always
|
||||
* enabled, and the half-complete interrupt can be used in circular
|
||||
* mode to determine when the buffer is half-full, or in double-buffered
|
||||
* mode to determine when one of the two buffers is full.
|
||||
*/
|
||||
scr |= (half ? DMA_SCR_HTIE : 0) | DMA_SCR_TCIE | DMA_SCR_TEIE;
|
||||
}
|
||||
|
||||
scr |= (half ? (DMA_SCR_HTIE|DMA_SCR_TEIE) : (DMA_SCR_TCIE|DMA_SCR_TEIE));
|
||||
dmast_putreg(dmast, STM32_DMA_SCR_OFFSET, scr);
|
||||
}
|
||||
|
||||
@@ -764,6 +808,38 @@ void stm32_dmastop(DMA_HANDLE handle)
|
||||
stm32_dmastreamdisable(dmast);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmaresidual
|
||||
*
|
||||
* Description:
|
||||
* Read the DMA bytes-remaining register.
|
||||
*
|
||||
* Assumptions:
|
||||
* - DMA handle allocated by stm32_dmachannel()
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
size_t stm32_dmaresidual(DMA_HANDLE handle)
|
||||
{
|
||||
struct stm32_dma_s *dmast = (struct stm32_dma_s *)handle;
|
||||
uint32_t residual;
|
||||
|
||||
/* Fetch the count of bytes remaining to be transferred.
|
||||
*
|
||||
* If the FIFO is enabled, this count may be inaccurate. ST don't
|
||||
* appear to document whether this counts the peripheral or the memory
|
||||
* side of the channel, and they don't make the memory pointer
|
||||
* available either.
|
||||
*
|
||||
* For reception in circular mode the FIFO is disabled in order that
|
||||
* this value can be useful.
|
||||
*/
|
||||
|
||||
residual = dmast_getreg(dmast, STM32_DMA_SNDTR_OFFSET);
|
||||
|
||||
return (size_t)residual;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dmasample
|
||||
*
|
||||
|
||||
@@ -660,7 +660,7 @@ config PIC32MX_UART2PRIO
|
||||
---help---
|
||||
UART 2. Range 4-31, Default 16.
|
||||
|
||||
config PIC32MX_CN
|
||||
config PIC32MX_CNPRIO
|
||||
int "CN"
|
||||
default 16
|
||||
depends on PIC32MX_CN
|
||||
|
||||
Reference in New Issue
Block a user