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Xtensa: Add more exception vectors. All just cause a PANIC now.
This commit is contained in:
Gregory Nutt
@@ -1,136 +0,0 @@
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/****************************************************************************
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* arch/xtensa/src/common/xtensa_nmi_handler.S
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*
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* Adapted from use in NuttX by:
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Derives from logic originally provided by Cadence Design Systems Inc.
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*
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* Copyright (c) 2006-2015 Cadence Design Systems Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
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* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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****************************************************************************/
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.file "xtensa_nmi_handler.S"
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/* NOTES on the use of 'call0' for long jumps instead of 'j':
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*
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* 1. This file should be assembled with the -mlongcalls option to xt-xcc.
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*
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* 2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
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* a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the
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* distance from the call to the destination. The linker then relaxes
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* it back to 'call0 dest' if it determines that dest is within range.
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* This allows more flexibility in locating code without the performance
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* overhead of the 'l32r' literal data load in cases where the destination
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* is in range of 'call0'. There is an additional benefit in that 'call0'
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* has a longer range than 'j' due to the target being word-aligned, so
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* the 'l32r' sequence is less likely needed.
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*
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* 3. The use of 'call0' with -mlongcalls requires that register a0 not be
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* live at the time of the call, which is always the case for a function
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* call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
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*
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* 4. This use of 'call0' is independent of the C function call ABI.
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*/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <arch/irq.h>
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#include <arch/chip/core-isa.h>
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#include <arch/xtensa/xtensa_specregs.h>
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#include "chip_macros.h"
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#include "xtensa_abi.h"
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/****************************************************************************
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* Assembly Language Macros
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* HIGH PRIORITY NMI LOW-LEVEL HANDLER
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*
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* High priority interrupts are by definition those with priorities greater
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* than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
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* interrupts cannot interact with the RTOS, that is they must save all regs
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* they use and not call any RTOS function.
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*
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* A further restriction imposed by the Xtensa windowed architecture is that
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* high priority interrupts must not modify the stack area even logically
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* "above" the top of the interrupted stack (they need to provide their
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* own stack or static save area).
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*
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* Cadence Design Systems recommends high priority interrupt handlers be
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* coded in assembly and used for purposes requiring very short service
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* times.
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*
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* The NMI vector goes at a predetermined location according to the Xtensa
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* hardware configuration, which is ensured by its placement in a special
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* section known to the Xtensa linker support package (LSP). It performs
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* the minimum necessary before jumping to the NMI andler.
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*
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* Below is a template for the high priority NMI interrupt handler.
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* A template and example can be found in the Cadence Design Systems tools
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* documentation: "Microprocessor Programmer's Guide".
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*
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****************************************************************************/
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#if XCHAL_HAVE_NMI
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.section HANDLER_SECTION, "ax"
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.type _xtensa_nmi, @function
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.align 4
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_xtensa_nmi:
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#if 1
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/* For now, just panic */
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mov a0, sp /* sp == a1 */
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addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */
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s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */
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rsr a0, EPS_2 /* Save interruptee's PS */
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s32i a0, sp, (4 * REG_PS)
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rsr a0, EPC_2 /* Save interruptee's PC */
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s32i a0, sp, (4 * REG_PC)
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rsr a0, EXCSAVE_2 /* Save interruptee's a0 */
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s32i a0, sp, (4 * REG_A0)
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s32i a2, sp, (4 * REG_A2)
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movi a2, XTENSA_NMI_EXCEPTION /* Address of state save on stack */
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call0 _xtensa_panic /* Does not return */
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#else
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/* Add high priority non-maskable interrupt (NMI) handler code here. */
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rsr a0, EXCSAVE + XCHAL_NMILEVEL /* Restore a0 */
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rfi XCHAL_NMILEVEL
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#endif
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#endif /* XCHAL_HAVE_NMI */
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@@ -64,7 +64,7 @@
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#include <arch/xtensa/xtensa_specregs.h>
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/****************************************************************************
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* Assembly Language Marcros
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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@@ -111,7 +111,7 @@ _xtensa_panic:
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/* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
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mov a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
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movi a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
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wsr a0, PS
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/* Call C panic handler: Arg1 (A2) = Exception code; Arg 2 (A3) = start
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@@ -48,15 +48,14 @@
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****************************************************************************/
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/****************************************************************************
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* C Prototype:
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* void _xtensa_levelN_vector(void)
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* Name: _xtensa_level[n]_vector, n=2..6
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*
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* Description:
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* Xtensa interrupt vectors. Each vector goes at a predetermined location
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* according to the Xtensa hardware configuration, which is ensured by its
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* placement in a special section known to the NuttX linker script. The
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* vector logic performs the minimum necessary operations before jumping
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* to the handler.
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* Xtensa medium/nigh priority interrupt vectors. Each vector goes at a
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* predetermined location according to the Xtensa hardware configuration,
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* which is ensured by its placement in a special section known to the
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* NuttX linker script. The vector logic performs the minimum necessary
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* operations before jumping to the handler.
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*
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****************************************************************************/
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@@ -154,15 +153,26 @@ _xtensa_level6_vector:
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#endif
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/****************************************************************************
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* C Prototype:
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* void _xtensa_nmi_vector(void)
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* Exception Vectors (except User, Co-processor and window exception
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* vectors).
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*
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* Each vector goes at a predetermined location according to the Xtensa
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* hardware configuration, which is ensured by its placement in a special
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* section known to the Xtensa linker support package (LSP). It performs
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* the minimum necessary before jumping to the handler in the .text section.
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*
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* The corresponding handler goes in the normal .text section. It sets up
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* the appropriate stack frame, saves a few vector-specific registers and
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* calls _xtensa_panic() to save the rest of the interrupted context
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* and enter the NuttX panic handler
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*
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****************************************************************************/
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/****************************************************************************
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* Name: _xtensa_nmi_vector
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*
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* Description:
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* Xtensa NMI vectors. This vector goes at a predetermined location
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* according to the Xtensa hardware configuration, which is ensured by its
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* placement in a special section known to the NuttX linker script. The
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* vector logic performs the minimum necessary operations before jumping
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* to the handler.
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* NMI Exception
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*
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****************************************************************************/
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@@ -175,11 +185,141 @@ _xtensa_level6_vector:
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_xtensa_nmi_vector:
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wsr a0, EXCSAVE + XCHAL_NMILEVEL /* Preserve a0 */
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call0 _xtensa_nmi /* Load interrupt handler */
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#if 1
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/* For now, just panic */
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/* Never returns here - call0 is used as a jump */
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wsr a0, EXCSAVE + XCHAL_NMILEVEL /* Preserve a0 */
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mov a0, sp /* sp == a1 */
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addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */
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s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */
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rsr a0, EPS + XCHAL_NMILEVEL /* Save interruptee's PS */
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s32i a0, sp, (4 * REG_PS)
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rsr a0, EPC_2 /* Save interruptee's PC */
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s32i a0, sp, (4 * REG_PC)
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rsr a0, EXCSAVE + XCHAL_NMILEVEL /* Save interruptee's a0 */
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s32i a0, sp, (4 * REG_A0)
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s32i a2, sp, (4 * REG_A2)
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movi a2, XTENSA_NMI_EXCEPTION /* Address of state save on stack */
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call0 _xtensa_panic /* Does not return */
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#else
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/* Add high priority non-maskable interrupt (NMI) handler code here. */
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rfi XCHAL_NMILEVEL
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#endif
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.size _xtensa_nmi_vector, . - _xtensa_nmi_vector
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.end literal_prefix
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/****************************************************************************
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* Name: _debug_exception_vector
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*
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* Description:
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* Debug exception vector
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*
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****************************************************************************/
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#if XCHAL_HAVE_DEBUG
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.begin literal_prefix .debug_exception_vector
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.section .debug_exception_vector.text, "ax"
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.global _debug_exception_vector
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.align 4
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_debug_exception_vector:
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mov a0, sp /* sp == a1 */
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addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */
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s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */
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rsr a0, EPS + XCHAL_DEBUGLEVEL /* Save interruptee's PS */
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s32i a0, sp, (4 * REG_PS)
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rsr a0, EPC + XCHAL_DEBUGLEVEL /* Save interruptee's PC */
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s32i a0, sp, (4 * REG_PC)
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rsr a0, EXCSAVE + XCHAL_DEBUGLEVEL /* Save interruptee's a0 */
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s32i a0, sp, (4 * REG_A0)
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s32i a2, sp, (4 * REG_A2)
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movi a2, XTENSA_DEBUG_EXCEPTION /* Address of state save on stack */
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call0 _xtensa_panic /* Does not return */
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.end literal_prefix
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#endif /* XCHAL_HAVE_DEBUG */
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/****************************************************************************
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* Name: _double_exception_vector
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*
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* Description:
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* Double Exception Vector. Double exceptions are not a normal occurrence.
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* They indicate a bug of some kind.
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*
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****************************************************************************/
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#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
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.begin literal_prefix .double_exception_vector
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.section .double_exception_vector.text, "ax"
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.global _double_exception_vector
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.align 4
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_double_exception_vector:
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#if XCHAL_HAVE_DEBUG
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break 1, 4 /* Unhandled double exception */
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#endif
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mov a0, sp /* sp == a1 */
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addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */
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s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */
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rsr a0, EPS_1 /* Save interruptee's PS -- REVISIT */
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s32i a0, sp, (4 * REG_PS)
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rsr a0, DEPC /* Save interruptee's PC */
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s32i a0, sp, (4 * REG_PC)
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rsr a0, EXCSAVE_1 /* Save interruptee's a0 -- REVISIT */
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s32i a0, sp, (4 * REG_A0)
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s32i a2, sp, (4 * REG_A2)
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movi a2, XTENSA_DOUBLE_EXCEPTION /* Address of state save on stack */
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call0 _xtensa_panic /* Does not return */
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.end literal_prefix
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#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */
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/****************************************************************************
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* Name: _kernel_exception_vector
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*
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* Description:
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* Kernel Exception (including Level 1 Interrupt from kernel mode).
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*
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****************************************************************************/
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.begin literal_prefix .kernel_exception_vector
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.section .kernel_exception_vector.text, "ax"
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.global _kernel_exception_vector
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.align 4
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_kernel_exception_vector:
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#if XCHAL_HAVE_DEBUG
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break 1, 0 /* Unhandled kernel exception */
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#endif
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mov a0, sp /* sp == a1 */
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addi sp, sp, -(4 * XCPTCONTEXT_SIZE) /* Allocate interrupt stack frame */
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s32i a0, sp, (4 * REG_A1) /* Save pre-interrupt SP */
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rsr a0, EPS_1 /* Save interruptee's PS */
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s32i a0, sp, (4 * REG_PS)
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rsr a0, EPC_1 /* Save interruptee's PC */
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s32i a0, sp, (4 * REG_PC)
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rsr a0, EXCSAVE_1 /* Save interruptee's a0 */
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s32i a0, sp, (4 * REG_A0)
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s32i a2, sp, (4 * REG_A2)
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movi a2, XTENSA_KERNEL_EXCEPTION /* Address of state save on stack */
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call0 _xtensa_panic /* Does not return */
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.end literal_prefix
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#endif
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@@ -41,7 +41,7 @@ HEAD_CSRC = esp32_start.c
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# Common XTENSA files (arch/xtensa/src/common)
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CMN_ASRCS = xtensa_context.S xtensa_coproc.S xtensa_cpuint.S
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CMN_ASRCS += xtensa_int_handlers.S xtensa_nmi_handler.S xtensa_vectors.S
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CMN_ASRCS += xtensa_int_handlers.S xtensa_panic.S xtensa_vectors.S
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CMN_CSRCS = xtensa_assert.c xtensa_blocktask.c xtensa_copystate.c
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CMN_CSRCS += xtensa_cpenable.c xtensa_createstack.c xtensa_exit.c xtensa_idle.c
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@@ -29,15 +29,15 @@ SECTIONS
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. = 0x240;
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KEEP(*(.xtensa_level5_vector.text));
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. = 0x280;
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KEEP(*(.DebugExceptionVector.text));
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KEEP(*(.debug_exception_vector.text));
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. = 0x2c0;
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KEEP(*(.nmi_vector.text));
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. = 0x300;
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KEEP(*(.KernelExceptionVector.text));
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KEEP(*(.kernel_exception_vector.text));
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. = 0x340;
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KEEP(*(.UserExceptionVector.text));
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. = 0x3C0;
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KEEP(*(.DoubleExceptionVector.text));
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KEEP(*(.double_exception_vector.text));
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. = 0x400;
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*(.*Vector.literal)
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