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Fix the coding style and typo issue

Browse Source 
Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
anjiahao
2022-09-06 14:18:45 +08:00
committed by Masayuki Ishikawa
parent d07792a343
commit a4563b8744
148 changed files with 1747 additions and 1744 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/cxd56xx/cxd56_adc.c
+1 -1
View File
@@ -173,7 +173,7 @@ struct cxd56adc_dev_s
uint8_t fifomode; /* fifo mode */
struct scufifo_wm_s *wm; /* water mark */
struct math_filter_s *filter; /* math filter */
struct scuev_notify_s * notify; /* notify */
struct scuev_notify_s *notify; /* notify */
mutex_t lock; /* exclusive mutex */
int crefs; /* reference count */
};
arch/arm/src/cxd56xx/cxd56_dmac.c
+7
View File
@@ -292,6 +292,10 @@ struct dma_channel_s
static struct dma_channel_s g_dmach[NCHANNELS];
static mutex_t g_dmalock = NXMUTEX_INITIALIZER;
/****************************************************************************
* Private Functions
****************************************************************************/
static int dma_init(int ch);
static int dma_uninit(int ch);
static int dma_open(int ch);
@@ -328,6 +332,7 @@ static struct dmac_register_map *get_device(int ch)
case 2: return (struct dmac_register_map *)DMAC2_REG_BASE;
case 3: return (struct dmac_register_map *)DMAC3_REG_BASE;
}
return NULL;
}
@@ -335,7 +340,9 @@ static struct dmac_ch_register_map *get_channel(int ch)
{
struct dmac_register_map *dev = get_device(ch);
if (dev == NULL)
{
return NULL;
}
if (is_dmac(2, dev))
{
arch/arm/src/cxd56xx/cxd56_emmc.c
+1 -3
View File
@@ -935,13 +935,11 @@ static int cxd56_emmc_geometry(struct inode *inode,
int cxd56_emmcinitialize(void)
{
struct cxd56_emmc_state_s *priv;
struct cxd56_emmc_state_s *priv = &g_emmcdev;
uint8_t *buf;
struct emmc_dma_desc_s *descs;
int ret;
priv = &g_emmcdev;
ret = emmc_hwinitialize();
if (ret != OK)
{
arch/arm/src/cxd56xx/cxd56_geofence.c
+1 -1
View File
@@ -550,7 +550,7 @@ static int cxd56_geofence_poll(struct file *filep,
struct pollfd *fds,
bool setup)
{
struct inode * inode;
struct inode *inode;
struct cxd56_geofence_dev_s *priv;
int ret = OK;
int i;
arch/arm/src/cxd56xx/cxd56_gnss.c
+4 -4
View File
@@ -161,7 +161,7 @@ struct cxd56_gnss_dev_s
uint8_t num_open;
uint8_t notify_data;
struct file cepfp;
void * cepbuf;
void *cepbuf;
struct pollfd *fds[CONFIG_CXD56_GNSS_NPOLLWAITERS];
#if CONFIG_CXD56_GNSS_NSIGNALRECEIVERS != 0
struct cxd56_gnss_sig_s sigs[CONFIG_CXD56_GNSS_NSIGNALRECEIVERS];
@@ -2688,7 +2688,7 @@ static int cxd56_gnss_initialize(struct cxd56_gnss_dev_s *dev)
static int cxd56_gnss_open(struct file *filep)
{
struct inode * inode;
struct inode *inode;
struct cxd56_gnss_dev_s *priv;
int ret = OK;
int retry = 50;
@@ -2795,7 +2795,7 @@ success:
static int cxd56_gnss_close(struct file *filep)
{
struct inode * inode;
struct inode *inode;
struct cxd56_gnss_dev_s *priv;
int ret = OK;
@@ -2937,7 +2937,7 @@ static ssize_t cxd56_gnss_write(struct file *filep,
static int cxd56_gnss_ioctl(struct file *filep, int cmd,
unsigned long arg)
{
struct inode * inode;
struct inode *inode;
struct cxd56_gnss_dev_s *priv;
int ret;
arch/arm/src/cxd56xx/cxd56_hostif.c
+1 -3
View File
@@ -442,9 +442,7 @@ static int hif_initialize(struct hostif_buff_s *buffer)
cxd56_iccinit(CXD56_PROTO_HOSTIF);
ret = cxd56_iccregisterhandler(CXD56_PROTO_HOSTIF, hif_rxhandler, NULL);
return ret;
return cxd56_iccregisterhandler(CXD56_PROTO_HOSTIF, hif_rxhandler, NULL);
}
/****************************************************************************
arch/arm/src/cxd56xx/cxd56_spi.c
+4 -4
View File
@@ -179,7 +179,7 @@ static struct cxd56_spidev_s g_spi4dev =
{
.spidev =
{
&g_spi4ops
.ops = &g_spi4ops,
},
.spibase = CXD56_IMG_SPI_BASE,
.spibasefreq = 0,
@@ -226,7 +226,7 @@ static struct cxd56_spidev_s g_spi5dev =
{
.spidev =
{
&g_spi5ops
.ops = &g_spi5ops,
},
.spibase = CXD56_IMG_WSPI_BASE,
.spibasefreq = 0,
@@ -272,7 +272,7 @@ static struct cxd56_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.spibase = CXD56_SPIM_BASE,
.spibasefreq = 0,
@@ -318,7 +318,7 @@ static struct cxd56_spidev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.spibase = CXD56_SCU_SPI_BASE,
.spibasefreq = 0,
arch/arm/src/cxd56xx/cxd56_uart0.c
+1 -9
View File
@@ -231,15 +231,7 @@ static ssize_t uart0_write(struct file *filep,
int cxd56_uart0initialize(const char *devname)
{
int ret;
ret = register_driver(devname, &g_uart0fops, 0666, NULL);
if (ret != 0)
{
return ERROR;
}
return OK;
return register_driver(devname, &g_uart0fops, 0666, NULL);
}
/****************************************************************************
arch/arm/src/efm32/efm32_i2c.c
+1 -1
View File
@@ -742,7 +742,7 @@ static void efm32_i2c_setclock(struct efm32_i2c_priv_s *priv,
#elif defined(CONFIG_EFM32_I2C_CLHR_ASYMMETRIC)
# define n (6 + 3) /* Ratio is 6:3 */
#else /* CLHR STANDARD */
# define n ( 4 + 4) /* Ratio is 4:4 */
# define n (4 + 4) /* Ratio is 4:4 */
#endif
div = (BOARD_HFPERCLK_FREQUENCY - (4 * frequency)) / (n * frequency);
arch/arm/src/gd32f4/gd32f4xx_spi.c
+1 -1
View File
@@ -294,7 +294,7 @@ static struct gd32_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops
},
.spibase = GD32_SPI0,
.spiclock = GD32_PCLK2_FREQUENCY,
arch/arm/src/imxrt/imxrt_ehci.c
+7 -7
View File
@@ -4978,19 +4978,19 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
/* Sanity checks */
DEBUGASSERT(controller == 0);
DEBUGASSERT(((uintptr_t) & g_asynchead & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_asynchead & 0x1f) == 0);
DEBUGASSERT((sizeof(struct imxrt_qh_s) & 0x1f) == 0);
DEBUGASSERT((sizeof(struct imxrt_qtd_s) & 0x1f) == 0);
# ifdef CONFIG_IMXRT_EHCI_PREALLOCATE
DEBUGASSERT(((uintptr_t) & g_qhpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t) & g_qtdpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_qhpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_qtdpool & 0x1f) == 0);
# endif
# ifndef CONFIG_USBHOST_INT_DISABLE
DEBUGASSERT(((uintptr_t) & g_intrhead & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_intrhead & 0x1f) == 0);
# ifdef CONFIG_IMXRT_EHCI_PREALLOCATE
DEBUGASSERT(((uintptr_t) g_framelist & 0xfff) == 0);
DEBUGASSERT(((uintptr_t)g_framelist & 0xfff) == 0);
# endif
# endif /* CONFIG_USBHOST_INT_DISABLE */
@@ -5199,7 +5199,7 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
*/
memset(&g_asynchead, 0, sizeof(struct imxrt_qh_s));
physaddr = imxrt_physramaddr((uintptr_t) & g_asynchead);
physaddr = imxrt_physramaddr((uintptr_t)&g_asynchead);
g_asynchead.hw.hlp = imxrt_swap32(physaddr | QH_HLP_TYP_QH);
g_asynchead.hw.epchar = imxrt_swap32(QH_EPCHAR_H | QH_EPCHAR_EPS_FULL);
g_asynchead.hw.overlay.nqp = imxrt_swap32(QH_NQP_T);
@@ -5230,7 +5230,7 @@ struct usbhost_connection_s *imxrt_ehci_initialize(int controller)
/* Attach the periodic QH to Period Frame List */
physaddr = imxrt_physramaddr((uintptr_t) & g_intrhead);
physaddr = imxrt_physramaddr((uintptr_t)&g_intrhead);
for (i = 0; i < FRAME_LIST_SIZE; i++)
{
g_framelist[i] = imxrt_swap32(physaddr) | PFL_TYP_QH;
arch/arm/src/imxrt/imxrt_enc.c
+1 -1
View File
@@ -1201,7 +1201,7 @@ static int imxrt_ioctl(struct qe_lowerhalf_s *lower, int cmd,
int imxrt_qeinitialize(const char *devpath, int enc)
{
struct imxrt_enc_lowerhalf_s * priv = NULL;
struct imxrt_enc_lowerhalf_s *priv = NULL;
switch (enc)
{
arch/arm/src/imxrt/imxrt_flexspi.c
+1 -1
View File
@@ -112,7 +112,7 @@ static struct imxrt_flexspidev_s g_flexspi0dev =
{
.ops = &g_flexspi0ops,
},
.base = (struct flexspi_type_s *) IMXRT_FLEXSPIC_BASE,
.base = (struct flexspi_type_s *)IMXRT_FLEXSPIC_BASE,
.lock = NXMUTEX_INITIALIZER,
};
arch/arm/src/imxrt/imxrt_lpi2c.c
+2 -2
View File
@@ -1070,7 +1070,7 @@ static void imxrt_lpi2c_setclock(struct imxrt_lpi2c_priv_s *priv,
CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT;
lpi2c_clk_div = lpi2c_clk_div + 1;
src_freq = (BOARD_XTAL_FREQUENCY * pll3_div) /
(8 * lpi2c_clk_div) ;
(8 * lpi2c_clk_div);
}
/* LPI2C output frequency = (Source Clock (Hz)/ 2^prescale) /
@@ -1976,7 +1976,7 @@ static int imxrt_lpi2c_dma_transfer(struct imxrt_lpi2c_priv_s *priv)
LPI2C_MIER_NDIE | LPI2C_MIER_ALIE |
LPI2C_MIER_PLTIE | LPI2C_MIER_FEIE);
imxrt_dmach_start(priv->dma, imxrt_dma_callback, (void *)priv);
imxrt_dmach_start(priv->dma, imxrt_dma_callback, priv);
imxrt_lpi2c_modifyreg(priv, IMXRT_LPI2C_MDER_OFFSET, 0,
LPI2C_MDER_TDDE | LPI2C_MDER_RDDE);
arch/arm/src/imxrt/imxrt_lpspi.c
+12 -12
View File
@@ -242,7 +242,7 @@ static struct imxrt_lpspidev_s g_lpspi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = IMXRT_LPSPI1_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@@ -291,7 +291,7 @@ static struct imxrt_lpspidev_s g_lpspi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = IMXRT_LPSPI2_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@@ -340,7 +340,7 @@ static struct imxrt_lpspidev_s g_lpspi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.spibase = IMXRT_LPSPI3_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@@ -389,7 +389,7 @@ static struct imxrt_lpspidev_s g_lpspi4dev =
{
.spidev =
{
&g_spi4ops
.ops = &g_spi4ops,
},
.spibase = IMXRT_LPSPI4_BASE,
#ifdef CONFIG_IMXRT_LPSPI_INTERRUPTS
@@ -1310,8 +1310,8 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *) rxbuffer;
const uint16_t *src = txbuffer;
uint16_t *dest = rxbuffer;
uint16_t word;
while (nwords-- > 0)
@@ -1343,8 +1343,8 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint8_t word;
while (nwords-- > 0)
@@ -1362,7 +1362,7 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
/* Exchange one word */
word = (uint8_t) imxrt_lpspi_send(dev, (uint32_t) word);
word = (uint8_t)imxrt_lpspi_send(dev, word);
/* Is there a buffer to receive the return value? */
@@ -1396,9 +1396,9 @@ static void imxrt_lpspi_exchange_nodma(struct spi_dev_s *dev,
****************************************************************************/
#ifdef CONFIG_IMXRT_LPSPI_DMA
static void imxrt_lpspi_exchange(struct spi_dev_s * dev,
const void * txbuffer,
void * rxbuffer, size_t nwords)
static void imxrt_lpspi_exchange(struct spi_dev_s *dev,
const void *txbuffer,
void *rxbuffer, size_t nwords)
{
int ret;
size_t adjust;
arch/arm/src/imxrt/imxrt_serial.c
+3 -3
View File
@@ -1538,7 +1538,7 @@ static int imxrt_dma_setup(struct uart_dev_s *dev)
* worth of time to claim bytes before they are overwritten.
*/
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, (void *)priv);
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, priv);
}
#endif
@@ -2398,7 +2398,7 @@ static void imxrt_dma_reenable(struct imxrt_uart_s *priv)
* worth of time to claim bytes before they are overwritten.
*/
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, (void *)priv);
imxrt_dmach_start(priv->rxdma, imxrt_dma_rxcallback, priv);
/* Clear DMA suspended flag. */
@@ -2569,7 +2569,7 @@ static void imxrt_dma_send(struct uart_dev_s *dev)
/* Start transmission with the callback on DMA completion */
imxrt_dmach_start(priv->txdma, imxrt_dma_txcallback, (void *)priv);
imxrt_dmach_start(priv->txdma, imxrt_dma_txcallback, priv);
}
#endif
arch/arm/src/imxrt/imxrt_usdhc.c
+6 -4
View File
@@ -950,7 +950,7 @@ static void imxrt_receive(struct imxrt_dev_s *priv)
{
/* Transfer any trailing fractional word */
uint8_t *ptr = (uint8_t *) priv->buffer;
uint8_t *ptr = (uint8_t *)priv->buffer;
int i;
for (i = 0; i < priv->remaining; i++)
@@ -2244,7 +2244,8 @@ static int imxrt_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer,
* handler and DMA memory invalidation.
*/
priv->buffer = (uint32_t *) buffer; priv->remaining = nbytes;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
/* Then set up the SDIO data path */
@@ -2292,7 +2293,8 @@ static int imxrt_sendsetup(struct sdio_dev_s *dev,
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32_t *) buffer; priv->remaining = nbytes;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
/* Then set up the SDIO data path */
@@ -3039,7 +3041,7 @@ static int imxrt_dmasendsetup(struct sdio_dev_s *dev,
# endif
#endif
priv->buffer = (uint32_t *) buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = buflen;
/* Then set up the SDIO data path */
arch/arm/src/kinetis/kinetis_usbhshost.c
+6 -10
View File
@@ -4042,10 +4042,6 @@ static int kinetis_epalloc(struct usbhost_driver_s *drvr,
epinfo->xfrtype = epdesc->xfrtype;
epinfo->speed = hport->speed;
/* The iocsem semaphore is used for signaling and, hence, should not have
* priority inheritance enabled.
*/
nxsem_init(&epinfo->iocsem, 0, 0);
/* Success.. return an opaque reference to the endpoint information
@@ -5052,19 +5048,19 @@ struct usbhost_connection_s *kinetis_ehci_initialize(int controller)
/* Sanity checks */
DEBUGASSERT(controller == 0);
DEBUGASSERT(((uintptr_t) & g_asynchead & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_asynchead & 0x1f) == 0);
DEBUGASSERT((sizeof(struct kinetis_qh_s) & 0x1f) == 0);
DEBUGASSERT((sizeof(struct kinetis_qtd_s) & 0x1f) == 0);
# ifdef CONFIG_KINETIS_EHCI_PREALLOCATE
DEBUGASSERT(((uintptr_t) & g_qhpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t) & g_qtdpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_qhpool & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_qtdpool & 0x1f) == 0);
# endif
# ifndef CONFIG_USBHOST_INT_DISABLE
DEBUGASSERT(((uintptr_t) & g_intrhead & 0x1f) == 0);
DEBUGASSERT(((uintptr_t)&g_intrhead & 0x1f) == 0);
# ifdef CONFIG_KINETIS_EHCI_PREALLOCATE
DEBUGASSERT(((uintptr_t) g_framelist & 0xfff) == 0);
DEBUGASSERT(((uintptr_t)g_framelist & 0xfff) == 0);
# endif
# endif /* CONFIG_USBHOST_INT_DISABLE */
@@ -5300,7 +5296,7 @@ struct usbhost_connection_s *kinetis_ehci_initialize(int controller)
/* Attach the periodic QH to Period Frame List */
physaddr = kinetis_physramaddr((uintptr_t) & g_intrhead);
physaddr = kinetis_physramaddr((uintptr_t)&g_intrhead);
for (i = 0; i < FRAME_LIST_SIZE; i++)
{
g_framelist[i] = kinetis_swap32(physaddr) | PFL_TYP_QH;
arch/arm/src/kl/kl_spi.c
+2 -2
View File
@@ -123,7 +123,7 @@ static struct kl_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops
},
.spibase = KL_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,
@@ -156,7 +156,7 @@ static struct kl_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops
},
.spibase = KL_SPI1_BASE,
.lock = NXMUTEX_INITIALIZER,
arch/arm/src/lc823450/lc823450_dma.c
+1 -1
View File
@@ -306,7 +306,7 @@ static void dma_done(DMA_HANDLE handle, void *arg, int result)
test_done = 1;
}
void lc823450_dma_test()
void lc823450_dma_test(void)
{
int i;
for (i = 0; i < 256; i++)
arch/arm/src/lc823450/lc823450_mtd.c
-1
View File
@@ -815,7 +815,6 @@ int lc823450_mtd_uninitialize(uint32_t devno)
DEBUGASSERT(ret == OK);
nxmutex_destroy(&priv->lock);
kmm_free(g_mtdmaster[ch]);
g_mtdmaster[ch] = NULL;
arch/arm/src/lc823450/lc823450_sdc.c
+1 -1
View File
@@ -82,7 +82,7 @@
static mutex_t _sdc_lock[2] =
{
NXMUTEX_INITIALIZER,
NXMUTEX_INITIALIZER
NXMUTEX_INITIALIZER,
};
static struct sddrcfg_s _sdch0;
arch/arm/src/lc823450/lc823450_serial.c
+1 -2
View File
@@ -168,7 +168,6 @@ struct up_dev_s
DMA_HANDLE hrxdma;
DMA_HANDLE htxdma;
sem_t rxdma_wait;
sem_t rxpkt_wait;
sem_t txdma_wait;
#endif /* CONFIG_HSUART */
spinlock_t lock;
@@ -1112,7 +1111,7 @@ static void uart_rxdma_callback(DMA_HANDLE hdma, void *arg, int result)
* Name: up_hs_dmasetup
****************************************************************************/
static void up_hs_dmasetup()
static void up_hs_dmasetup(void)
{
irqstate_t flags;
arch/arm/src/lc823450/lc823450_spi.c
+1 -1
View File
@@ -128,7 +128,7 @@ static struct lc823450_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
.ops = &g_spiops
},
#ifndef CONFIG_SPI_OWNBUS
.lock = NXMUTEX_INITIALIZER,
arch/arm/src/lc823450/lc823450_usbdev.c
+3 -4
View File
@@ -560,7 +560,7 @@ static struct usbdev_req_s *lc823450_epallocreq(struct usbdev_ep_s *ep)
usbtrace(TRACE_EPALLOCREQ, ((struct lc823450_ep_s *)ep)->epphy);
privreq = (struct lc823450_req_s *)
kmm_malloc(sizeof(struct lc823450_req_s));
kmm_zalloc(sizeof(struct lc823450_req_s));
if (!privreq)
{
@@ -568,7 +568,6 @@ static struct usbdev_req_s *lc823450_epallocreq(struct usbdev_ep_s *ep)
return NULL;
}
memset(privreq, 0, sizeof(struct lc823450_req_s));
return &privreq->req;
}
@@ -1710,7 +1709,7 @@ int usbdev_unregister(struct usbdevclass_driver_s *driver)
* Name: usbdev_msc_read_enter
****************************************************************************/
void usbdev_msc_read_enter()
void usbdev_msc_read_enter(void)
{
struct lc823450_ep_s *privep;
# ifdef CONFIG_DVFS
@@ -1727,7 +1726,7 @@ void usbdev_msc_read_enter()
* Name: usbdev_msc_read_exit
****************************************************************************/
void usbdev_msc_read_exit()
void usbdev_msc_read_exit(void)
{
struct lc823450_ep_s *privep;
arch/arm/src/lpc17xx_40xx/lpc17_40_i2c.c
+4 -4
View File
@@ -139,7 +139,7 @@ static void lpc17_40_stopnext(struct lpc17_40_i2cdev_s *priv);
static int lpc17_40_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int lpc17_40_i2c_reset(struct i2c_master_s * dev);
static int lpc17_40_i2c_reset(struct i2c_master_s *dev);
#endif
/****************************************************************************
@@ -505,7 +505,7 @@ static int lpc17_40_i2c_interrupt(int irq, void *context, void *arg)
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int lpc17_40_i2c_reset(struct i2c_master_s * dev)
static int lpc17_40_i2c_reset(struct i2c_master_s *dev)
{
return OK;
}
@@ -651,9 +651,9 @@ struct i2c_master_s *lpc17_40_i2cbus_initialize(int port)
*
****************************************************************************/
int lpc17_40_i2cbus_uninitialize(struct i2c_master_s * dev)
int lpc17_40_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct lpc17_40_i2cdev_s *priv = (struct lpc17_40_i2cdev_s *) dev;
struct lpc17_40_i2cdev_s *priv = (struct lpc17_40_i2cdev_s *)dev;
/* Disable I2C */
arch/arm/src/lpc17xx_40xx/lpc17_40_spi.c
+1 -1
View File
@@ -140,7 +140,7 @@ static struct lpc17_40_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};
arch/arm/src/lpc17xx_40xx/lpc17_40_ssp.c
+3 -3
View File
@@ -178,7 +178,7 @@ static struct lpc17_40_sspdev_s g_ssp0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.sspbase = LPC17_40_SSP0_BASE,
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
@@ -214,7 +214,7 @@ static struct lpc17_40_sspdev_s g_ssp1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.sspbase = LPC17_40_SSP1_BASE,
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
@@ -250,7 +250,7 @@ static struct lpc17_40_sspdev_s g_ssp2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.sspbase = LPC17_40_SSP2_BASE,
#ifdef CONFIG_LPC17_40_SSP_INTERRUPTS
arch/arm/src/lpc2378/lpc23xx_i2c.c
+4 -4
View File
@@ -145,7 +145,7 @@ static void lpc2378_stopnext(struct lpc2378_i2cdev_s *priv);
static int lpc2378_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int lpc2378_i2c_reset(struct i2c_master_s * dev);
static int lpc2378_i2c_reset(struct i2c_master_s *dev);
#endif
/****************************************************************************
@@ -457,7 +457,7 @@ static int lpc2378_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int lpc2378_i2c_reset(struct i2c_master_s * dev)
static int lpc2378_i2c_reset(struct i2c_master_s *dev)
{
return OK;
}
@@ -614,9 +614,9 @@ struct i2c_master_s *lpc2378_i2cbus_initialize(int port)
*
****************************************************************************/
int lpc2378_i2cbus_uninitialize(struct i2c_master_s * dev)
int lpc2378_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct lpc2378_i2cdev_s *priv = (struct lpc2378_i2cdev_s *) dev;
struct lpc2378_i2cdev_s *priv = (struct lpc2378_i2cdev_s *)dev;
/* Disable I2C */
arch/arm/src/lpc2378/lpc23xx_spi.c
+1 -1
View File
@@ -159,7 +159,7 @@ static struct lpc23xx_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};
arch/arm/src/lpc31xx/lpc31_i2c.c
+4 -4
View File
@@ -115,7 +115,7 @@ static void i2c_setfrequency(struct lpc31_i2cdev_s *priv,
static int i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int i2c_reset(struct i2c_master_s * dev);
static int i2c_reset(struct i2c_master_s *dev);
#endif
/****************************************************************************
@@ -418,7 +418,7 @@ out:
static void i2c_timeout(wdparm_t arg)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) arg;
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *)arg;
irqstate_t flags = enter_critical_section();
@@ -478,7 +478,7 @@ static void i2c_hwreset(struct lpc31_i2cdev_s *priv)
static int i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count)
{
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *) dev;
struct lpc31_i2cdev_s *priv = (struct lpc31_i2cdev_s *)dev;
irqstate_t flags;
int ret;
@@ -539,7 +539,7 @@ static int i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int i2c_reset(struct i2c_master_s * dev)
static int i2c_reset(struct i2c_master_s *dev)
{
return OK;
}
arch/arm/src/lpc31xx/lpc31_spi.c
+2 -2
View File
@@ -155,7 +155,7 @@ static struct lpc31_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};
@@ -489,7 +489,7 @@ static int spi_lock(struct spi_dev_s *dev, bool lock)
static void spi_select(struct spi_dev_s *dev, uint32_t devid,
bool selected)
{
struct lpc31_spidev_s *priv = (struct lpc31_spidev_s *) dev;
struct lpc31_spidev_s *priv = (struct lpc31_spidev_s *)dev;
uint8_t slave = 0;
/* FIXME: map the devid to the SPI slave - this should really
arch/arm/src/lpc43xx/lpc43_i2c.c
+4 -4
View File
@@ -145,7 +145,7 @@ static void lpc43_i2c_setfrequency(struct lpc43_i2cdev_s *priv,
static int lpc43_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int lpc43_i2c_reset(struct i2c_master_s * dev);
static int lpc43_i2c_reset(struct i2c_master_s *dev);
#endif
/****************************************************************************
@@ -436,7 +436,7 @@ static int lpc43_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int lpc43_i2c_reset(struct i2c_master_s * dev)
static int lpc43_i2c_reset(struct i2c_master_s *dev)
{
return OK;
}
@@ -558,9 +558,9 @@ struct i2c_master_s *lpc43_i2cbus_initialize(int port)
*
****************************************************************************/
int lpc43_i2cbus_uninitialize(struct i2c_master_s * dev)
int lpc43_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *) dev;
struct lpc43_i2cdev_s *priv = (struct lpc43_i2cdev_s *)dev;
putreg32(I2C_CONCLRT_I2ENC, priv->base + LPC43_I2C_CONCLR_OFFSET);
up_disable_irq(priv->irqid);
arch/arm/src/lpc43xx/lpc43_spi.c
+1 -1
View File
@@ -131,7 +131,7 @@ static struct lpc43_spidev_s g_spidev =
{
.spidev =
{
&g_spiops
.ops = &g_spiops,
},
.lock = NXMUTEX_INITIALIZER,
};
arch/arm/src/lpc43xx/lpc43_ssp.c
+2 -2
View File
@@ -145,7 +145,7 @@ static struct lpc43_sspdev_s g_ssp0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.sspbase = LPC43_SSP0_BASE,
.sspbasefreq = BOARD_SSP0_BASEFREQ,
@@ -186,7 +186,7 @@ static struct lpc43_sspdev_s g_ssp1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.sspbase = LPC43_SSP1_BASE,
.sspbasefreq = BOARD_SSP1_BASEFREQ,
arch/arm/src/lpc54xx/lpc54_i2c_master.c
+4 -4
View File
@@ -169,7 +169,7 @@ static int lpc54_i2c_poll(struct lpc54_i2cdev_s *priv);
static int lpc54_i2c_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int lpc54_i2c_reset(struct i2c_master_s * dev);
static int lpc54_i2c_reset(struct i2c_master_s *dev);
#endif
/****************************************************************************
@@ -878,7 +878,7 @@ static int lpc54_i2c_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int lpc54_i2c_reset(struct i2c_master_s * dev)
static int lpc54_i2c_reset(struct i2c_master_s *dev)
{
#warning Missing logic
return OK;
@@ -1302,9 +1302,9 @@ struct i2c_master_s *lpc54_i2cbus_initialize(int port)
*
****************************************************************************/
int lpc54_i2cbus_uninitialize(struct i2c_master_s * dev)
int lpc54_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct lpc54_i2cdev_s *priv = (struct lpc54_i2cdev_s *) dev;
struct lpc54_i2cdev_s *priv = (struct lpc54_i2cdev_s *)dev;
uint32_t regval;
/* Disable I2C interrupts */
arch/arm/src/max326xx/max32660/max32660_spim.c
+1 -1
View File
@@ -233,7 +233,7 @@ static struct max326_spidev_s g_spi0dev =
{
.dev =
{
&g_sp0iops
.ops = &g_sp0iops,
},
.base = MAX326_SPI0_BASE,
.lock = NXMUTEX_INITIALIZER,
arch/arm/src/nrf52/nrf52_rng.c
+2 -2
View File
@@ -145,7 +145,7 @@ static int nrf52_rng_initialize(void)
static int nrf52_rng_irqhandler(int irq, void *context, void *arg)
{
struct rng_dev_s *priv = (struct rng_dev_s *) &g_rngdev;
struct rng_dev_s *priv = (struct rng_dev_s *)&g_rngdev;
uint8_t *addr;
if (getreg32(NRF52_RNG_EVENTS_RDY) == RNG_INT_RDY)
@@ -200,7 +200,7 @@ static ssize_t nrf52_rng_read(struct file *filep, char *buffer,
return -EBUSY;
}
priv->rd_buf = (uint8_t *) buffer;
priv->rd_buf = (uint8_t *)buffer;
priv->buflen = buflen;
priv->rd_count = 0;
arch/arm/src/nrf52/nrf52_spi.c
+4 -4
View File
@@ -198,7 +198,7 @@ static struct nrf52_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.base = NRF52_SPIM0_BASE,
@@ -251,7 +251,7 @@ static struct nrf52_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.base = NRF52_SPIM1_BASE,
@@ -304,7 +304,7 @@ static struct nrf52_spidev_s g_spi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.base = NRF52_SPIM2_BASE,
@@ -357,7 +357,7 @@ static struct nrf52_spidev_s g_spi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.base = NRF52_SPIM3_BASE,
arch/arm/src/rp2040/rp2040_flash_mtd.c
+8 -8
View File
@@ -68,8 +68,8 @@
#define FLASH_BLOCK_ERASE_CMD 0x20
#define BOOT_2_SIZE 256
#define FLASH_START_OFFSET (rp2040_smart_flash_start - (uint8_t *) XIP_BASE)
#define FLASH_END_OFFSET (rp2040_smart_flash_end - (uint8_t *) XIP_BASE)
#define FLASH_START_OFFSET (rp2040_smart_flash_start - (uint8_t *)XIP_BASE)
#define FLASH_END_OFFSET (rp2040_smart_flash_end - (uint8_t *)XIP_BASE)
#define FLASH_START_READ (rp2040_smart_flash_start + 0x03000000)
/* Note: There is some ambiguity in terminology when it comes to flash.
@@ -247,7 +247,7 @@ static int rp2040_flash_erase(struct mtd_dev_s *dev,
off_t startblock,
size_t nblocks)
{
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *) dev;
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *)dev;
irqstate_t flags;
int ret = OK;
@@ -293,7 +293,7 @@ static ssize_t rp2040_flash_block_read(struct mtd_dev_s *dev,
size_t nblocks,
uint8_t *buffer)
{
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *) dev;
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *)dev;
int start;
int length;
int ret = OK;
@@ -336,7 +336,7 @@ static ssize_t rp2040_flash_block_write(struct mtd_dev_s *dev,
size_t nblocks,
const uint8_t *buffer)
{
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *) dev;
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *)dev;
irqstate_t flags;
int ret;
@@ -443,7 +443,7 @@ static int rp2040_flash_ioctl(struct mtd_dev_s *dev,
int cmd,
unsigned long arg)
{
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *) dev;
rp2040_flash_dev_t *rp_dev = (rp2040_flash_dev_t *)dev;
int ret = OK;
UNUSED(rp_dev);
@@ -452,7 +452,7 @@ static int rp2040_flash_ioctl(struct mtd_dev_s *dev,
{
case MTDIOC_GEOMETRY:
{
struct mtd_geometry_s *geo = (struct mtd_geometry_s *) arg;
struct mtd_geometry_s *geo = (struct mtd_geometry_s *)arg;
if (geo != NULL)
{
@@ -525,7 +525,7 @@ struct mtd_dev_s *rp2040_flash_mtd_initialize(void)
* the rom until after this call completes.
*/
memcpy(my_dev.boot_2, (void *) XIP_BASE, BOOT_2_SIZE);
memcpy(my_dev.boot_2, (void *)XIP_BASE, BOOT_2_SIZE);
rom_functions.flash_enable_xip = (flash_enable_xip_f)my_dev.boot_2 + 1;
/* Do we need to initialize the flash? */
arch/arm/src/rp2040/rp2040_i2s.c
+2 -2
View File
@@ -1095,7 +1095,7 @@ static int rp2040_i2s_ioctl(struct i2s_dev_s *dev, int cmd,
{
i2sinfo("AUDIOIOC_ALLOCBUFFER\n");
bufdesc = (struct audio_buf_desc_s *) arg;
bufdesc = (struct audio_buf_desc_s *)arg;
ret = apb_alloc(bufdesc);
}
break;
@@ -1109,7 +1109,7 @@ static int rp2040_i2s_ioctl(struct i2s_dev_s *dev, int cmd,
{
i2sinfo("AUDIOIOC_FREEBUFFER\n");
bufdesc = (struct audio_buf_desc_s *) arg;
bufdesc = (struct audio_buf_desc_s *)arg;
DEBUGASSERT(bufdesc->u.buffer != NULL);
apb_free(bufdesc->u.buffer);
ret = sizeof(struct audio_buf_desc_s);
arch/arm/src/rp2040/rp2040_spi.c
+2 -3
View File
@@ -178,7 +178,7 @@ static struct rp2040_spidev_s g_spi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.spibase = RP2040_SPI0_BASE,
.spibasefreq = 0,
@@ -227,7 +227,7 @@ static struct rp2040_spidev_s g_spi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = RP2040_SPI1_BASE,
.spibasefreq = 0,
@@ -874,7 +874,6 @@ struct spi_dev_s *rp2040_spibus_initialize(int port)
/* Set a initialized flag */
priv->initialized = 1;
return &priv->spidev;
}
arch/arm/src/s32k1xx/s32k1xx_lpi2c.c
+2 -2
View File
@@ -1776,8 +1776,8 @@ static int s32k1xx_lpi2c_dma_transfer(struct s32k1xx_lpi2c_priv_s *priv)
LPI2C_MIER_NDIE | LPI2C_MIER_ALIE |
LPI2C_MIER_PLTIE | LPI2C_MIER_FEIE);
s32k1xx_dmach_start(priv->rxdma, s32k1xx_rxdma_callback, (void *)priv);
s32k1xx_dmach_start(priv->txdma, s32k1xx_txdma_callback, (void *)priv);
s32k1xx_dmach_start(priv->rxdma, s32k1xx_rxdma_callback, priv);
s32k1xx_dmach_start(priv->txdma, s32k1xx_txdma_callback, priv);
s32k1xx_lpi2c_modifyreg(priv, S32K1XX_LPI2C_MDER_OFFSET, 0,
LPI2C_MDER_TDDE | LPI2C_MDER_RDDE);
arch/arm/src/s32k1xx/s32k1xx_lpspi.c
+11 -11
View File
@@ -255,7 +255,7 @@ static struct s32k1xx_lpspidev_s g_lpspi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.spibase = S32K1XX_LPSPI0_BASE,
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
@@ -306,7 +306,7 @@ static struct s32k1xx_lpspidev_s g_lpspi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = S32K1XX_LPSPI1_BASE,
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
@@ -357,7 +357,7 @@ static struct s32k1xx_lpspidev_s g_lpspi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = S32K1XX_LPSPI2_BASE,
#ifdef CONFIG_S32K1XX_LPSPI_INTERRUPTS
@@ -1369,8 +1369,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
* take care of big endian mode of hardware !!
*/
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K1XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@@ -1447,8 +1447,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 32-bit or 64 bit, word size memory transfers */
const uint32_t *src = (const uint32_t *)txbuffer;
uint32_t *dest = (uint32_t *) rxbuffer;
const uint32_t *src = txbuffer;
uint32_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K1XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@@ -1528,8 +1528,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *) rxbuffer;
const uint16_t *src = txbuffer;
uint16_t *dest = rxbuffer;
uint16_t word;
while (nwords-- > 0)
@@ -1563,8 +1563,8 @@ static void s32k1xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint8_t word;
while (nwords-- > 0)
arch/arm/src/s32k3xx/s32k3xx_lpspi.c
+14 -14
View File
@@ -246,7 +246,7 @@ static struct s32k3xx_lpspidev_s g_lpspi0dev =
{
.spidev =
{
&g_spi0ops
.ops = &g_spi0ops,
},
.spibase = S32K3XX_LPSPI0_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@@ -296,7 +296,7 @@ static struct s32k3xx_lpspidev_s g_lpspi1dev =
{
.spidev =
{
&g_spi1ops
.ops = &g_spi1ops,
},
.spibase = S32K3XX_LPSPI1_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@@ -346,7 +346,7 @@ static struct s32k3xx_lpspidev_s g_lpspi2dev =
{
.spidev =
{
&g_spi2ops
.ops = &g_spi2ops,
},
.spibase = S32K3XX_LPSPI2_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@@ -396,7 +396,7 @@ static struct s32k3xx_lpspidev_s g_lpspi3dev =
{
.spidev =
{
&g_spi3ops
.ops = &g_spi3ops,
},
.spibase = S32K3XX_LPSPI3_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@@ -446,7 +446,7 @@ static struct s32k3xx_lpspidev_s g_lpspi4dev =
{
.spidev =
{
&g_spi4ops
.ops = &g_spi4ops,
},
.spibase = S32K3XX_LPSPI4_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@@ -496,7 +496,7 @@ static struct s32k3xx_lpspidev_s g_lpspi5dev =
{
.spidev =
{
&g_spi5ops
.ops = &g_spi5ops,
},
.spibase = S32K3XX_LPSPI5_BASE,
#ifdef CONFIG_S32K3XX_LPSPI_INTERRUPTS
@@ -1535,8 +1535,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
* take care of big endian mode of hardware !!
*/
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K3XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@@ -1613,8 +1613,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 32-bit or 64 bit, word size memory transfers */
const uint32_t *src = (const uint32_t *)txbuffer;
uint32_t *dest = (uint32_t *) rxbuffer;
const uint32_t *src = txbuffer;
uint32_t *dest = rxbuffer;
uint32_t word = 0x0;
#ifdef CONFIG_S32K3XX_LPSPI_DWORD
uint32_t word1 = 0x0;
@@ -1694,8 +1694,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 16-bit mode */
const uint16_t *src = (const uint16_t *)txbuffer;
uint16_t *dest = (uint16_t *) rxbuffer;
const uint16_t *src = txbuffer;
uint16_t *dest = rxbuffer;
uint16_t word;
while (nwords-- > 0)
@@ -1729,8 +1729,8 @@ static void s32k3xx_lpspi_exchange_nodma(struct spi_dev_s *dev,
{
/* 8-bit mode */
const uint8_t *src = (const uint8_t *)txbuffer;
uint8_t *dest = (uint8_t *) rxbuffer;
const uint8_t *src = txbuffer;
uint8_t *dest = rxbuffer;
uint8_t word;
while (nwords-- > 0)
arch/arm/src/sam34/sam_twi.c
+4 -4
View File
@@ -174,7 +174,7 @@ static void twi_startmessage(struct twi_dev_s *priv, struct i2c_msg_s *msg);
static int twi_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int twi_reset(struct i2c_master_s * dev);
static int twi_reset(struct i2c_master_s *dev);
#endif
/* Initialization */
@@ -747,7 +747,7 @@ static int twi_transfer(struct i2c_master_s *dev,
****************************************************************************/
#ifdef CONFIG_I2C_RESET
static int twi_reset(struct i2c_master_s * dev)
static int twi_reset(struct i2c_master_s *dev)
{
return OK;
}
@@ -982,9 +982,9 @@ struct i2c_master_s *sam_i2cbus_initialize(int bus)
*
****************************************************************************/
int sam_i2cbus_uninitialize(struct i2c_master_s * dev)
int sam_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct twi_dev_s *priv = (struct twi_dev_s *) dev;
struct twi_dev_s *priv = (struct twi_dev_s *)dev;
i2cinfo("TWI%d Un-initializing\n", priv->twi);
arch/arm/src/sama5/sam_sdmmc.c
+9 -8
View File
@@ -1111,7 +1111,7 @@ static void sam_receive(struct sam_dev_s *priv)
{
/* Transfer any trailing fractional word */
uint8_t *ptr = (uint8_t *) priv->buffer;
uint8_t *ptr = (uint8_t *)priv->buffer;
int i;
for (i = 0; i < priv->remaining; i++)
@@ -1873,7 +1873,7 @@ static void sam_frequency(struct sdio_dev_s *dev, uint32_t frequency)
static void sam_clock(struct sdio_dev_s *dev, enum sdio_clock_e rate)
{
struct sam_dev_s *priv = (struct sam_dev_s *) dev;
struct sam_dev_s *priv = (struct sam_dev_s *)dev;
uint32_t regval;
int wait_microseconds = 0;
@@ -2354,7 +2354,7 @@ static int sam_recvsetup(struct sdio_dev_s *dev, uint8_t *buffer,
* handler and DMA memory invalidation.
*/
priv->buffer = (uint32_t *) buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
/* Then set up the SDIO data path */
@@ -2408,7 +2408,8 @@ static int sam_sendsetup(struct sdio_dev_s *dev,
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32_t *) buffer; priv->remaining = nbytes;
priv->buffer = (uint32_t *)buffer;
priv->remaining = nbytes;
/* Then set up the SDIO data path */
@@ -3052,7 +3053,7 @@ static int sam_dmarecvsetup(struct sdio_dev_s *dev,
* handler
*/
priv->buffer = (uint32_t *) buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = buflen;
priv->bufferend = (uint32_t *)(buffer + buflen);
@@ -3122,7 +3123,7 @@ static int sam_dmasendsetup(struct sdio_dev_s *dev,
/* Save the source buffer information for use by the interrupt handler */
priv->buffer = (uint32_t *) buffer;
priv->buffer = (uint32_t *)buffer;
priv->remaining = buflen;
priv->bufferend = (uint32_t *)(buffer + buflen);
@@ -3610,8 +3611,8 @@ struct sdio_dev_s *sam_sdmmc_sdio_initialize(int slotno)
sam_configpio(PIO_SDMMC0_CK);
sam_configpio(PIO_SDMMC0_CMD);
# if ( defined(CONFIG_SAMA5_SDMMC0_WIDTH_D1_D4) || \
defined(CONFIG_SAMA5_SDMMC0_WIDTH_D1_D8) )
# if (defined(CONFIG_SAMA5_SDMMC0_WIDTH_D1_D4) || \
defined(CONFIG_SAMA5_SDMMC0_WIDTH_D1_D8))
sam_configpio(PIO_SDMMC0_DAT1);
sam_configpio(PIO_SDMMC0_DAT2);
sam_configpio(PIO_SDMMC0_DAT3);
arch/arm/src/sama5/sam_twi.c
+2 -2
View File
@@ -217,7 +217,7 @@ static void twi_startmessage(struct twi_dev_s *priv, struct i2c_msg_s *msg);
static int twi_transfer(struct i2c_master_s *dev,
struct i2c_msg_s *msgs, int count);
#ifdef CONFIG_I2C_RESET
static int twi_reset(struct i2c_master_s * dev);
static int twi_reset(struct i2c_master_s *dev);
#endif
/* Initialization */
@@ -1289,7 +1289,7 @@ errout_with_lock:
int sam_i2cbus_uninitialize(struct i2c_master_s *dev)
{
struct twi_dev_s *priv = (struct twi_dev_s *) dev;
struct twi_dev_s *priv = (struct twi_dev_s *)dev;
i2cinfo("TWI%d Un-initializing\n", priv->attr->twi);
arch/arm/src/samd2l2/sam_spi.c
+2 -2
View File
@@ -1174,8 +1174,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Start RX and TX DMA channels */
sam_dmastart(priv->dma_tx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_tx, spi_dma_callback, priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, priv);
/* Enable SPI to trigger the TX DMA channel */
arch/arm/src/samd5e5/sam_spi.c
+2 -2
View File
@@ -1270,8 +1270,8 @@ static void spi_exchange(struct spi_dev_s *dev, const void *txbuffer,
/* Start RX and TX DMA channels */
sam_dmastart(priv->dma_tx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, (void *)priv);
sam_dmastart(priv->dma_tx, spi_dma_callback, priv);
sam_dmastart(priv->dma_rx, spi_dma_callback, priv);
/* Enable SPI to trigger the TX DMA channel */

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