Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-06-08 01:42:58 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

EFM32: Finishes USB naming fixup. Still some missing initialization logic

Browse Source
This commit is contained in:
Gregory Nutt
2014-11-14 08:36:18 -06:00
parent 3a4e126f2d
commit a451f3b99e
4 changed files with 150 additions and 128 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/efm32/chip/efm32_usb.h
+18 -15
View File
@@ -77,16 +77,16 @@
*******************************************************************************************************************************/
/* General definitions */
#define USB_EPTYPE_CTRL (0) /* Control */
#define USB_EPTYPE_ISOC (1) /* Isochronous */
#define USB_EPTYPE_BULK (2) /* Bulk */
#define USB_EPTYPE_INTR (3) /* Interrupt */
#define EFM32_USB_EPTYPE_CTRL (0) /* Control */
#define EFM32_USB_EPTYPE_ISOC (1) /* Isochronous */
#define EFM32_USB_EPTYPE_BULK (2) /* Bulk */
#define EFM32_USB_EPTYPE_INTR (3) /* Interrupt */
#define USB_PID_DATA0 (0)
#define USB_PID_DATA2 (1)
#define USB_PID_DATA1 (2)
#define USB_PID_MDATA (3) /* Non-control */
#define USB_PID_SETUP (3) /* Control */
#define EFM32_USB_PID_DATA0 (0)
#define EFM32_USB_PID_DATA2 (1)
#define EFM32_USB_PID_DATA1 (2)
#define EFM32_USB_PID_MDATA (3) /* Non-control */
#define EFM32_USB_PID_SETUP (3) /* Control */
/* USB Register Offsets ********************************************************************************************************/
@@ -936,6 +936,7 @@
#define USB_GRSTCTL_TXFNUM_F4 (_USB_GRSTCTL_TXFNUM_F4 << 6) /* Shifted mode F4 for USB_GRSTCTL */
#define USB_GRSTCTL_TXFNUM_F5 (_USB_GRSTCTL_TXFNUM_F5 << 6) /* Shifted mode F5 for USB_GRSTCTL */
#define USB_GRSTCTL_TXFNUM_F6 (_USB_GRSTCTL_TXFNUM_F6 << 6) /* Shifted mode F6 for USB_GRSTCTL */
#define USB_GRSTCTL_TXFNUM_F(n) ((uint32_t)(n) << 6) /* TXFIFO n flush, n=0-15 */
#define USB_GRSTCTL_TXFNUM_FALL (_USB_GRSTCTL_TXFNUM_FALL << 6) /* Shifted mode FALL for USB_GRSTCTL */
#define USB_GRSTCTL_DMAREQ (0x1UL << 30) /* DMA Request Signal (host and device) */
#define _USB_GRSTCTL_DMAREQ_SHIFT 30 /* Shift value for USB_DMAREQ */
@@ -1570,13 +1571,14 @@
/* Bit fields for USB HAINT */
#define _USB_HAINT_RESETVALUE 0x00000000UL /* Default value for USB_HAINT */
#define _USB_HAINT_MASK 0x00003FFFUL /* Mask for USB_HAINT */
#define _USB_HAINT_RESETVALUE 0x00000000UL /* Default value for USB_HAINT */
#define _USB_HAINT_MASK 0x00003FFFUL /* Mask for USB_HAINT */
#define _USB_HAINT_HAINT_SHIFT 0 /* Shift value for USB_HAINT */
#define _USB_HAINT_HAINT_MASK 0x3FFFUL /* Bit mask for USB_HAINT */
#define _USB_HAINT_HAINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HAINT */
#define USB_HAINT_HAINT_DEFAULT (_USB_HAINT_HAINT_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HAINT */
#define _USB_HAINT_HAINT_SHIFT 0 /* Shift value for USB_HAINT */
#define _USB_HAINT_HAINT_MASK 0x3FFFUL /* Bit mask for USB_HAINT */
#define _USB_HAINT_HAINT_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_HAINT */
#define USB_HAINT_HAINT_DEFAULT (_USB_HAINT_HAINT_DEFAULT << 0) /* Shifted mode DEFAULT for USB_HAINT */
#define USB_HAINT(n) (1UL << ((n) + _USB_HAINT_HAINT_SHIFT)) /* Channel n interrupt */
/* Bit fields for USB HAINTMSK */
@@ -2330,6 +2332,7 @@
#define _USB_DIEPEMPMSK_DIEPEMPMSK_MASK 0xFFFFUL /* Bit mask for USB_DIEPEMPMSK */
#define _USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT 0x00000000UL /* Mode DEFAULT for USB_DIEPEMPMSK */
#define USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT (_USB_DIEPEMPMSK_DIEPEMPMSK_DEFAULT << 0) /* Shifted mode DEFAULT for USB_DIEPEMPMSK */
#define USB_DIEPEMPMSK(n) (1UL << ((n) + _USB_DIEPEMPMSK_DIEPEMPMSK_SHIFT))
/* Bit fields for USB DIEP0CTL */
arch/arm/src/efm32/efm32_usb.h
+25 -2
View File
@@ -73,7 +73,7 @@ extern "C"
#endif
/*******************************************************************************
* Name: efm32_otgfshost_initialize
* Name: efm32_usbhost_initialize
*
* Description:
* Initialize USB host device controller hardware.
@@ -99,7 +99,27 @@ extern "C"
#ifdef CONFIG_USBHOST
struct usbhost_connection_s;
FAR struct usbhost_connection_s *efm32_otgfshost_initialize(int controller);
FAR struct usbhost_connection_s *efm32_usbhost_initialize(int controller);
#endif
/***********************************************************************************
* Name: efm32_usbhost_vbusdrive
*
* Description:
* Enable/disable driving of VBUS 5V output. This function must be provided be
* each platform that implements the EFM32 OTG FS host interface
*
* Input Parameters:
* iface - For future growth to handle multiple USB host interface. Should be zero.
* enable - true: enable VBUS power; false: disable VBUS power
*
* Returned Value:
* None
*
***********************************************************************************/
#ifdef CONFIG_USBHOST
void efm32_usbhost_vbusdrive(int iface, bool enable);
#endif
/************************************************************************************
@@ -113,7 +133,10 @@ FAR struct usbhost_connection_s *efm32_otgfshost_initialize(int controller);
*
************************************************************************************/
#ifdef CONFIG_USBDEV
struct usbdev_s;
void efm32_usbsuspend(FAR struct usbdev_s *dev, bool resume);
#endif
#undef EXTERN
#if defined(__cplusplus)
arch/arm/src/efm32/efm32_usbdev.c
+8 -8
View File
@@ -1035,7 +1035,7 @@ static void efm32_txfifo_write(FAR struct efm32_ep_s *privep,
/* Get the TxFIFO for this endpoint (same as the endpoint number) */
regaddr = EFM32_USB_DFIFO_DEP(privep->epphy);
regaddr = EFM32_USB_FIFO_BASE(privep->epphy);
/* Then transfer each word to the TxFIFO */
@@ -1309,7 +1309,7 @@ static void efm32_epin_request(FAR struct efm32_usbdev_s *priv,
* n: n words available
*/
regaddr = EFM32_USB_DTXFSTS(privep->epphy);
regaddr = EFM32_USB_DIEPTXFSTS(privep->epphy);
/* Check for space in the TxFIFO. If space in the TxFIFO is not
* available, then set up an interrupt to resume the transfer when
@@ -1394,7 +1394,7 @@ static void efm32_rxfifo_read(FAR struct efm32_ep_s *privep,
* we might as well use the addess associated with EP0.
*/
regaddr = EFM32_USB_DFIFO_DEP(EP0);
regaddr = EFM32_USB_FIFO_BASE(EP0);
/* Read 32-bits and write 4 x 8-bits at time (to avoid unaligned accesses) */
@@ -1435,10 +1435,10 @@ static void efm32_rxfifo_discard(FAR struct efm32_ep_s *privep, int len)
int i;
/* Get the address of the RxFIFO Note: there is only one RxFIFO so
* we might as well use the addess associated with EP0.
* we might as well use the address associated with EP0.
*/
regaddr = EFM32_USB_DFIFO_DEP(EP0);
regaddr = EFM32_USB_FIFO_BASE(EP0);
/* Read 32-bits at time */
@@ -1790,7 +1790,7 @@ static void efm32_ep_flush(struct efm32_ep_s *privep)
{
if (privep->isin)
{
efm32_txfifo_flush(USB_GRSTCTL_TXFNUM_D(privep->epphy));
efm32_txfifo_flush(USB_GRSTCTL_TXFNUM_F(privep->epphy));
}
else
{
@@ -1954,7 +1954,7 @@ static void efm32_usbreset(struct efm32_usbdev_s *priv)
/* Flush the EP0 Tx FIFO */
efm32_txfifo_flush(USB_GRSTCTL_TXFNUM_D(EP0));
efm32_txfifo_flush(USB_GRSTCTL_TXFNUM_F(EP0));
/* Tell the class driver that we are disconnected. The class
* driver should then accept any new configurations.
@@ -4156,7 +4156,7 @@ static void efm32_epin_disable(FAR struct efm32_ep_s *privep)
/* Flush any data remaining in the TxFIFO */
efm32_txfifo_flush(USB_GRSTCTL_TXFNUM_D(privep->epphy));
efm32_txfifo_flush(USB_GRSTCTL_TXFNUM_F(privep->epphy));
/* Disable endpoint interrupts */
arch/arm/src/efm32/efm32_usbhost.c
+99 -103
View File
File diff suppressed because it is too large Load Diff