Changes from review of last PR. Mostly costmetic.

arch/arm/src/stm32f7/Kconfig

@@ -983,6 +983,10 @@ config STM32F7_SPI
 	bool
 	default n
 
+config STM32F7_TIM
+	bool
+	default n
+
 config STM32F7_USART
 	bool
 	default n
@@ -1239,62 +1243,77 @@ config STM32F7_SPI6
 config STM32F7_TIM1
 	bool "TIM1"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM2
 	bool "TIM2"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM3
 	bool "TIM3"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM4
 	bool "TIM4"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM5
 	bool "TIM5"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM6
 	bool "TIM6"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM7
 	bool "TIM7"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM8
 	bool "TIM8"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM9
 	bool "TIM9"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM10
 	bool "TIM10"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM11
 	bool "TIM11"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM12
 	bool "TIM12"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM13
 	bool "TIM13"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM14
 	bool "TIM14"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_TIM15
 	bool "TIM15"
 	default n
+	select STM32F7_TIM
 
 config STM32F7_USART1
 	bool "USART1"

arch/arm/src/stm32f7/Make.defs

@@ -114,7 +114,7 @@ endif
 CHIP_ASRCS  =
 CHIP_CSRCS  = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c
 CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c stm32_serial.c
-CHIP_CSRCS += stm32_i2c.c stm32_spi.c stm32_start.c stm32_tim.c
+CHIP_CSRCS += stm32_start.c
 
 ifneq ($(CONFIG_SCHED_TICKLESS),y)
 CHIP_CSRCS += stm32_timerisr.c
@@ -139,6 +139,18 @@ ifeq ($(CONFIG_STM32_PWR),y)
 CHIP_CSRCS += stm32_exti_pwr.c
 endif
 
+ifeq ($(CONFIG_STM32F7_I2C),y)
+CHIP_CSRCS += stm32_i2c.c
+endif
+
+ifeq ($(CONFIG_STM32F7_SPI),y)
+CHIP_CSRCS += stm32_spi.c
+endif
+
+ifeq ($(CONFIG_STM32F7_TIM),y)
+CHIP_CSRCS += stm32_tim.c
+endif
+
 ifeq ($(CONFIG_ADC),y)
 CHIP_CSRCS += stm32_adc.c
 endif
@@ -149,10 +161,6 @@ CHIP_CSRCS += stm32_exti_alarm.c
 endif
 endif
 
-ifeq ($(CONFIG_STM32F7_SPI),y)
-CHIP_CSRCS += stm32_spi.c
-endif
-
 ifeq ($(CONFIG_STM32F7_ETHMAC),y)
 CHIP_CSRCS += stm32_ethernet.c
 endif

arch/arm/src/stm32f7/chip.h

@@ -50,7 +50,6 @@
 #include <arch/stm32f7/chip.h>
 #include "chip/stm32_pinmap.h"
 #include "chip/stm32_memorymap.h"
-#include "chip/stm32_pinmap.h"
 
 /* If the common ARMv7-M vector handling logic is used, then it expects the
  * following definition in this file that provides the number of supported external

arch/arm/src/stm32f7/chip/stm32_adc.h

@@ -1,7 +1,7 @@
 /****************************************************************************************************
  * arch/arm/src/stm32f7/chip/stm32_adc.h
  *
- *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -426,7 +426,7 @@
 #define ADC_CSR_JSTRT2               (1 << 11) /* Bit 11: Injected channel Start flag of ADC2 (copy of JSTRT in ADC2_SR) */
 #define ADC_CSR_STRT2                (1 << 12) /* Bit 12: Regular channel Start flag of ADC2 (copy of STRT in ADC2_SR) */
 #define ADC_CSR_OVR2                 (1 << 13) /* Bit 13: Overrun flag of ADC2 (copy of OVR in ADC2_SR) */
-#                                          /* Bits 14-15: Reserved, must be kept at reset value. */
+                                               /* Bits 14-15: Reserved, must be kept at reset value. */
 #define ADC_CSR_AWD3                 (1 << 16) /* Bit 16: ADC3 Analog watchdog flag (copy of AWD in ADC3_SR) */
 #define ADC_CSR_EOC3                 (1 << 17) /* Bit 17: ADC3 End of conversion (copy of EOC in ADC3_SR) */
 #define ADC_CSR_JEOC3                (1 << 18) /* Bit 18: ADC3 Injected channel end of conversion (copy of JEOC in ADC3_SR) */

arch/arm/src/stm32f7/chip/stm32_i2c.h

@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/stm32f7/chip/stm32_i2c.h
  *
- *   Copyright (C) 2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without

arch/arm/src/stm32f7/chip/stm32_tim.h

@@ -1,7 +1,7 @@
 /****************************************************************************************************
  * arch/arm/src/stm32f7/chip/stm32_tim.h
  *
- *   Copyright (C) 2009, 2011-2012 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without

arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h

@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/stm32f7/chip/stm32f74xx75xx_spi.h
  *
- *   Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <gnutt@nuttx.org>
  *
  * Redistribution and use in source and binary forms, with or without
@@ -163,7 +163,7 @@
 #define SPI_CR2_TXEIE               (1 << 7)  /* Bit 7: Tx buffer empty interrupt enable */
 #define SPI_CR2_DS_SHIFT            (8)       /* Bits 8-11:  Data size */
 #define SPI_CR2_DS_MASK             (15 << SPI_CR2_DS_SHIFT)
-#  define SPI_CR2_DS_VAL(bits)    ( ((bits)-1) << SPI_CR2_DS_SHIFT)
+#  define SPI_CR2_DS_VAL(bits)      (((uint32_t)(bits)-1) << SPI_CR2_DS_SHIFT)
 #  define SPI_CR2_DS_4BIT           SPI_CR2_DS_VAL( 4)
 #  define SPI_CR2_DS_5BIT           SPI_CR2_DS_VAL( 5)
 #  define SPI_CR2_DS_6BIT           SPI_CR2_DS_VAL( 6)

arch/arm/src/stm32f7/stm32_adc.c

@@ -1622,7 +1622,7 @@ static int adc123_interrupt(int irq, FAR void *context)
  ****************************************************************************/
 
 /****************************************************************************
- * Name: stm32_adcinitialize
+ * Name: stm32_adc_initialize
  *
  * Description:
  *   Initialize the ADC.
@@ -1647,7 +1647,7 @@ static int adc123_interrupt(int irq, FAR void *context)
  *
  ****************************************************************************/
 
-struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
+struct adc_dev_s *stm32_adc_initialize(int intf, FAR const uint8_t *chanlist,
                                        int cchannels)
 {
   FAR struct adc_dev_s   *dev;

arch/arm/src/stm32f7/stm32_adc.h

@@ -1,7 +1,7 @@
 /************************************************************************************
  * arch/arm/src/stm32f7/stm32_adc.h
  *
- *   Copyright (C) 2009, 2011, 2015 Gregory Nutt. All rights reserved.
+ *   Copyright (C) 2009, 2011, 2015-2016 Gregory Nutt. All rights reserved.
  *   Copyright (C) 2015 Omni Hoverboards Inc. All rights reserved.
  *   Authors: Gregory Nutt <gnutt@nuttx.org>
  *            Paul Alexander Patience <paul-a.patience@polymtl.ca>
@@ -412,7 +412,6 @@
 #define ADC3_EXTSEL_T8TRGO     ADC_CR2_EXTSEL_T8TRGO
 #define ADC3_EXTSEL_T8TRGO2     ADC_CR2_EXTSEL_T8TRGO2
 
-
 #if defined(CONFIG_STM32F7_TIM1_ADC1)
 #  if CONFIG_STM32F7_ADC1_TIMTRIG == 0
 #    define ADC1_EXTSEL_VALUE ADC1_EXTSEL_T1CC1
@@ -729,7 +728,6 @@
  * Public Types
  ************************************************************************************/
 
-
 /************************************************************************************
  * Public Function Prototypes
  ************************************************************************************/
@@ -744,7 +742,7 @@ extern "C"
 #endif
 
 /****************************************************************************
- * Name: stm32_adcinitialize
+ * Name: stm32_adc_initialiize
  *
  * Description:
  *   Initialize the ADC.
@@ -760,7 +758,8 @@ extern "C"
  ****************************************************************************/
 
 struct adc_dev_s;
-struct adc_dev_s *stm32_adcinitialize(int intf, FAR const uint8_t *chanlist,
+struct adc_dev_s *stm32_adc_initialiize(int intf,
+                                        FAR const uint8_t *chanlist,
                                         int nchannels);
 #undef EXTERN
 #ifdef __cplusplus

arch/arm/src/stm32f7/stm32_i2c.c

@@ -726,7 +726,6 @@ static inline void stm32_i2c_enableinterrupts(struct stm32_i2c_priv_s *priv)
 }
 #endif
 
-
 /************************************************************************************
  * Name: stm32_i2c_sem_waitdone
  *
@@ -1294,6 +1293,7 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
         {
           stm32_i2c_modifyreg32(priv, STM32F7_I2C_CR1_OFFSET, 0, I2C_CR1_PE);
         }
+
       priv->frequency = frequency;
     }
 }
@@ -1327,7 +1327,6 @@ static void stm32_i2c_setclock(FAR struct stm32_i2c_priv_s *priv, uint32_t frequ
 
 static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
 {
-
   /* Flag the first byte as an address byte */
 
   priv->astart = true;
@@ -1371,11 +1370,14 @@ static inline void stm32_i2c_sendstart(FAR struct stm32_i2c_priv_s *priv)
    * it otherwise.
    */
 
-  if ((priv->flags & I2C_M_NORESTART) || priv->dcnt > 255) {
+  if ((priv->flags & I2C_M_NORESTART) || priv->dcnt > 255)
+    {
       i2cerr("RELOAD enabled: dcnt = %i msgc = %i\n",
           priv->dcnt, priv->msgc);
       stm32_i2c_enable_reload(priv);
-  } else {
+    }
+  else
+    {
       i2cerr("RELOAD disable: dcnt = %i msgc = %i\n",
           priv->dcnt, priv->msgc);
       stm32_i2c_disable_reload(priv);
@@ -1487,7 +1489,6 @@ static inline void stm32_i2c_clearinterrupts(struct stm32_i2c_priv_s *priv)
 
 static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 {
-
   uint32_t status;
 
   /* Get state of the I2C controller */
@@ -1547,7 +1548,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
           i2cinfo("NACK: Address invalid: dcnt=%i msgc=%i status=0x%08x\n",
           priv->dcnt, priv->msgc, status);
           stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
-
         }
       else
         {
@@ -1556,7 +1556,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
           i2cinfo("NACK: NACK received: dcnt=%i msgc=%i status=0x%08x\n",
           priv->dcnt, priv->msgc, status);
           stm32_i2c_traceevent(priv, I2CEVENT_ADDRESS_NACKED, priv->msgv->addr);
-
         }
 
       /* Set flags to terminate message transmission:
@@ -1570,7 +1569,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
       priv->dcnt = -1;
       priv->msgc = 0;
-
     }
 
   /* Transmit Interrupt Status (TXIS) Handler
@@ -1630,7 +1628,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
       if (priv->dcnt > 0)
         {
-
           /* Prepare to transmit the current byte */
 
           stm32_i2c_traceevent(priv, I2CEVENT_WRITE_TO_DR, priv->dcnt);
@@ -1642,18 +1639,17 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
           /* If we are about to transmit the last byte in the current message */
 
-	  if (priv->dcnt == 0) {
+          if (priv->dcnt == 0)
-
+            {
               /* If this is also the last message to send, disable RELOAD so
                * TC fires next and issues STOP condition.  If we don't do this
                * TCR will fire next, and since there are no bytes to send we
                * can't write NBYTES to clear TCR so it will fire forever.
                */
 
-	      if ((priv->msgc - 1) == 0) {
+              if ((priv->msgc - 1) == 0)
-
+                {
                   stm32_i2c_disable_reload(priv);
-
                 }
             }
 
@@ -1664,7 +1660,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
           /* Advance to next byte */
 
           priv->ptr++;
-
         }
       else
         {
@@ -1673,15 +1668,12 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
           i2cerr("TXIS: UNSUPPORTED STATE DETECTED, dcnt=%i, status 0x%08x\n",
           priv->dcnt, status);
           stm32_i2c_traceevent(priv, I2CEVENT_WRITE_ERROR, 0);
-
         }
 
       i2cinfo("TXIS: EXIT  dcnt = %i msgc = %i status 0x%08x\n",
               priv->dcnt, priv->msgc, status);
-
     }
 
-
   /* Receive Buffer Not Empty (RXNE) State Handler
    *
    * This branch is only triggered when the RXNE interrupt occurs.  This
@@ -1726,7 +1718,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
       if (priv->dcnt > 0)
         {
-
           stm32_i2c_traceevent(priv, I2CEVENT_RCVBYTE, priv->dcnt);
 
           /* No interrupts or context switches may occur in the following
@@ -1753,11 +1744,9 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 #ifdef CONFIG_I2C_POLLED
           leave_critical_section(state);
 #endif
-
         }
       else
         {
-
           /* Unsupported state */
 
           stm32_i2c_traceevent(priv, I2CEVENT_READ_ERROR, 0);
@@ -1769,7 +1758,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
           priv->dcnt = -1;
           priv->msgc = 0;
-
         }
 
       i2cinfo("RXNE: EXIT  dcnt = %i msgc = %i status 0x%08x\n",
@@ -1816,8 +1804,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
       /* if additional messages remain to be transmitted / received */
 
-	if (priv->msgc > 0) {
+      if (priv->msgc > 0)
-
+        {
           i2cinfo("TC: RESTART: dcnt=%i, msgc=%i\n",
           priv->dcnt, priv->msgc);
           stm32_i2c_traceevent(priv, I2CEVENT_TC_NO_RESTART, priv->msgc);
@@ -1836,8 +1824,9 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
           stm32_i2c_sendstart(priv);
 
-	} else {
+        }
-
+      else
+        {
           /* Issue a STOP conditions.
            *
            * No additional messages to transmit / receive, so the
@@ -1855,15 +1844,12 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
           priv->dcnt = -1;
           priv->msgc = 0;
-
         }
 
       i2cinfo("TC: EXIT dcnt = %i msgc = %i status 0x%08x\n",
       priv->dcnt, priv->msgc, status);
-
     }
 
-
   /* Transfer Complete (Reload) State Handler
    *
    * This branch is only triggered when the TCR interrupt occurs.  This
@@ -1906,8 +1892,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
 
       /* If no more bytes in the current message to transfer */
 
-	if (priv->dcnt == 0) {
+      if (priv->dcnt == 0)
-
+        {
           /* Prior message has been sent successfully */
 
           priv->msgc--;
@@ -1925,7 +1911,8 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
           /* if this is the last message, disable reload so the
            * TC event fires next time */
 
-	    if (priv->msgc == 0) {
+          if (priv->msgc == 0)
+            {
               i2cinfo("TCR: DISABLE RELOAD: dcnt = %i msgc = %i\n",
               priv->dcnt, priv->msgc);
 
@@ -1938,16 +1925,16 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
                   priv->dcnt, priv->msgc);
 
           stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
-
+        }
-	} else {
+      else
-
+        {
           /* More bytes in the current (greater than 255 byte payload
            * length) message, so set NBYTES according to the bytes
            * remaining in the message, up to a maximum each cycle of 255.
            */
 
-	    if (priv->dcnt > 255) {
+          if (priv->dcnt > 255)
-
+            {
               i2cinfo("TCR: ENABLE RELOAD: NBYTES = 255 dcnt = %i msgc = %i\n",
               priv->dcnt, priv->msgc);
 
@@ -1964,9 +1951,9 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
               stm32_i2c_enable_reload(priv);
 
               stm32_i2c_set_bytes_to_transfer(priv, 255);
-
+            }
-	    } else {
+          else
-
+            {
               /* Less than 255 bytes left to transfer, which means we'll
                * complete the transfer of all bytes in the current message
                * the next time around.
@@ -1983,7 +1970,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
               stm32_i2c_disable_reload(priv);
 
               stm32_i2c_set_bytes_to_transfer(priv, priv->dcnt);
-
             }
 
           i2cinfo("TCR: EXIT dcnt = %i msgc = %i status 0x%08x\n",
@@ -2080,7 +2066,6 @@ static int stm32_i2c_isr(struct stm32_i2c_priv_s *priv)
           priv->intstate = INTSTATE_DONE;
         }
 #endif
-
     }
 
   status = stm32_i2c_getreg32(priv, STM32F7_I2C_ISR_OFFSET);
@@ -2172,7 +2157,6 @@ static int stm32_i2c_init(FAR struct stm32_i2c_priv_s *priv)
     }
 
 #ifndef CONFIG_I2C_POLLED
-
   /* Attach error and event interrupts to the ISRs */
 
   irq_attach(priv->config->ev_irq, priv->config->isr);
@@ -2231,7 +2215,6 @@ static int stm32_i2c_deinit(FAR struct stm32_i2c_priv_s *priv)
   return OK;
 }
 
-
 /************************************************************************************
  * Name: stm32_i2c_process
  *
@@ -2283,7 +2266,6 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
   priv->status = 0;
 
 #ifndef CONFIG_I2C_POLLED
-
   /* Enable transmit and receive interrupts here so when we send the start
    * condition below the ISR will fire if the data was sent and some
    * response from the slave received.  All other interrupts relevant to
@@ -2423,7 +2405,6 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
 
   else if ((status & I2C_ISR_BUSY) != 0)
     {
-
       /* I2C Bus Busy
        *
        * This is a status condition rather than an error.
@@ -2446,6 +2427,7 @@ static int stm32_i2c_process(FAR struct i2c_master_s *dev, FAR struct i2c_msg_s
               errval = EBUSY;
               break;
             }
+
           status = stm32_i2c_getstatus(priv);
         }
     }
@@ -2713,5 +2695,4 @@ out:
 }
 #endif /* CONFIG_I2C_RESET */
 
-
 #endif /* CONFIG_STM32F7_I2C1 || CONFIG_STM32F7_I2C2 || CONFIG_STM32F7_I2C3 */

configs/stm32f746-ws/src/stm32_boot.c

@@ -75,7 +75,6 @@ void stm32_boardinitialize(void)
       stm32_spidev_initialize();
     }
 #endif
-
 }
 
 /************************************************************************************

configs/stm32f746-ws/src/stm32_spi.c

@@ -57,23 +57,6 @@
     defined(CONFIG_STM32F7_SPI3) || defined(CONFIG_STM32F7_SPI4) || \
     defined(CONFIG_STM32F7_SPI5) || defined(CONFIG_STM32F7_SPI6)
 
-/************************************************************************************
- * Pre-processor Definitions
- ************************************************************************************/
-
-#ifdef CONFIG_DEBUG_SPI
-#  define spidbg  lldbg
-#  ifdef SPI_VERBOSE
-#    define spivdbg lldbg
-#  else
-#    define spivdbg(x...)
-#  endif
-#else
-#  undef SPI_VERBOSE
-#  define spidbg(x...)
-#  define spivdbg(x...)
-#endif
-
 /************************************************************************************
  * Public Functions
  ************************************************************************************/