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https://github.com/apache/nuttx.git
synced 2026-06-06 16:50:55 +08:00
Adding PWR, RTC, BBSRAM for stm32f7
This commit is contained in:
David Sidrane
@@ -1195,6 +1195,10 @@ config STM32F7_QUADSPI
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bool "QuadSPI"
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default n
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config STM32F7_PWR
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bool "PWR"
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default n
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config STM32F7_RNG
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bool "RNG"
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default n
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@@ -1794,6 +1798,63 @@ config SDMMC2_WIDTH_D1_ONLY
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endmenu # "SDMMC2 Configuration"
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if STM32F7_BKPSRAM
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config STM32F7_BBSRAM
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bool "BBSRAM File Support"
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default n
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config STM32F7_BBSRAM_FILES
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int "Max Files to support in BBSRAM"
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default 4
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config STM32F7_SAVE_CRASHDUMP
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bool "Enable Saving Panic to BBSRAM"
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default n
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endif # STM32F7_BKPSRAM
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config STM32F7_HAVE_RTC_COUNTER
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bool
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default n
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config STM32F7_HAVE_RTC_SUBSECONDS
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bool
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default n
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config RTC_MAGIC_REG
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int "The BKP register used to store/check the Magic value to determine if RTC is set already"
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default 0
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range 0 31
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depends on RTC && !STM32F7_HAVE_RTC_COUNTER
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config RTC_MAGIC
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hex "Value used as Magic to determine if RTC is set already"
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default 0xfacefeee
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depends on RTC && !STM32F7_HAVE_RTC_COUNTER
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choice
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prompt "RTC clock source"
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default STM32F7_RTC_LSECLOCK
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depends on RTC
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config STM32F7_RTC_HSECLOCK
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bool "HSE clock"
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---help---
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Drive the RTC with the HSE clock, divided down to 1MHz.
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config STM32F7_RTC_LSECLOCK
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bool "LSE clock"
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---help---
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Drive the RTC with the LSE clock
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config STM32F7_RTC_LSICLOCK
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bool "LSI clock"
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---help---
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Drive the RTC with the LSI clock
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endchoice #"RTC clock source"
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config STM32F7_CUSTOM_CLOCKCONFIG
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bool "Custom clock configuration"
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default n
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@@ -135,8 +135,18 @@ ifeq ($(CONFIG_STM32F7_DMA),y)
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CHIP_CSRCS += stm32_dma.c
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endif
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ifeq ($(CONFIG_STM32_PWR),y)
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CHIP_CSRCS += stm32_exti_pwr.c
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ifeq ($(CONFIG_STM32F7_PWR),y)
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CHIP_CSRCS += stm32_pwr.c stm32_exti_pwr.c
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endif
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ifeq ($(CONFIG_RTC),y)
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CHIP_CSRCS += stm32_rtc.c
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ifeq ($(CONFIG_RTC_ALARM),y)
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CHIP_CSRCS += stm32_exti_alarm.c
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endif
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ifeq ($(CONFIG_RTC_DRIVER),y)
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CHIP_CSRCS += stm32_rtc_lowerhalf.c
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endif
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endif
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ifeq ($(CONFIG_STM32F7_I2C),y)
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@@ -180,3 +190,7 @@ endif
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ifeq ($(CONFIG_DEBUG_FEATURES),y)
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CHIP_CSRCS += stm32_dumpgpio.c
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endif
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ifeq ($(CONFIG_STM32F7_BBSRAM),y)
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CHIP_CSRCS += stm32_bbsram.c
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endif
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@@ -0,0 +1,405 @@
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/************************************************************************************
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* arch/arm/src/stm32f7/chip/stm32_rtcc.h.h
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*
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* Copyright (C) 2011-2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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* David Sidrane <david_s5@nscdg.com>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H
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#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Register Offsets *****************************************************************/
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#define STM32_RTC_TR_OFFSET 0x0000 /* RTC time register */
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#define STM32_RTC_DR_OFFSET 0x0004 /* RTC date register */
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#define STM32_RTC_CR_OFFSET 0x0008 /* RTC control register */
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#define STM32_RTC_ISR_OFFSET 0x000c /* RTC initialization and status register */
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#define STM32_RTC_PRER_OFFSET 0x0010 /* RTC prescaler register */
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#define STM32_RTC_WUTR_OFFSET 0x0014 /* RTC wakeup timer register */
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#define STM32_RTC_ALRMAR_OFFSET 0x001c /* RTC alarm A register */
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#define STM32_RTC_ALRMBR_OFFSET 0x0020 /* RTC alarm B register */
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#define STM32_RTC_WPR_OFFSET 0x0024 /* RTC write protection register */
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#define STM32_RTC_SSR_OFFSET 0x0028 /* RTC sub second register */
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#define STM32_RTC_SHIFTR_OFFSET 0x002c /* RTC shift control register */
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#define STM32_RTC_TSTR_OFFSET 0x0030 /* RTC time stamp time register */
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#define STM32_RTC_TSDR_OFFSET 0x0034 /* RTC time stamp date register */
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#define STM32_RTC_TSSSR_OFFSET 0x0038 /* RTC timestamp sub second register */
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#define STM32_RTC_CALR_OFFSET 0x003c /* RTC calibration register */
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#define STM32_RTC_TAMPCR_OFFSET 0x0040 /* RTC tamper configuration register */
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#define STM32_RTC_ALRMASSR_OFFSET 0x0044 /* RTC alarm A sub second register */
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#define STM32_RTC_ALRMBSSR_OFFSET 0x0048 /* RTC alarm B sub second register */
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#define STM32_RTC_OR_OFFSET 0x004c /* RTC option register */
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#define STM32_RTC_BKR_OFFSET(n) (0x0050+((n)<<2))
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#define STM32_RTC_BK0R_OFFSET 0x0050 /* RTC backup register 0 */
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#define STM32_RTC_BK1R_OFFSET 0x0054 /* RTC backup register 1 */
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#define STM32_RTC_BK2R_OFFSET 0x0058 /* RTC backup register 2 */
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#define STM32_RTC_BK3R_OFFSET 0x005c /* RTC backup register 3 */
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#define STM32_RTC_BK4R_OFFSET 0x0060 /* RTC backup register 4 */
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#define STM32_RTC_BK5R_OFFSET 0x0064 /* RTC backup register 5 */
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#define STM32_RTC_BK6R_OFFSET 0x0068 /* RTC backup register 6 */
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#define STM32_RTC_BK7R_OFFSET 0x006c /* RTC backup register 7 */
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#define STM32_RTC_BK8R_OFFSET 0x0070 /* RTC backup register 8 */
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#define STM32_RTC_BK9R_OFFSET 0x0074 /* RTC backup register 9 */
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#define STM32_RTC_BK10R_OFFSET 0x0078 /* RTC backup register 10 */
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#define STM32_RTC_BK11R_OFFSET 0x007c /* RTC backup register 11 */
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#define STM32_RTC_BK12R_OFFSET 0x0080 /* RTC backup register 12 */
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#define STM32_RTC_BK13R_OFFSET 0x0084 /* RTC backup register 13 */
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#define STM32_RTC_BK14R_OFFSET 0x0088 /* RTC backup register 14 */
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#define STM32_RTC_BK15R_OFFSET 0x008c /* RTC backup register 15 */
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#define STM32_RTC_BK16R_OFFSET 0x0090 /* RTC backup register 16 */
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#define STM32_RTC_BK17R_OFFSET 0x0094 /* RTC backup register 17 */
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#define STM32_RTC_BK18R_OFFSET 0x0098 /* RTC backup register 18 */
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#define STM32_RTC_BK19R_OFFSET 0x009c /* RTC backup register 19 */
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#define STM32_RTC_BK20R_OFFSET 0x00a0 /* RTC backup register 20 */
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#define STM32_RTC_BK21R_OFFSET 0x00a4 /* RTC backup register 21 */
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#define STM32_RTC_BK22R_OFFSET 0x00a8 /* RTC backup register 22 */
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#define STM32_RTC_BK23R_OFFSET 0x00ac /* RTC backup register 23 */
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#define STM32_RTC_BK24R_OFFSET 0x00b0 /* RTC backup register 24 */
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#define STM32_RTC_BK25R_OFFSET 0x00b4 /* RTC backup register 25 */
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#define STM32_RTC_BK26R_OFFSET 0x00b8 /* RTC backup register 26 */
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#define STM32_RTC_BK27R_OFFSET 0x00bc /* RTC backup register 27 */
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#define STM32_RTC_BK28R_OFFSET 0x00c0 /* RTC backup register 28 */
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#define STM32_RTC_BK29R_OFFSET 0x00c4 /* RTC backup register 29 */
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#define STM32_RTC_BK30R_OFFSET 0x00c8 /* RTC backup register 30 */
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#define STM32_RTC_BK31R_OFFSET 0x00cc /* RTC backup register 31 */
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/* Register Addresses ***************************************************************/
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#define STM32_RTC_TR (STM32_RTC_BASE+STM32_RTC_TR_OFFSET)
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#define STM32_RTC_DR (STM32_RTC_BASE+STM32_RTC_DR_OFFSET)
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#define STM32_RTC_CR (STM32_RTC_BASE+STM32_RTC_CR_OFFSET)
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#define STM32_RTC_ISR (STM32_RTC_BASE+STM32_RTC_ISR_OFFSET)
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#define STM32_RTC_PRER (STM32_RTC_BASE+STM32_RTC_PRER_OFFSET)
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#define STM32_RTC_WUTR (STM32_RTC_BASE+STM32_RTC_WUTR_OFFSET)
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#define STM32_RTC_ALRMAR (STM32_RTC_BASE+STM32_RTC_ALRMAR_OFFSET)
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#define STM32_RTC_ALRMBR (STM32_RTC_BASE+STM32_RTC_ALRMBR_OFFSET)
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#define STM32_RTC_WPR (STM32_RTC_BASE+STM32_RTC_WPR_OFFSET)
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#define STM32_RTC_SSR (STM32_RTC_BASE+STM32_RTC_SSR_OFFSET)
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#define STM32_RTC_SHIFTR (STM32_RTC_BASE+STM32_RTC_SHIFTR_OFFSET)
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#define STM32_RTC_TSTR (STM32_RTC_BASE+STM32_RTC_TSTR_OFFSET)
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#define STM32_RTC_TSDR (STM32_RTC_BASE+STM32_RTC_TSDR_OFFSET)
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#define STM32_RTC_TSSSR (STM32_RTC_BASE+STM32_RTC_TSSSR_OFFSET)
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#define STM32_RTC_CALR (STM32_RTC_BASE+STM32_RTC_CALR_OFFSET)
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#define STM32_RTC_TAMPCR (STM32_RTC_BASE+STM32_RTC_TAMPCR_OFFSET)
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#define STM32_RTC_ALRMASSR (STM32_RTC_BASE+STM32_RTC_ALRMASSR_OFFSET)
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#define STM32_RTC_ALRMBSSR (STM32_RTC_BASE+STM32_RTC_ALRMBSSR_OFFSET)
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#define STM32_RTC_BKR(n) (STM32_RTC_BASE+STM32_RTC_BKR_OFFSET(n))
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#define STM32_RTC_BK0R (STM32_RTC_BASE+STM32_RTC_BK0R_OFFSET)
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#define STM32_RTC_BK1R (STM32_RTC_BASE+STM32_RTC_BK1R_OFFSET)
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#define STM32_RTC_BK2R (STM32_RTC_BASE+STM32_RTC_BK2R_OFFSET)
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#define STM32_RTC_BK3R (STM32_RTC_BASE+STM32_RTC_BK3R_OFFSET)
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#define STM32_RTC_BK4R (STM32_RTC_BASE+STM32_RTC_BK4R_OFFSET)
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#define STM32_RTC_BK5R (STM32_RTC_BASE+STM32_RTC_BK5R_OFFSET)
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#define STM32_RTC_BK6R (STM32_RTC_BASE+STM32_RTC_BK6R_OFFSET)
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#define STM32_RTC_BK7R (STM32_RTC_BASE+STM32_RTC_BK7R_OFFSET)
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#define STM32_RTC_BK8R (STM32_RTC_BASE+STM32_RTC_BK8R_OFFSET)
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#define STM32_RTC_BK9R (STM32_RTC_BASE+STM32_RTC_BK9R_OFFSET)
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#define STM32_RTC_BK10R (STM32_RTC_BASE+STM32_RTC_BK10R_OFFSET)
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#define STM32_RTC_BK11R (STM32_RTC_BASE+STM32_RTC_BK11R_OFFSET)
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#define STM32_RTC_BK12R (STM32_RTC_BASE+STM32_RTC_BK12R_OFFSET)
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#define STM32_RTC_BK13R (STM32_RTC_BASE+STM32_RTC_BK13R_OFFSET)
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#define STM32_RTC_BK14R (STM32_RTC_BASE+STM32_RTC_BK14R_OFFSET)
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#define STM32_RTC_BK15R (STM32_RTC_BASE+STM32_RTC_BK15R_OFFSET)
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#define STM32_RTC_BK16R (STM32_RTC_BASE+STM32_RTC_BK16R_OFFSET)
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#define STM32_RTC_BK17R (STM32_RTC_BASE+STM32_RTC_BK17R_OFFSET)
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#define STM32_RTC_BK18R (STM32_RTC_BASE+STM32_RTC_BK18R_OFFSET)
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#define STM32_RTC_BK19R (STM32_RTC_BASE+STM32_RTC_BK19R_OFFSET)
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#define STM32_RTC_BK20R (STM32_RTC_BASE+STM32_RTC_BK20R_OFFSET)
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#define STM32_RTC_BK21R (STM32_RTC_BASE+STM32_RTC_BK21R_OFFSET)
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#define STM32_RTC_BK22R (STM32_RTC_BASE+STM32_RTC_BK22R_OFFSET)
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#define STM32_RTC_BK23R (STM32_RTC_BASE+STM32_RTC_BK23R_OFFSET)
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#define STM32_RTC_BK24R (STM32_RTC_BASE+STM32_RTC_BK24R_OFFSET)
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#define STM32_RTC_BK25R (STM32_RTC_BASE+STM32_RTC_BK25R_OFFSET)
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#define STM32_RTC_BK26R (STM32_RTC_BASE+STM32_RTC_BK26R_OFFSET)
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#define STM32_RTC_BK27R (STM32_RTC_BASE+STM32_RTC_BK27R_OFFSET)
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#define STM32_RTC_BK28R (STM32_RTC_BASE+STM32_RTC_BK28R_OFFSET)
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#define STM32_RTC_BK29R (STM32_RTC_BASE+STM32_RTC_BK29R_OFFSET)
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#define STM32_RTC_BK30R (STM32_RTC_BASE+STM32_RTC_BK30R_OFFSET)
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#define STM32_RTC_BK31R (STM32_RTC_BASE+STM32_RTC_BK31R_OFFSET)
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#define STM32_RTC_BKCOUNT 32
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/* Register Bitfield Definitions ****************************************************/
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/* RTC time register */
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#define RTC_TR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format */
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#define RTC_TR_SU_MASK (15 << RTC_TR_SU_SHIFT)
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#define RTC_TR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format */
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#define RTC_TR_ST_MASK (7 << RTC_TR_ST_SHIFT)
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#define RTC_TR_MNU_SHIFT (8) /* Bit 8-11: Minute units in BCD format */
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#define RTC_TR_MNU_MASK (15 << RTC_TR_MNU_SHIFT)
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#define RTC_TR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format */
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#define RTC_TR_MNT_MASK (7 << RTC_TR_MNT_SHIFT)
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#define RTC_TR_HU_SHIFT (16) /* Bit 16-19: Hour units in BCD format */
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#define RTC_TR_HU_MASK (15 << RTC_TR_HU_SHIFT)
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#define RTC_TR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format */
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#define RTC_TR_HT_MASK (3 << RTC_TR_HT_SHIFT)
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#define RTC_TR_PM (1 << 22) /* Bit 22: AM/PM notation */
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#define RTC_TR_RESERVED_BITS (0xff808080)
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/* RTC date register */
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#define RTC_DR_DU_SHIFT (0) /* Bits 0-3: Date units in BCD format */
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#define RTC_DR_DU_MASK (15 << RTC_DR_DU_SHIFT)
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#define RTC_DR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
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#define RTC_DR_DT_MASK (3 << RTC_DR_DT_SHIFT)
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#define RTC_DR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
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#define RTC_DR_MU_MASK (15 << RTC_DR_MU_SHIFT)
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#define RTC_DR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
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#define RTC_DR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
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#define RTC_DR_WDU_MASK (7 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_MONDAY (1 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_TUESDAY (2 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_WEDNESDAY (3 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_THURSDAY (4 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_FRIDAY (5 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_SATURDAY (6 << RTC_DR_WDU_SHIFT)
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# define RTC_DR_WDU_SUNDAY (7 << RTC_DR_WDU_SHIFT)
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#define RTC_DR_YU_SHIFT (16) /* Bits 16-19: Year units in BCD format */
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#define RTC_DR_YU_MASK (15 << RTC_DR_YU_SHIFT)
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#define RTC_DR_YT_SHIFT (20) /* Bits 20-23: Year tens in BCD format */
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#define RTC_DR_YT_MASK (15 << RTC_DR_YT_SHIFT)
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#define RTC_DR_RESERVED_BITS (0xff0000c0)
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/* RTC control register */
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#define RTC_CR_WUCKSEL_SHIFT (0) /* Bits 0-2: Wakeup clock selection */
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#define RTC_CR_WUCKSEL_MASK (7 << RTC_CR_WUCKSEL_SHIFT)
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# define RTC_CR_WUCKSEL_RTCDIV16 (0 << RTC_CR_WUCKSEL_SHIFT) /* 000: RTC/16 clock is selected */
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# define RTC_CR_WUCKSEL_RTCDIV8 (1 << RTC_CR_WUCKSEL_SHIFT) /* 001: RTC/8 clock is selected */
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# define RTC_CR_WUCKSEL_RTCDIV4 (2 << RTC_CR_WUCKSEL_SHIFT) /* 010: RTC/4 clock is selected */
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# define RTC_CR_WUCKSEL_RTCDIV2 (3 << RTC_CR_WUCKSEL_SHIFT) /* 011: RTC/2 clock is selected */
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# define RTC_CR_WUCKSEL_CKSPRE (4 << RTC_CR_WUCKSEL_SHIFT) /* 10x: ck_spre clock is selected */
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# define RTC_CR_WUCKSEL_CKSPREADD (6 << RTC_CR_WUCKSEL_SHIFT) /* 11x: ck_spr clock and 216 added WUT counter */
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#define RTC_CR_TSEDGE (1 << 3) /* Bit 3: Timestamp event active edge */
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#define RTC_CR_REFCKON (1 << 4) /* Bit 4: Reference clock detection enable (50 or 60 Hz) */
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#define RTC_CR_BYPSHAD (1 << 5) /* Bit 5: Bypass the shadow registers */
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#define RTC_CR_FMT (1 << 6) /* Bit 6: Hour format */
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#define RTC_CR_ALRAE (1 << 8) /* Bit 8: Alarm A enable */
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#define RTC_CR_ALRBE (1 << 9) /* Bit 9: Alarm B enable */
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#define RTC_CR_WUTE (1 << 10) /* Bit 10: Wakeup timer enable */
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#define RTC_CR_TSE (1 << 11) /* Bit 11: Time stamp enable */
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#define RTC_CR_ALRAIE (1 << 12) /* Bit 12: Alarm A interrupt enable */
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#define RTC_CR_ALRBIE (1 << 13) /* Bit 13: Alarm B interrupt enable */
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#define RTC_CR_WUTIE (1 << 14) /* Bit 14: Wakeup timer interrupt enable */
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#define RTC_CR_TSIE (1 << 15) /* Bit 15: Timestamp interrupt enable */
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#define RTC_CR_ADD1H (1 << 16) /* Bit 16: Add 1 hour (summer time change) */
|
||||
#define RTC_CR_SUB1H (1 << 17) /* Bit 17: Subtract 1 hour (winter time change) */
|
||||
#define RTC_CR_BKP (1 << 18) /* Bit 18: Backup */
|
||||
#define RTC_CR_COSEL (1 << 19) /* Bit 19 : Calibration output selection */
|
||||
#define RTC_CR_POL (1 << 20) /* Bit 20: Output polarity */
|
||||
#define RTC_CR_OSEL_SHIFT (21) /* Bits 21-22: Output selection */
|
||||
#define RTC_CR_OSEL_MASK (3 << RTC_CR_OSEL_SHIFT)
|
||||
# define RTC_CR_OSEL_DISABLED (0 << RTC_CR_OSEL_SHIFT) /* 00: Output disabled */
|
||||
# define RTC_CR_OSEL_ALRMA (1 << RTC_CR_OSEL_SHIFT) /* 01: Alarm A output enabled */
|
||||
# define RTC_CR_OSEL_ALRMB (2 << RTC_CR_OSEL_SHIFT) /* 10: Alarm B output enabled */
|
||||
# define RTC_CR_OSEL_WUT (3 << RTC_CR_OSEL_SHIFT) /* 11: Wakeup output enabled */
|
||||
#define RTC_CR_COE (1 << 23) /* Bit 23: Calibration output enable */
|
||||
#define RTC_CR_ITSE (1 << 24) /* Bit 24: Timestamp on internal event enable */
|
||||
|
||||
/* RTC initialization and status register */
|
||||
|
||||
#define RTC_ISR_ALRAWF (1 << 0) /* Bit 0: Alarm A write flag */
|
||||
#define RTC_ISR_ALRBWF (1 << 1) /* Bit 1: Alarm B write flag */
|
||||
#define RTC_ISR_WUTWF (1 << 2) /* Bit 2: Wakeup timer write flag */
|
||||
#define RTC_ISR_SHPF (1 << 3) /* Bit 3: Shift operation pending */
|
||||
#define RTC_ISR_INITS (1 << 4) /* Bit 4: Initialization status flag */
|
||||
#define RTC_ISR_RSF (1 << 5) /* Bit 5: Registers synchronization flag */
|
||||
#define RTC_ISR_INITF (1 << 6) /* Bit 6: Initialization flag */
|
||||
#define RTC_ISR_INIT (1 << 7) /* Bit 7: Initialization mode */
|
||||
#define RTC_ISR_ALRAF (1 << 8) /* Bit 8: Alarm A flag */
|
||||
#define RTC_ISR_ALRBF (1 << 9) /* Bit 9: Alarm B flag */
|
||||
#define RTC_ISR_WUTF (1 << 10) /* Bit 10: Wakeup timer flag */
|
||||
#define RTC_ISR_TSF (1 << 11) /* Bit 11: Timestamp flag */
|
||||
#define RTC_ISR_TSOVF (1 << 12) /* Bit 12: Timestamp overflow flag */
|
||||
#define RTC_ISR_TAMP1F (1 << 13) /* Bit 13: Tamper detection flag */
|
||||
#define RTC_ISR_TAMP2F (1 << 14) /* Bit 14: TAMPER2 detection flag */
|
||||
#define RTC_ISR_TAMP3F (1 << 15) /* Bit 15: TAMPER3 detection flag */
|
||||
#define RTC_ISR_RECALPF (1 << 16) /* Bit 16: Recalibration pending Flag */
|
||||
#define RTC_ISR_ITSF (1 << 17) /* Bit 17:Internal tTime-stamp flagg */
|
||||
#define RTC_ISR_ALLFLAGS (0x0003ffff)
|
||||
|
||||
/* RTC prescaler register */
|
||||
|
||||
#define RTC_PRER_PREDIV_S_SHIFT (0) /* Bits 0-14: Synchronous prescaler factor */
|
||||
#define RTC_PRER_PREDIV_S_MASK (0x7fff << RTC_PRER_PREDIV_S_SHIFT)
|
||||
#define RTC_PRER_PREDIV_A_SHIFT (16) /* Bits 16-22: Asynchronous prescaler factor */
|
||||
#define RTC_PRER_PREDIV_A_MASK (0x7f << RTC_PRER_PREDIV_A_SHIFT)
|
||||
|
||||
/* RTC wakeup timer register */
|
||||
|
||||
#define RTC_WUTR_MASK (0xffff) /* Bits 15:0 Wakeup auto-reload value bits */
|
||||
|
||||
/* RTC alarm A/B registers */
|
||||
|
||||
#define RTC_ALRMR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
|
||||
#define RTC_ALRMR_SU_MASK (15 << RTC_ALRMR_SU_SHIFT)
|
||||
#define RTC_ALRMR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
|
||||
#define RTC_ALRMR_ST_MASK (7 << RTC_ALRMR_ST_SHIFT)
|
||||
#define RTC_ALRMR_MSK1 (1 << 7) /* Bit 7 : Alarm A seconds mask */
|
||||
#define RTC_ALRMR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
|
||||
#define RTC_ALRMR_MNU_MASK (15 << RTC_ALRMR_MNU_SHIFT)
|
||||
#define RTC_ALRMR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
|
||||
#define RTC_ALRMR_MNT_MASK (7 << RTC_ALRMR_MNT_SHIFT)
|
||||
#define RTC_ALRMR_MSK2 (1 << 15) /* Bit 15 : Alarm A minutes mask */
|
||||
#define RTC_ALRMR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
|
||||
#define RTC_ALRMR_HU_MASK (15 << RTC_ALRMR_HU_SHIFT)
|
||||
#define RTC_ALRMR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
|
||||
#define RTC_ALRMR_HT_MASK (3 << RTC_ALRMR_HT_SHIFT)
|
||||
#define RTC_ALRMR_PM (1 << 22) /* Bit 22 : AM/PM notation */
|
||||
#define RTC_ALRMR_MSK3 (1 << 23) /* Bit 23 : Alarm A hours mask */
|
||||
#define RTC_ALRMR_DU_SHIFT (24) /* Bits 24-27: Date units or day in BCD format. */
|
||||
#define RTC_ALRMR_DU_MASK (15 << RTC_ALRMR_DU_SHIFT)
|
||||
#define RTC_ALRMR_DT_SHIFT (28) /* Bits 28-29: Date tens in BCD format. */
|
||||
#define RTC_ALRMR_DT_MASK (3 << RTC_ALRMR_DT_SHIFT)
|
||||
#define RTC_ALRMR_WDSEL (1 << 30) /* Bit 30: Week day selection */
|
||||
#define RTC_ALRMR_MSK4 (1 << 31) /* Bit 31: Alarm A date mask */
|
||||
|
||||
/* RTC write protection register */
|
||||
|
||||
#define RTC_WPR_MASK (0xff) /* Bits 0-7: Write protection key */
|
||||
|
||||
/* RTC sub second register */
|
||||
|
||||
#define RTC_SSR_MASK (0xffff) /* Bits 0-15: Sub second value */
|
||||
|
||||
/* RTC shift control register */
|
||||
|
||||
#define RTC_SHIFTR_SUBFS_SHIFT (0) /* Bits 0-14: Subtract a fraction of a second */
|
||||
#define RTC_SHIFTR_SUBFS_MASK (0x7ffff << RTC_SHIFTR_SUBFS_SHIFT)
|
||||
#define RTC_SHIFTR_ADD1S (1 << 31) /* Bit 31: Add one second */
|
||||
|
||||
/* RTC time stamp time register */
|
||||
|
||||
#define RTC_TSTR_SU_SHIFT (0) /* Bits 0-3: Second units in BCD format. */
|
||||
#define RTC_TSTR_SU_MASK (15 << RTC_TSTR_SU_SHIFT)
|
||||
#define RTC_TSTR_ST_SHIFT (4) /* Bits 4-6: Second tens in BCD format. */
|
||||
#define RTC_TSTR_ST_MASK (7 << RTC_TSTR_ST_SHIFT)
|
||||
#define RTC_TSTR_MNU_SHIFT (8) /* Bits 8-11: Minute units in BCD format. */
|
||||
#define RTC_TSTR_MNU_MASK (15 << RTC_TSTR_MNU_SHIFT)
|
||||
#define RTC_TSTR_MNT_SHIFT (12) /* Bits 12-14: Minute tens in BCD format. */
|
||||
#define RTC_TSTR_MNT_MASK (7 << RTC_TSTR_MNT_SHIFT)
|
||||
#define RTC_TSTR_HU_SHIFT (16) /* Bits 16-19: Hour units in BCD format. */
|
||||
#define RTC_TSTR_HU_MASK (15 << RTC_TSTR_HU_SHIFT)
|
||||
#define RTC_TSTR_HT_SHIFT (20) /* Bits 20-21: Hour tens in BCD format. */
|
||||
#define RTC_TSTR_HT_MASK (3 << RTC_TSTR_HT_SHIFT)
|
||||
#define RTC_TSTR_PM (1 << 22) /* Bit 22: AM/PM notation */
|
||||
|
||||
/* RTC time stamp date register */
|
||||
|
||||
#define RTC_TSDR_DU_SHIFT (0) /* Bit 0-3: Date units in BCD format */
|
||||
#define RTC_TSDR_DU_MASK (15 << RTC_TSDR_DU_SHIFT) */
|
||||
#define RTC_TSDR_DT_SHIFT (4) /* Bits 4-5: Date tens in BCD format */
|
||||
#define RTC_TSDR_DT_MASK (3 << RTC_TSDR_DT_SHIFT)
|
||||
#define RTC_TSDR_MU_SHIFT (8) /* Bits 8-11: Month units in BCD format */
|
||||
#define RTC_TSDR_MU_MASK (xx << RTC_TSDR_MU_SHIFT)
|
||||
#define RTC_TSDR_MT (1 << 12) /* Bit 12: Month tens in BCD format */
|
||||
#define RTC_TSDR_WDU_SHIFT (13) /* Bits 13-15: Week day units */
|
||||
#define RTC_TSDR_WDU_MASK (7 << RTC_TSDR_WDU_SHIFT)
|
||||
|
||||
/* RTC timestamp sub second register */
|
||||
|
||||
#define RTC_TSSSR_MASK (0xffff) /* Bits 0-15: Sub second value */
|
||||
|
||||
/* RTC calibration register */
|
||||
|
||||
#define RTC_CALR_CALM_SHIFT (0) /* Bits 0-8: Calibration minus */
|
||||
#define RTC_CALR_CALM_MASK (0x1ff << RTC_CALR_CALM_SHIFT)
|
||||
#define RTC_CALR_CALW16 (1 << 13) /* Bit 13: Use a 16-second calibration cycle period */
|
||||
#define RTC_CALR_CALW8 (1 << 14) /* Bit 14: Use an 8-second calibration cycle period */
|
||||
#define RTC_CALR_CALP (1 << 15) /* Bit 15: Increase frequency of RTC by 488.5 ppm */
|
||||
|
||||
/* RTC tamper configuration register */
|
||||
|
||||
#define RTC_TAMPCR_TAMP1E (1 << 0) /* Bit 0: RTC_TAMP1 input detection enable */
|
||||
#define RTC_TAMPCR_TAMP1TRG (1 << 1) /* Bit 1: Active level for RTC_TAMP1 input */
|
||||
#define RTC_TAMPCR_TAMPIE (1 << 2) /* Bit 2: Tamper interrupt enable */
|
||||
#define RTC_TAMPCR_TAMP2E (1 << 3) /* Bit 3: RTC_TAMP2 input detection enable */
|
||||
#define RTC_TAMPCR_TAMP2TRG (1 << 4) /* Bit 4: Active level for RTC_TAMP2 input */
|
||||
#define RTC_TAMPCR_TAMP3E (1 << 5) /* Bit 5: RTC_TAMP3 detection enable */
|
||||
#define RTC_TAMPCR_TAMP3TRG (1 << 6) /* Bit 6: Active level for RTC_TAMP3 input */
|
||||
#define RTC_TAMPCR_TAMPTS (1 << 7) /* Bit 7: Activate timestamp on tamper detection event */
|
||||
#define RTC_TAMPCR_TAMPFREQ_SHIFT (8) /* Bits 8-10: Tamper sampling frequency */
|
||||
#define RTC_TAMPCR_TAMPFREQ_MASK (7 << RTC_TAMPCR_TAMPFREQ_SHIFT)
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV32768 (0 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 32768 (1 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV16384 (1 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 16384 (2 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV8192 (2 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 8192 (4 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV4096 (3 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 4096 (8 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV2048 (4 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 2048 (16 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV1024 (5 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 1024 (32 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV512 (6 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 512 (64 Hz) */
|
||||
# define RTC_TAMPCR_TAMPFREQ_DIV256 (7 << RTC_TAMPCR_TAMPFREQ_SHIFT) /* RTCCLK / 256 (128 Hz) */
|
||||
#define RTC_TAMPCR_TAMPFLT_SHIFT (11) /* Bits 11-12: RTC_TAMPx filter count */
|
||||
#define RTC_TAMPCR_TAMPFLT_MASK (3 << RTC_TAMPCR_TAMPFLT_SHIFT)
|
||||
#define RTC_TAMPCR_TAMPPRCH_SHIFT (13) /* Bits 13-14: RTC_TAMPx precharge duration */
|
||||
#define RTC_TAMPCR_TAMPPRCH_MASK (3 << RTC_TAMPCR_TAMPPRCH_SHIFT)
|
||||
# define RTC_TAMPCR_TAMPPRCH_1CYCLE (0 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 1 RTCCLK cycle */
|
||||
# define RTC_TAMPCR_TAMPPRCH_2CYCLES (1 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 2 RTCCLK cycles */
|
||||
# define RTC_TAMPCR_TAMPPRCH_4CYCLES (2 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 4 RTCCLK cycles */
|
||||
# define RTC_TAMPCR_TAMPPRCH_5CYCLES (3 << RTC_TAMPCR_TAMPPRCH_SHIFT) /* 8 RTCCLK cycles */
|
||||
#define RTC_TAMPCR_TAMPPUDIS (1 << 15) /* Bit 15: RTC_TAMPx pull-up disable */
|
||||
#define RTC_TAMPCR_TAMP1IE (1 << 16) /* Bit 16: Tamper 1 interrupt enable */
|
||||
#define RTC_TAMPCR_TAMP1NOERASE (1 << 17) /* Bit 17: Tamper 1 no erase */
|
||||
#define RTC_TAMPCR_TAMP1MF (1 << 18) /* Bit 18: Tamper 1 mask flag */
|
||||
#define RTC_TAMPCR_TAMP2IE (1 << 19) /* Bit 19: Tamper 2 interrupt enable */
|
||||
#define RTC_TAMPCR_TAMP2NOERASE (1 << 20) /* Bit 20: Tamper 2 no erase */
|
||||
#define RTC_TAMPCR_TAMP2MF (1 << 21) /* Bit 21: Tamper 2 mask flag */
|
||||
#define RTC_TAMPCR_TAMP3IE (1 << 22) /* Bit 22: Tamper 3 interrupt enable */
|
||||
#define RTC_TAMPCR_TAMP3NOERASE (1 << 23) /* Bit 23: Tamper 3 no erase */
|
||||
#define RTC_TAMPCR_TAMP3MF (1 << 24) /* Bit 24: Tamper 3 mask flag */
|
||||
|
||||
/* RTC alarm A/B sub second register */
|
||||
|
||||
#define RTC_ALRMSSR_SS_SHIFT (0) /* Bits 0-14: Sub second value */
|
||||
#define RTC_ALRMSSR_SS_MASK (0x7fff << RTC_ALRMSSR_SS_SHIFT)
|
||||
#define RTC_ALRMSSR_MASKSS_SHIFT (24) /* Bits 24-27: Mask the most-significant bits starting at this bit */
|
||||
#define RTC_ALRMSSR_MASKSS_MASK (0xf << RTC_ALRMSSR_MASKSS_SHIFT)
|
||||
|
||||
/* RTC option register */
|
||||
|
||||
#define RTC_OR_TSINSEL_SHIFT (1) /* Bits 1-2: TIMESTAMP mapping */
|
||||
#define RTC_OR_TSINSEL_MASK (3 << RTC_OR_TSINSEL_SHIFT)
|
||||
# define RTC_OR_PC13 (0 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC13*/
|
||||
# define RTC_OR_PI8 (1 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PI8 */
|
||||
# define RTC_OR_PC1 (2 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC1 */
|
||||
# define RTC_OR_PC1_1 (3 << RTC_OR_TSINSEL_SHIFT) /* TIMESTAMP is mapped on PC1 */
|
||||
#define RTC_OR_RTC_ALARM_TYPE (1 << 3) /* RTC_ALARM on PC13 output type */
|
||||
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_RTCC_H */
|
||||
@@ -0,0 +1,112 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/include/stm32f7/stm32_alarm.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Neil hancock - delegated to Gregory Nutt Mar 30, 2016
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_ALARM_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_STM32_ALARM_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <time.h>
|
||||
|
||||
#ifdef CONFIG_RTC_ALARM
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
typedef CODE void (*alm_callback_t)(FAR void *arg, unsigned int alarmid);
|
||||
|
||||
/* These features map to STM32 RTC from stm32F7xx
|
||||
*/
|
||||
|
||||
enum alm_id_e
|
||||
{
|
||||
RTC_ALARMA = 0, /* RTC ALARM A */
|
||||
RTC_ALARMB, /* RTC ALARM B */
|
||||
RTC_ALARM_LAST
|
||||
};
|
||||
|
||||
/* Structure used to pass parameters to set an alarm */
|
||||
|
||||
struct alm_setalarm_s
|
||||
{
|
||||
int as_id; /* enum alm_id_e */
|
||||
struct tm as_time; /* Alarm expiration time */
|
||||
alm_callback_t as_cb; /* Callback (if non-NULL) */
|
||||
FAR void *as_arg; /* Argument for callback */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rtc_setalarm
|
||||
*
|
||||
* Description:
|
||||
* Set an alarm to an absolute time using associated hardware.
|
||||
*
|
||||
* Input Parameters:
|
||||
* alminfo - Information about the alarm configuration.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_rtc_setalarm(FAR struct alm_setalarm_s *alminfo);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rtc_cancelalarm
|
||||
*
|
||||
* Description:
|
||||
* Cancel an alarm.
|
||||
*
|
||||
* Input Parameters:
|
||||
* alarmid - Identifies the alarm to be cancelled
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_rtc_cancelalarm(enum alm_id_e alarmid);
|
||||
|
||||
#endif /* CONFIG_RTC_ALARM */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_ALARM_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,166 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_bbsram.h
|
||||
*
|
||||
* Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_BBSRAM_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_STM32_BBSRAM_H
|
||||
|
||||
/****************************************************************************
|
||||
* The purpose of this driver is to add battery backup file to the file
|
||||
* system. There can be CONFIG_STM32F7_BBRSRAM_COUNT files defined.
|
||||
* These files are of fixed size up to the maximum of the backing 4K SRAM.
|
||||
*
|
||||
* If CONFIG_SAVE_CRASHDUMP is defined The driver also supports a feature
|
||||
* to save the context of a PANIC in one of these files.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/fs/ioctl.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX) || \
|
||||
defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
|
||||
# define STM32F7_BBSRAM_SIZE 4096
|
||||
#else
|
||||
# error "No backup SRAM on this STM32 Device"
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_STM32F7_BBSRAM_FILES)
|
||||
# define CONFIG_STM32F7_BBSRAM_FILES 4
|
||||
#endif
|
||||
|
||||
/* REVISIT: What guarantees that STM32F7_BBSRAM_GETDESC_IOCTL has a unique
|
||||
* value among all over _DIOC() values?
|
||||
*/
|
||||
|
||||
#define STM32F7_BBSRAM_GETDESC_IOCTL _DIOC(0x0010) /* Returns a bbsramd_s */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
enum bbsramdf_e
|
||||
{
|
||||
eCRCValid = 1, /* The crc is valid */
|
||||
eDirty = 2, /* The file was closed */
|
||||
|
||||
};
|
||||
|
||||
struct bbsramd_s
|
||||
{
|
||||
uint8_t flags; /* The crc is valid and the file was closed */
|
||||
uint8_t fileno; /* The minor number */
|
||||
uint16_t len; /* Total Bytes in this file*/
|
||||
struct timespec lastwrite; /* Last write time */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
# define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
# define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
/****************************************************************************
|
||||
* Function: stm32_bbsraminitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the Battery Backed up SRAM driver.
|
||||
*
|
||||
* Parameters:
|
||||
* devpath - the path to instantiate the files.
|
||||
* sizes - Pointer to a any array of file sizes to create
|
||||
* the last entry should be 0
|
||||
* A size of -1 will use all the remaining spaces
|
||||
*
|
||||
* If the length of sizes is greater then CONFIG_STM32F7_BBSRAM_FILES
|
||||
* CONFIG_STM32F7_BBSRAM_FILES will be returned.
|
||||
*
|
||||
* Returned Value:
|
||||
* Number of files created on success; Negated errno on failure.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_bbsraminitialize(char *devpath, int *sizes);
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_bbsram_savepanic
|
||||
*
|
||||
* Description:
|
||||
* Saves the panic context in a previously allocated BBSRAM file
|
||||
*
|
||||
* Parameters:
|
||||
* fileno - the value returned by the ioctl STM32F7_BBSRAM_GETDESC_IOCTL
|
||||
* context - Pointer to a any array of bytes to save
|
||||
* length - The length of the data pointed to byt context
|
||||
*
|
||||
* Returned Value:
|
||||
* Length saved or negated errno.
|
||||
*
|
||||
* Assumptions:
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
|
||||
int stm32_bbsram_savepanic(int fileno, uint8_t *context, int length);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_BBSRAM_H */
|
||||
@@ -0,0 +1,72 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_exti_pwr.h
|
||||
*
|
||||
* Copyright (C) 2015 Haltian Ltd. All rights reserved.
|
||||
* Authors: Dmitry Nikolaev <dmitry.nikolaev@haltian.com>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_EXTI_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_STM32_EXTI_PWR_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_exti_pvd
|
||||
*
|
||||
* Description:
|
||||
* Sets/clears EXTI PVD interrupt.
|
||||
*
|
||||
* Parameters:
|
||||
* - rising/falling edge: enables interrupt on rising/falling edge
|
||||
* - event: generate event when set
|
||||
* - func: when non-NULL, generate interrupt
|
||||
*
|
||||
* Returns:
|
||||
* The previous value of the interrupt handler function pointer. This
|
||||
* value may, for example, be used to restore the previous handler when
|
||||
* multiple handlers are used.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
xcpt_t stm32_exti_pvd(bool risingedge, bool fallingedge, bool event,
|
||||
xcpt_t func);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_EXTI_PWR_H */
|
||||
@@ -0,0 +1,264 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_pwr.c
|
||||
*
|
||||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
|
||||
* Authors: Uros Platise <uros.platise@isotel.eu>
|
||||
* Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "stm32_pwr.h"
|
||||
|
||||
#if defined(CONFIG_STM32F7_PWR)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
************************************************************************************/
|
||||
|
||||
static inline uint16_t stm32_pwr_getreg(uint8_t offset)
|
||||
{
|
||||
return (uint16_t)getreg32(STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
static inline void stm32_pwr_putreg(uint8_t offset, uint16_t value)
|
||||
{
|
||||
putreg32((uint32_t)value, STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
static inline void stm32_pwr_modifyreg(uint8_t offset, uint16_t clearbits, uint16_t setbits)
|
||||
{
|
||||
modifyreg32(STM32_PWR_BASE + (uint32_t)offset, (uint32_t)clearbits, (uint32_t)setbits);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablebkp
|
||||
*
|
||||
* Description:
|
||||
* Enables access to the backup domain (RTC registers, RTC backup data registers
|
||||
* and backup SRAM).
|
||||
*
|
||||
* Input Parameters:
|
||||
* writable - True: enable ability to write to backup domain registers
|
||||
*
|
||||
* Returned Value:
|
||||
* True: The backup domain was previously writable.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
bool stm32_pwr_enablebkp(bool writable)
|
||||
{
|
||||
uint16_t regval;
|
||||
bool waswritable;
|
||||
|
||||
/* Get the current state of the STM32 PWR control register */
|
||||
|
||||
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
|
||||
waswritable = ((regval & PWR_CR1_DBP) != 0);
|
||||
|
||||
/* Enable or disable the ability to write */
|
||||
|
||||
if (waswritable && !writable)
|
||||
{
|
||||
/* Disable backup domain access */
|
||||
|
||||
regval &= ~PWR_CR1_DBP;
|
||||
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
}
|
||||
else if (!waswritable && writable)
|
||||
{
|
||||
/* Enable backup domain access */
|
||||
|
||||
regval |= PWR_CR1_DBP;
|
||||
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
|
||||
/* Enable does not happen right away */
|
||||
|
||||
up_udelay(4);
|
||||
}
|
||||
|
||||
return waswritable;
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablebreg
|
||||
*
|
||||
* Description:
|
||||
* Enables the Backup regulator, the Backup regulator (used to maintain backup
|
||||
* SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup
|
||||
* regulator is switched off. The backup SRAM can still be used but its content will
|
||||
* be lost in the Standby and VBAT modes. Once set, the application must wait that
|
||||
* the Backup Regulator Ready flag (BRR) is set to indicate that the data written
|
||||
* into the RAM will be maintained in the Standby and VBAT modes.
|
||||
*
|
||||
* Input Parameters:
|
||||
* regon - state to set it to
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_enablebreg(bool regon)
|
||||
{
|
||||
uint16_t regval;
|
||||
|
||||
regval = stm32_pwr_getreg(STM32_PWR_CSR1_OFFSET);
|
||||
regval &= ~PWR_CSR1_BRE;
|
||||
regval |= regon ? PWR_CSR1_BRE : 0;
|
||||
stm32_pwr_putreg(STM32_PWR_CSR1_OFFSET, regval);
|
||||
|
||||
if (regon)
|
||||
{
|
||||
while ((stm32_pwr_getreg(STM32_PWR_CSR1_OFFSET) & PWR_CSR1_BRR) == 0);
|
||||
}
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_setvos
|
||||
*
|
||||
* Description:
|
||||
* Set voltage scaling.
|
||||
*
|
||||
* Input Parameters:
|
||||
* vos - Properly aligned voltage scaling select bits for the PWR_CR register.
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* At present, this function is called only from initialization logic. If used
|
||||
* for any other purpose that protection to assure that its operation is atomic
|
||||
* will be required.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_setvos(uint16_t vos)
|
||||
{
|
||||
uint16_t regval;
|
||||
|
||||
/* The following sequence is required to program the voltage regulator ranges:
|
||||
* 1. Check VDD to identify which ranges are allowed...
|
||||
* 2. Configure the voltage scaling range by setting the VOS bits in the PWR_CR1
|
||||
* register.
|
||||
*/
|
||||
|
||||
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
|
||||
regval &= ~PWR_CR1_VOS_MASK;
|
||||
regval |= (vos & PWR_CR1_VOS_MASK);
|
||||
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_setpvd
|
||||
*
|
||||
* Description:
|
||||
* Sets power voltage detector
|
||||
*
|
||||
* Input Parameters:
|
||||
* pls - PVD level
|
||||
*
|
||||
* Returned Values:
|
||||
* None
|
||||
*
|
||||
* Assumptions:
|
||||
* At present, this function is called only from initialization logic. If used
|
||||
* for any other purpose that protection to assure that its operation is atomic
|
||||
* will be required.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_setpvd(uint16_t pls)
|
||||
{
|
||||
uint16_t regval;
|
||||
|
||||
/* Set PLS */
|
||||
|
||||
regval = stm32_pwr_getreg(STM32_PWR_CR1_OFFSET);
|
||||
regval &= ~PWR_CR1_PLS_MASK;
|
||||
regval |= (pls & PWR_CR1_PLS_MASK);
|
||||
|
||||
/* Write value to register */
|
||||
|
||||
stm32_pwr_putreg(STM32_PWR_CR1_OFFSET, regval);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_enablepvd
|
||||
*
|
||||
* Description:
|
||||
* Enable the Programmable Voltage Detector
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_enablepvd(void)
|
||||
{
|
||||
/* Enable PVD by setting the PVDE bit in PWR_CR register. */
|
||||
|
||||
stm32_pwr_modifyreg(STM32_PWR_CR1_OFFSET, 0, PWR_CR1_PVDE);
|
||||
}
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwr_disablepvd
|
||||
*
|
||||
* Description:
|
||||
* Disable the Programmable Voltage Detector
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void stm32_pwr_disablepvd(void)
|
||||
{
|
||||
/* Disable PVD by clearing the PVDE bit in PWR_CR register. */
|
||||
|
||||
stm32_pwr_modifyreg(STM32_PWR_CR1_OFFSET, PWR_CR1_PVDE, 0);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32_PWR */
|
||||
@@ -1,8 +1,9 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_pwr.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Gregory Nutt <gnutt@nuttx.org>
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,178 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32f7/stm32_rtc.h
|
||||
*
|
||||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Copyright (C) 2011-2013, 2015-2016 Gregory Nutt. All rights reserved.
|
||||
* Authors: Uros Platise <uros.platise@isotel.eu> (Original for the F1)
|
||||
* Gregory Nutt <gnutt@nuttx.org> (On-going support and development)
|
||||
* David Sidrane <david_s5@nscdg.com>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32F7_STM32_RTC_H
|
||||
#define __ARCH_ARM_SRC_STM32F7_STM32_RTC_H
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/* The STMF7 family use a more traditional Realtime Clock/Calendar (RTCC) with
|
||||
* broken-out data/time in BCD format. The backup registers are integrated into
|
||||
* the RTCC in these families.
|
||||
*/
|
||||
|
||||
#include "chip/stm32_rtcc.h"
|
||||
#include "stm32_alarm.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define STM32_RTC_PRESCALER_SECOND 32767 /* Default prescaler to get a second base */
|
||||
#define STM32_RTC_PRESCALER_MIN 1 /* Maximum speed of 16384 Hz */
|
||||
|
||||
#if !defined(CONFIG_RTC_MAGIC)
|
||||
# define CONFIG_RTC_MAGIC (0xfacefeee)
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_RTC_MAGIC_REG)
|
||||
# define CONFIG_RTC_MAGIC_REG (0)
|
||||
#endif
|
||||
|
||||
#define RTC_MAGIC CONFIG_RTC_MAGIC
|
||||
#define RTC_MAGIC_REG STM32_RTC_BKR(CONFIG_RTC_MAGIC_REG)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rtc_getdatetime_with_subseconds
|
||||
*
|
||||
* Description:
|
||||
* Get the current date and time from the date/time RTC. This interface
|
||||
* is only supported by the date/time RTC hardware implementation.
|
||||
* It is used to replace the system timer. It is only used by the RTOS
|
||||
* during initialization to set up the system time when CONFIG_RTC and
|
||||
* CONFIG_RTC_DATETIME are selected (and CONFIG_RTC_HIRES is not).
|
||||
*
|
||||
* NOTE: Some date/time RTC hardware is capability of sub-second accuracy.
|
||||
* Thatsub-second accuracy is returned through 'nsec'.
|
||||
*
|
||||
* Input Parameters:
|
||||
* tp - The location to return the high resolution time value.
|
||||
* nsec - The location to return the subsecond time value.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32F7_HAVE_RTC_SUBSECONDS
|
||||
int stm32_rtc_getdatetime_with_subseconds(FAR struct tm *tp, FAR long *nsec);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rtc_setdatetime
|
||||
*
|
||||
* Description:
|
||||
* Set the RTC to the provided time. RTC implementations which provide
|
||||
* up_rtc_getdatetime() (CONFIG_RTC_DATETIME is selected) should provide
|
||||
* this function.
|
||||
*
|
||||
* Input Parameters:
|
||||
* tp - the time to use
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) on success; a negated errno on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTC_DATETIME
|
||||
struct tm;
|
||||
int stm32_rtc_setdatetime(FAR const struct tm *tp);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rtc_lowerhalf
|
||||
*
|
||||
* Description:
|
||||
* Instantiate the RTC lower half driver for the STM32. General usage:
|
||||
*
|
||||
* #include <nuttx/timers/rtc.h>
|
||||
* #include "stm32_rtc.h>
|
||||
*
|
||||
* struct rtc_lowerhalf_s *lower;
|
||||
* lower = stm32_rtc_lowerhalf();
|
||||
* rtc_initialize(0, lower);
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, a non-NULL RTC lower interface is returned. NULL is
|
||||
* returned on any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_RTC_DRIVER
|
||||
struct rtc_lowerhalf_s;
|
||||
FAR struct rtc_lowerhalf_s *stm32_rtc_lowerhalf(void);
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32F7_STM32_RTC_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -746,7 +746,7 @@ static void stm32_stdclockconfig(void)
|
||||
regval |= STM32_RCC_CFGR_PPRE1;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
#ifdef CONFIG_RTC_HSECLOCK
|
||||
#ifdef CONFIG_STM32F7_RTC_HSECLOCK
|
||||
/* Set the RTC clock divisor */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
@@ -936,13 +936,13 @@ static void stm32_stdclockconfig(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK)
|
||||
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
stm32_rcc_enablelsi();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTC_LSECLOCK)
|
||||
#if defined(CONFIG_STM32F7_RTC_LSECLOCK)
|
||||
/* Low speed external clock source LSE
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
|
||||
@@ -742,7 +742,7 @@ static void stm32_stdclockconfig(void)
|
||||
regval |= STM32_RCC_CFGR_PPRE1;
|
||||
putreg32(regval, STM32_RCC_CFGR);
|
||||
|
||||
#ifdef CONFIG_RTC_HSECLOCK
|
||||
#ifdef CONFIG_STM32F7_RTC_HSECLOCK
|
||||
/* Set the RTC clock divisor */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR);
|
||||
@@ -939,13 +939,13 @@ static void stm32_stdclockconfig(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_RTC_LSICLOCK)
|
||||
#if defined(CONFIG_STM32F7_IWDG) || defined(CONFIG_STM32F7_RTC_LSICLOCK)
|
||||
/* Low speed internal clock source LSI */
|
||||
|
||||
stm32_rcc_enablelsi();
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_RTC_LSECLOCK)
|
||||
#if defined(CONFIG_STM32F7_RTC_LSECLOCK)
|
||||
/* Low speed external clock source LSE
|
||||
*
|
||||
* TODO: There is another case where the LSE needs to
|
||||
|
||||
Reference in New Issue
Block a user