Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-05-31 14:27:37 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

Merged in david_s5/nuttx/master_h7 (pull request #1025)

Browse Source 
stm32h7: bbsram issues causing no writes and  hardfaults

* stm32_pwr:Ensure data is flushed on backup domain access changes

* stm32h7:bbsram convince compiler to perform 32 bit write

Approved-by: Gregory Nutt <gnutt@nuttx.org>
This commit is contained in:
David Sidrane
2019-08-26 18:34:25 +00:00
committed by Gregory Nutt
parent 4710ec1e77
commit a3bea40c46
2 changed files with 5 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32h7/stm32_bbsram.c
+1 -1
View File
@@ -334,7 +334,7 @@ static void stm32_bbsram_ecc_workaround(FAR struct bbsramfh_s *pf)
{ {
/* Force the last writes to be a a full 32 bit word */ /* Force the last writes to be a a full 32 bit word */
pf->unit32 = (volatile uint32_t) pf->unit32; *((volatile uint32_t *) &pf->unit32) = (volatile uint32_t) pf->unit32;
} }
#else #else
#define stm32_bbsram_ecc_workaround() #define stm32_bbsram_ecc_workaround()
arch/arm/src/stm32h7/stm32_pwr.c
+4 -1
View File
@@ -47,6 +47,7 @@
#include <stdbool.h> #include <stdbool.h>
#include <errno.h> #include <errno.h>
#include "barriers.h"
#include "up_arch.h" #include "up_arch.h"
#include "stm32_pwr.h" #include "stm32_pwr.h"
@@ -151,6 +152,7 @@ void stm32_pwr_enablebkp(bool writable)
bool wait = false; bool wait = false;
flags = enter_critical_section(); flags = enter_critical_section();
ARM_DSB();
/* Get the current state of the STM32 PWR control register */ /* Get the current state of the STM32 PWR control register */
@@ -186,13 +188,14 @@ void stm32_pwr_enablebkp(bool writable)
wait = true; wait = true;
} }
ARM_DSB();
leave_critical_section(flags); leave_critical_section(flags);
if (wait) if (wait)
{ {
/* Enable does not happen right away */ /* Enable does not happen right away */
up_udelay(4000); up_udelay(4);
} }
} }