From a3bea40c46fb5e1b6f60faff0cb78fc173b38d5d Mon Sep 17 00:00:00 2001 From: David Sidrane Date: Mon, 26 Aug 2019 18:34:25 +0000 Subject: [PATCH] Merged in david_s5/nuttx/master_h7 (pull request #1025) stm32h7: bbsram issues causing no writes and hardfaults * stm32_pwr:Ensure data is flushed on backup domain access changes * stm32h7:bbsram convince compiler to perform 32 bit write Approved-by: Gregory Nutt --- arch/arm/src/stm32h7/stm32_bbsram.c | 2 +- arch/arm/src/stm32h7/stm32_pwr.c | 5 ++++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/src/stm32h7/stm32_bbsram.c b/arch/arm/src/stm32h7/stm32_bbsram.c index ee7d5bed8ec..6a4f0a22dc5 100644 --- a/arch/arm/src/stm32h7/stm32_bbsram.c +++ b/arch/arm/src/stm32h7/stm32_bbsram.c @@ -334,7 +334,7 @@ static void stm32_bbsram_ecc_workaround(FAR struct bbsramfh_s *pf) { /* Force the last writes to be a a full 32 bit word */ - pf->unit32 = (volatile uint32_t) pf->unit32; + *((volatile uint32_t *) &pf->unit32) = (volatile uint32_t) pf->unit32; } #else #define stm32_bbsram_ecc_workaround() diff --git a/arch/arm/src/stm32h7/stm32_pwr.c b/arch/arm/src/stm32h7/stm32_pwr.c index b98baae3202..4063d4fd704 100644 --- a/arch/arm/src/stm32h7/stm32_pwr.c +++ b/arch/arm/src/stm32h7/stm32_pwr.c @@ -47,6 +47,7 @@ #include #include +#include "barriers.h" #include "up_arch.h" #include "stm32_pwr.h" @@ -151,6 +152,7 @@ void stm32_pwr_enablebkp(bool writable) bool wait = false; flags = enter_critical_section(); + ARM_DSB(); /* Get the current state of the STM32 PWR control register */ @@ -186,13 +188,14 @@ void stm32_pwr_enablebkp(bool writable) wait = true; } + ARM_DSB(); leave_critical_section(flags); if (wait) { /* Enable does not happen right away */ - up_udelay(4000); + up_udelay(4); } }