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WM8904: Add logic to program the FLL to achieve the bitrate

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This commit is contained in:
Gregory Nutt
2014-08-02 12:40:57 -06:00
parent 06657a3b6f
commit a2d6c0c2b4
3 changed files with 397 additions and 43 deletions
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drivers/audio/wm8904.c
+395 -42
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drivers/audio/wm8904.h
+1
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@@ -814,6 +814,7 @@
# define WM8904_FLL_CTRL_RATE(n) ((uint16_t)((n)-1) << WM8904_FLL_CTRL_RATE_SHIFT)
#define WM8904_FLL_FRATIO_SHIFT (0) /* Bits 0-2: FVCO clock divider */
#define WM8904_FLL_FRATIO_MASK (7 << WM8904_FLL_FRATIO_SHIFT)
# define WM8904_FLL_FRATIO(n) ((uint32_t)(n) << WM8904_FLL_FRATIO_SHIFT)
# define WM8904_FLL_FRATIO_DIV1 (0 << WM8904_FLL_FRATIO_SHIFT) /* Divide by 1 */
# define WM8904_FLL_FRATIO_DIV2 (1 << WM8904_FLL_FRATIO_SHIFT) /* Divide by 2 */
# define WM8904_FLL_FRATIO_DIV4 (2 << WM8904_FLL_FRATIO_SHIFT) /* Divide by 4 */
include/nuttx/audio/wm8904.h
+1 -1
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@@ -161,7 +161,7 @@ struct wm8904_lower_s
* the frequency of MCLK in order to generate the correct bitrates.
*/
uint32_t mcclk; /* W8904 Master clock frequency */
uint32_t mclk; /* W8904 Master clock frequency */
/* IRQ/GPIO access callbacks. These operations all hidden behind
* callbacks to isolate the WM8904 driver from differences in GPIO