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arch/arm/src/tiva: Add CC13xx PRCM support library.
This commit is contained in:
Gregory Nutt
@@ -93,9 +93,9 @@ CHIP_CSRCS += tiva_start.c lm4f_gpio.c tiva_gpioirq.c
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else ifeq ($(CONFIG_ARCH_CHIP_TM4C),y)
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CHIP_CSRCS += tiva_start.c tm4c_gpio.c tiva_gpioirq.c
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else ifeq ($(CONFIG_ARCH_CHIP_CC13X0),y)
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CHIP_CSRCS += cc13xx_start.c cc13xx_gpio.c cc13xx_gpioirq.c
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CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_gpio.c cc13xx_gpioirq.c
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else ifeq ($(CONFIG_ARCH_CHIP_CC13X2),y)
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CHIP_CSRCS += cc13xx_start.c cc13xx_gpio.c cc13xx_gpioirq.c
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CHIP_CSRCS += cc13xx_start.c cc13xx_prcm.c cc13xx_gpio.c cc13xx_gpioirq.c
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endif
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ifeq ($(CONFIG_DEBUG_GPIO_INFO),y)
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@@ -1,5 +1,5 @@
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/****************************************************************************
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* arch/arm/src/tiva/cc13x0/cc13x0_gpio.h
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* arch/arm/src/tiva/cc13xx/cc13xx_gpio.h
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*
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* Copyright (C) 2018 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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@@ -35,8 +35,8 @@
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_TIVA_CC13X0_CC13X0_GPIO_H
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#define __ARCH_ARM_SRC_TIVA_CC13X0_CC13X0_GPIO_H
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#ifndef __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_GPIO_H
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#define __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_GPIO_H
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/****************************************************************************
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* Included Files
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@@ -246,8 +246,17 @@
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#define GPIO_DIO_MASK (0x1f << GPIO_PORTID_SHIFT)
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# define GPIO_DIO(n) ((uint32_t)(n) << GPIO_PORTID_SHIFT)
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/* Helper Definitions *******************************************************/
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#define GPIO_STD_INPUT (GPIO_IOCURR_2MA | GPIO_IOSTR_AUTO | \
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GPIO_PULL_DISABLE | GPIO_EDGE_NONE | \
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GPIO_IOMODE_NORMAL | GPIO_IE)
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#define GPIO_STD_OUTPUT (GPIO_IOCURR_2MA | GPIO_IOSTR_AUTO | \
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GPIO_PULL_DISABLE | GPIO_EDGE_NONE | \
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GPIO_IOMODE_NORMAL)
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#endif /* __ARCH_ARM_SRC_TIVA_CC13X0_CC13X0_GPIO_H */
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#endif /* __ARCH_ARM_SRC_TIVA_CC13XX_CC13XX_GPIO_H */
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File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -270,15 +270,23 @@ void __start(void)
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showprogress('E');
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#endif
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/* Initialize the Power Manager internal state. It must be called prior
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* to any other Power API.
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*/
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cc13xx_power_initialize();
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showprogress('F');
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/* Initialize onboard resources */
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tiva_boardinitialize();
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showprogress('F');
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showprogress('G');
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#ifdef CONFIG_TIVA_EEPROM
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/*Initialize the EEPROM */
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tiva_eeprom_initialize();
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showprogress('H');
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#endif
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/* Then start NuttX */
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@@ -220,119 +220,79 @@
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# define PRCM_VIMSCLKG_CLKEN_DISSYSCLK (1 << PRCM_VIMSCLKG_CLKEN_SHIFT) /* Disable clock when SYCLK disabled */
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# define PRCM_VIMSCLKG_CLKEN_ENA (3 << PRCM_VIMSCLKG_CLKEN_SHIFT) /* Enable clock */
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/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes */
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/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes,
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* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode, and
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* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode
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*/
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#define PRCM_SECDMACLKGR_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
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#define PRCM_SECDMACLKGR_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
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#define PRCM_SECDMACLKGR_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
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#define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (1 << 0) /* Bit 0: Enable cypto clock */
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#define PRCM_SECDMACLKG_CRYPTO_CLKEN (1 << PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT)
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#define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1 << 1) /* Bit 1: Enable TRNG clock */
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#define PRCM_SECDMACLKG_TRNG_CLKEN (1 << PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT)
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#define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (1 << 8) /* Bit 8: Enable DMA clock */
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#define PRCM_SECDMACLKG_DMA_CLKEN (1 << PRCM_SECDMACLKG_DMA_CLKEN_SHIFT)
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/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode */
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/* GPIO Clock Gate For Run And All Modes, GPIO Clock Gate For Sleep Mode, and
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* GPIO Clock Gate For Deep Sleep Mode
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*/
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#define PRCM_SECDMACLKGS_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
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#define PRCM_SECDMACLKGS_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
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#define PRCM_SECDMACLKGS_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
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#define PRCM_GPIOCLKG_CLKEN_SHIFT (0) /* Bit 0: Enable clock */
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#define PRCM_GPIOCLKG_CLKEN (1 << PRCM_GPIOCLKG_CLKEN_SHIFT)
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/* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode */
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/* GPT Clock Gate For Run And All Modes, GPT Clock Gate For Sleep Mode, and
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* GPT Clock Gate For Deep Sleep Mode
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*/
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#define PRCM_SECDMACLKGDS_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
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#define PRCM_SECDMACLKGDS_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
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#define PRCM_SECDMACLKGDS_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
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#define PRCM_GPTCLKG_CLKEN_GPT0_SHIFT (0) /* Bit 0: Enable clock for GPT0 */
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#define PRCM_GPTCLKG_CLKEN_GPT0 (1 << PRCM_GPTCLKG_CLKEN_GPT0_SHIFT)
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#define PRCM_GPTCLKG_CLKEN_GPT1_SHIFT (1) /* Bit 1: Enable clock for GPT1 */
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#define PRCM_GPTCLKG_CLKEN_GPT1 (1 << PRCM_GPTCLKG_CLKEN_GPT1_SHIFT)
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#define PRCM_GPTCLKG_CLKEN_GPT2_SHIFT (2) /* Bit 2: Enable clock for GPT2 */
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#define PRCM_GPTCLKG_CLKEN_GPT2 (1 << PRCM_GPTCLKG_CLKEN_GPT2_SHIFT)
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#define PRCM_GPTCLKG_CLKEN_GPT3_SHIFT (3) /* Bit 3: Enable clock for GPT3 */
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#define PRCM_GPTCLKG_CLKEN_GPT3 (1 << PRCM_GPTCLKG_CLKEN_GPT3_SHIFT)
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/* GPIO Clock Gate For Run And All Modes */
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/* I2C Clock Gate For Run And All Modes, 2C Clock Gate For Sleep Mode, and
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* 2C Clock Gate For Deep Sleep Mode
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*/
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#define PRCM_GPIOCLKGR_CLKEN (1 << 0) /* Bit 0: Enable clock */
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#define PRCM_I2CCLKGR_CLKEN_SHIFT (0) /* Bit 0: Enable clock */
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#define PRCM_I2CCLKGR_CLKEN (1 << PRCM_I2CCLKGR_CLKEN_SHIFT)
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/* GPIO Clock Gate For Sleep Mode */
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/* UART Clock Gate For Run And All Modes, UART Clock Gate For Sleep Mode, and
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* UART Clock Gate For Deep Sleep Mode
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*/
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#define PRCM_GPIOCLKGS_CLKEN (1 << 0) /* Bit 0: Enable clock */
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#define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (1 << 0) /* Bit 0: UART0 Enable clock */
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#define PRCM_UARTCLKG_CLKEN_UART0 (1 << PRCM_UARTCLKGDS_CLKEN_UART0_SHIFT)
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/* GPIO Clock Gate For Deep Sleep Mode */
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/* SSI Clock Gate For Run And All Modes, SSI Clock Gate For Sleep Mode, and
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* SSI Clock Gate For Deep Sleep Mode.
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*/
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#define PRCM_GPIOCLKGDS_CLKEN (1 << 0) /* Bit 0: Enable clock */
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#define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (1 << 0) /* Bit 0: SSI0 Enable clock */
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#define PRCM_SSICLKG_CLKEN_SSI0 (1 << PRCM_SSICLKG_CLKEN_SSI0_SHIFT)
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#define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1 << 1) /* Bit 1: SSI1 Enable clock */
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#define PRCM_SSICLKG_CLKEN_SSI1 (1 << PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
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/* GPT Clock Gate For Run And All Modes */
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/* I2S Clock Gate For Run And All Modes, I2S Clock Gate For Sleep Mode, and
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* I2S Clock Gate For Deep Sleep Mode
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*/
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#define PRCM_GPTCLKGR_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
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#define PRCM_GPTCLKGR_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
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#define PRCM_GPTCLKGR_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
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#define PRCM_GPTCLKGR_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
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/* GPT Clock Gate For Sleep Mode */
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#define PRCM_GPTCLKGS_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
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#define PRCM_GPTCLKGS_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
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#define PRCM_GPTCLKGS_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
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#define PRCM_GPTCLKGS_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
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/* GPT Clock Gate For Deep Sleep Mode */
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#define PRCM_GPTCLKGDS_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
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#define PRCM_GPTCLKGDS_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
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#define PRCM_GPTCLKGDS_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
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#define PRCM_GPTCLKGDS_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
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/* I2C Clock Gate For Run And All Modes */
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#define PRCM_I2CCLKGR_CLKEN (1 << 0) /* Bit 0: Enable clock */
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/* I2C Clock Gate For Sleep Mode */
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#define PRCM_I2CCLKGS_CLKEN (1 << 0) /* Bit 0: Enable clock */
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/* I2C Clock Gate For Deep Sleep Mode */
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#define PRCM_I2CCLKGDS_CLKEN (1 << 0) /* Bit 0: Enable clock */
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/* UART Clock Gate For Run And All Modes */
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#define PRCM_UARTCLKGR_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
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/* UART Clock Gate For Sleep Mode */
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#define PRCM_UARTCLKGS_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
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/* UART Clock Gate For Deep Sleep Mode */
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#define PRCM_UARTCLKGDS_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
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/* SSI Clock Gate For Run And All Modes */
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#define PRCM_SSICLKGR_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
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#define PRCM_SSICLKGR_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
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/* SSI Clock Gate For Sleep Mode */
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#define PRCM_SSICLKGS_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
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#define PRCM_SSICLKGS_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
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/* SSI Clock Gate For Deep Sleep Mode */
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#define PRCM_SSICLKGDS_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
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#define PRCM_SSICLKGDS_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
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/* I2S Clock Gate For Run And All Modes */
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#define PRCM_I2SCLKGR_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
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/* I2S Clock Gate For Sleep Mode */
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#define PRCM_I2SCLKGS_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
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/* I2S Clock Gate For Deep Sleep Mode */
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#define PRCM_I2SCLKGDS_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
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#define PRCM_I2SCLKG_CLKEN_SHIFT (0) /* Bit 0: I2S Enable clock */
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#define PRCM_I2SCLKG_CLKEN (1 << PRCM_I2SCLKG_CLKEN_SHIFT)
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/* Internal */
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#define PRCM_CPUCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */
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# define PRCM_CPUCLKDIV_DIV1 (0)
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# define PRCM_CPUCLKDIV_DIV2 PRCM_CPUCLKDIV_DIV
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#define PRCM_CPUCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */
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# define PRCM_CPUCLKDIV_DIV1 (0)
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# define PRCM_CPUCLKDIV_DIV2 PRCM_CPUCLKDIV_DIV
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/* I2S Clock Control */
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#define PRCM_I2SBCLKSEL_SRC (1 << 0) /* Bit 0: BCLK source selector */
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# define PRCM_I2SBCLKSEL_EXTERNAL (0)
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# define PRCM_I2SBCLKSEL_INTERNAL PRCM_I2SBCLKSEL_SRC
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#define PRCM_I2SBCLKSEL_SRC (1 << 0) /* Bit 0: BCLK source selector */
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# define PRCM_I2SBCLKSEL_EXTERNAL (0)
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# define PRCM_I2SBCLKSEL_INTERNAL PRCM_I2SBCLKSEL_SRC
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/* GPT Scalar */
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@@ -344,7 +304,7 @@
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# define PRCM_GPTCLKDIV_DIV8 (3 << PRCM_GPTCLKDIV_SHIFT)
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# define PRCM_GPTCLKDIV_DIV16 (4 << PRCM_GPTCLKDIV_SHIFT)
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# define PRCM_GPTCLKDIV_DIV32 (5 << PRCM_GPTCLKDIV_SHIFT)
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# define PRCM_GPTCLKDIV_DIV65 (6 << PRCM_GPTCLKDIV_SHIFT)
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# define PRCM_GPTCLKDIV_DIV64 (6 << PRCM_GPTCLKDIV_SHIFT)
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# define PRCM_GPTCLKDIV_DIV128 (7 << PRCM_GPTCLKDIV_SHIFT)
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# define PRCM_GPTCLKDIV_DIV256 (8 << PRCM_GPTCLKDIV_SHIFT)
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@@ -245,130 +245,109 @@
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# define PRCM_VIMSCLKG_CLKEN_DISSYSCLK (1 << PRCM_VIMSCLKG_CLKEN_SHIFT) /* Disable clock when SYCLK disabled */
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# define PRCM_VIMSCLKG_CLKEN_ENA (3 << PRCM_VIMSCLKG_CLKEN_SHIFT) /* Enable clock */
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/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes */
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/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes,
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* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode, and
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* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode
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*/
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#define PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT (1 << 0) /* Bit 0: Enable cypto clock */
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#define PRCM_SECDMACLKG_CRYPTO_CLKEN (1 << PRCM_SECDMACLKG_CRYPTO_CLKEN_SHIFT)
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#define PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT (1 << 1) /* Bit 1: Enable TRNG clock */
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#define PRCM_SECDMACLKG_TRNG_CLKEN (1 << PRCM_SECDMACLKG_TRNG_CLKEN_SHIFT)
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#define PRCM_SECDMACLKG_PKA_CLKEN_SHIFT (1 << 2) /* Bit 2: Enable PKA clock */
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#define PRCM_SECDMACLKG_PKA_CLKEN (1 << PRCM_SECDMACLKG_PKA_CLKEN_SHIFT)
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#define PRCM_SECDMACLKG_DMA_CLKEN_SHIFT (1 << 8) /* Bit 8: Enable DMA clock */
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#define PRCM_SECDMACLKG_DMA_CLKEN (1 << PRCM_SECDMACLKG_DMA_CLKEN_SHIFT)
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/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Run And All Modes (only) */
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#define PRCM_SECDMACLKGR_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
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#define PRCM_SECDMACLKGR_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
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#define PRCM_SECDMACLKGR_PKA_CLKEN (1 << 2) /* Bit 2: Enable PKA clock */
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#define PRCM_SECDMACLKGR_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
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#define PRCM_SECDMACLKGR_CRYPTO_AMCLKEN (1 << 16) /* Bit 16: Force Crypto clock on all modes */
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#define PRCM_SECDMACLKGR_TRNG_AMCLKEN (1 << 17) /* Bit 17: Force TRNG clock on all modes */
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#define PRCM_SECDMACLKGR_PKA_AMCLKEN (1 << 18) /* Bit 18: Force PKA clock on all modes */
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#define PRCM_SECDMACLKGR_PKA_ZER0RESETN (1 << 19) /* Bit 18: Enable PKA zeroize of memory */
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#define PRCM_SECDMACLKGR_DMA_AMCLKEN (1 << 24) /* Bit 24: Force DMA clock on all modes */
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/* SEC (PKA And TRNG And CRYPTO) And UDMA Clock Gate For Sleep Mode */
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/* GPIO Clock Gate For Run And All Modes, GPIO Clock Gate For Sleep Mode, and
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* GPIO Clock Gate For Deep Sleep Mode
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*/
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#define PRCM_SECDMACLKGS_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
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#define PRCM_SECDMACLKGS_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
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#define PRCM_SECDMACLKGS_PKA_CLKEN (1 << 2) /* Bit 2: Enable PKA clock */
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#define PRCM_SECDMACLKGS_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
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#define PRCM_GPIOCLKG_CLKEN_SHIFT (0) /* Bit 0: Enable clock */
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#define PRCM_GPIOCLKG_CLKEN (1 << PRCM_GPIOCLKG_CLKEN_SHIFT)
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/* SEC (PKA And TRNG and CRYPTO) And UDMA Clock Gate For Deep Sleep Mode */
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/* GPIO Clock Gate For Run And All Modes (only) */
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#define PRCM_SECDMACLKGDS_CRYPTO_CLKEN (1 << 0) /* Bit 0: Enable cypto clock */
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#define PRCM_SECDMACLKGDS_TRNG_CLKEN (1 << 1) /* Bit 1: Enable TRNG clock */
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#define PRCM_SECDMACLKGDS_PKA_CLKEN (1 << 2) /* Bit 2: Enable PKA clock */
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#define PRCM_SECDMACLKGDS_DMA_CLKEN (1 << 8) /* Bit 8: Enable DMA clock */
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/* GPIO Clock Gate For Run And All Modes */
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#define PRCM_GPIOCLKGR_CLKEN (1 << 0) /* Bit 0: Enable clock */
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#define PRCM_GPIOCLKGR_AMCLKEN (1 << 8) /* Bit 8 Force clock for all modes */
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/* GPIO Clock Gate For Sleep Mode */
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/* GPT Clock Gate For Run And All Modes, GPT Clock Gate For Sleep Mode, and
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* GPT Clock Gate For Deep Sleep Mode.
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*/
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#define PRCM_GPIOCLKGS_CLKEN (1 << 0) /* Bit 0: Enable clock */
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#define PRCM_GPTCLKG_CLKEN_GPT0_SHIFT (0) /* Bit 0: Enable clock for GPT0 */
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#define PRCM_GPTCLKG_CLKEN_GPT0 (1 << PRCM_GPTCLKG_CLKEN_GPT0_SHIFT)
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#define PRCM_GPTCLKG_CLKEN_GPT1_SHIFT (1) /* Bit 1: Enable clock for GPT1 */
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#define PRCM_GPTCLKG_CLKEN_GPT1 (1 << PRCM_GPTCLKG_CLKEN_GPT1_SHIFT)
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#define PRCM_GPTCLKG_CLKEN_GPT2_SHIFT (2) /* Bit 2: Enable clock for GPT2 */
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||||
#define PRCM_GPTCLKG_CLKEN_GPT2 (1 << PRCM_GPTCLKG_CLKEN_GPT2_SHIFT)
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||||
#define PRCM_GPTCLKG_CLKEN_GPT3_SHIFT (3) /* Bit 3: Enable clock for GPT3 */
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||||
#define PRCM_GPTCLKG_CLKEN_GPT3 (1 << PRCM_GPTCLKG_CLKEN_GPT3_SHIFT)
|
||||
|
||||
/* GPIO Clock Gate For Deep Sleep Mode */
|
||||
/* GPT Clock Gate For Run And All Modes (only) */
|
||||
|
||||
#define PRCM_GPIOCLKGDS_CLKEN (1 << 0) /* Bit 0: Enable clock */
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||||
|
||||
/* GPT Clock Gate For Run And All Modes */
|
||||
|
||||
#define PRCM_GPTCLKGR_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
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||||
#define PRCM_GPTCLKGR_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
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||||
#define PRCM_GPTCLKGR_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
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||||
#define PRCM_GPTCLKGR_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
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||||
#define PRCM_GPTCLKGR_AMCLKEN_AMGPT0 (1 << 8) /* Bit 8: Enable clock for GPT0 in all modes */
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||||
#define PRCM_GPTCLKGR_AMCLKEN_AMGPT1 (1 << 9) /* Bit 9: Enable clock for GPT1 in all modes */
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||||
#define PRCM_GPTCLKGR_AMCLKEN_AMGPT2 (1 << 10) /* Bit 11: Enable clock for GPT2 in all modes */
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||||
#define PRCM_GPTCLKGR_AMCLKEN_AMGPT3 (1 << 11) /* Bit 11: Enable clock for GPT3 in all modes */
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||||
|
||||
/* GPT Clock Gate For Sleep Mode */
|
||||
/* I2C Clock Gate For Run And All Modes, 2C Clock Gate For Sleep Mode, and
|
||||
* 2C Clock Gate For Deep Sleep Mode
|
||||
*/
|
||||
|
||||
#define PRCM_GPTCLKGS_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
|
||||
#define PRCM_GPTCLKGS_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
|
||||
#define PRCM_GPTCLKGS_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
|
||||
#define PRCM_GPTCLKGS_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
|
||||
#define PRCM_I2CCLKGR_CLKEN_SHIFT (0) /* Bit 0: Enable clock */
|
||||
#define PRCM_I2CCLKGR_CLKEN (1 << PRCM_I2CCLKGR_CLKEN_SHIFT)
|
||||
|
||||
/* GPT Clock Gate For Deep Sleep Mode */
|
||||
/* I2C Clock Gate For Run And All Modes (only) */
|
||||
|
||||
#define PRCM_GPTCLKGDS_CLKEN_GPT0 (1 << 0) /* Bit 0: Enable clock for GPT0 */
|
||||
#define PRCM_GPTCLKGDS_CLKEN_GPT1 (1 << 1) /* Bit 1: Enable clock for GPT1 */
|
||||
#define PRCM_GPTCLKGDS_CLKEN_GPT2 (1 << 2) /* Bit 2: Enable clock for GPT2 */
|
||||
#define PRCM_GPTCLKGDS_CLKEN_GPT3 (1 << 3) /* Bit 3: Enable clock for GPT3 */
|
||||
|
||||
/* I2C Clock Gate For Run And All Modes */
|
||||
|
||||
#define PRCM_I2CCLKGR_CLKEN (1 << 0) /* Bit 0: Enable clock */
|
||||
#define PRCM_I2CCLKGR_AMCLKEN (1 << 8) /* Bit 8: Force clock on for all modes */
|
||||
|
||||
/* I2C Clock Gate For Sleep Mode */
|
||||
/* UART Clock Gate For Run And All Modes, UART Clock Gate For Sleep Mode, and
|
||||
* UART Clock Gate For Deep Sleep Mode
|
||||
*/
|
||||
|
||||
#define PRCM_I2CCLKGS_CLKEN (1 << 0) /* Bit 0: Enable clock */
|
||||
#define PRCM_UARTCLKG_CLKEN_UART0_SHIFT (1 << 0) /* Bit 0: UART0 Enable clock */
|
||||
#define PRCM_UARTCLKG_CLKEN_UART0 (1 << PRCM_UARTCLKGDS_CLKEN_UART0_SHIFT)
|
||||
#define PRCM_UARTCLKG_CLKEN_UART1_SHIFT (1 << 1) /* Bit 1: UART1 Enable clock */
|
||||
#define PRCM_UARTCLKG_CLKEN_UART1 (1 << PRCM_UARTCLKGDS_CLKEN_UART1_SHIFT)
|
||||
|
||||
/* I2C Clock Gate For Deep Sleep Mode */
|
||||
/* UART Clock Gate For Run And All Modes (only) */
|
||||
|
||||
#define PRCM_I2CCLKGDS_CLKEN (1 << 0) /* Bit 0: Enable clock */
|
||||
|
||||
/* UART Clock Gate For Run And All Modes */
|
||||
|
||||
#define PRCM_UARTCLKGR_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
|
||||
#define PRCM_UARTCLKGR_CLKEN_UART1 (1 << 1) /* Bit 1: UART1 Enable clock */
|
||||
#define PRCM_UARTCLKGR_AMCLKEN_UART0 (1 << 8) /* Bit 8: UART0 Force clock on for all modes */
|
||||
#define PRCM_UARTCLKGR_AMCLKEN_UART1 (1 << 9) /* Bit 9: UART1 Force clock on for all modes */
|
||||
|
||||
/* UART Clock Gate For Sleep Mode */
|
||||
/* SSI Clock Gate For Run And All Modes, SSI Clock Gate For Sleep Mode, and
|
||||
* SSI Clock Gate For Deep Sleep Mode
|
||||
*/
|
||||
|
||||
#define PRCM_UARTCLKGS_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
|
||||
#define PRCM_UARTCLKGS_CLKEN_UART1 (1 << 1) /* Bit 1: UART1 Enable clock */
|
||||
#define PRCM_SSICLKG_CLKEN_SSI0_SHIFT (1 << 0) /* Bit 0: SSI0 Enable clock */
|
||||
#define PRCM_SSICLKG_CLKEN_SSI0 (1 << PRCM_SSICLKG_CLKEN_SSI0_SHIFT)
|
||||
#define PRCM_SSICLKG_CLKEN_SSI1_SHIFT (1 << 1) /* Bit 1: SSI1 Enable clock */
|
||||
#define PRCM_SSICLKG_CLKEN_SSI1 (1 << PRCM_SSICLKG_CLKEN_SSI1_SHIFT)
|
||||
|
||||
/* UART Clock Gate For Deep Sleep Mode */
|
||||
/* SSI Clock Gate For Run And All Modes (only) */
|
||||
|
||||
#define PRCM_UARTCLKGDS_CLKEN_UART0 (1 << 0) /* Bit 0: UART0 Enable clock */
|
||||
#define PRCM_UARTCLKGDS_CLKEN_UART1 (1 << 1) /* Bit 1: UART1 Enable clock */
|
||||
|
||||
/* SSI Clock Gate For Run And All Modes */
|
||||
|
||||
#define PRCM_SSICLKGR_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
|
||||
#define PRCM_SSICLKGR_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
|
||||
#define PRCM_SSICLKGR_AMCLKEN_SSI0 (1 << 8) /* Bit 8: SSI0 Force clock on for all modes */
|
||||
#define PRCM_SSICLKGR_AMCLKEN_SSI1 (1 << 9) /* Bit 9: SSI1 Force clock on for all modes */
|
||||
|
||||
/* SSI Clock Gate For Sleep Mode */
|
||||
/* I2S Clock Gate For Run And All Modes, I2S Clock Gate For Sleep Mode, and
|
||||
* I2S Clock Gate For Deep Sleep Mode
|
||||
*/
|
||||
|
||||
#define PRCM_SSICLKGS_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
|
||||
#define PRCM_SSICLKGS_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
|
||||
#define PRCM_I2SCLKG_CLKEN_SHIFT (0) /* Bit 0: I2S Enable clock */
|
||||
#define PRCM_I2SCLKG_CLKEN (1 << PRCM_I2SCLKG_CLKEN_SHIFT)
|
||||
|
||||
/* SSI Clock Gate For Deep Sleep Mode */
|
||||
/* I2S Clock Gate For Run And All Modes (only) */
|
||||
|
||||
#define PRCM_SSICLKGDS_CLKEN_SSI0 (1 << 0) /* Bit 0: SSI0 Enable clock */
|
||||
#define PRCM_SSICLKGDS_CLKEN_SSI1 (1 << 1) /* Bit 1: SSI1 Enable clock */
|
||||
|
||||
/* I2S Clock Gate For Run And All Modes */
|
||||
|
||||
#define PRCM_I2SCLKGR_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
|
||||
#define PRCM_I2SCLKGR_AMCLKEN (1 << 8) /* Bit 8: SSI0 Force clock on for all modes */
|
||||
|
||||
/* I2S Clock Gate For Sleep Mode */
|
||||
|
||||
#define PRCM_I2SCLKGS_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
|
||||
|
||||
/* I2S Clock Gate For Deep Sleep Mode */
|
||||
|
||||
#define PRCM_I2SCLKGDS_CLKEN (1 << 0) /* Bit 0: SSI0 Enable clock */
|
||||
|
||||
/* Internal */
|
||||
|
||||
#define PRCM_SYSBUSCLKDIV_DIV (1 << 0) /* Bit 0: Ratio */
|
||||
@@ -425,7 +404,7 @@
|
||||
# define PRCM_GPTCLKDIV_DIV8 (3 << PRCM_GPTCLKDIV_SHIFT)
|
||||
# define PRCM_GPTCLKDIV_DIV16 (4 << PRCM_GPTCLKDIV_SHIFT)
|
||||
# define PRCM_GPTCLKDIV_DIV32 (5 << PRCM_GPTCLKDIV_SHIFT)
|
||||
# define PRCM_GPTCLKDIV_DIV65 (6 << PRCM_GPTCLKDIV_SHIFT)
|
||||
# define PRCM_GPTCLKDIV_DIV64 (6 << PRCM_GPTCLKDIV_SHIFT)
|
||||
# define PRCM_GPTCLKDIV_DIV128 (7 << PRCM_GPTCLKDIV_SHIFT)
|
||||
# define PRCM_GPTCLKDIV_DIV256 (8 << PRCM_GPTCLKDIV_SHIFT)
|
||||
|
||||
|
||||
@@ -108,9 +108,10 @@
|
||||
* UART0 (PA0/U0RX and PA1/U0TX).
|
||||
*/
|
||||
|
||||
#define GPIO_UART0_RX (GPIO_PORTID(IOC_IOCFG_PORTID_UART0_RX) | IOC_IOCFG_IE | \
|
||||
GPIO_DIO(0))
|
||||
#define GPIO_UART0_TX (GPIO_PORTID(IOC_IOCFG_PORTID_UART0_TX) | GPIO_DIO(1))
|
||||
#define GPIO_UART0_RX (GPIO_PORTID(IOC_IOCFG_PORTID_UART0_RX) | \
|
||||
GPIO_STD_INPUT | GPIO_DIO(0))
|
||||
#define GPIO_UART0_TX (GPIO_PORTID(IOC_IOCFG_PORTID_UART0_TX) | \
|
||||
GPIO_STD_OUTPUT | GPIO_DIO(1))
|
||||
|
||||
/* DMA **********************************************************************/
|
||||
|
||||
|
||||
@@ -81,6 +81,9 @@ void tiva_boardinitialize(void)
|
||||
|
||||
board_autoled_initialize();
|
||||
#endif
|
||||
|
||||
/* TODO: Initialize antenna switch */
|
||||
/* TODO: Shutdown external FLASH */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
Reference in New Issue
Block a user