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SAMA5D2: Finish implementtion of the PIO driver

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This commit is contained in:
Gregory Nutt
2015-09-12 11:36:06 -06:00
parent ac986987de
commit a27e673967
7 changed files with 185 additions and 332 deletions
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arch/arm/include/sama5/sama5d2_irq.h
+2 -2
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@@ -69,7 +69,7 @@
#define SAM_PID_MATRIX0 (15) /* H64MX, 64-bit AHB Matrix */
#define SAM_PID_SECUMOD (16) /* Secure Module */
#define SAM_PID_HSMC (17) /* Multi-bit ECC Interrupt */
#define SAM_PID_PIOA (18) /* Parallel I/O Controller A */
#define SAM_PID_PIO (18) /* Parallel I/O Controller */
#define SAM_PID_FLEXCOM0 (19) /* FLEXCOM 0 */
#define SAM_PID_FLEXCOM1 (20) /* FLEXCOM 1 */
@@ -159,7 +159,7 @@
#define SAM_IRQ_MATRIX0 SAM_PID_MATRIX0 /* H64MX, 64-bit AHB Matrix */
#define SAM_IRQ_SECUMOD SAM_PID_SECUMOD /* Secure Module */
#define SAM_IRQ_HSMC SAM_PID_HSMC /* Multi-bit ECC Interrupt */
#define SAM_IRQ_PIOA SAM_PID_PIOA /* Parallel I/O Controller A */
#define SAM_IRQ_PIO SAM_PID_PIO /* Parallel I/O Controller */
#define SAM_IRQ_FLEXCOM0 SAM_PID_FLEXCOM0 /* FLEXCOM 0 */
#define SAM_IRQ_FLEXCOM1 SAM_PID_FLEXCOM1 /* FLEXCOM 1 */
arch/arm/src/sama5/chip/sama5d2x_pio.h
+8 -6
View File
@@ -67,7 +67,7 @@
#define SAM_PIO_MSKR_OFFSET 0x0000 /* PIO Mask Register */
#define SAM_PIO_CFGR_OFFSET 0x0004 /* PIO Configuration Register */
#define SAM_PIO_PDS_OFFSET 0x0008 /* PIO Pin Data Status Register */
#define SAM_PIO_PDSR_OFFSET 0x0008 /* PIO Pin Data Status Register */
#define SAM_PIO_LOCKSR_OFFSET 0x000c /* PIO Lock Status Register */
#define SAM_PIO_SODR_OFFSET 0x0010 /* PIO Set Output Data Register */
#define SAM_PIO_CODR_OFFSET 0x0014 /* PIO Clear Output Data Register */
@@ -124,7 +124,7 @@
#define SAM_PIOA_MSKR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_MSKR_OFFSET)
#define SAM_PIOA_CFGR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_CFGR_OFFSET)
#define SAM_PIOA_PDS (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_PDS_OFFSET)
#define SAM_PIOA_PDSR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOA_LOCKSR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOA_SODR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOA_CODR (SAM_PIO_IOGROUPA_VBASE+SAM_PIO_CODR_OFFSET)
@@ -137,7 +137,7 @@
#define SAM_PIOB_MSKR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_MSKR_OFFSET)
#define SAM_PIOB_CFGR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_CFGR_OFFSET)
#define SAM_PIOB_PDS (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_PDS_OFFSET)
#define SAM_PIOB_PDSR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOB_LOCKSR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOB_SODR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOB_CODR (SAM_PIO_IOGROUPB_VBASE+SAM_PIO_CODR_OFFSET)
@@ -150,7 +150,7 @@
#define SAM_PIOC_MSKR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_MSKR_OFFSET)
#define SAM_PIOC_CFGR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_CFGR_OFFSET)
#define SAM_PIOC_PDS (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_PDS_OFFSET)
#define SAM_PIOC_PDSR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOC_LOCKSR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOC_SODR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOC_CODR (SAM_PIO_IOGROUPC_VBASE+SAM_PIO_CODR_OFFSET)
@@ -163,7 +163,7 @@
#define SAM_PIOD_MSKR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_MSKR_OFFSET)
#define SAM_PIOD_CFGR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_CFGR_OFFSET)
#define SAM_PIOD_PDS (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_PDS_OFFSET)
#define SAM_PIOD_PDSR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_PDSR_OFFSET)
#define SAM_PIOD_LOCKSR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_LOCKSR_OFFSET)
#define SAM_PIOD_SODR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_SODR_OFFSET)
#define SAM_PIOD_CODR (SAM_PIO_IOGROUPD_VBASE+SAM_PIO_CODR_OFFSET)
@@ -262,7 +262,7 @@
#define PIO_CFGR_FUNC_SHIFT (0) /* Bits 0-2: I/O Line Function */
#define PIO_CFGR_FUNC_MASK (7 << PIO_CFGR_FUNC_SHIFT)
# define PIO_CFGR_FUNC_GPIO (0 << PIO_CFGR_FUNC_SHIFT) /* Select PIO mode */
# define PIO_CFGR_FUNC_PERIPH(n) ((uint32_t)((n)+1) << PIO_CFGR_FUNC_SHIFT)
# define PIO_CFGR_FUNC_PERIPH(n) ((uint32_t)(n) << PIO_CFGR_FUNC_SHIFT)
# define PIO_CFGR_FUNC_PERIPHA (1 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral A */
# define PIO_CFGR_FUNC_PERIPHB (2 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral B */
# define PIO_CFGR_FUNC_PERIPHC (3 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral C */
@@ -271,6 +271,8 @@
# define PIO_CFGR_FUNC_PERIPHF (6 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral F */
# define PIO_CFGR_FUNC_PERIPHG (7 << PIO_CFGR_FUNC_SHIFT) /* Select peripheral G */
#define PIO_CFGR_DIR (1 << 8) /* Bit 8: Direction */
# define PIO_CFGR_DIR_INPUT (0) /* 0=Input */
# define PIO_CFGR_DIR_OUTPUT (1 << 8) /* 1=Output */
#define PIO_CFGR_PUEN (1 << 9) /* Bit 9: Pull-Up Enable */
#define PIO_CFGR_PDEN (1 << 10) /* Bit 10: Pull-Down Enable */
#define PIO_CFGR_IFEN (1 << 12) /* Bit 12: Input Filter Enable */
arch/arm/src/sama5/sam_clockconfig.c
+8
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@@ -44,10 +44,12 @@
#include <nuttx/arch.h>
#include <arch/board/board.h>
#include <arch/sama5/chip.h>
#include "up_arch.h"
#include "up_internal.h"
#include "sam_periphclks.h"
#include "sam_clockconfig.h"
#include "chip/sam_pmc.h"
#include "chip/sam_sfr.h"
@@ -700,6 +702,12 @@ void __ramfunc__ sam_clockconfig(void)
}
#endif /* NEED_PLLSETUP */
#ifdef ATSAMA5D2
/* Enable clocking to the PIO module */
sam_pio_enableclk();
#endif
/* Setup USB clocking */
sam_usbclockconfig();
arch/arm/src/sama5/sama5d2x_periphclks.h
+3 -3
View File
@@ -74,7 +74,7 @@
#define sam_matrix0_enableclk() sam_enableperiph0(SAM_PID_MATRIX0)
#define sam_secumod_enableclk() sam_enableperiph0(SAM_PID_SECUMOD)
#define sam_hsmc_enableclk() sam_enableperiph0(SAM_PID_HSMC)
#define sam_pioa_enableclk() sam_enableperiph0(SAM_PID_PIOA)
#define sam_pio_enableclk() sam_enableperiph0(SAM_PID_PIO)
#define sam_flexcom0_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_enableclk() sam_enableperiph0(SAM_PID_FLEXCOM2)
@@ -144,7 +144,7 @@
#define sam_matrix0_disableclk() sam_disableperiph0(SAM_PID_MATRIX0)
#define sam_secumod_disableclk() sam_disableperiph0(SAM_PID_SECUMOD)
#define sam_hsmc_disableclk() sam_disableperiph0(SAM_PID_HSMC)
#define sam_pioa_disableclk() sam_disableperiph0(SAM_PID_PIOA)
#define sam_pio_disableclk() sam_disableperiph0(SAM_PID_PIO)
#define sam_flexcom0_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_disableclk() sam_disableperiph0(SAM_PID_FLEXCOM2)
@@ -214,7 +214,7 @@
#define sam_matrix0_isenabled() sam_isenabled0(SAM_PID_MATRIX0)
#define sam_secumod_isenabled() sam_isenabled0(SAM_PID_SECUMOD)
#define sam_hsmc_isenabled() sam_isenabled0(SAM_PID_HSMC)
#define sam_pioa_isenabled() sam_isenabled0(SAM_PID_PIOA)
#define sam_pio_isenabled() sam_isenabled0(SAM_PID_PIO)
#define sam_flexcom0_isenabled() sam_isenabled0(SAM_PID_FLEXCOM0)
#define sam_flexcom1_isenabled() sam_isenabled0(SAM_PID_FLEXCOM1)
#define sam_flexcom2_isenabled() sam_isenabled0(SAM_PID_FLEXCOM2)
arch/arm/src/sama5/sama5d2x_pio.c
+149 -307
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File diff suppressed because it is too large Load Diff
arch/arm/src/sama5/sama5d2x_pio.h
+13 -12
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@@ -73,15 +73,15 @@
/* 32-bit Encoding:
*
* .... ...M MMMM CCCC CDDI IISV .PPB BBBB
* .... .MMM MM.C CCCC CDDI IISV .PPB BBBB
*/
/* Input/Output mode:
*
* .... ...M MMMM .... .... .... .... ....
* .... .MMM MM.. .... .... .... .... ....
*/
#define PIO_MODE_SHIFT (20) /* Bits 20-24: PIO mode */
#define PIO_MODE_SHIFT (22) /* Bits 22-26: PIO mode */
#define PIO_MODE_MASK (15 << PIO_MODE_SHIFT)
# define PIO_INPUT (0 << PIO_MODE_SHIFT) /* Input */
# define PIO_OUTPUT (1 << PIO_MODE_SHIFT) /* Output */
@@ -97,17 +97,18 @@
/* These bits set the configuration of the pin:
* NOTE: No definitions for parallel capture mode
*
* .... .... .... CCCC C... .... .... ....
* .... .... ...C CCCC C... .... .... ....
*/
#define PIO_CFG_SHIFT (15) /* Bits 15-19: PIO configuration bits */
#define PIO_CFG_MASK (31 << PIO_CFG_SHIFT)
# define PIO_CFG_DEFAULT (0 << PIO_CFG_SHIFT) /* Default, no attribute */
# define PIO_CFG_PULLUP (1 << PIO_CFG_SHIFT) /* Bit 15: Internal pull-up */
# define PIO_CFG_PULLDOWN (2 << PIO_CFG_SHIFT) /* Bit 16: Internal pull-down */
# define PIO_CFG_DEGLITCH (4 << PIO_CFG_SHIFT) /* Bit 17: Internal input filter */
# define PIO_CFG_OPENDRAIN (8 << PIO_CFG_SHIFT) /* Bit 18: Open drain */
# define PIO_CFG_SCHMITT (16 << PIO_CFG_SHIFT) /* Bit 19: Schmitt trigger */
#define PIO_CFG_SHIFT (15) /* Bits 15-20: PIO configuration bits */
#define PIO_CFG_MASK (0x3f << PIO_CFG_SHIFT)
# define PIO_CFG_DEFAULT (0x00 << PIO_CFG_SHIFT) /* Default, no attribute */
# define PIO_CFG_PULLUP (0x01 << PIO_CFG_SHIFT) /* Bit 15: Internal pull-up */
# define PIO_CFG_PULLDOWN (0x02 << PIO_CFG_SHIFT) /* Bit 16: Internal pull-down */
# define PIO_CFG_DEGLITCH (0x04 << PIO_CFG_SHIFT) /* Bit 17: Internal input filter (Tmck/2)*/
# define PIO_CFG_SLOWCLK (0x0c << PIO_CFG_SHIFT) /* Bits 17+18: Internal input filter (Tslwclk/2)*/
# define PIO_CFG_OPENDRAIN (0x10 << PIO_CFG_SHIFT) /* Bit 19: Open drain */
# define PIO_CFG_SCHMITT (0x20 << PIO_CFG_SHIFT) /* Bit 20: Schmitt trigger */
/* Drive Strength:
*
arch/arm/src/sama5/sama5d3x4x_pio.c
+2 -2
View File
@@ -51,7 +51,7 @@
#include "up_internal.h"
#include "up_arch.h"
#include "chip/sam_pio.h"
#include "chip/sama5d3x4x_pio.h"
#include "chip.h"
#include "sam_periphclks.h"
@@ -689,7 +689,7 @@ int sam_configpio(pio_pinset_t cfgset)
putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
/* Put the pin in an intial state -- a vanilla input pin */
/* Put the pin in an initial state -- a vanilla input pin */
(void)sam_configinput(base, pin, MK_INPUT(cfgset));