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Merged in raiden00/nuttx_pe (pull request #796)

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arch/arm/src/stm32: unified naming for DAC interfaces

Approved-by: GregoryN <gnutt@nuttx.org>
This commit is contained in:
raiden00pl
2019-01-02 12:12:28 +00:00
committed by GregoryN
parent 7d2413a6a0
commit a20e874883
31 changed files with 151 additions and 187 deletions
Download Patch File Download Diff File Expand all files Collapse all files

140
arch/arm/include/stm32/chip.h
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File diff suppressed because it is too large Load Diff

36
arch/arm/src/stm32/Kconfig
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@@ -233,7 +233,6 @@ config ARCH_CHIP_STM32F100C8
select STM32_VALUELINE
select STM32_MEDIUMDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -243,7 +242,6 @@ config ARCH_CHIP_STM32F100CB
select STM32_VALUELINE
select STM32_MEDIUMDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -253,7 +251,6 @@ config ARCH_CHIP_STM32F100R8
select STM32_VALUELINE
select STM32_MEDIUMDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -263,7 +260,6 @@ config ARCH_CHIP_STM32F100RB
select STM32_VALUELINE
select STM32_MEDIUMDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -273,7 +269,6 @@ config ARCH_CHIP_STM32F100RC
select STM32_VALUELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -283,7 +278,6 @@ config ARCH_CHIP_STM32F100RD
select STM32_VALUELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -293,7 +287,6 @@ config ARCH_CHIP_STM32F100RE
select STM32_VALUELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -303,7 +296,6 @@ config ARCH_CHIP_STM32F100V8
select STM32_VALUELINE
select STM32_MEDIUMDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -313,7 +305,6 @@ config ARCH_CHIP_STM32F100VB
select STM32_VALUELINE
select STM32_MEDIUMDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -323,7 +314,6 @@ config ARCH_CHIP_STM32F100VC
select STM32_VALUELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -333,7 +323,6 @@ config ARCH_CHIP_STM32F100VD
select STM32_VALUELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -343,7 +332,6 @@ config ARCH_CHIP_STM32F100VE
select STM32_VALUELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -413,7 +401,6 @@ config ARCH_CHIP_STM32F103RC
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -423,7 +410,6 @@ config ARCH_CHIP_STM32F103RD
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -433,7 +419,6 @@ config ARCH_CHIP_STM32F103RE
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -443,7 +428,6 @@ config ARCH_CHIP_STM32F103RG
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -469,7 +453,6 @@ config ARCH_CHIP_STM32F103VC
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -479,7 +462,6 @@ config ARCH_CHIP_STM32F103VE
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -489,7 +471,6 @@ config ARCH_CHIP_STM32F103ZE
select STM32_PERFORMANCELINE
select STM32_HIGHDENSITY
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -498,7 +479,6 @@ config ARCH_CHIP_STM32F105VB
select STM32_STM32F10XX
select STM32_CONNECTIVITYLINE
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -507,7 +487,6 @@ config ARCH_CHIP_STM32F105RB
select STM32_STM32F10XX
select STM32_CONNECTIVITYLINE
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_TIM4
@@ -516,7 +495,6 @@ config ARCH_CHIP_STM32F107VC
select STM32_STM32F10XX
select STM32_CONNECTIVITYLINE
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_TIM4
config ARCH_CHIP_STM32F205RG
@@ -683,18 +661,21 @@ config ARCH_CHIP_STM32F303K6
select STM32_STM32F30XX
select STM32_STM32F303
select ARCH_HAVE_FPU
select STM32_HAVE_DAC2
config ARCH_CHIP_STM32F303K8
bool "STM32F303K8"
select STM32_STM32F30XX
select STM32_STM32F303
select ARCH_HAVE_FPU
select STM32_HAVE_DAC2
config ARCH_CHIP_STM32F303C6
bool "STM32F303C6"
select STM32_STM32F30XX
select STM32_STM32F303
select ARCH_HAVE_FPU
select STM32_HAVE_DAC2
select STM32_HAVE_USART3
config ARCH_CHIP_STM32F303C8
@@ -702,6 +683,7 @@ config ARCH_CHIP_STM32F303C8
select STM32_STM32F30XX
select STM32_STM32F303
select ARCH_HAVE_FPU
select STM32_HAVE_DAC2
select STM32_HAVE_USART3
config ARCH_CHIP_STM32F303CB
@@ -1329,7 +1311,6 @@ config STM32_STM32L15XX
select STM32_ENERGYLITE
select STM32_HAVE_USBDEV
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_SPI2
select STM32_HAVE_SPI3
@@ -1504,7 +1485,6 @@ config STM32_STM32F205
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_I2C3
select STM32_HAVE_RNG
@@ -1538,7 +1518,6 @@ config STM32_STM32F207
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_I2C2
select STM32_HAVE_I2C3
select STM32_HAVE_RNG
@@ -1580,7 +1559,6 @@ config STM32_STM32F303
select STM32_HAVE_ADC2
select STM32_HAVE_ADC2_DMA
select STM32_HAVE_CCM
select STM32_HAVE_DAC2
select STM32_HAVE_TIM7
config STM32_STM32F33XX
@@ -1736,7 +1714,6 @@ config STM32_STM32F405
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
@@ -1771,7 +1748,6 @@ config STM32_STM32F407
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_SPI3
select STM32_HAVE_I2S3
select STM32_HAVE_I2C3
@@ -1810,7 +1786,6 @@ config STM32_STM32F427
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_RNG
select STM32_HAVE_ETHMAC
select STM32_HAVE_SPI2
@@ -1854,7 +1829,6 @@ config STM32_STM32F429
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_RNG
select STM32_HAVE_ETHMAC
select STM32_HAVE_SPI2
@@ -1893,7 +1867,6 @@ config STM32_STM32F446
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_SPI3
select STM32_HAVE_SPI4
select STM32_HAVE_I2S3
@@ -1935,7 +1908,6 @@ config STM32_STM32F469
select STM32_HAVE_CAN1
select STM32_HAVE_CAN2
select STM32_HAVE_DAC1
select STM32_HAVE_DAC2
select STM32_HAVE_RNG
select STM32_HAVE_SPI3
select STM32_HAVE_SPI4

20
arch/arm/src/stm32/chip/stm32_dac.h
View File

@@ -66,22 +66,7 @@
/* Register Addresses ***************************************************************/
#if STM32_NDAC < 2
# define STM32_DAC_CR (STM32_DAC_BASE+STM32_DAC_CR_OFFSET)
# define STM32_DAC_SWTRIGR (STM32_DAC_BASE+STM32_DAC_SWTRIGR_OFFSET)
# define STM32_DAC_DHR12R1 (STM32_DAC_BASE+STM32_DAC_DHR12R1_OFFSET)
# define STM32_DAC_DHR12L1 (STM32_DAC_BASE+STM32_DAC_DHR12L1_OFFSET)
# define STM32_DAC_DHR8R1 (STM32_DAC_BASE+STM32_DAC_DHR8R1_OFFSET)
# define STM32_DAC_DHR12R2 (STM32_DAC_BASE+STM32_DAC_DHR12R2_OFFSET)
# define STM32_DAC_DHR12L2 (STM32_DAC_BASE+STM32_DAC_DHR12L2_OFFSET)
# define STM32_DAC_DHR8R2 (STM32_DAC_BASE+STM32_DAC_DHR8R2_OFFSET)
# define STM32_DAC_DHR12RD (STM32_DAC_BASE+STM32_DAC_DHR12RD_OFFSET)
# define STM32_DAC_DHR12LD (STM32_DAC_BASE+STM32_DAC_DHR12LD_OFFSET)
# define STM32_DAC_DHR8RD (STM32_DAC_BASE+STM32_DAC_DHR8RD_OFFSET)
# define STM32_DAC_DOR1 (STM32_DAC_BASE+STM32_DAC_DOR1_OFFSET)
# define STM32_DAC_DOR2 (STM32_DAC_BASE+STM32_DAC_DOR2_OFFSET)
# define STM32_DAC_SR (STM32_DAC_BASE+STM32_DAC_SR_OFFSET)
#else
#if STM32_NDAC > 0
/* DAC1 */
# define STM32_DAC1_CR (STM32_DAC1_BASE+STM32_DAC_CR_OFFSET)
@@ -99,6 +84,9 @@
# define STM32_DAC1_DOR2 (STM32_DAC1_BASE+STM32_DAC_DOR2_OFFSET)
# define STM32_DAC1_SR (STM32_DAC1_BASE+STM32_DAC_SR_OFFSET)
#endif
#if STM32_NDAC > 2
/* DAC2 */
# define STM32_DAC2_CR (STM32_DAC2_BASE+STM32_DAC_CR_OFFSET)

5
arch/arm/src/stm32/chip/stm32_dma_v1.h
View File

@@ -475,7 +475,7 @@
# define DMACHAN_TIM1_CH2_1 STM32_DMA1_CHAN3
# define DMACHAN_TIM3_CH4 STM32_DMA1_CHAN3
# define DMACHAN_TIM3_UP_2 STM32_DMA1_CHAN3
# define DMACHAN_DAC_CH1 STM32_DMA1_CHAN3
# define DMACHAN_DAC1_CH1 STM32_DMA1_CHAN3
# define DMACHAN_SPI2_RX STM32_DMA1_CHAN4
# define DMACHAN_I2S2_RX STM32_DMA1_CHAN4
@@ -486,7 +486,7 @@
# define DMACHAN_TIM1_COM STM32_DMA1_CHAN4
# define DMACHAN_TIM4_CH2 STM32_DMA1_CHAN4
# define DMACHAN_TIM7_UP_1 STM32_DMA1_CHAN4
# define DMACHAN_DAC_CH2 STM32_DMA1_CHAN4
# define DMACHAN_DAC1_CH2 STM32_DMA1_CHAN4 /* NOTE: a typo in the ref manual */
# define DMACHAN_SPI2_TX STM32_DMA1_CHAN5
# define DMACHAN_I2S2_TX STM32_DMA1_CHAN5
@@ -499,6 +499,7 @@
# define DMACHAN_TIM15_UP STM32_DMA1_CHAN5
# define DMACHAN_TIM15_TRIG STM32_DMA1_CHAN5
# define DMACHAN_TIM15_COM STM32_DMA1_CHAN5
# define DMACHAN_DAC2_CH1 STM32_DMA1_CHAN5
# define DMACHAN_USART2_RX STM32_DMA1_CHAN6
# define DMACHAN_I2C1_TX STM32_DMA1_CHAN6

4
arch/arm/src/stm32/chip/stm32_dma_v2.h
View File

@@ -480,8 +480,8 @@
#define DMAMAP_I2C2_RX_1 STM32_DMA_MAP(DMA1,DMA_STREAM2,DMA_CHAN7)
#define DMAMAP_I2C2_RX_2 STM32_DMA_MAP(DMA1,DMA_STREAM3,DMA_CHAN7)
#define DMAMAP_USART3_TX_2 STM32_DMA_MAP(DMA1,DMA_STREAM4,DMA_CHAN7)
#define DMAMAP_DAC1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7)
#define DMAMAP_DAC2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7)
#define DMAMAP_DAC1_CH1 STM32_DMA_MAP(DMA1,DMA_STREAM5,DMA_CHAN7)
#define DMAMAP_DAC1_CH2 STM32_DMA_MAP(DMA1,DMA_STREAM6,DMA_CHAN7)
#define DMAMAP_I2C2_TX STM32_DMA_MAP(DMA1,DMA_STREAM7,DMA_CHAN7)
#define DMAMAP_ADC1_1 STM32_DMA_MAP(DMA2,DMA_STREAM0,DMA_CHAN0)

4
arch/arm/src/stm32/chip/stm32f100_pinmap.h
View File

@@ -88,8 +88,8 @@
* pin should first be configured to analog (AIN)."
*/
#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#define GPIO_DAC1_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
/* FSMC */

4
arch/arm/src/stm32/chip/stm32f103v_pinmap.h
View File

@@ -131,8 +131,8 @@
#define GPIO_NPS_NE1 (GPIO_ALT|GPIO_CNF_AFPP|GPIO_MODE_50MHz|GPIO_PORTD|GPIO_PIN7)
#if 0 /* Needs further investigation */
#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#define GPIO_DAC1_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#endif
#if defined(CONFIG_STM32_I2C1_REMAP)

4
arch/arm/src/stm32/chip/stm32f103z_pinmap.h
View File

@@ -106,8 +106,8 @@
* should first be configured to analog (AIN)."
*/
#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#define GPIO_DAC1_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
/* TIMERS */

4
arch/arm/src/stm32/chip/stm32f105r_pinmap.h
View File

@@ -84,8 +84,8 @@
#endif
#if 0 /* Needs further investigation */
#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#define GPIO_DAC1_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#endif
#if defined(CONFIG_STM32_I2C1_REMAP)

4
arch/arm/src/stm32/chip/stm32f105v_pinmap.h
View File

@@ -87,8 +87,8 @@
#endif
#if 0 /* Needs further investigation */
#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#define GPIO_DAC1_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#endif
#if defined(CONFIG_STM32_I2C1_REMAP)

4
arch/arm/src/stm32/chip/stm32f107v_pinmap.h
View File

@@ -87,8 +87,8 @@
#endif
#if 0 /* Needs further investigation */
#define GPIO_DAC_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#define GPIO_DAC1_OUT1 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_OUT2 (GPIO_INPUT|GPIO_CNF_ANALOGIN|GPIO_MODE_INPUT|GPIO_PORTA|GPIO_PIN5)
#endif
/* Section 29.3 in the stm32 datasheet (Doc ID 13902 Rev 14) */

2
arch/arm/src/stm32/chip/stm32f10xxx_memorymap.h
View File

@@ -95,7 +95,7 @@
#define STM32_CAN2_BASE 0x40006800 /* 0x40006800 - 0x40006bff: bxCAN2 */
#define STM32_BKP_BASE 0x40006c00 /* 0x40006c00 - 0x40006fff: Backup registers (BKP) */
#define STM32_PWR_BASE 0x40007000 /* 0x40007000 - 0x400073ff: Power control PWR */
#define STM32_DAC_BASE 0x40007400 /* 0x40007400 - 0x400077ff: DAC */
#define STM32_DAC1_BASE 0x40007400 /* 0x40007400 - 0x400077ff: DAC1 */
#define STM32_CEC_BASE 0x40007800 /* 0x40007800 - 0x40007bff: CEC */
/* 0x40007c00 - 0x4000ffff: Reserved */
/* APB2 bus */

4
arch/arm/src/stm32/chip/stm32f10xxx_rcc.h
View File

@@ -269,7 +269,7 @@
#endif
#define RCC_APB1RSTR_BKPRST (1 << 27) /* Bit 27: Backup interface reset */
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC interface reset */
#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 interface reset */
#ifdef CONFIG_STM32_VALUELINE
# define RCC_APB1RSTR_CECRST (1 << 30) /* Bit 30: CEC reset */
#endif
@@ -357,7 +357,7 @@
#endif
#define RCC_APB1ENR_BKPEN (1 << 27) /* Bit 27: Backup interface clock enable */
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
#define RCC_APB1ENR_DAC1EN (1 << 29) /* Bit 29: DAC1 interface clock enable */
#ifdef CONFIG_STM32_VALUELINE
# define RCC_APB1ENR_CECEN (1 << 30) /* Bit 30: CEC clock enable */
#endif

2
arch/arm/src/stm32/chip/stm32f20xxx_memorymap.h
View File

@@ -147,7 +147,7 @@
#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff: bxCAN1 */
#define STM32_CAN2_BASE 0x40006800 /* 0x40006800-0x40006bff: bxCAN2 */
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff: Power control PWR */
#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff: DAC */
#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff: DAC1 */
/* APB2 Base Addresses **************************************************************/

4
arch/arm/src/stm32/chip/stm32f20xxx_pinmap.h
View File

@@ -143,8 +143,8 @@
* should first be configured to analog (AIN)".
*/
#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
#define GPIO_DAC1_OUT1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_OUT2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
/* Digital Camera Interface (DCMI) */

4
arch/arm/src/stm32/chip/stm32f20xxx_rcc.h
View File

@@ -281,7 +281,7 @@
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* Bit 26: CAN2 reset */
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC reset */
#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 reset */
/* APB2 Peripheral reset register */
@@ -356,7 +356,7 @@
#define RCC_APB1ENR_CAN1EN (1 << 25) /* Bit 25: CAN 1 clock enable */
#define RCC_APB1ENR_CAN2EN (1 << 26) /* Bit 26: CAN 2 clock enable */
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
#define RCC_APB1ENR_DAC1EN (1 << 29) /* Bit 29: DAC1 interface clock enable */
#define RCC_APB1ENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */
#define RCC_APB1ENR_UART8EN (1 << 31) /* Bit 31: UART8 clock enable */

5
arch/arm/src/stm32/chip/stm32f30xxx_memorymap.h
View File

@@ -111,7 +111,10 @@
#define STM32_USBRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */
#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff bxCAN */
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC (dual) */
#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC1 */
#ifdef CONFIG_STM32_HAVE_DAC2
# define STM32_DAC2_BASE 0x40009800 /* 0x40009800-0x40009bff DAC2 */
#endif
/* APB2 Base Addresses **************************************************************/

4
arch/arm/src/stm32/chip/stm32f30xxx_pinmap.h
View File

@@ -167,8 +167,8 @@
* should first be configured to analog (AIN)".
*/
#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
#define GPIO_DAC1_OUT1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_OUT2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
/* I2C */

6
arch/arm/src/stm32/chip/stm32f30xxx_rcc.h
View File

@@ -207,8 +207,9 @@
#define RCC_APB1RSTR_I2C2RST (1 << 22) /* Bit 22: I2C 2 reset */
#define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */
#define RCC_APB1RSTR_DAC2RST (1 << 26) /* Bit 26: DAC2 interface reset */
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC interface reset */
#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 interface reset */
/* AHB Peripheral Clock enable register */
@@ -256,8 +257,9 @@
#define RCC_APB1ENR_I2C2EN (1 << 22) /* Bit 22: I2C 2 clock enable */
#define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */
#define RCC_APB1ENR_CAN1EN (1 << 25) /* Bit 25: CAN1 clock enable */
#define RCC_APB1ENR_DAC2EN (1 << 26) /* Bit 26: DAC2 interface clock enable */
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
#define RCC_APB1ENR_DAC1EN (1 << 29) /* Bit 29: DAC1 interface clock enable */
/* Backup domain control register */

2
arch/arm/src/stm32/chip/stm32f40xxx_memorymap.h
View File

@@ -147,7 +147,7 @@
#define STM32_CAN1_BASE 0x40006400 /* 0x40006400-0x400067ff: bxCAN1 */
#define STM32_CAN2_BASE 0x40006800 /* 0x40006800-0x40006bff: bxCAN2 */
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff: Power control PWR */
#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff: DAC */
#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff: DAC1 */
#define STM32_UART7_BASE 0x40007800 /* 0x40007800-0x40007bff: UART7 */
#define STM32_UART8_BASE 0x40007c00 /* 0x40007c00-0x40007fff: UART8 */

4
arch/arm/src/stm32/chip/stm32f40xxx_pinmap.h
View File

@@ -146,8 +146,8 @@
* should first be configured to analog (AIN)".
*/
#define GPIO_DAC1_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC2_OUT (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
#define GPIO_DAC1_OUT1 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN4)
#define GPIO_DAC1_OUT2 (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
/* Digital Camera Interface (DCMI) */

4
arch/arm/src/stm32/chip/stm32f40xxx_rcc.h
View File

@@ -339,7 +339,7 @@
#define RCC_APB1RSTR_CAN1RST (1 << 25) /* Bit 25: CAN1 reset */
#define RCC_APB1RSTR_CAN2RST (1 << 26) /* Bit 26: CAN2 reset */
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC reset */
#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 reset */
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
# define RCC_APB1RSTR_UART7RST (1 << 30) /* Bit 30: USART 7 reset */
@@ -485,7 +485,7 @@
# define RCC_APB1ENR_CECEN (1 << 27) /* Bit 27: CEC clock enable */
#endif
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
#define RCC_APB1ENR_DAC1EN (1 << 29) /* Bit 29: DAC1 interface clock enable */
#if defined(CONFIG_STM32_STM32F427) || defined(CONFIG_STM32_STM32F429) || \
defined(CONFIG_STM32_STM32F469)
# define RCC_APB1ENR_UART7EN (1 << 30) /* Bit 30: UART7 clock enable */

2
arch/arm/src/stm32/chip/stm32l15xxx_memorymap.h
View File

@@ -100,7 +100,7 @@
#define STM32_USB_BASE 0x40005c00 /* 0x40005c00-0x40005fff USB device FS */
#define STM32_USBRAM_BASE 0x40006000 /* 0x40006000-0x400063ff USB SRAM 512B */
#define STM32_PWR_BASE 0x40007000 /* 0x40007000-0x400073ff PWR */
#define STM32_DAC_BASE 0x40007400 /* 0x40007400-0x400077ff DAC (dual) */
#define STM32_DAC1_BASE 0x40007400 /* 0x40007400-0x400077ff DAC1 */
#define STM32_DAC_COMP 0x40007c00 /* 0x40007c00-0x40007c03 COMP */
#define STM32_DAC_RI 0x40007c04 /* 0x40007c04-0x40007c5b RI */
#define STM32_DAC_OPAMP 0x40007c5c /* 0x40007c5c-0x40007fff OPAMP */

4
arch/arm/src/stm32/chip/stm32l15xxx_pinmap.h
View File

@@ -108,8 +108,8 @@
/* DAC */
#define GPIO_DAC_OUT1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
#define GPIO_DAC_OUT2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
#define GPIO_DAC1_OUT1 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN4)
#define GPIO_DAC1_OUT2 (GPIO_ANALOG | GPIO_PORTA | GPIO_PIN5)
/* I2C */

4
arch/arm/src/stm32/chip/stm32l15xxx_rcc.h
View File

@@ -291,7 +291,7 @@
#define RCC_APB1RSTR_USBRST (1 << 23) /* Bit 23: USB reset */
/* Bits 24-27: Reserved */
#define RCC_APB1RSTR_PWRRST (1 << 28) /* Bit 28: Power interface reset */
#define RCC_APB1RSTR_DACRST (1 << 29) /* Bit 29: DAC interface reset */
#define RCC_APB1RSTR_DAC1RST (1 << 29) /* Bit 29: DAC1 interface reset */
/* Bit 30: Reserved */
#define RCC_APB1RSTR_COMPRST (1 << 31) /* Bit 31: COMP interface reset */
@@ -360,7 +360,7 @@
#define RCC_APB1ENR_USBEN (1 << 23) /* Bit 23: USB clock enable */
/* Bits 24-27: Reserved */
#define RCC_APB1ENR_PWREN (1 << 28) /* Bit 28: Power interface clock enable */
#define RCC_APB1ENR_DACEN (1 << 29) /* Bit 29: DAC interface clock enable */
#define RCC_APB1ENR_DAC1EN (1 << 29) /* Bit 29: DAC1 interface clock enable */
/* Bit 30: Reserved */
#define RCC_APB1ENR_COMPEN (1 << 31) /* Bit 31: COMP interface clock enable */

22
arch/arm/src/stm32/stm32_dac.c
View File

@@ -70,7 +70,13 @@
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/* Up to 2 DAC interfaces for up to 3 channels are supported */
/* Up to 2 DAC interfaces for up to 3 channels are supported
*
* NOTE: STM32_NDAC tells how many channels chip supports.
* ST is not consistent in the naming of DAC interfaces, so we introduce
* our own naming convention. We distinguish DAC1 and DAC2 only if the chip
* has two separate areas in memory map to support DAC channels.
*/
#if STM32_NDAC < 3
# warning
@@ -629,15 +635,9 @@ uint16_t dac1ch1_buffer[CONFIG_STM32_DAC1CH1_DMA_BUFFER_SIZE];
static struct stm32_chan_s g_dac1ch1priv =
{
.intf = 0,
#if STM32_NDAC < 2
.pin = GPIO_DAC1_OUT,
.dro = STM32_DAC_DHR12R1,
.cr = STM32_DAC_CR,
#else
.pin = GPIO_DAC1_OUT1,
.dro = STM32_DAC1_DHR12R1,
.cr = STM32_DAC1_CR,
#endif
#ifdef CONFIG_STM32_DAC1CH1_DMA
.hasdma = 1,
.dmachan = DAC1CH1_DMA_CHAN,
@@ -1513,29 +1513,21 @@ static int dac_blockinit(void)
flags = enter_critical_section();
regval = getreg32(STM32_RCC_APB1RSTR);
#if STM32_NDAC < 2
regval |= RCC_APB1RSTR_DACRST;
#else
#ifdef CONFIG_STM32_DAC1
regval |= RCC_APB1RSTR_DAC1RST;
#endif
#ifdef CONFIG_STM32_DAC2
regval |= RCC_APB1RSTR_DAC2RST;
#endif
#endif
putreg32(regval, STM32_RCC_APB1RSTR);
/* Take the DAC out of reset state */
#if STM32_NDAC < 2
regval &= ~RCC_APB1RSTR_DACRST;
#else
#ifdef CONFIG_STM32_DAC1
regval &= ~RCC_APB1RSTR_DAC1RST;
#endif
#ifdef CONFIG_STM32_DAC2
regval &= ~RCC_APB1RSTR_DAC2RST;
#endif
#endif
putreg32(regval, STM32_RCC_APB1RSTR);
leave_critical_section(flags);

6
arch/arm/src/stm32/stm32f10xxx_rcc.c
View File

@@ -367,10 +367,10 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR_PWREN;
#endif
#if defined(CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
/* DAC interface clock enable */
#if defined(CONFIG_STM32_DAC1)
/* DAC1 interface clock enable */
regval |= RCC_APB1ENR_DACEN;
regval |= RCC_APB1ENR_DAC1EN;
#endif
#ifdef CONFIG_STM32_CEC

6
arch/arm/src/stm32/stm32f20xxx_rcc.c
View File

@@ -435,10 +435,10 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR_PWREN;
#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
/* DAC interface clock enable */
#if defined (CONFIG_STM32_DAC1)
/* DAC1 interface clock enable */
regval |= RCC_APB1ENR_DACEN;
regval |= RCC_APB1ENR_DAC1EN;
#endif
putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */

12
arch/arm/src/stm32/stm32f30xxx_rcc.c
View File

@@ -314,10 +314,16 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR_PWREN;
#endif
#ifdef CONFIG_STM32_DAC
/* DAC interface clock enable */
#ifdef CONFIG_STM32_DAC1
/* DAC2 interface clock enable */
regval |= RCC_APB1ENR_DACEN;
regval |= RCC_APB1ENR_DAC1EN;
#endif
#ifdef CONFIG_STM32_DAC2
/* DAC2 interface clock enable */
regval |= RCC_APB1ENR_DAC2EN;
#endif
putreg32(regval, STM32_RCC_APB1ENR);

6
arch/arm/src/stm32/stm32f40xxx_rcc.c
View File

@@ -463,10 +463,10 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR_PWREN;
#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
/* DAC interface clock enable */
#if defined (CONFIG_STM32_DAC1)
/* DAC1 interface clock enable */
regval |= RCC_APB1ENR_DACEN;
regval |= RCC_APB1ENR_DAC1EN;
#endif
#ifdef CONFIG_STM32_UART7

6
arch/arm/src/stm32/stm32l15xxx_rcc.c
View File

@@ -371,10 +371,10 @@ static inline void rcc_enableapb1(void)
regval |= RCC_APB1ENR_PWREN;
#endif
#ifdef CONFIG_STM32_DAC
/* DAC interface clock enable */
#ifdef CONFIG_STM32_DAC1
/* DAC1 interface clock enable */
regval |= RCC_APB1ENR_DACEN;
regval |= RCC_APB1ENR_DAC1EN;
#endif
#ifdef CONFIG_STM32_COMP