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Correct #if to #ifdef when the macro can be undefined. Fix bug in AT32UC3 clock initialization: AVR32_CLOCK_PLL_OSC1 should be AVR32_CLOCK_PLL0_OSC1 and AVR32_CLOCK_PLL1_OSC1.

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This commit is contained in:
Paul A. Patience
2015-09-01 09:52:32 -04:00
parent 9ba349f2b8
commit a0dc724a5d
42 changed files with 146 additions and 147 deletions
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arch/arm/src/calypso/calypso_serial.c
+1 -1
View File
@@ -377,7 +377,7 @@ static inline void up_setrate(struct up_dev_s *priv, unsigned int rate)
break;
}
#if UART_DIV_BIT_RATE_OFFS
#ifdef UART_DIV_BIT_RATE_OFFS
up_serialout(priv, UART_DIV_BIT_RATE_OFFS, div_bit_rate);
#else
up_serialout(priv, UART_DIV_LOW_OFFS, div_bit_rate);
arch/arm/src/kinetis/kinetis_enet.c
+2 -2
View File
@@ -1338,7 +1338,7 @@ static inline void kinetis_initphy(struct kinetis_driver_s *priv)
* configuration and the auto negotiation results.
*/
#if CONFIG_ENET_USEMII
#ifdef CONFIG_ENET_USEMII
rcr = ENET_RCR_MII_MODE | ENET_RCR_CRCFWD |
CONFIG_NET_ETH_MTU << ENET_RCR_MAX_FL_SHIFT;
#else
@@ -1527,7 +1527,7 @@ int kinetis_netinitialize(int intf)
/* Configure all ENET/MII pins */
#if CONFIG_ENET_USEMII
#ifdef CONFIG_ENET_USEMII
kinetis_pinconfig(PIN_MII0_MDIO);
kinetis_pinconfig(PIN_MII0_MDC);
kinetis_pinconfig(PIN_MII0_RXDV);
arch/arm/src/kinetis/kinetis_sdhc.c
+5 -5
View File
@@ -65,7 +65,7 @@
#include "kinetis_sim.h"
#include "kinetis_sdhc.h"
#if CONFIG_KINETIS_SDHC
#ifdef CONFIG_KINETIS_SDHC
/****************************************************************************
* Pre-processor Definitions
@@ -102,7 +102,7 @@
* and divider values.
*/
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
# ifndef CONFIG_KINETIS_IDMODE_FREQ
# define CONFIG_KINETIS_IDMODE_FREQ 400000 /* 400 KHz, ID mode */
# endif
@@ -287,7 +287,7 @@ static int kinetis_lock(FAR struct sdio_dev_s *dev, bool lock);
static void kinetis_reset(FAR struct sdio_dev_s *dev);
static uint8_t kinetis_status(FAR struct sdio_dev_s *dev);
static void kinetis_widebus(FAR struct sdio_dev_s *dev, bool enable);
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency);
#endif
static void kinetis_clock(FAR struct sdio_dev_s *dev,
@@ -1387,7 +1387,7 @@ static void kinetis_widebus(FAR struct sdio_dev_s *dev, bool wide)
*
****************************************************************************/
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
{
uint32_t sdclkfs;
@@ -1523,7 +1523,7 @@ static void kinetis_frequency(FAR struct sdio_dev_s *dev, uint32_t frequency)
*
****************************************************************************/
#if CONFIG_KINETIS_SDHC_ABSFREQ
#ifdef CONFIG_KINETIS_SDHC_ABSFREQ
static void kinetis_clock(FAR struct sdio_dev_s *dev, enum sdio_clock_e rate)
{
uint32_t frequency;
arch/arm/src/lpc17xx/lpc176x_rtc.c
+2 -2
View File
@@ -250,7 +250,7 @@ static int rtc_resume(void)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static int rtc_interrupt(int irq, void *context)
{
#warning "Missing logic"
@@ -285,7 +285,7 @@ int up_rtcinitialize(void)
/* Attach the RTC interrupt handler */
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
ret = irq_attach(LPC17_IRQ_RTC, rtc_interrupt);
if (ret == OK)
{
arch/arm/src/lpc17xx/lpc17_ethernet.c
+1 -1
View File
@@ -1564,7 +1564,7 @@ static void lpc17_poll_process(FAR struct lpc17_driver_s *priv)
if (considx != prodidx)
{
#if CONFIG_NET_NOINTS
#ifdef CONFIG_NET_NOINTS
work_queue(HPWORK, &priv->lp_rxwork, (worker_t)lpc17_rxdone_work,
priv, 0);
arch/arm/src/lpc17xx/lpc17_lcd.c
+1 -1
View File
@@ -565,7 +565,7 @@ int up_fbinitialize(void)
/* TFT panel */
#if CONFIG_LPC17_LCD_TFTPANEL
#ifdef CONFIG_LPC17_LCD_TFTPANEL
regval |= LCD_CTRL_LCDTFT;
#endif
arch/arm/src/lpc17xx/lpc17_sdcard.c
+1 -1
View File
@@ -67,7 +67,7 @@
#include "chip/lpc17_syscon.h"
#include "chip/lpc17_pinconfig.h"
#if CONFIG_LPC17_SDCARD
#ifdef CONFIG_LPC17_SDCARD
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/lpc17xx/lpc17_usbdev.c
+1 -1
View File
@@ -2088,7 +2088,7 @@ static int lpc17_usbinterrupt(int irq, FAR void *context)
#endif
#if CONFIG_DEBUG
#ifdef CONFIG_DEBUG
/* USB engine error interrupt */
if ((devintstatus & USBDEV_INT_ERRINT) != 0)
arch/arm/src/lpc214x/lpc214x_usbdev.c
+1 -1
View File
@@ -2052,7 +2052,7 @@ static int lpc214x_usbinterrupt(int irq, FAR void *context)
#endif
#if CONFIG_DEBUG
#ifdef CONFIG_DEBUG
/* USB engine error interrupt */
if ((devintstatus & USBDEV_DEVINT_EPRINT))
arch/arm/src/lpc43xx/lpc43_spifi.c
+1 -1
View File
@@ -1093,7 +1093,7 @@ static inline int lpc43_rominit(FAR struct lpc43_dev_s *priv)
fvdbg(" blksize: %08x\n", priv->blksize);
fvdbg(" nblocks: %d\n", priv->nblocks);
#if CONFIG_SPIFI_SECTOR512
#ifdef CONFIG_SPIFI_SECTOR512
DEBUGASSERT(log2 > 9);
#endif
arch/arm/src/sam34/sam4l_clockconfig.c
+1 -1
View File
@@ -1293,7 +1293,7 @@ void sam_clockconfig(void)
* OSC32: Might be source clock for DFLL0
*/
#if NEED_OSC0
#ifdef NEED_OSC0
/* Enable OSC0 using the settings in board.h */
sam_enableosc0();
arch/arm/src/sam34/sam_hsmci.c
+1 -1
View File
@@ -80,7 +80,7 @@
# include "chip/sam_pdc.h"
#endif
#if CONFIG_SAM34_HSMCI
#ifdef CONFIG_SAM34_HSMCI
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/sam34/sam_rtc.c
+3 -3
View File
@@ -254,7 +254,7 @@ static int rtc_bcd2bin(uint32_t value)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static void rtc_worker(FAR void *arg)
{
/* Sample once (atomically) */
@@ -287,7 +287,7 @@ static void rtc_worker(FAR void *arg)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static int rtc_interrupt(int irq, void *context)
{
int ret;
@@ -414,7 +414,7 @@ int up_rtcinitialize(void)
#endif
#if defined(CONFIG_RTC_HIRES) && defined (CONFIG_SAM34_RTT)
#if defined(CONFIG_RTC_HIRES) && defined(CONFIG_SAM34_RTT)
/* Using the RTT for subsecond ticks. */
sam_rtt_enableclk();
arch/arm/src/sam34/sam_timerisr.c
+2 -2
View File
@@ -85,7 +85,7 @@
#undef CONFIG_SAM34_SYSTICK_HCLKd8 /* Power up default is MCK, not MCK/8 */
#if CONFIG_SAM34_SYSTICK_HCLKd8
#ifdef CONFIG_SAM34_SYSTICK_HCLKd8
# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / 8 / CLK_TCK) - 1)
#else
# define SYSTICK_RELOAD ((SAM_SYSTICK_CLOCK / CLK_TCK) - 1)
@@ -152,7 +152,7 @@ void up_timer_initialize(void)
#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
regval = getreg32(NVIC_SYSTICK_CTRL);
#if CONFIG_SAM34_SYSTICK_HCLKd8
#ifdef CONFIG_SAM34_SYSTICK_HCLKd8
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
#else
regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
arch/arm/src/sama5/sam_adc.c
+2 -2
View File
@@ -1577,10 +1577,10 @@ static void sam_adc_offset(struct sam_adc_s *priv)
* used for all channel.
*/
#if CONFIG_SAMA5_ADC_OFFSET
#ifdef CONFIG_SAMA5_ADC_OFFSET
regval |= ADC_COR_OFF0;
#endif
#if CONFIG_SAMA5_ADC_DIFFMODE
#ifdef CONFIG_SAMA5_ADC_DIFFMODE
regval |= ADC_COR_DIFF0;
#endif
#endif
arch/arm/src/sama5/sam_rtc.c
+2 -2
View File
@@ -245,7 +245,7 @@ static int rtc_bcd2bin(uint32_t value)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static void rtc_worker(FAR void *arg)
{
/* Sample once (atomically) */
@@ -278,7 +278,7 @@ static void rtc_worker(FAR void *arg)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static int rtc_interrupt(int irq, void *context)
{
int ret;
arch/arm/src/sama5/sam_tsd.c
+1 -1
View File
@@ -1552,7 +1552,7 @@ static void sam_tsd_initialize(struct sam_tsd_s *priv)
sam_adc_getreg(priv->adc, SAM_ADC_XPOSR);
sam_adc_getreg(priv->adc, SAM_ADC_YPOSR);
#if CONFIG_SAMA5_TSD_4WIRE
#ifdef CONFIG_SAMA5_TSD_4WIRE
sam_adc_getreg(priv->adc, SAM_ADC_PRESSR);
#endif
arch/arm/src/stm32/chip/stm32_adc.h
+1 -1
View File
@@ -270,7 +270,7 @@
#ifdef CONFIG_STM32_STM32F10XX
# define ADC_CR2_CAL (1 << 2) /* Bit 2: A/D Calibration */
#elif CONFIG_STM32_STM32L15XX
#elif defined(CONFIG_STM32_STM32L15XX)
# define ADC_CR2_CFG (1 << 2) /* Bit 2 : ADC configuration. This bit must be modified only when no
* conversion is on going. This bit is available in high and medium+
* density devices only.
arch/arm/src/stm32/stm32_adc.c
+4 -5
View File
@@ -960,7 +960,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable)
if (enable)
{
#if CONFIG_ADC_CONTINUOUS
#ifdef CONFIG_ADC_CONTINUOUS
/* Set continuous mode */
@@ -974,7 +974,7 @@ static void adc_startconv(struct stm32_dev_s *priv, bool enable)
}
else
{
#if CONFIG_ADC_CONTINUOUS
#ifdef CONFIG_ADC_CONTINUOUS
/* Disable the continuous conversion */
@@ -1761,10 +1761,9 @@ static void adc_shutdown(FAR struct adc_dev_s *dev)
{
FAR struct stm32_dev_s *priv = (FAR struct stm32_dev_s *)dev->ad_priv;
#if CONFIG_STM32_STM32L15XX
#ifdef CONFIG_STM32_STM32L15XX
adc_enable(priv, false);
# if defined(CONFIG_STM32_STM32L15XX) && ((STM32_CFGR_PLLSRC != 0) || \
(STM32_SYSCLK_SW != RCC_CFGR_SW_HSI))
# if (STM32_CFGR_PLLSRC != 0) || (STM32_SYSCLK_SW != RCC_CFGR_SW_HSI)
adc_enable_hsi(false);
# endif
#endif
arch/arm/src/stm32/stm32_eth.c
+1 -1
View File
@@ -467,7 +467,7 @@
* checksum is OK the DMA can handle the frame otherwise the frame is dropped
*/
#if CONFIG_STM32_ETH_HWCHECKSUM
#ifdef CONFIG_STM32_ETH_HWCHECKSUM
# define DMAOMR_SET_MASK \
(ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \
ETH_DMAOMR_TSF | ETH_DMAOMR_RSF)
arch/arm/src/stm32/stm32_gpio.c
+2 -2
View File
@@ -208,9 +208,9 @@ static inline void stm32_gpioremap(void)
#ifdef CONFIG_STM32_JTAG_FULL_ENABLE
/* The reset default */
#elif CONFIG_STM32_JTAG_NOJNTRST_ENABLE
#elif defined(CONFIG_STM32_JTAG_NOJNTRST_ENABLE)
val |= AFIO_MAPR_SWJ; /* enabled but without JNTRST */
#elif CONFIG_STM32_JTAG_SW_ENABLE
#elif defined(CONFIG_STM32_JTAG_SW_ENABLE)
val |= AFIO_MAPR_SWDP; /* set JTAG-DP disabled and SW-DP enabled */
#else
val |= AFIO_MAPR_DISAB; /* set JTAG-DP and SW-DP Disabled */
arch/arm/src/stm32/stm32_lowputc.c
+4 -4
View File
@@ -406,7 +406,7 @@ void up_lowputc(char ch)
/* Wait until the TX data register is empty */
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TXE) == 0);
#if STM32_CONSOLE_RS485_DIR
#ifdef STM32_CONSOLE_RS485_DIR
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
@@ -414,7 +414,7 @@ void up_lowputc(char ch)
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
#if STM32_CONSOLE_RS485_DIR
#ifdef STM32_CONSOLE_RS485_DIR
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_SR_OFFSET) & USART_SR_TC) == 0);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
@@ -519,7 +519,7 @@ void stm32_lowsetup(void)
stm32_configgpio(STM32_CONSOLE_RX);
#endif
#if STM32_CONSOLE_RS485_DIR
#ifdef STM32_CONSOLE_RS485_DIR
stm32_configgpio(STM32_CONSOLE_RS485_DIR);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
@@ -591,7 +591,7 @@ void stm32_lowsetup(void)
stm32_configgpio(STM32_CONSOLE_RX);
#endif
#if STM32_CONSOLE_RS485_DIR
#ifdef STM32_CONSOLE_RS485_DIR
stm32_configgpio(STM32_CONSOLE_RS485_DIR);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
arch/arm/src/stm32/stm32_rtcc.c
+1 -1
View File
@@ -580,7 +580,7 @@ static void rtc_resume(void)
*
************************************************************************************/
#if CONFIG_RTC_ALARM
#ifdef CONFIG_RTC_ALARM
static int rtc_interrupt(int irq, void *context)
{
#warning "Missing logic"
arch/arm/src/stm32/stm32_sdio.c
+1 -1
View File
@@ -64,7 +64,7 @@
#include "stm32_dma.h"
#include "stm32_sdio.h"
#if CONFIG_STM32_SDIO
#ifdef CONFIG_STM32_SDIO
/****************************************************************************
* Pre-processor Definitions
arch/arm/src/stm32/stm32_serial.c
+4 -4
View File
@@ -77,7 +77,7 @@
* have also been selected.
*/
#if SERIAL_HAVE_DMA
#ifdef SERIAL_HAVE_DMA
# if defined(CONFIG_STM32_STM32F20XX) || defined(CONFIG_STM32_STM32F40XX)
/* Verify that DMA has been enabled and the DMA channel has been defined.
@@ -1469,7 +1469,7 @@ static int up_setup(struct uart_dev_s *dev)
}
#endif
#if HAVE_RS485
#ifdef HAVE_RS485
if (priv->rs485_dir_gpio != 0)
{
stm32_configgpio(priv->rs485_dir_gpio);
@@ -1671,7 +1671,7 @@ static void up_shutdown(struct uart_dev_s *dev)
}
#endif
#if HAVE_RS485
#ifdef HAVE_RS485
if (priv->rs485_dir_gpio != 0)
{
stm32_unconfiggpio(priv->rs485_dir_gpio);
@@ -2712,7 +2712,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, enum pm_state_e pmstate)
*
****************************************************************************/
#if USE_EARLYSERIALINIT
#ifdef USE_EARLYSERIALINIT
void up_earlyserialinit(void)
{
#ifdef HAVE_UART
arch/arm/src/stm32/stm32_tim.c
+38 -38
View File
@@ -327,35 +327,35 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#if CONFIG_STM32_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
vectorno = STM32_IRQ_TIM2;
break;
#endif
#if CONFIG_STM32_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
vectorno = STM32_IRQ_TIM3;
break;
#endif
#if CONFIG_STM32_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
vectorno = STM32_IRQ_TIM4;
break;
#endif
#if CONFIG_STM32_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
vectorno = STM32_IRQ_TIM5;
break;
#endif
#if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
vectorno = STM32_IRQ_TIM6;
break;
#endif
#endif
#if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
vectorno = STM32_IRQ_TIM7;
break;
@@ -364,12 +364,12 @@ static int stm32_tim_setisr(FAR struct stm32_tim_dev_s *dev,
#if STM32_NATIM > 0
/* TODO: add support for multiple sources and callbacks */
#if CONFIG_STM32_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
vectorno = STM32_IRQ_TIM1UP;
break;
#endif
#if CONFIG_STM32_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
vectorno = STM32_IRQ_TIM8UP;
break;
@@ -570,7 +570,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#if CONFIG_STM32_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
switch (channel)
{
@@ -599,7 +599,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
}
break;
#endif
#if CONFIG_STM32_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
switch (channel)
{
@@ -628,7 +628,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
}
break;
#endif
#if CONFIG_STM32_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
switch (channel)
{
@@ -656,7 +656,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
}
break;
#endif
#if CONFIG_STM32_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
switch (channel)
{
@@ -686,7 +686,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
#endif
#if STM32_NATIM > 0
#if CONFIG_STM32_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
switch (channel)
{
@@ -710,7 +710,7 @@ static int stm32_tim_setchannel(FAR struct stm32_tim_dev_s *dev, uint8_t channel
}
break;
#endif
#if CONFIG_STM32_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
switch (channel)
{
@@ -811,7 +811,7 @@ struct stm32_tim_ops_s stm32_tim_ops =
.ackint = &stm32_tim_ackint
};
#if CONFIG_STM32_TIM2
#ifdef CONFIG_STM32_TIM2
struct stm32_tim_priv_s stm32_tim2_priv =
{
.ops = &stm32_tim_ops,
@@ -820,7 +820,7 @@ struct stm32_tim_priv_s stm32_tim2_priv =
};
#endif
#if CONFIG_STM32_TIM3
#ifdef CONFIG_STM32_TIM3
struct stm32_tim_priv_s stm32_tim3_priv =
{
.ops = &stm32_tim_ops,
@@ -829,7 +829,7 @@ struct stm32_tim_priv_s stm32_tim3_priv =
};
#endif
#if CONFIG_STM32_TIM4
#ifdef CONFIG_STM32_TIM4
struct stm32_tim_priv_s stm32_tim4_priv =
{
.ops = &stm32_tim_ops,
@@ -838,7 +838,7 @@ struct stm32_tim_priv_s stm32_tim4_priv =
};
#endif
#if CONFIG_STM32_TIM5
#ifdef CONFIG_STM32_TIM5
struct stm32_tim_priv_s stm32_tim5_priv =
{
.ops = &stm32_tim_ops,
@@ -848,7 +848,7 @@ struct stm32_tim_priv_s stm32_tim5_priv =
#endif
#if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6
#ifdef CONFIG_STM32_TIM6
struct stm32_tim_priv_s stm32_tim6_priv =
{
.ops = &stm32_tim_ops,
@@ -859,7 +859,7 @@ struct stm32_tim_priv_s stm32_tim6_priv =
#endif
#if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7
#ifdef CONFIG_STM32_TIM7
struct stm32_tim_priv_s stm32_tim7_priv =
{
.ops = &stm32_tim_ops,
@@ -871,7 +871,7 @@ struct stm32_tim_priv_s stm32_tim7_priv =
#if STM32_NATIM > 0
#if CONFIG_STM32_TIM1
#ifdef CONFIG_STM32_TIM1
struct stm32_tim_priv_s stm32_tim1_priv =
{
.ops = &stm32_tim_ops,
@@ -880,7 +880,7 @@ struct stm32_tim_priv_s stm32_tim1_priv =
};
#endif
#if CONFIG_STM32_TIM8
#ifdef CONFIG_STM32_TIM8
struct stm32_tim_priv_s stm32_tim8_priv =
{
.ops = &stm32_tim_ops,
@@ -903,25 +903,25 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
switch (timer)
{
#if CONFIG_STM32_TIM2
#ifdef CONFIG_STM32_TIM2
case 2:
dev = (struct stm32_tim_dev_s *)&stm32_tim2_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN);
break;
#endif
#if CONFIG_STM32_TIM3
#ifdef CONFIG_STM32_TIM3
case 3:
dev = (struct stm32_tim_dev_s *)&stm32_tim3_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN);
break;
#endif
#if CONFIG_STM32_TIM4
#ifdef CONFIG_STM32_TIM4
case 4:
dev = (struct stm32_tim_dev_s *)&stm32_tim4_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN);
break;
#endif
#if CONFIG_STM32_TIM5
#ifdef CONFIG_STM32_TIM5
case 5:
dev = (struct stm32_tim_dev_s *)&stm32_tim5_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN);
@@ -929,7 +929,7 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
#endif
#if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6
#ifdef CONFIG_STM32_TIM6
case 6:
dev = (struct stm32_tim_dev_s *)&stm32_tim6_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM6EN);
@@ -937,7 +937,7 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
#endif
#endif
#if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7
#ifdef CONFIG_STM32_TIM7
case 7:
dev = (struct stm32_tim_dev_s *)&stm32_tim7_priv;
modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM7EN);
@@ -946,13 +946,13 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer)
#endif
#if STM32_NATIM > 0
#if CONFIG_STM32_TIM1
#ifdef CONFIG_STM32_TIM1
case 1:
dev = (struct stm32_tim_dev_s *)&stm32_tim1_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN);
break;
#endif
#if CONFIG_STM32_TIM8
#ifdef CONFIG_STM32_TIM8
case 8:
dev = (struct stm32_tim_dev_s *)&stm32_tim8_priv;
modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN);
@@ -985,35 +985,35 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
switch (((struct stm32_tim_priv_s *)dev)->base)
{
#if CONFIG_STM32_TIM2
#ifdef CONFIG_STM32_TIM2
case STM32_TIM2_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0);
break;
#endif
#if CONFIG_STM32_TIM3
#ifdef CONFIG_STM32_TIM3
case STM32_TIM3_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0);
break;
#endif
#if CONFIG_STM32_TIM4
#ifdef CONFIG_STM32_TIM4
case STM32_TIM4_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0);
break;
#endif
#if CONFIG_STM32_TIM5
#ifdef CONFIG_STM32_TIM5
case STM32_TIM5_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0);
break;
#endif
#if STM32_NBTIM > 0
#if CONFIG_STM32_TIM6
#ifdef CONFIG_STM32_TIM6
case STM32_TIM6_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM6EN, 0);
break;
#endif
#endif
#if STM32_NBTIM > 1
#if CONFIG_STM32_TIM7
#ifdef CONFIG_STM32_TIM7
case STM32_TIM7_BASE:
modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM7EN, 0);
break;
@@ -1021,12 +1021,12 @@ int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev)
#endif
#if STM32_NATIM > 0
#if CONFIG_STM32_TIM1
#ifdef CONFIG_STM32_TIM1
case STM32_TIM1_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0);
break;
#endif
#if CONFIG_STM32_TIM8
#ifdef CONFIG_STM32_TIM8
case STM32_TIM8_BASE:
modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0);
break;
arch/arm/src/stm32/stm32_timerisr.c
+2 -2
View File
@@ -71,7 +71,7 @@
#undef CONFIG_STM32_SYSTICK_HCLKd8 /* Power up default is HCLK, not HCLK/8 */
/* And I don't know now to re-configure it yet */
#if CONFIG_STM32_SYSTICK_HCLKd8
#ifdef CONFIG_STM32_SYSTICK_HCLKd8
# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
#else
# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1)
@@ -138,7 +138,7 @@ void up_timer_initialize(void)
#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
regval = getreg32(NVIC_SYSTICK_CTRL);
#if CONFIG_STM32_SYSTICK_HCLKd8
#ifdef CONFIG_STM32_SYSTICK_HCLKd8
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
#else
regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
arch/arm/src/stm32f7/stm32_ethernet.c
+1 -1
View File
@@ -482,7 +482,7 @@
* checksum is OK the DMA can handle the frame otherwise the frame is dropped
*/
#if CONFIG_STM32F7_ETH_HWCHECKSUM
#ifdef CONFIG_STM32F7_ETH_HWCHECKSUM
# define DMAOMR_SET_MASK \
(ETH_DMAOMR_OSF | ETH_DMAOMR_RTC_64 | ETH_DMAOMR_TTC_64 | \
ETH_DMAOMR_TSF | ETH_DMAOMR_RSF)
arch/arm/src/stm32f7/stm32_lowputc.c
+3 -3
View File
@@ -338,7 +338,7 @@ void up_lowputc(char ch)
/* Wait until the TX data register is empty */
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TXE) == 0);
#if STM32_CONSOLE_RS485_DIR
#ifdef STM32_CONSOLE_RS485_DIR
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
@@ -346,7 +346,7 @@ void up_lowputc(char ch)
putreg32((uint32_t)ch, STM32_CONSOLE_BASE + STM32_USART_TDR_OFFSET);
#if STM32_CONSOLE_RS485_DIR
#ifdef STM32_CONSOLE_RS485_DIR
while ((getreg32(STM32_CONSOLE_BASE + STM32_USART_ISR_OFFSET) & USART_ISR_TC) == 0);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
@@ -389,7 +389,7 @@ void stm32_lowsetup(void)
stm32_configgpio(STM32_CONSOLE_RX);
#endif
#if STM32_CONSOLE_RS485_DIR
#ifdef STM32_CONSOLE_RS485_DIR
stm32_configgpio(STM32_CONSOLE_RS485_DIR);
stm32_gpiowrite(STM32_CONSOLE_RS485_DIR, !STM32_CONSOLE_RS485_DIR_POLARITY);
#endif
arch/arm/src/stm32f7/stm32_serial.c
+4 -4
View File
@@ -86,7 +86,7 @@
* have also been selected.
*/
#if SERIAL_HAVE_DMA
#ifdef SERIAL_HAVE_DMA
/* Verify that DMA has been enabled and the DMA channel has been defined.
*/
@@ -1400,7 +1400,7 @@ static int up_setup(struct uart_dev_s *dev)
}
#endif
#if HAVE_RS485
#ifdef HAVE_RS485
if (priv->rs485_dir_gpio != 0)
{
stm32_configgpio(priv->rs485_dir_gpio);
@@ -1603,7 +1603,7 @@ static void up_shutdown(struct uart_dev_s *dev)
}
#endif
#if HAVE_RS485
#ifdef HAVE_RS485
if (priv->rs485_dir_gpio != 0)
{
stm32_unconfiggpio(priv->rs485_dir_gpio);
@@ -2642,7 +2642,7 @@ static int up_pm_prepare(struct pm_callback_s *cb, enum pm_state_e pmstate)
*
****************************************************************************/
#if USE_EARLYSERIALINIT
#ifdef USE_EARLYSERIALINIT
void up_earlyserialinit(void)
{
#ifdef HAVE_UART
arch/arm/src/str71x/str71x_decodeirq.c
+1 -1
View File
@@ -132,7 +132,7 @@ void up_decodeirq(uint32_t *regs)
current_regs = savestate;
}
#if CONFIG_DEBUG
#ifdef CONFIG_DEBUG
else
{
PANIC(); /* Normally never happens */
arch/arm/src/str71x/str71x_lowputc.c
+5 -5
View File
@@ -78,7 +78,7 @@
* RX needs to be configured for input, tristate, cmos {0, 1, 0}
*/
#if CONFIG_STR71X_UART0
#ifdef CONFIG_STR71X_UART0
# define STR71X_UART0_GPIO0_MASK (0x0300) /* P0.8->U0.TX, B0.9->U0.RX */
# define STR71X_UART0_GPIO0_PC0BITS (0x0200)
# define STR71X_UART0_GPIO0_PC1BITS (0x0300)
@@ -90,7 +90,7 @@
# define STR71X_UART0_GPIO0_PC2BITS (0)
#endif
#if CONFIG_STR71X_UART1
#ifdef CONFIG_STR71X_UART1
# define STR71X_UART1_GPIO0_MASK (0x0c00) /* P0,10->U1.RX, P0.11->U1.TX */
# define STR71X_UART1_GPIO0_PC0BITS (0x0800)
# define STR71X_UART1_GPIO0_PC1BITS (0x0c00)
@@ -102,7 +102,7 @@
# define STR71X_UART1_GPIO0_PC2BITS (0)
#endif
#if CONFIG_STR71X_UART2
#ifdef CONFIG_STR71X_UART2
# define STR71X_UART2_GPIO0_MASK (0x6000) /* P0.13->U2.RX, P0.14>U2.TX */
# define STR71X_UART2_GPIO0_PC0BITS (0x4000)
# define STR71X_UART2_GPIO0_PC1BITS (0x6000)
@@ -114,7 +114,7 @@
# define STR71X_UART2_GPIO0_PC2BITS (0)
#endif
#if CONFIG_STR71X_UART3
#ifdef CONFIG_STR71X_UART3
# define STR71X_UART3_GPIO0_MASK (0x0003) /* P0.0->U3.TX, P0.1->U3.RX */
# define STR71X_UART3_GPIO0_PC0BITS (0x0001)
# define STR71X_UART3_GPIO0_PC1BITS (0x0003)
@@ -298,7 +298,7 @@ void up_lowsetup(void)
* (the serial driver later depends on this configuration)
*/
#if HAVE_UART
#ifdef HAVE_UART
reg16 = getreg16(STR71X_GPIO0_PC0);
reg16 &= ~STR71X_UART_GPIO0_MASK;
reg16 |= STR71X_UART_GPIO0_PC0BITS;
arch/arm/src/tiva/tiva_adc.h
+2 -2
View File
@@ -61,7 +61,7 @@
#ifdef CONFIG_ARCH_CHIP_TM4C123
# define TIVA_ADC_CLOCK_MAX (16000000)
# define TIVA_ADC_CLOCK_MIN (16000000)
#elif CONFIG_ARCH_CHIP_TM4C129
#elif defined(CONFIG_ARCH_CHIP_TM4C129)
# define TIVA_ADC_CLOCK_MAX (32000000)
# define TIVA_ADC_CLOCK_MIN (16000000)
#else
@@ -75,7 +75,7 @@
# define TIVA_ADC_SAMPLE_RATE_SLOW (ADC_PC_SR_250K)
# define TIVA_ADC_SAMPLE_RATE_FAST (ADC_PC_SR_500K)
# define TIVA_ADC_SAMPLE_RATE_FASTEST (ADC_PC_SR_1M)
#elif CONFIG_ARCH_CHIP_TM4C129
#elif defined(CONFIG_ARCH_CHIP_TM4C129)
# define TIVA_ADC_SAMPLE_RATE_SLOWEST (ADC_PC_MCR_1_8)
# define TIVA_ADC_SAMPLE_RATE_SLOW (ADC_PC_MCR_1_4)
# define TIVA_ADC_SAMPLE_RATE_FAST (ADC_PC_MCR_1_2)
arch/arm/src/tiva/tm4c_ethernet.c
+2 -2
View File
@@ -479,7 +479,7 @@
* checksum is OK the DMA can handle the frame otherwise the frame is dropped
*/
#if CONFIG_TIVA_EMAC_HWCHECKSUM
#ifdef CONFIG_TIVA_EMAC_HWCHECKSUM
# define DMAOPMODE_SET_MASK \
(EMAC_DMAOPMODE_OSF | EMAC_DMAOPMODE_RTC_64 | EMAC_DMAOPMODE_TTC_64 | \
EMAC_DMAOPMODE_TSF | EMAC_DMAOPMODE_RSF)
@@ -748,7 +748,7 @@ static void tiva_rxdescinit(FAR struct tiva_ethmac_s *priv);
/* PHY Initialization */
#if CONFIG_TIVA_PHY_INTERRUPTS
#ifdef CONFIG_TIVA_PHY_INTERRUPTS
static void tiva_phy_intenable(bool enable);
#endif
static int tiva_phyread(uint16_t phydevaddr, uint16_t phyregaddr, uint16_t *value);
arch/avr/src/at32uc3/at32uc3_clkinit.c
+2 -2
View File
@@ -230,7 +230,7 @@ static inline void up_enablepll0(void)
/* Select PLL0/1 oscillator */
#if AVR32_CLOCK_PLL_OSC1
#ifdef AVR32_CLOCK_PLL0_OSC1
regval |= PM_PLL_PLLOSC;
#endif
@@ -280,7 +280,7 @@ static inline void up_enablepll1(void)
/* Select PLL0/1 oscillator */
#if AVR32_CLOCK_PLL_OSC1
#ifdef AVR32_CLOCK_PLL1_OSC1
regval |= PM_PLL_PLLOSC;
#endif
arch/avr/src/at32uc3/chip.h
+8 -8
View File
@@ -53,7 +53,7 @@
/* UC3 B0 (64-pin) / B1 (48-pin, no USB host) Series */
#if CONFIG_ARCH_CHIP_AT32UC3B064
#ifdef CONFIG_ARCH_CHIP_AT32UC3B064
# define CONFIG_ARCH_CHIP_AT32UC3B 1 /* UC3 B series */
# define CONFIG_ARCH_CHIP_AT32UC3B0 1 /* UC3 B0 (64-pin) series */
# define AVR32_ONCHIP_FLASH_SIZE (64*1024) /* Size of on-chip FLASH (bytes) */
@@ -71,7 +71,7 @@
# define AVR32_NOSC 2 /* Number of crystal oscillators */
# define AVR32_NADC10 8 /* Number of 10-bit A/D channels */
# define AVR32_NDMAC 7 /* Number of DMA channels */
#elif CONFIG_ARCH_CHIP_AT32UC3B0128
#elif defined(CONFIG_ARCH_CHIP_AT32UC3B0128)
# define CONFIG_ARCH_CHIP_AT32UC3B 1 /* UC3 B series */
# define CONFIG_ARCH_CHIP_AT32UC3B0 1 /* UC3 B0 (64-pin) series */
# define AVR32_ONCHIP_FLASH_SIZE (128*1024) /* Size of on-chip FLASH (bytes) */
@@ -89,7 +89,7 @@
# define AVR32_NOSC 2 /* Number of crystal oscillators */
# define AVR32_NADC10 8 /* Number of 10-bit A/D channels */
# define AVR32_NDMAC 7 /* Number of DMA channels */
#elif CONFIG_ARCH_CHIP_AT32UC3B0256
#elif defined(CONFIG_ARCH_CHIP_AT32UC3B0256)
# define CONFIG_ARCH_CHIP_AT32UC3B 1 /* UC3 B series */
# define CONFIG_ARCH_CHIP_AT32UC3B0 1 /* UC3 B0 (64-pin) series */
# define AVR32_ONCHIP_FLASH_SIZE (256*1024) /* Size of on-chip FLASH (bytes) */
@@ -107,7 +107,7 @@
# define AVR32_NOSC 2 /* Number of crystal oscillators */
# define AVR32_NADC10 8 /* Number of 10-bit A/D channels */
# define AVR32_NDMAC 7 /* Number of DMA channels */
#elif CONFIG_ARCH_CHIP_AT32UC3B0512
#elif defined(CONFIG_ARCH_CHIP_AT32UC3B0512)
# define CONFIG_ARCH_CHIP_AT32UC3B 1 /* UC3 B series */
# define CONFIG_ARCH_CHIP_AT32UC3B0 1 /* UC3 B0 (64-pin) series */
# define AVR32_ONCHIP_FLASH_SIZE (512*1024) /* Size of on-chip FLASH (bytes) */
@@ -125,7 +125,7 @@
# define AVR32_NOSC 2 /* Number of crystal oscillators */
# define AVR32_NADC10 8 /* Number of 10-bit A/D channels */
# define AVR32_NDMAC 7 /* Number of DMA channels */
#elif CONFIG_ARCH_CHIP_AT32UC3B164
#elif defined(CONFIG_ARCH_CHIP_AT32UC3B164)
# define CONFIG_ARCH_CHIP_AT32UC3B 1 /* UC3 B series */
# define CONFIG_ARCH_CHIP_AT32UC3B1 1 /* UC3 B0 (48-pin) series */
# define AVR32_ONCHIP_FLASH_SIZE (64*1024) /* Size of on-chip FLASH (bytes) */
@@ -143,7 +143,7 @@
# define AVR32_NOSC 1 /* Number of crystal oscillators */
# define AVR32_NADC10 6 /* Number of 10-bit A/D channels */
# define AVR32_NDMAC 7 /* Number of DMA channels */
#elif CONFIG_ARCH_CHIP_AT32UC3B1128
#elif defined(CONFIG_ARCH_CHIP_AT32UC3B1128)
# define CONFIG_ARCH_CHIP_AT32UC3B 1 /* UC3 B series */
# define CONFIG_ARCH_CHIP_AT32UC3B1 1 /* UC3 B0 (48-pin) series */
# define AVR32_ONCHIP_FLASH_SIZE (128*1024) /* Size of on-chip FLASH (bytes) */
@@ -161,7 +161,7 @@
# define AVR32_NOSC 1 /* Number of crystal oscillators */
# define AVR32_NADC10 6 /* Number of 10-bit A/D channels */
# define AVR32_NDMAC 7 /* Number of DMA channels */
#elif CONFIG_ARCH_CHIP_AT32UC3B1256
#elif defined(CONFIG_ARCH_CHIP_AT32UC3B1256)
# define CONFIG_ARCH_CHIP_AT32UC3B 1 /* UC3 B series */
# define CONFIG_ARCH_CHIP_AT32UC3B1 1 /* UC3 B0 (48-pin) series */
# define AVR32_ONCHIP_FLASH_SIZE (256*1024) /* Size of on-chip FLASH (bytes) */
@@ -179,7 +179,7 @@
# define AVR32_NOSC 1 /* Number of crystal oscillators */
# define AVR32_NADC10 6 /* Number of 10-bit A/D channels */
# define AVR32_NDMAC 7 /* Number of DMA channels */
#elif CONFIG_ARCH_CHIP_AT32UC3B1512
#elif defined(CONFIG_ARCH_CHIP_AT32UC3B1512)
# define CONFIG_ARCH_CHIP_AT32UC3B 1 /* UC3 B series */
# define CONFIG_ARCH_CHIP_AT32UC3B1 1 /* UC3 B0 (48-pin) series */
# define AVR32_ONCHIP_FLASH_SIZE (512*1024) /* Size of on-chip FLASH (bytes) */
arch/mips/src/mips32/up_vfork.c
+5 -5
View File
@@ -117,7 +117,7 @@ pid_t up_vfork(const struct vfork_s *context)
struct task_tcb_s *child;
size_t stacksize;
uint32_t newsp;
#if CONFIG_MIPS32_FRAMEPOINTER
#ifdef CONFIG_MIPS32_FRAMEPOINTER
uint32_t newfp;
#endif
uint32_t stackutil;
@@ -125,7 +125,7 @@ pid_t up_vfork(const struct vfork_s *context)
svdbg("s0:%08x s1:%08x s2:%08x s3:%08x s4:%08x\n",
context->s0, context->s1, context->s2, context->s3, context->s4);
#if CONFIG_MIPS32_FRAMEPOINTER
#ifdef CONFIG_MIPS32_FRAMEPOINTER
svdbg("s5:%08x s6:%08x s7:%08x\n",
context->s5, context->s6, context->s7);
#ifdef MIPS32_SAVE_GP
@@ -199,7 +199,7 @@ pid_t up_vfork(const struct vfork_s *context)
/* Was there a frame pointer in place before? */
#if CONFIG_MIPS32_FRAMEPOINTER
#ifdef CONFIG_MIPS32_FRAMEPOINTER
if (context->fp <= (uint32_t)parent->adj_stack_ptr &&
context->fp >= (uint32_t)parent->adj_stack_ptr - stacksize)
{
@@ -237,13 +237,13 @@ pid_t up_vfork(const struct vfork_s *context)
child->cmn.xcp.regs[REG_S5] = context->s5; /* Volatile register s5 */
child->cmn.xcp.regs[REG_S6] = context->s6; /* Volatile register s6 */
child->cmn.xcp.regs[REG_S7] = context->s7; /* Volatile register s7 */
#if CONFIG_MIPS32_FRAMEPOINTER
#ifdef CONFIG_MIPS32_FRAMEPOINTER
child->cmn.xcp.regs[REG_FP] = newfp; /* Frame pointer */
#else
child->cmn.xcp.regs[REG_S8] = context->s8; /* Volatile register s8 */
#endif
child->cmn.xcp.regs[REG_SP] = newsp; /* Stack pointer */
#if MIPS32_SAVE_GP
#ifdef MIPS32_SAVE_GP
child->cmn.xcp.regs[REG_GP] = newsp; /* Global pointer */
#endif
arch/mips/src/pic32mz/pic32mz-config.h
+1 -1
View File
@@ -472,7 +472,7 @@
#endif
#undef CONFIG_PIC32MZ_FWDTEN
#if CONFIG_PIC32MZ_WDTENABLE
#ifdef CONFIG_PIC32MZ_WDTENABLE
# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDT_ENSABLED
#else
# define CONFIG_PIC32MZ_FWDTEN DEVCFG1_FWDT_DISABLED
arch/rgmp/include/math.h
+23 -23
View File
@@ -65,7 +65,7 @@ extern "C"
/* General Functions ********************************************************/
float ceilf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double ceil (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -73,7 +73,7 @@ long double ceill (long double x);
#endif
float floorf(float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double floor (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -81,7 +81,7 @@ long double floorl(long double x);
#endif
float fabsf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double fabs (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -89,7 +89,7 @@ long double fabsl (long double x);
#endif
float modff (float x, float *iptr);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double modf (double x, double *iptr);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -97,7 +97,7 @@ long double modfl (long double x, long double *iptr);
#endif
float fmodf (float x, float div);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double fmod (double x, double div);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -107,7 +107,7 @@ long double fmodl (long double x, long double div);
/* Exponential and Logarithmic Functions ************************************/
float powf (float b, float e);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double pow (double b, double e);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -115,7 +115,7 @@ long double powl (long double b, long double e);
#endif
float expf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double exp (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -123,7 +123,7 @@ long double expl (long double x);
#endif
float logf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double log (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -131,7 +131,7 @@ long double logl (long double x);
#endif
float log10f(float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double log10 (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -139,7 +139,7 @@ long double log10l(long double x);
#endif
float log2f (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double log2 (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -147,7 +147,7 @@ long double log2l (long double x);
#endif
float sqrtf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double sqrt (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -155,7 +155,7 @@ long double sqrtl (long double x);
#endif
float ldexpf(float x, int n);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
double ldexp (double x, int n);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -163,7 +163,7 @@ long double ldexpl(long double x, int n);
#endif
float frexpf(float x, int *exp);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
double frexp (double x, int *exp);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -173,7 +173,7 @@ long double frexpl(long double x, int *exp);
/* Trigonometric Functions **************************************************/
float sinf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double sin (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -181,7 +181,7 @@ long double sinl (long double x);
#endif
float cosf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double cos (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -189,7 +189,7 @@ long double cosl (long double x);
#endif
float tanf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double tan (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -197,7 +197,7 @@ long double tanl (long double x);
#endif
float asinf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double asin (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -205,7 +205,7 @@ long double asinl (long double x);
#endif
float acosf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double acos (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -213,7 +213,7 @@ long double acosl (long double x);
#endif
float atanf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double atan (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -221,7 +221,7 @@ long double atanl (long double x);
#endif
float atan2f(float y, float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double atan2 (double y, double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -229,7 +229,7 @@ long double atan2l(long double y, long double x);
#endif
float sinhf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double sinh (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -237,7 +237,7 @@ long double sinhl (long double x);
#endif
float coshf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double cosh (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
@@ -245,7 +245,7 @@ long double coshl (long double x);
#endif
float tanhf (float x);
#if CONFIG_HAVE_DOUBLE
#ifdef CONFIG_HAVE_DOUBLE
//double tanh (double x);
#endif
#ifdef CONFIG_HAVE_LONG_DOUBLE
arch/sim/src/up_internal.h
+1 -1
View File
@@ -159,7 +159,7 @@
/* Simulated Heap Definitions **********************************************/
/* Size of the simulated heap */
#if CONFIG_MM_SMALL
#ifdef CONFIG_MM_SMALL
# define SIM_HEAP_SIZE (64*1024)
#else
# define SIM_HEAP_SIZE (4*1024*1024)
arch/z80/src/common/up_initialize.c
+1 -1
View File
@@ -140,7 +140,7 @@ void up_initialize(void)
* needs to be done before any tasks are created).
*/
#if CONFIG_ARCH_ADDRENV
#ifdef CONFIG_ARCH_ADDRENV
(void)up_mmuinit();
#endif
arch/z80/src/common/up_internal.h
+1 -1
View File
@@ -145,7 +145,7 @@ void up_sigdeliver(void);
/* Defined in CPU-specific logic (only for Z180) */
#if CONFIG_ARCH_ADDRENV
#ifdef CONFIG_ARCH_ADDRENV
int up_mmuinit(void);
#endif