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SAMA5 GMAC and GMII support is code complete and ready for test

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This commit is contained in:
Gregory Nutt
2013-09-27 13:12:04 -06:00
parent f519f94926
commit 9fcbd8879a
5 changed files with 319 additions and 372 deletions
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arch/arm/src/sama5/Kconfig
+24 -97
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@@ -314,121 +314,48 @@ config SAMA5_GMAC_PHYINIT
provide sam_phyinitialize(); The SAMA5 GMAC driver will call this function
one time before it first uses the PHY.
config SAMA5_GMAC_GMII
bool "Use MII interface"
default n
---help---
Support Ethernet MII interface (vs RMII).
config SAMA5_GMAC_RGMII
bool
default y if !SAMA5_GMAC_GMII
default n if SAMA5_GMAC_GMII
config SAMA5_GMAC_AUTONEG
bool "Use autonegotiation"
default y
---help---
Use PHY autonegotiation to determine speed and mode
if !SAMA5_GMAC_AUTONEG
config SAMA5_GMAC_ETHFD
bool "Full duplex"
default n
depends on !SAMA5_GMAC_AUTONEG
---help---
If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to select full duplex
mode. Default: half-duplex
If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to
select full duplex mode. Default: half-duplex
choice
prompt "GMAC Speed"
default SAMA5_GMAC_ETH100MBPS
---help---
If autonegation is not used, then you must select the fixed speed
of the PHY
config SAMA5_GMAC_ETH10MBPS
bool "10 Mbps"
---help---
If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to select 10 MBps
speed. Default: 100 Mbps
config SAMA5_GMAC_ETH100MBPS
bool "100 Mbps"
default n
depends on !SAMA5_GMAC_AUTONEG
---help---
If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to select 100 MBps
speed. Default: 10 Mbps
speed. Default: 100 Mbps
config SAMA5_GMAC_PHYSR
int "PHY Status Register Address (decimal)"
depends on SAMA5_GMAC_AUTONEG
config SAMA5_GMAC_ETH1000MBPS
bool "1000 Mbps"
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. The PHY status register
address may diff from PHY to PHY. This configuration sets the address of
the PHY status register.
If SAMA5_GMAC_AUTONEG is not defined, then this may be defined to select 1000 MBps
speed. Default: 100 Mbps
config SAMA5_GMAC_PHYSR_ALTCONFIG
bool "PHY Status Alternate Bit Layout"
default n
depends on SAMA5_GMAC_AUTONEG
---help---
Different PHYs present speed and mode information in different ways. Some
will present separate information for speed and mode (this is the default).
Those PHYs, for example, may provide a 10/100 Mbps indication and a separate
full/half duplex indication. This options selects an alternative representation
where speed and mode information are combined. This might mean, for example,
separate bits for 10HD, 100HD, 10FD and 100FD.
config SAMA5_GMAC_PHYSR_SPEED
hex "PHY Speed Mask"
depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This provides bit mask
for isolating the 10 or 100MBps speed indication.
config SAMA5_GMAC_PHYSR_100MBPS
hex "PHY 100Mbps Speed Value"
depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This provides the value
of the speed bit(s) indicating 100MBps speed.
config SAMA5_GMAC_PHYSR_MODE
hex "PHY Mode Mask"
depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This provide bit mask
for isolating the full or half duplex mode bits.
config SAMA5_GMAC_PHYSR_FULLDUPLEX
hex "PHY Full Duplex Mode Value"
depends on SAMA5_GMAC_AUTONEG && !SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This provides the
value of the mode bits indicating full duplex mode.
config SAMA5_GMAC_PHYSR_ALTMODE
hex "PHY Mode Mask"
depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This provide bit mask
for isolating the speed and full/half duplex mode bits.
config SAMA5_GMAC_PHYSR_10HD
hex "10MBase-T Half Duplex Value"
depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, half duplex setting.
config SAMA5_GMAC_PHYSR_100HD
hex "100Base-T Half Duplex Value"
depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, half duplex setting.
config SAMA5_GMAC_PHYSR_10FD
hex "10Base-T Full Duplex Value"
depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 10Mbps, full duplex setting.
config SAMA5_GMAC_PHYSR_100FD
hex "100Base-T Full Duplex Value"
depends on SAMA5_GMAC_AUTONEG && SAMA5_GMAC_PHYSR_ALTCONFIG
---help---
This must be provided if SAMA5_GMAC_AUTONEG is defined. This is the value
under the bit mask that represents the 100Mbps, full duplex setting.
endchoice # GMAC speed
endif # !SAMA5_GMAC_AUTONEG
config SAMA5_GMAC_REGDEBUG
bool "Register-Level Debug"
arch/arm/src/sama5/chip/sam_emac.h
+1
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@@ -237,6 +237,7 @@
#define EMAC_INT_WOL (1 << 14) /* Bit 14: Wake On LAN */
#define EMAC_INT_ALL (0x00007cff)
#define EMAC_INT_UNUSED (0xffff8300)
/* Phy Maintenance Register */
arch/arm/src/sama5/chip/sam_gmac.h
+1
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@@ -583,6 +583,7 @@
#define GMAC_INT_WOL (1 << 28) /* Bit 28: Wake On LAN (not in IMR) */
#define GMAC_INT_ALL (0x17fcfcff)
#define GMAC_INT_UNUSED (0xe8030300)
/* PHY Maintenance Register */
arch/arm/src/sama5/sam_emac.c
+12 -4
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@@ -1307,7 +1307,7 @@ static int sam_emac_interrupt(int irq, void *context)
tsr = sam_getreg(priv, SAM_EMAC_TSR);
imr = sam_getreg(priv, SAM_EMAC_IMR);
pending = isr & ~(imr | 0xffc300);
pending = isr & ~(imr | EMAC_INT_UNUSED);
nllvdbg("isr: %08x pending: %08x\n", isr, pending);
/* Check for the completion of a transmission. This should be done before
@@ -2159,10 +2159,12 @@ static int sam_autonegotiate(struct sam_emac_s *priv)
nllvdbg("PHYID2: %04x PHY address: %02x\n", phyid2, priv->phyaddr);
if (phyid1 == MII_OUI_MSB &&
((phyid2 & MII_PHYID2_OUI) >> 10) == MII_OUI_LSB)
((phyid2 & MII_PHYID2_OUI_MASK) >> MII_PHYID2_OUI_SHIFT) == MII_OUI_LSB)
{
nllvdbg(" Vendor Model Number: %04x\n", ((phyid2 >> 4) & 0x3f));
nllvdbg(" Model Revision Number: %04x\n", (phyid2 & 7));
nllvdbg(" Vendor Model Number: %04x\n",
(phyid2 & MII_PHYID2_MODEL_MASK) >> MII_PHYID2_MODEL_SHIFT);
nllvdbg(" Model Revision Number: %04x\n",
(phyid2 & MII_PHYID2_REV_MASK) >> MII_PHYID2_REV_SHIFT);
}
else
{
@@ -2570,6 +2572,12 @@ static void sam_txreset(struct sam_emac_s *priv)
txdesc[CONFIG_SAMA5_EMAC_NTXBUFFERS - 1].status =
EMACTXD_STA_USED | EMACTXD_STA_WRAP;
/* Flush the entire TX descriptor table to RAM */
cp15_clean_dcache((uintptr_t)txdesc,
(uintptr_t)txdesc +
CONFIG_SAMA5_EMAC_NTXBUFFERS * sizeof(struct emac_txdesc_s));
/* Set the Transmit Buffer Queue Pointer Register */
physaddr = sam_physramaddr((uintptr_t)txdesc);
arch/arm/src/sama5/sam_gmac.c
+281 -271
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