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arch/arm/src/stm32l4/stm32l4_iwdg.c: Do not unconditionally enable debug

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The DBGMCU_APB1_FZ bit persists over regular software resets until next POR-reset. It can impact device power consumption and things that persist over resets are a bane for FOTA updates so make it disabled by default.

OpenOCD sets this via DAP when connecting to target so enabling this from Kconfig is only useful for users of some other debug tooling.
This commit is contained in:
Juha Niskanen
2020-03-06 07:09:35 -06:00
committed by Gregory Nutt
parent f735584514
commit 9f6df9ce62
2 changed files with 39 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/stm32l4/Kconfig
+20
View File
@@ -1666,6 +1666,26 @@ config STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW
from one flash bank while writing on other flash bank. See your STM32
errata to check if your STM32 is affected by this problem.
choice
prompt "JTAG Configuration"
default STM32L4_JTAG_DISABLE
---help---
JTAG Enable settings (by default JTAG-DP and SW-DP are disabled)
config STM32L4_JTAG_DISABLE
bool "Disable all JTAG clocking"
config STM32L4_JTAG_FULL_ENABLE
bool "Enable full SWJ (JTAG-DP + SW-DP)"
config STM32L4_JTAG_NOJNTRST_ENABLE
bool "Enable full SWJ (JTAG-DP + SW-DP) but without JNTRST"
config STM32L4_JTAG_SW_ENABLE
bool "Set JTAG-DP disabled and SW-DP enabled"
endchoice
config STM32L4_DISABLE_IDLE_SLEEP_DURING_DEBUG
bool "Disable IDLE Sleep (WFI) in debug mode"
default n
arch/arm/src/stm32l4/stm32l4_iwdg.c
+19 -6
View File
@@ -60,7 +60,9 @@
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Clocking *****************************************************************/
/* The minimum frequency of the IWDG clock is:
*
* Fmin = Flsi / 256
@@ -92,6 +94,7 @@
/****************************************************************************
* Private Types
****************************************************************************/
/* This structure provides the private representation of the "lower-half"
* driver state structure. This structure must be cast-compatible with the
* well-known watchdog_lowerhalf_s structure.
@@ -111,6 +114,7 @@ struct stm32l4_lowerhalf_s
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/* Register operations ******************************************************/
#ifdef CONFIG_STM32L4_IWDG_REGDEBUG
@@ -136,6 +140,7 @@ static int stm32l4_settimeout(FAR struct watchdog_lowerhalf_s *lower,
/****************************************************************************
* Private Data
****************************************************************************/
/* "Lower half" driver methods */
static const struct watchdog_ops_s g_wdgops =
@@ -203,7 +208,7 @@ static uint16_t stm32l4_getreg(uint32_t addr)
{
/* Yes.. then show how many times the value repeated */
wdinfo("[repeats %d more times]\n", count-3);
wdinfo("[repeats %d more times]\n", count - 3);
}
/* Save the new address, value, and count */
@@ -610,7 +615,6 @@ static int stm32l4_settimeout(FAR struct watchdog_lowerhalf_s *lower,
void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
{
FAR struct stm32l4_lowerhalf_s *priv = &g_wdgdev;
uint32_t cr;
wdinfo("Entry: devpath=%s lsifreq=%d\n", devpath, lsifreq);
@@ -639,7 +643,8 @@ void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
* device option bits, the watchdog is automatically enabled at power-on.
*/
stm32l4_settimeout((FAR struct watchdog_lowerhalf_s *)priv, CONFIG_STM32L4_IWDG_DEFTIMOUT);
stm32l4_settimeout((FAR struct watchdog_lowerhalf_s *)priv,
CONFIG_STM32L4_IWDG_DEFTIMOUT);
/* Register the watchdog driver as /dev/watchdog0 */
@@ -650,9 +655,17 @@ void stm32l4_iwdginitialize(FAR const char *devpath, uint32_t lsifreq)
* on DBG_IWDG_STOP configuration bit in DBG module.
*/
cr = getreg32(STM32_DBGMCU_APB1_FZ);
cr |= DBGMCU_APB1_IWDGSTOP;
putreg32(cr, STM32_DBGMCU_APB1_FZ);
#if defined(CONFIG_STM32L4_JTAG_FULL_ENABLE) || \
defined(CONFIG_STM32L4_JTAG_NOJNTRST_ENABLE) || \
defined(CONFIG_STM32L4_JTAG_SW_ENABLE)
{
uint32_t cr;
cr = getreg32(STM32_DBGMCU_APB1_FZ);
cr |= DBGMCU_APB1_IWDGSTOP;
putreg32(cr, STM32_DBGMCU_APB1_FZ);
}
#endif
}
#endif /* CONFIG_WATCHDOG && CONFIG_STM32L4_IWDG */