mirror of
https://github.com/apache/nuttx.git
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Update PIC32 Ethernet driver from debugging (still does not work
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4465 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -1,8 +1,8 @@
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/****************************************************************************
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* arch/mips/src/common/up_etherstub.c
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -73,7 +73,7 @@
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* In this case, up_initialize will still try to call up_netinitialize()
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* when one does not exist. This cornercase would occur if, for example,
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* only a USB network interface is being used or perhaps if a SLIP is
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* being used).
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* being used). In those cases, the initialization path is very different.
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*
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* In the long run, it might be better to have some kind of CONFIG_NO_ETHERNET
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* to suppress the call to up_netinitialize() in up_initialize(). Then
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@@ -50,9 +50,11 @@ CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
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# Configuration dependent common files
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ifneq ($(CONFIG_PIC32MX_ETHERNET),y)
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ifeq ($(CONFIG_NET),y)
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CMN_CSRCS += up_etherstub.c
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endif
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endif
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ifeq ($(CONFIG_ARCH_STACKDUMP),y)
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CMN_CSRCS += up_dumpstate.c
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@@ -78,3 +80,4 @@ endif
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ifeq ($(CONFIG_PIC32MX_ETHERNET),y)
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CHIP_CSRCS += pic32mx-ethernet.c
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endif
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+166
-166
@@ -1,166 +1,166 @@
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/********************************************************************************************
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* arch/mips/src/pic32mx/pic32mx-bmx.h
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
|
||||
* are met:
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||||
*
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||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
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||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
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||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mx-memorymap.h"
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/********************************************************************************************
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* Pre-Processor Definitions
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********************************************************************************************/
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/* Register Offsets *************************************************************************/
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#define PIC32MX_BMX_CON_OFFSET 0x0000 /* Configuration Register */
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#define PIC32MX_BMX_CONCLR_OFFSET 0x0000 /* Configuration Clear Register */
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#define PIC32MX_BMX_CONSET_OFFSET 0x0004 /* Configuration Set Register */
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#define PIC32MX_BMX_CONINV_OFFSET 0x0008 /* Configuration Invert Register */
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#define PIC32MX_BMX_DKPBA_OFFSET 0x001c /* Data RAM Kernel Program Base Address Register */
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#define PIC32MX_BMX_DKPBACLR_OFFSET 0x0010 /* Data RAM Kernel Program Base Address Clear Register */
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#define PIC32MX_BMX_DKPBASET_OFFSET 0x0014 /* Data RAM Kernel Program Base Address Set Register */
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#define PIC32MX_BMX_DKPBAINV_OFFSET 0x0018 /* Data RAM Kernel Program Base Address Invert Register */
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#define PIC32MX_BMX_DUDBA_OFFSET 0x002c /* Data RAM User Data Base Address Register */
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#define PIC32MX_BMX_DUDBACLR_OFFSET 0x0020 /* Data RAM User Data Base Address Clear Register */
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#define PIC32MX_BMX_DUDBASET_OFFSET 0x0024 /* Data RAM User Data Base Address Set Register */
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#define PIC32MX_BMX_DUDBAINV_OFFSET 0x0028 /* Data RAM User Data Base Address Invert Register */
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#define PIC32MX_BMX_DUPBA_OFFSET 0x003c /* Data RAM User Program Base Address Register */
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#define PIC32MX_BMX_DUPBACLR_OFFSET 0x0030 /* Data RAM User Program Base Address Clear Register */
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#define PIC32MX_BMX_DUPBASET_OFFSET 0x0034 /* Data RAM User Program Base Address Set Register */
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#define PIC32MX_BMX_DUPBAINV_OFFSET 0x0038 /* Data RAM User Program Base Address Invert Register */
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#define PIC32MX_BMX_DRMSZ_OFFSET 0x0040 /* Data RAM Size Register */
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#define PIC32MX_BMX_PUPBA_OFFSET 0x0050 /* Program Flash (PFM) User Program Base Address Register */
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#define PIC32MX_BMX_PUPBACLR_OFFSET 0x0054 /* Program Flash (PFM) User Program Base Address Clear Register */
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#define PIC32MX_BMX_PUPBASET_OFFSET 0x0058 /* Program Flash (PFM) User Program Base Address Set Register */
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#define PIC32MX_BMX_PUPBINVA_OFFSET 0x005c /* Program Flash (PFM) User Program Base Address Invert Register */
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#define PIC32MX_BMX_PFMSZ_OFFSET 0x0060 /* Program Flash Size Register */
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#define PIC32MX_BMX_BOOTSZ_OFFSET 0x0070 /* Boot Flash Size Register */
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/* Register Addresses ***********************************************************************/
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#define PIC32MX_BMX_CON (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CON_OFFSET)
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#define PIC32MX_BMX_CONCLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONCLR_OFFSET)
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#define PIC32MX_BMX_CONSET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONSET_OFFSET)
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#define PIC32MX_BMX_CONINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONINV_OFFSET)
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#define PIC32MX_BMX_DKPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBA_OFFSET)
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#define PIC32MX_BMX_DKPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBACLR_OFFSET)
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#define PIC32MX_BMX_DKPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBASET_OFFSET)
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#define PIC32MX_BMX_DKPBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBAINV_OFFSET)
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#define PIC32MX_BMX_DUDBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBA_OFFSET)
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#define PIC32MX_BMX_DUDBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBACLR_OFFSET)
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#define PIC32MX_BMX_DUDBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBASET_OFFSET)
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#define PIC32MX_BMX_DUDBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBAINV_OFFSET)
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#define PIC32MX_BMX_DUPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBA_OFFSET)
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#define PIC32MX_BMX_DUPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBACLR_OFFSET)
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#define PIC32MX_BMX_DUPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBASET_OFFSET)
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#define PIC32MX_BMX_DUPBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBAINV_OFFSET)
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#define PIC32MX_BMX_DRMSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DRMSZ_OFFSET)
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#define PIC32MX_BMX_PUPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBA_OFFSET)
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#define PIC32MX_BMX_PUPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBACLR_OFFSET)
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#define PIC32MX_BMX_PUPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBASET_OFFSET)
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#define PIC32MX_BMX_PUPBINVA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBINVA_OFFSET)
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#define PIC32MX_BMX_PFMSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PFMSZ_OFFSET)
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#define PIC32MX_BMX_BOOTSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_BOOTSZ_OFFSET)
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/* Register Bit-Field Definitions ***********************************************************/
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/* Configuration Register */
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#define BMX_CON_BMXARB_SHIFT (0) /* Bits 0-2: : Bus matrix arbitration mode */
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#define BMX_CON_BMXARB_MASK (7 << BMX_CON_BMXARB_SHIFT)
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# define BMX_CON_BMXARB(n) ((n) << BMX_CON_BMXARB_SHIFT) /* Mode n, n=0,1,2 */
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#define BMX_CON_BMXWSDRM (1 << 6) /* Bit 6: CPU Instruction or data access from data RAM wait state */
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#define BMX_CON_BMXERRIS (1 << 16) /* Bit 16: Bus error from CPU instruction access */
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#define BMX_CON_BMXERRDS (1 << 17) /* Bit 17: Bus error from CPU data access */
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#define BMX_CON_BMXERRDMA (1 << 18) /* Bit 18: Bus error from DMA */
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#define BMX_CON_BMXERRICD (1 << 19) /* Bit 19: Enable bus error from ICD debug unit */
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#define BMX_CON_BMXERRIXI (1 << 20) /* Bit 20: Enable bus error from IXI */
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#define BMX_CON_BMXCHEDMA (1 << 26) /* Bit 26: BMX PFM cacheability for DMA accesses */
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/* Data RAM Kernel Program Base Address Register */
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#define BMX_DKPBA_MASK 0x0000ffff /* Bits 0-15 */
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/* Data RAM User Data Base Address Register */
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#define BMX_DUDBA_MASK 0x0000ffff /* Bits 0-15 */
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/* Data RAM User Program Base Address Register */
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#define BMX_DUPBA_MASK 0x0000ffff /* Bits 0-15 */
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/* Data RAM Size Register -- 32-bit size value */
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/* Program Flash (PFM) User Program Base Address Register */
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#define BMX_PUPBA_MASK 0x000fffff /* Bits 0-19 */
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/* Program Flash Size Register -- 32-bit size value */
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/* Boot Flash Size Register -- 32-bit size value */
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/********************************************************************************************
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* Public Types
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********************************************************************************************/
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#ifndef __ASSEMBLY__
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/********************************************************************************************
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* Inline Functions
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********************************************************************************************/
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/********************************************************************************************
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* Public Function Prototypes
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********************************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H */
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/********************************************************************************************
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* arch/mips/src/pic32mx/pic32mx-bmx.h
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*
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* Copyright (C) 2011-2012 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
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*
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********************************************************************************************/
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#ifndef __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H
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#define __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H
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/********************************************************************************************
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* Included Files
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********************************************************************************************/
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#include <nuttx/config.h>
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#include "pic32mx-memorymap.h"
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/********************************************************************************************
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* Pre-Processor Definitions
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********************************************************************************************/
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/* Register Offsets *************************************************************************/
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#define PIC32MX_BMX_CON_OFFSET 0x0000 /* Configuration Register */
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#define PIC32MX_BMX_CONCLR_OFFSET 0x0004 /* Configuration Clear Register */
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#define PIC32MX_BMX_CONSET_OFFSET 0x0008 /* Configuration Set Register */
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#define PIC32MX_BMX_CONINV_OFFSET 0x000c /* Configuration Invert Register */
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#define PIC32MX_BMX_DKPBA_OFFSET 0x0010 /* Data RAM Kernel Program Base Address Register */
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#define PIC32MX_BMX_DKPBACLR_OFFSET 0x0014 /* Data RAM Kernel Program Base Address Clear Register */
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#define PIC32MX_BMX_DKPBASET_OFFSET 0x0018 /* Data RAM Kernel Program Base Address Set Register */
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#define PIC32MX_BMX_DKPBAINV_OFFSET 0x001c /* Data RAM Kernel Program Base Address Invert Register */
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#define PIC32MX_BMX_DUDBA_OFFSET 0x0020 /* Data RAM User Data Base Address Register */
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#define PIC32MX_BMX_DUDBACLR_OFFSET 0x0024 /* Data RAM User Data Base Address Clear Register */
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#define PIC32MX_BMX_DUDBASET_OFFSET 0x0028 /* Data RAM User Data Base Address Set Register */
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#define PIC32MX_BMX_DUDBAINV_OFFSET 0x002c /* Data RAM User Data Base Address Invert Register */
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#define PIC32MX_BMX_DUPBA_OFFSET 0x0030 /* Data RAM User Program Base Address Register */
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#define PIC32MX_BMX_DUPBACLR_OFFSET 0x0034 /* Data RAM User Program Base Address Clear Register */
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#define PIC32MX_BMX_DUPBASET_OFFSET 0x0038 /* Data RAM User Program Base Address Set Register */
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#define PIC32MX_BMX_DUPBAINV_OFFSET 0x003c /* Data RAM User Program Base Address Invert Register */
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#define PIC32MX_BMX_DRMSZ_OFFSET 0x0040 /* Data RAM Size Register */
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#define PIC32MX_BMX_PUPBA_OFFSET 0x0050 /* Program Flash (PFM) User Program Base Address Register */
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#define PIC32MX_BMX_PUPBACLR_OFFSET 0x0054 /* Program Flash (PFM) User Program Base Address Clear Register */
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#define PIC32MX_BMX_PUPBASET_OFFSET 0x0058 /* Program Flash (PFM) User Program Base Address Set Register */
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#define PIC32MX_BMX_PUPBINVA_OFFSET 0x005c /* Program Flash (PFM) User Program Base Address Invert Register */
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#define PIC32MX_BMX_PFMSZ_OFFSET 0x0060 /* Program Flash Size Register */
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#define PIC32MX_BMX_BOOTSZ_OFFSET 0x0070 /* Boot Flash Size Register */
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/* Register Addresses ***********************************************************************/
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#define PIC32MX_BMX_CON (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CON_OFFSET)
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#define PIC32MX_BMX_CONCLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONCLR_OFFSET)
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#define PIC32MX_BMX_CONSET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONSET_OFFSET)
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#define PIC32MX_BMX_CONINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_CONINV_OFFSET)
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#define PIC32MX_BMX_DKPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBA_OFFSET)
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||||
#define PIC32MX_BMX_DKPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBACLR_OFFSET)
|
||||
#define PIC32MX_BMX_DKPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBASET_OFFSET)
|
||||
#define PIC32MX_BMX_DKPBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DKPBAINV_OFFSET)
|
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#define PIC32MX_BMX_DUDBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBA_OFFSET)
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#define PIC32MX_BMX_DUDBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBACLR_OFFSET)
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||||
#define PIC32MX_BMX_DUDBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBASET_OFFSET)
|
||||
#define PIC32MX_BMX_DUDBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUDBAINV_OFFSET)
|
||||
#define PIC32MX_BMX_DUPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBA_OFFSET)
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||||
#define PIC32MX_BMX_DUPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBACLR_OFFSET)
|
||||
#define PIC32MX_BMX_DUPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBASET_OFFSET)
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||||
#define PIC32MX_BMX_DUPBAINV (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DUPBAINV_OFFSET)
|
||||
#define PIC32MX_BMX_DRMSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_DRMSZ_OFFSET)
|
||||
#define PIC32MX_BMX_PUPBA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBA_OFFSET)
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||||
#define PIC32MX_BMX_PUPBACLR (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBACLR_OFFSET)
|
||||
#define PIC32MX_BMX_PUPBASET (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBASET_OFFSET)
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||||
#define PIC32MX_BMX_PUPBINVA (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PUPBINVA_OFFSET)
|
||||
#define PIC32MX_BMX_PFMSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_PFMSZ_OFFSET)
|
||||
#define PIC32MX_BMX_BOOTSZ (PIC32MX_BMX_K1BASE+PIC32MX_BMX_BOOTSZ_OFFSET)
|
||||
|
||||
/* Register Bit-Field Definitions ***********************************************************/
|
||||
|
||||
/* Configuration Register */
|
||||
|
||||
#define BMX_CON_BMXARB_SHIFT (0) /* Bits 0-2: : Bus matrix arbitration mode */
|
||||
#define BMX_CON_BMXARB_MASK (7 << BMX_CON_BMXARB_SHIFT)
|
||||
# define BMX_CON_BMXARB(n) ((n) << BMX_CON_BMXARB_SHIFT) /* Mode n, n=0,1,2 */
|
||||
#define BMX_CON_BMXWSDRM (1 << 6) /* Bit 6: CPU Instruction or data access from data RAM wait state */
|
||||
#define BMX_CON_BMXERRIS (1 << 16) /* Bit 16: Bus error from CPU instruction access */
|
||||
#define BMX_CON_BMXERRDS (1 << 17) /* Bit 17: Bus error from CPU data access */
|
||||
#define BMX_CON_BMXERRDMA (1 << 18) /* Bit 18: Bus error from DMA */
|
||||
#define BMX_CON_BMXERRICD (1 << 19) /* Bit 19: Enable bus error from ICD debug unit */
|
||||
#define BMX_CON_BMXERRIXI (1 << 20) /* Bit 20: Enable bus error from IXI */
|
||||
#define BMX_CON_BMXCHEDMA (1 << 26) /* Bit 26: BMX PFM cacheability for DMA accesses */
|
||||
|
||||
/* Data RAM Kernel Program Base Address Register */
|
||||
|
||||
#define BMX_DKPBA_MASK 0x0000ffff /* Bits 0-15 */
|
||||
|
||||
/* Data RAM User Data Base Address Register */
|
||||
|
||||
#define BMX_DUDBA_MASK 0x0000ffff /* Bits 0-15 */
|
||||
|
||||
/* Data RAM User Program Base Address Register */
|
||||
|
||||
#define BMX_DUPBA_MASK 0x0000ffff /* Bits 0-15 */
|
||||
|
||||
/* Data RAM Size Register -- 32-bit size value */
|
||||
|
||||
/* Program Flash (PFM) User Program Base Address Register */
|
||||
|
||||
#define BMX_PUPBA_MASK 0x000fffff /* Bits 0-19 */
|
||||
|
||||
/* Program Flash Size Register -- 32-bit size value */
|
||||
|
||||
/* Boot Flash Size Register -- 32-bit size value */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/********************************************************************************************
|
||||
* Inline Functions
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Function Prototypes
|
||||
********************************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_MIPS_SRC_PIC32MX_PIC32MX_BMX_H */
|
||||
|
||||
@@ -607,11 +607,11 @@
|
||||
|
||||
/* Unless overridden in the .config file, all pins are in the default setting */
|
||||
|
||||
#ifndef CONFIG_PIC32MX_FMIIEN /* Ethernet MII enable */
|
||||
#ifndef CONFIG_PIC32MX_FMIIEN /* Ethernet MII enable: 0=RMII 1=MII */
|
||||
# define CONFIG_PIC32MX_FMIIEN 1 /* MII enabled */
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_PIC32MX_FETHIO /* SCM1 pin C selection */
|
||||
#ifndef CONFIG_PIC32MX_FETHIO /* Ethernet I/O Pins 0=alternate 1=default */
|
||||
# define CONFIG_PIC32MX_FETHIO 1 /* Default Ethernet I/O Pins */
|
||||
#endif
|
||||
|
||||
|
||||
@@ -156,6 +156,10 @@
|
||||
|
||||
#define PIC32MX_TXTIMEOUT (60*CLK_TCK)
|
||||
|
||||
/* PHY timout = 1 minute */
|
||||
|
||||
#define PIC32MX_MIITIMEOUT (666666)
|
||||
|
||||
/* Ethernet MII clocking.
|
||||
*
|
||||
* The clock divider used to create the MII Management Clock (MDC). The MIIM
|
||||
@@ -219,8 +223,6 @@
|
||||
# undef PIC32MX_HAVE_PHY
|
||||
#endif
|
||||
|
||||
#define MII_BIG_TIMEOUT 666666
|
||||
|
||||
/* These definitions are used to remember the speed/duplex settings */
|
||||
|
||||
#define PIC32MX_SPEED_MASK 0x01
|
||||
@@ -415,7 +417,7 @@ static void pic32mx_showmii(uint8_t phyaddr, const char *msg);
|
||||
# endif
|
||||
|
||||
static void pic32mx_phywrite(uint8_t phyaddr, uint8_t regaddr,
|
||||
uint16_t phydata);
|
||||
uint16_t phydata);
|
||||
static uint16_t pic32mx_phyread(uint8_t phyaddr, uint8_t regaddr);
|
||||
static inline int pic32mx_phyreset(uint8_t phyaddr);
|
||||
# ifdef CONFIG_PHY_AUTONEG
|
||||
@@ -1682,7 +1684,8 @@ static int pic32mx_ifup(struct uip_driver_s *dev)
|
||||
*/
|
||||
|
||||
#if CONFIG_PIC32MX_FMIIEN == 0
|
||||
# warning "Missing logic"
|
||||
pic32mx_putreg(EMAC1_SUPP_RESETRMII, PIC32MX_EMAC1_SUPPSET);
|
||||
pic32mx_putreg((EMAC1_SUPP_RESETRMII | EMAC1_SUPP_SPEEDRMII), PIC32MX_EMAC1_SUPPCLR);
|
||||
#endif
|
||||
|
||||
/* Issue an MIIM block reset, by setting the RESETMGMT (EMAC1MCFG:15) bit,
|
||||
@@ -1721,7 +1724,6 @@ static int pic32mx_ifup(struct uip_driver_s *dev)
|
||||
/* Set other misc configuration-related registers to default values */
|
||||
|
||||
pic32mx_putreg(0, PIC32MX_EMAC1_CFG2);
|
||||
pic32mx_putreg(0, PIC32MX_EMAC1_SUPP);
|
||||
pic32mx_putreg(0, PIC32MX_EMAC1_TEST);
|
||||
|
||||
/* Having available the Duplex and Speed settings, configure the MAC
|
||||
@@ -1732,7 +1734,7 @@ static int pic32mx_ifup(struct uip_driver_s *dev)
|
||||
*/
|
||||
|
||||
pic32mx_putreg(EMAC1_CFG1_RXEN | EMAC1_CFG1_RXPAUSE | EMAC1_CFG1_TXPAUSE,
|
||||
PIC32MX_EMAC1_MCFGSET);
|
||||
PIC32MX_EMAC1_CFG1SET);
|
||||
|
||||
/* Select the desired auto-padding and CRC capabilities, and the enabling
|
||||
* of the huge frames and the Duplex type in the EMAC1CFG2 register.
|
||||
@@ -1850,7 +1852,7 @@ static int pic32mx_ifup(struct uip_driver_s *dev)
|
||||
|
||||
/* Configure to pass all received frames */
|
||||
|
||||
regval = pic32mx_getreg(PIC32MX_EMAC1_CFG1);
|
||||
regval = pic32mx_getreg(PIC32MX_EMAC1_CFG1);
|
||||
regval |= EMAC1_CFG1_PASSALL;
|
||||
pic32mx_putreg(regval, PIC32MX_EMAC1_CFG1);
|
||||
|
||||
@@ -2207,7 +2209,7 @@ static uint16_t pic32mx_phyread(uint8_t phyaddr, uint8_t regaddr)
|
||||
#ifdef PIC32MX_HAVE_PHY
|
||||
static inline int pic32mx_phyreset(uint8_t phyaddr)
|
||||
{
|
||||
int32_t timeout;
|
||||
int32_t timeout;
|
||||
uint16_t phyreg;
|
||||
|
||||
/* Reset the PHY. Needs a minimal 50uS delay after reset. */
|
||||
@@ -2222,7 +2224,7 @@ static inline int pic32mx_phyreset(uint8_t phyaddr)
|
||||
* that the reset is complete.
|
||||
*/
|
||||
|
||||
for (timeout = MII_BIG_TIMEOUT; timeout > 0; timeout--)
|
||||
for (timeout = PIC32MX_MIITIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
phyreg = pic32mx_phyread(phyaddr, MII_MCR);
|
||||
if ((phyreg & MII_MCR_RESET) == 0)
|
||||
@@ -2265,7 +2267,7 @@ static inline int pic32mx_phyautoneg(uint8_t phyaddr)
|
||||
|
||||
/* Wait for autonegotiation to complete */
|
||||
|
||||
for (timeout = MII_BIG_TIMEOUT; timeout > 0; timeout--)
|
||||
for (timeout = PIC32MX_MIITIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if auto-negotiation has completed */
|
||||
|
||||
@@ -2336,7 +2338,7 @@ static int pic32mx_phymode(uint8_t phyaddr, uint8_t mode)
|
||||
|
||||
/* Then wait for the link to be established */
|
||||
|
||||
for (timeout = MII_BIG_TIMEOUT; timeout > 0; timeout--)
|
||||
for (timeout = PIC32MX_MIITIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
#ifdef CONFIG_PHY_DP83848C
|
||||
phyreg = pic32mx_phyread(phyaddr, MII_DP83848C_STS);
|
||||
@@ -2387,9 +2389,28 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv)
|
||||
uint32_t regval;
|
||||
int ret;
|
||||
|
||||
/* Clear any ongoing PHY command bits */
|
||||
#if CONFIG_PIC32MX_FMIIEN == 0
|
||||
/* Set the RMII operation mode. This usually requires access to a vendor
|
||||
* specific control register.
|
||||
*/
|
||||
|
||||
pic32mx_putreg(0, PIC32MX_EMAC1_MCMD);
|
||||
#ifdef CONFIG_PHY_DP83848C
|
||||
/* The RMII/MII of operation can be selected by strap options or register
|
||||
* control (using the RBR register). For RMII mode, it is required to use the
|
||||
* strap option, since it requires a 50 MHz clock instead of the normal 25 MHz.
|
||||
*/
|
||||
#endif
|
||||
|
||||
#else
|
||||
/* Set the MII/ operation mode. This usually requires access to a vendor-
|
||||
* specific control register.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_PHY_DP83848C
|
||||
# warning "Missing logic"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
/* Find PHY Address. Because the controller has a pull-up and the
|
||||
* PHY has pull-down resistors on RXD lines some times the PHY
|
||||
@@ -2398,9 +2419,26 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv)
|
||||
|
||||
for (phyaddr = 1; phyaddr < 32; phyaddr++)
|
||||
{
|
||||
/* Check if we can see the selected device ID at this
|
||||
* PHY address.
|
||||
*/
|
||||
/* Clear any ongoing PHY command bits */
|
||||
|
||||
pic32mx_putreg(0, PIC32MX_EMAC1_MCMD);
|
||||
|
||||
/* Reset the PHY (use Control Register 0). */
|
||||
|
||||
ret = pic32mx_phyreset(phyaddr);
|
||||
if (ret < 0)
|
||||
{
|
||||
ndbg("Failed to reset PHY at address %d\n");
|
||||
continue;
|
||||
}
|
||||
|
||||
/* Set the normal, swapped or auto (preferred) MDIX. This usually
|
||||
* requires access to a vendor-specific control register.
|
||||
*/
|
||||
|
||||
/* Check if we can see the selected device ID at this
|
||||
* PHY address.
|
||||
*/
|
||||
|
||||
phyreg = (unsigned int)pic32mx_phyread(phyaddr, MII_PHYID1);
|
||||
nvdbg("Addr: %d PHY ID1: %04x\n", phyaddr, phyreg);
|
||||
@@ -2410,7 +2448,7 @@ static inline int pic32mx_phyinit(struct pic32mx_driver_s *priv)
|
||||
phyreg = pic32mx_phyread(phyaddr, MII_PHYID2);
|
||||
nvdbg("Addr: %d PHY ID2: %04x\n", phyaddr, phyreg);
|
||||
|
||||
if (phyreg == PIC32MX_PHYID2)
|
||||
if (phyreg == PIC32MX_PHYID2)
|
||||
{
|
||||
break;
|
||||
}
|
||||
@@ -2667,8 +2705,9 @@ static void pic32mx_macmode(uint8_t mode)
|
||||
pic32mx_putreg((EMAC1_CFG2_CRCEN | EMAC1_CFG2_PADCRCEN), PIC32MX_EMAC1_CFG2SET);
|
||||
}
|
||||
|
||||
/* Set the MAC speed. */
|
||||
/* Set the RMII MAC speed. */
|
||||
|
||||
#if CONFIG_PIC32MX_FMIIEN == 0
|
||||
if ((mode & PIC32MX_SPEED_MASK) == PIC32MX_SPEED_100)
|
||||
{
|
||||
pic32mx_putreg(EMAC1_SUPP_SPEEDRMII, PIC32MX_EMAC1_SUPPSET);
|
||||
@@ -2677,6 +2716,7 @@ static void pic32mx_macmode(uint8_t mode)
|
||||
{
|
||||
pic32mx_putreg(EMAC1_SUPP_SPEEDRMII, PIC32MX_EMAC1_SUPPCLR);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -2738,7 +2778,7 @@ static void pic32mx_ethreset(struct pic32mx_driver_s *priv)
|
||||
/* Clear the TX and RX start addresses by using ETHTXSTCLR and ETHRXSTCLR */
|
||||
|
||||
pic32mx_putreg(0xffffffff, PIC32MX_ETH_TXSTCLR);
|
||||
pic32mx_putreg(0xffffffff, PIC32MX_ETH_RXSTSET);
|
||||
pic32mx_putreg(0xffffffff, PIC32MX_ETH_RXSTCLR);
|
||||
|
||||
/* MAC Initialization *****************************************************/
|
||||
/* Put the MAC into the reset state */
|
||||
|
||||
@@ -52,175 +52,175 @@
|
||||
/* Controller and DMA Engine Configuration/Status Registers */
|
||||
|
||||
#define PIC32MX_ETH_CON1_OFFSET 0x0000 /* Ethernet Controller Control 1 Register */
|
||||
#define PIC32MX_ETH_CON1SET_OFFSET 0x0004
|
||||
#define PIC32MX_ETH_CON1CLR_OFFSET 0x0008
|
||||
#define PIC32MX_ETH_CON1CLR_OFFSET 0x0004
|
||||
#define PIC32MX_ETH_CON1SET_OFFSET 0x0008
|
||||
#define PIC32MX_ETH_CON1INV_OFFSET 0x000c
|
||||
#define PIC32MX_ETH_CON2_OFFSET 0x0010 /* Ethernet Controller Control 2 Register */
|
||||
#define PIC32MX_ETH_CON2SET_OFFSET 0x0014
|
||||
#define PIC32MX_ETH_CON2CLR_OFFSET 0x0018
|
||||
#define PIC32MX_ETH_CON2CLR_OFFSET 0x0014
|
||||
#define PIC32MX_ETH_CON2SET_OFFSET 0x0018
|
||||
#define PIC32MX_ETH_CON2INV_OFFSET 0x001c
|
||||
#define PIC32MX_ETH_TXST_OFFSET 0x0020 /* Ethernet Controller TX Packet Descriptor Start Address Register */
|
||||
#define PIC32MX_ETH_TXSTSET_OFFSET 0x0024
|
||||
#define PIC32MX_ETH_TXSTCLR_OFFSET 0x0028
|
||||
#define PIC32MX_ETH_TXSTCLR_OFFSET 0x0024
|
||||
#define PIC32MX_ETH_TXSTSET_OFFSET 0x0028
|
||||
#define PIC32MX_ETH_TXSTINV_OFFSET 0x002c
|
||||
#define PIC32MX_ETH_RXST_OFFSET 0x0030 /* Ethernet Controller RX Packet Descriptor Start Address Register */
|
||||
#define PIC32MX_ETH_RXSTSET_OFFSET 0x0034
|
||||
#define PIC32MX_ETH_RXSTCLR_OFFSET 0x0038
|
||||
#define PIC32MX_ETH_RXSTCLR_OFFSET 0x0034
|
||||
#define PIC32MX_ETH_RXSTSET_OFFSET 0x0038
|
||||
#define PIC32MX_ETH_RXSTINV_OFFSET 0x003c
|
||||
|
||||
#define PIC32MX_ETH_IEN_OFFSET 0x00c0 /* Ethernet Controller Interrupt Enable Register */
|
||||
#define PIC32MX_ETH_IENSET_OFFSET 0x00c4
|
||||
#define PIC32MX_ETH_IENCLR_OFFSET 0x00c8
|
||||
#define PIC32MX_ETH_IENCLR_OFFSET 0x00c4
|
||||
#define PIC32MX_ETH_IENSET_OFFSET 0x00c8
|
||||
#define PIC32MX_ETH_IENINV_OFFSET 0x00cc
|
||||
#define PIC32MX_ETH_IRQ_OFFSET 0x00d0 /* Ethernet Controller Interrupt Request Register */
|
||||
#define PIC32MX_ETH_IRQSET_OFFSET 0x00d4
|
||||
#define PIC32MX_ETH_IRQCLR_OFFSET 0x00d8
|
||||
#define PIC32MX_ETH_IRQCLR_OFFSET 0x00d4
|
||||
#define PIC32MX_ETH_IRQSET_OFFSET 0x00d8
|
||||
#define PIC32MX_ETH_IRQINV_OFFSET 0x00dc
|
||||
#define PIC32MX_ETH_STAT_OFFSET 0x00e0 /* Ethernet Controller Status Register */
|
||||
|
||||
/* RX Filtering Configuration Registers */
|
||||
|
||||
#define PIC32MX_ETH_RXFC_OFFSET 0x00a0 /* Ethernet Controller Receive Filter Configuration Register */
|
||||
#define PIC32MX_ETH_RXFCSET_OFFSET 0x00a4
|
||||
#define PIC32MX_ETH_RXFCCLR_OFFSET 0x00a8
|
||||
#define PIC32MX_ETH_RXFCCLR_OFFSET 0x00a4
|
||||
#define PIC32MX_ETH_RXFCSET_OFFSET 0x00a8
|
||||
#define PIC32MX_ETH_RXFCINV_OFFSET 0x00ac
|
||||
|
||||
#define PIC32MX_ETH_HT0_OFFSET 0x0040 /* Ethernet Controller Hash Table 0 Register */
|
||||
#define PIC32MX_ETH_HT0SET_OFFSET 0x0044
|
||||
#define PIC32MX_ETH_HT0CLR_OFFSET 0x0048
|
||||
#define PIC32MX_ETH_HT0CLR_OFFSET 0x0044
|
||||
#define PIC32MX_ETH_HT0SET_OFFSET 0x0048
|
||||
#define PIC32MX_ETH_HT0INV_OFFSET 0x004c
|
||||
#define PIC32MX_ETH_HT1_OFFSET 0x0050 /* Ethernet Controller Hash Table 1 Register */
|
||||
#define PIC32MX_ETH_HT1SET_OFFSET 0x0054
|
||||
#define PIC32MX_ETH_HT1CLR_OFFSET 0x0058
|
||||
#define PIC32MX_ETH_HT1CLR_OFFSET 0x0054
|
||||
#define PIC32MX_ETH_HT1SET_OFFSET 0x0058
|
||||
#define PIC32MX_ETH_HT1INV_OFFSET 0x005c
|
||||
#define PIC32MX_ETH_PMM0_OFFSET 0x0060 /* Ethernet Controller Pattern Match Mask 0 Register */
|
||||
#define PIC32MX_ETH_PMM0SET_OFFSET 0x0064
|
||||
#define PIC32MX_ETH_PMM0CLR_OFFSET 0x0068
|
||||
#define PIC32MX_ETH_PMM0CLR_OFFSET 0x0064
|
||||
#define PIC32MX_ETH_PMM0SET_OFFSET 0x0068
|
||||
#define PIC32MX_ETH_PMM0INV_OFFSET 0x006c
|
||||
#define PIC32MX_ETH_PMM1_OFFSET 0x0070 /* Ethernet Controller Pattern Match Mask 1 Register */
|
||||
#define PIC32MX_ETH_PMM1SET_OFFSET 0x0074
|
||||
#define PIC32MX_ETH_PMM1CLR_OFFSET 0x0078
|
||||
#define PIC32MX_ETH_PMM1CLR_OFFSET 0x0074
|
||||
#define PIC32MX_ETH_PMM1SET_OFFSET 0x0078
|
||||
#define PIC32MX_ETH_PMM1INV_OFFSET 0x007c
|
||||
#define PIC32MX_ETH_PMCS_OFFSET 0x0080 /* Ethernet Controller Pattern Match Checksum Register */
|
||||
#define PIC32MX_ETH_PMCSSET_OFFSET 0x0084
|
||||
#define PIC32MX_ETH_PMCSCLR_OFFSET 0x0088
|
||||
#define PIC32MX_ETH_PMCSCLR_OFFSET 0x0084
|
||||
#define PIC32MX_ETH_PMCSSET_OFFSET 0x0088
|
||||
#define PIC32MX_ETH_PMCSINV_OFFSET 0x008c
|
||||
#define PIC32MX_ETH_PMO_OFFSET 0x0090 /* Ethernet Controller Pattern Match Offset Register */
|
||||
#define PIC32MX_ETH_PMOSET_OFFSET 0x0094
|
||||
#define PIC32MX_ETH_PMOCLR_OFFSET 0x0098
|
||||
#define PIC32MX_ETH_PMOCLR_OFFSET 0x0094
|
||||
#define PIC32MX_ETH_PMOSET_OFFSET 0x0098
|
||||
#define PIC32MX_ETH_PMOINV_OFFSET 0x009c
|
||||
|
||||
/* Flow Control Configuring Register */
|
||||
|
||||
#define PIC32MX_ETH_RXWM_OFFSET 0x00b0 /* Ethernet Controller Receive Watermarks Register */
|
||||
#define PIC32MX_ETH_RXWMSET_OFFSET 0x00b4
|
||||
#define PIC32MX_ETH_RXWMCLR_OFFSET 0x00b8
|
||||
#define PIC32MX_ETH_RXWMCLR_OFFSET 0x00b4
|
||||
#define PIC32MX_ETH_RXWMSET_OFFSET 0x00b8
|
||||
#define PIC32MX_ETH_RXWMINV_OFFSET 0x00bc
|
||||
|
||||
/* Ethernet Statistics Registers */
|
||||
|
||||
#define PIC32MX_ETH_RXOVFLOW_OFFSET 0x0100 /* Ethernet Controller Receive Overflow Statistics Register */
|
||||
#define PIC32MX_ETH_RXOVFLOWSET_OFFSET 0x0104
|
||||
#define PIC32MX_ETH_RXOVFLOWCLR_OFFSET 0x0108
|
||||
#define PIC32MX_ETH_RXOVFLOWCLR_OFFSET 0x0104
|
||||
#define PIC32MX_ETH_RXOVFLOWSET_OFFSET 0x0108
|
||||
#define PIC32MX_ETH_RXOVFLOWINV_OFFSET 0x010c
|
||||
#define PIC32MX_ETH_FRMTXOK_OFFSET 0x0110 /* Ethernet Controller Frames Transmitted OK Statistics Register */
|
||||
#define PIC32MX_ETH_FRMTXOKSET_OFFSET 0x0114
|
||||
#define PIC32MX_ETH_FRMTXOKCLR_OFFSET 0x0118
|
||||
#define PIC32MX_ETH_FRMTXOKCLR_OFFSET 0x0114
|
||||
#define PIC32MX_ETH_FRMTXOKSET_OFFSET 0x0118
|
||||
#define PIC32MX_ETH_FRMTXOKINV_OFFSET 0x011c
|
||||
#define PIC32MX_ETH_SCOLFRM_OFFSET 0x0120 /* Ethernet Controller Single Collision Frames Statistics Register */
|
||||
#define PIC32MX_ETH_SCOLFRMSET_OFFSET 0x0124
|
||||
#define PIC32MX_ETH_SCOLFRMCLR_OFFSET 0x0128
|
||||
#define PIC32MX_ETH_SCOLFRMCLR_OFFSET 0x0124
|
||||
#define PIC32MX_ETH_SCOLFRMSET_OFFSET 0x0128
|
||||
#define PIC32MX_ETH_SCOLFRMINV_OFFSET 0x012c
|
||||
#define PIC32MX_ETH_MCOLFRM_OFFSET 0x0130 /* Ethernet Controller Multiple Collision Frames Statistics Register */
|
||||
#define PIC32MX_ETH_MCOLFRMSET_OFFSET 0x0134
|
||||
#define PIC32MX_ETH_MCOLFRMCLR_OFFSET 0x0138
|
||||
#define PIC32MX_ETH_MCOLFRMCLR_OFFSET 0x0134
|
||||
#define PIC32MX_ETH_MCOLFRMSET_OFFSET 0x0138
|
||||
#define PIC32MX_ETH_MCOLFRMINV_OFFSET 0x013c
|
||||
#define PIC32MX_ETH_FRMRXOK_OFFSET 0x0140 /* Ethernet Controller Frames Received OK Statistics Register */
|
||||
#define PIC32MX_ETH_FRMRXOKSET_OFFSET 0x0144
|
||||
#define PIC32MX_ETH_FRMRXOKCLR_OFFSET 0x0148
|
||||
#define PIC32MX_ETH_FRMRXOKCLR_OFFSET 0x0144
|
||||
#define PIC32MX_ETH_FRMRXOKSET_OFFSET 0x0148
|
||||
#define PIC32MX_ETH_FRMRXOKINV_OFFSET 0x014c
|
||||
#define PIC32MX_ETH_FCSERR_OFFSET 0x0150 /* Ethernet Controller Frame Check Sequence Error Statistics Register */
|
||||
#define PIC32MX_ETH_FCSERRSET_OFFSET 0x0154
|
||||
#define PIC32MX_ETH_FCSERRCLR_OFFSET 0x0158
|
||||
#define PIC32MX_ETH_FCSERRCLR_OFFSET 0x0154
|
||||
#define PIC32MX_ETH_FCSERRSET_OFFSET 0x0158
|
||||
#define PIC32MX_ETH_FCSERRINV_OFFSET 0x015c
|
||||
#define PIC32MX_ETH_ALGNERR_OFFSET 0x0160 /* Ethernet Controller Alignment Errors Statistics Register */
|
||||
#define PIC32MX_ETH_ALGNERRSET_OFFSET 0x0164
|
||||
#define PIC32MX_ETH_ALGNERRCLR_OFFSET 0x0168
|
||||
#define PIC32MX_ETH_ALGNERRCLR_OFFSET 0x0164
|
||||
#define PIC32MX_ETH_ALGNERRSET_OFFSET 0x0168
|
||||
#define PIC32MX_ETH_ALGNERRINV_OFFSET 0x016c
|
||||
|
||||
/* MAC Configuration Registers */
|
||||
|
||||
#define PIC32MX_EMAC1_CFG1_OFFSET 0x0200 /* Ethernet Controller MAC Configuration 1 Register */
|
||||
#define PIC32MX_EMAC1_CFG1SET_OFFSET 0x0204
|
||||
#define PIC32MX_EMAC1_CFG1CLR_OFFSET 0x0208
|
||||
#define PIC32MX_EMAC1_CFG1CLR_OFFSET 0x0204
|
||||
#define PIC32MX_EMAC1_CFG1SET_OFFSET 0x0208
|
||||
#define PIC32MX_EMAC1_CFG1INV_OFFSET 0x020c
|
||||
#define PIC32MX_EMAC1_CFG2_OFFSET 0x0210 /* Ethernet Controller MAC Configuration 2 Register */
|
||||
#define PIC32MX_EMAC1_CFG2SET_OFFSET 0x0214
|
||||
#define PIC32MX_EMAC1_CFG2CLR_OFFSET 0x0218
|
||||
#define PIC32MX_EMAC1_CFG2CLR_OFFSET 0x0214
|
||||
#define PIC32MX_EMAC1_CFG2SET_OFFSET 0x0218
|
||||
#define PIC32MX_EMAC1_CFG2INV_OFFSET 0x021c
|
||||
#define PIC32MX_EMAC1_IPGT_OFFSET 0x0220 /* Ethernet Controller MAC Back-to-Back Interpacket Gap Register */
|
||||
#define PIC32MX_EMAC1_IPGTSET_OFFSET 0x0224
|
||||
#define PIC32MX_EMAC1_IPGTCLR_OFFSET 0x0228
|
||||
#define PIC32MX_EMAC1_IPGTCLR_OFFSET 0x0224
|
||||
#define PIC32MX_EMAC1_IPGTSET_OFFSET 0x0228
|
||||
#define PIC32MX_EMAC1_IPGTINV_OFFSET 0x022c
|
||||
#define PIC32MX_EMAC1_IPGR_OFFSET 0x0230 /* Ethernet Controller MAC Non-Back-to-Back Interpacket Gap Register */
|
||||
#define PIC32MX_EMAC1_IPGRSET_OFFSET 0x0234
|
||||
#define PIC32MX_EMAC1_IPGRCLR_OFFSET 0x0238
|
||||
#define PIC32MX_EMAC1_IPGRCLR_OFFSET 0x0234
|
||||
#define PIC32MX_EMAC1_IPGRSET_OFFSET 0x0238
|
||||
#define PIC32MX_EMAC1_IPGRINV_OFFSET 0x023c
|
||||
#define PIC32MX_EMAC1_CLRT_OFFSET 0x0240 /* Ethernet Controller MAC Collision Window/Retry Limit Register */
|
||||
#define PIC32MX_EMAC1_CLRTSET_OFFSET 0x0244
|
||||
#define PIC32MX_EMAC1_CLRTCLR_OFFSET 0x0248
|
||||
#define PIC32MX_EMAC1_CLRTCLR_OFFSET 0x0244
|
||||
#define PIC32MX_EMAC1_CLRTSET_OFFSET 0x0248
|
||||
#define PIC32MX_EMAC1_CLRTINV_OFFSET 0x024c
|
||||
#define PIC32MX_EMAC1_MAXF_OFFSET 0x0250 /* Ethernet Controller MAC Maximum Frame Length Register */
|
||||
#define PIC32MX_EMAC1_MAXFSET_OFFSET 0x0254
|
||||
#define PIC32MX_EMAC1_MAXFCLR_OFFSET 0x0258
|
||||
#define PIC32MX_EMAC1_MAXFCLR_OFFSET 0x0254
|
||||
#define PIC32MX_EMAC1_MAXFSET_OFFSET 0x0258
|
||||
#define PIC32MX_EMAC1_MAXFINV_OFFSET 0x025c
|
||||
#define PIC32MX_EMAC1_SUPP_OFFSET 0x0260 /* Ethernet Controller MAC PHY Support Register */
|
||||
#define PIC32MX_EMAC1_SUPPSET_OFFSET 0x0264
|
||||
#define PIC32MX_EMAC1_SUPPCLR_OFFSET 0x0268
|
||||
#define PIC32MX_EMAC1_SUPPCLR_OFFSET 0x0264
|
||||
#define PIC32MX_EMAC1_SUPPSET_OFFSET 0x0268
|
||||
#define PIC32MX_EMAC1_SUPPINV_OFFSET 0x026c
|
||||
#define PIC32MX_EMAC1_TEST_OFFSET 0x0270 /* Ethernet Controller MAC Test Register */
|
||||
#define PIC32MX_EMAC1_TESTSET_OFFSET 0x0274
|
||||
#define PIC32MX_EMAC1_TESTCLR_OFFSET 0x0278
|
||||
#define PIC32MX_EMAC1_TESTCLR_OFFSET 0x0274
|
||||
#define PIC32MX_EMAC1_TESTSET_OFFSET 0x0278
|
||||
#define PIC32MX_EMAC1_TESTINV_OFFSET 0x027c
|
||||
|
||||
#define PIC32MX_EMAC1_SA0_OFFSET 0x0300 /* Ethernet Controller MAC Station Address 0 Register */
|
||||
#define PIC32MX_EMAC1_SA0SET_OFFSET 0x0304
|
||||
#define PIC32MX_EMAC1_SA0CLR_OFFSET 0x0308
|
||||
#define PIC32MX_EMAC1_SA0CLR_OFFSET 0x0304
|
||||
#define PIC32MX_EMAC1_SA0SET_OFFSET 0x0308
|
||||
#define PIC32MX_EMAC1_SA0INV_OFFSET 0x030c
|
||||
#define PIC32MX_EMAC1_SA1_OFFSET 0x0310 /* Ethernet Controller MAC Station Address 1 Register */
|
||||
#define PIC32MX_EMAC1_SA1SET_OFFSET 0x0314
|
||||
#define PIC32MX_EMAC1_SA1CLR_OFFSET 0x0318
|
||||
#define PIC32MX_EMAC1_SA1CLR_OFFSET 0x0314
|
||||
#define PIC32MX_EMAC1_SA1SET_OFFSET 0x0318
|
||||
#define PIC32MX_EMAC1_SA1INV_OFFSET 0x031c
|
||||
#define PIC32MX_EMAC1_SA2_OFFSET 0x0320 /* Ethernet Controller MAC Station Address 2 Register */
|
||||
#define PIC32MX_EMAC1_SA2SET_OFFSET 0x0324
|
||||
#define PIC32MX_EMAC1_SA2CLR_OFFSET 0x0328
|
||||
#define PIC32MX_EMAC1_SA2CLR_OFFSET 0x0324
|
||||
#define PIC32MX_EMAC1_SA2SET_OFFSET 0x0328
|
||||
#define PIC32MX_EMAC1_SA2INV_OFFSET 0x032c
|
||||
|
||||
/* MII Management Registers */
|
||||
|
||||
#define PIC32MX_EMAC1_MCFG_OFFSET 0x0280 /* Ethernet Controller MAC MII Management Configuration Register */
|
||||
#define PIC32MX_EMAC1_MCFGSET_OFFSET 0x0284
|
||||
#define PIC32MX_EMAC1_MCFGCLR_OFFSET 0x0288
|
||||
#define PIC32MX_EMAC1_MCFGCLR_OFFSET 0x0284
|
||||
#define PIC32MX_EMAC1_MCFGSET_OFFSET 0x0288
|
||||
#define PIC32MX_EMAC1_MCFGINV_OFFSET 0x028c
|
||||
#define PIC32MX_EMAC1_MCMD_OFFSET 0x0290 /* Ethernet Controller MAC MII Management Command Register */
|
||||
#define PIC32MX_EMAC1_MCMDSET_OFFSET 0x0294
|
||||
#define PIC32MX_EMAC1_MCMDCLR_OFFSET 0x0298
|
||||
#define PIC32MX_EMAC1_MCMDCLR_OFFSET 0x0294
|
||||
#define PIC32MX_EMAC1_MCMDSET_OFFSET 0x0298
|
||||
#define PIC32MX_EMAC1_MCMDINV_OFFSET 0x029c
|
||||
#define PIC32MX_EMAC1_MADR_OFFSET 0x02a0 /* Ethernet Controller MAC MII Management Address Register */
|
||||
#define PIC32MX_EMAC1_MADRSET_OFFSET 0x02a4
|
||||
#define PIC32MX_EMAC1_MADRCLR_OFFSET 0x02a8
|
||||
#define PIC32MX_EMAC1_MADRCLR_OFFSET 0x02a4
|
||||
#define PIC32MX_EMAC1_MADRSET_OFFSET 0x02a8
|
||||
#define PIC32MX_EMAC1_MADRINV_OFFSET 0x02ac
|
||||
#define PIC32MX_EMAC1_MWTD_OFFSET 0x02b0 /* Ethernet Controller MAC MII Management Write Data Register */
|
||||
#define PIC32MX_EMAC1_MWTDSET_OFFSET 0x02b4
|
||||
#define PIC32MX_EMAC1_MWTDCLR_OFFSET 0x02b8
|
||||
#define PIC32MX_EMAC1_MWTDCLR_OFFSET 0x02b4
|
||||
#define PIC32MX_EMAC1_MWTDSET_OFFSET 0x02b8
|
||||
#define PIC32MX_EMAC1_MWTDINV_OFFSET 0x02bc
|
||||
#define PIC32MX_EMAC1_MRDD_OFFSET 0x02c0 /* Ethernet Controller MAC MII Management Read Data Register */
|
||||
#define PIC32MX_EMAC1_MRDDSET_OFFSET 0x02c4
|
||||
#define PIC32MX_EMAC1_MRDDCLR_OFFSET 0x02c8
|
||||
#define PIC32MX_EMAC1_MRDDCLR_OFFSET 0x02c4
|
||||
#define PIC32MX_EMAC1_MRDDSET_OFFSET 0x02c8
|
||||
#define PIC32MX_EMAC1_MRDDINV_OFFSET 0x02cc
|
||||
#define PIC32MX_EMAC1_MIND_OFFSET 0x02d0 /* Ethernet Controller MAC MII Management Indicators Register */
|
||||
#define PIC32MX_EMAC1_MINDSET_OFFSET 0x02d4
|
||||
#define PIC32MX_EMAC1_MINDCLR_OFFSET 0x02d8
|
||||
#define PIC32MX_EMAC1_MINDCLR_OFFSET 0x02d4
|
||||
#define PIC32MX_EMAC1_MINDSET_OFFSET 0x02d8
|
||||
#define PIC32MX_EMAC1_MINDINV_OFFSET 0x02dc
|
||||
|
||||
/* Register Addresses ***********************************************************************/
|
||||
@@ -228,172 +228,172 @@
|
||||
/* Controller and DMA Engine Configuration/Status Registers */
|
||||
|
||||
#define PIC32MX_ETH_CON1 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON1_OFFSET)
|
||||
#define PIC32MX_ETH_CON1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON1SET_OFFSET)
|
||||
#define PIC32MX_ETH_CON1CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON1CLR_OFFSET)
|
||||
#define PIC32MX_ETH_CON1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON1SET_OFFSET)
|
||||
#define PIC32MX_ETH_CON1INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON1INV_OFFSET)
|
||||
#define PIC32MX_ETH_CON2 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON2_OFFSET)
|
||||
#define PIC32MX_ETH_CON2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON2SET_OFFSET)
|
||||
#define PIC32MX_ETH_CON2CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON2CLR_OFFSET)
|
||||
#define PIC32MX_ETH_CON2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON2SET_OFFSET)
|
||||
#define PIC32MX_ETH_CON2INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_CON2INV_OFFSET)
|
||||
#define PIC32MX_ETH_TXST (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_TXST_OFFSET)
|
||||
#define PIC32MX_ETH_TXSTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_TXSTSET_OFFSET)
|
||||
#define PIC32MX_ETH_TXSTCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_TXSTCLR_OFFSET)
|
||||
#define PIC32MX_ETH_TXSTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_TXSTSET_OFFSET)
|
||||
#define PIC32MX_ETH_TXSTINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_TXSTINV_OFFSET)
|
||||
#define PIC32MX_ETH_RXST (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXST_OFFSET)
|
||||
#define PIC32MX_ETH_RXSTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXSTSET_OFFSET)
|
||||
#define PIC32MX_ETH_RXSTCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXSTCLR_OFFSET)
|
||||
#define PIC32MX_ETH_RXSTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXSTSET_OFFSET)
|
||||
#define PIC32MX_ETH_RXSTINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXSTINV_OFFSET)
|
||||
#define PIC32MX_ETH_IEN (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IEN_OFFSET)
|
||||
#define PIC32MX_ETH_IENSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENSET_OFFSET)
|
||||
#define PIC32MX_ETH_IENCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENCLR_OFFSET)
|
||||
#define PIC32MX_ETH_IENSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENSET_OFFSET)
|
||||
#define PIC32MX_ETH_IENINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IENINV_OFFSET)
|
||||
#define PIC32MX_ETH_IRQ (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQ_OFFSET)
|
||||
#define PIC32MX_ETH_IRQSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQSET_OFFSET)
|
||||
#define PIC32MX_ETH_IRQCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQCLR_OFFSET)
|
||||
#define PIC32MX_ETH_IRQSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQSET_OFFSET)
|
||||
#define PIC32MX_ETH_IRQINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_IRQINV_OFFSET)
|
||||
#define PIC32MX_ETH_STAT (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_STAT_OFFSET)
|
||||
|
||||
/* RX Filtering Configuration Registers */
|
||||
|
||||
#define PIC32MX_ETH_RXFC (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXFC_OFFSET)
|
||||
#define PIC32MX_ETH_RXFCSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXFCSET_OFFSET)
|
||||
#define PIC32MX_ETH_RXFCCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXFCCLR_OFFSET)
|
||||
#define PIC32MX_ETH_RXFCSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXFCSET_OFFSET)
|
||||
#define PIC32MX_ETH_RXFCINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXFCINV_OFFSET)
|
||||
#define PIC32MX_ETH_HT0 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT0_OFFSET)
|
||||
#define PIC32MX_ETH_HT0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT0SET_OFFSET)
|
||||
#define PIC32MX_ETH_HT0CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT0CLR_OFFSET)
|
||||
#define PIC32MX_ETH_HT0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT0SET_OFFSET)
|
||||
#define PIC32MX_ETH_HT0INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT0INV_OFFSET)
|
||||
#define PIC32MX_ETH_HT1 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT1_OFFSET)
|
||||
#define PIC32MX_ETH_HT1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT1SET_OFFSET)
|
||||
#define PIC32MX_ETH_HT1CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT1CLR_OFFSET)
|
||||
#define PIC32MX_ETH_HT1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT1SET_OFFSET)
|
||||
#define PIC32MX_ETH_HT1INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_HT1INV_OFFSET)
|
||||
#define PIC32MX_ETH_PMM0 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM0_OFFSET)
|
||||
#define PIC32MX_ETH_PMM0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM0SET_OFFSET)
|
||||
#define PIC32MX_ETH_PMM0CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM0CLR_OFFSET)
|
||||
#define PIC32MX_ETH_PMM0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM0SET_OFFSET)
|
||||
#define PIC32MX_ETH_PMM0INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM0INV_OFFSET)
|
||||
#define PIC32MX_ETH_PMM1 (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM1_OFFSET)
|
||||
#define PIC32MX_ETH_PMM1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM1SET_OFFSET)
|
||||
#define PIC32MX_ETH_PMM1CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM1CLR_OFFSET)
|
||||
#define PIC32MX_ETH_PMM1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM1SET_OFFSET)
|
||||
#define PIC32MX_ETH_PMM1INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMM1INV_OFFSET)
|
||||
#define PIC32MX_ETH_PMCS (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMCS_OFFSET)
|
||||
#define PIC32MX_ETH_PMCSSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMCSSET_OFFSET)
|
||||
#define PIC32MX_ETH_PMCSCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMCSCLR_OFFSET)
|
||||
#define PIC32MX_ETH_PMCSSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMCSSET_OFFSET)
|
||||
#define PIC32MX_ETH_PMCSINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMCSINV_OFFSET)
|
||||
#define PIC32MX_ETH_PMO (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMO_OFFSET)
|
||||
#define PIC32MX_ETH_PMOSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMOSET_OFFSET)
|
||||
#define PIC32MX_ETH_PMOCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMOCLR_OFFSET)
|
||||
#define PIC32MX_ETH_PMOSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMOSET_OFFSET)
|
||||
#define PIC32MX_ETH_PMOINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_PMOINV_OFFSET)
|
||||
|
||||
/* Flow Control Configuring Register */
|
||||
|
||||
#define PIC32MX_ETH_RXWM (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXWM_OFFSET)
|
||||
#define PIC32MX_ETH_RXWMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXWMSET_OFFSET)
|
||||
#define PIC32MX_ETH_RXWMCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXWMCLR_OFFSET)
|
||||
#define PIC32MX_ETH_RXWMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXWMSET_OFFSET)
|
||||
#define PIC32MX_ETH_RXWMINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXWMINV_OFFSET)
|
||||
|
||||
/* Ethernet Statistics Registers */
|
||||
|
||||
#define PIC32MX_ETH_RXOVFLOW (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXOVFLOW_OFFSET)
|
||||
#define PIC32MX_ETH_RXOVFLOWSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXOVFLOWSET_OFFSET)
|
||||
#define PIC32MX_ETH_RXOVFLOWCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXOVFLOWCLR_OFFSET)
|
||||
#define PIC32MX_ETH_RXOVFLOWSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXOVFLOWSET_OFFSET)
|
||||
#define PIC32MX_ETH_RXOVFLOWINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_RXOVFLOWINV_OFFSET)
|
||||
#define PIC32MX_ETH_FRMTXOK (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMTXOK_OFFSET)
|
||||
#define PIC32MX_ETH_FRMTXOKSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMTXOKSET_OFFSET)
|
||||
#define PIC32MX_ETH_FRMTXOKCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMTXOKCLR_OFFSET)
|
||||
#define PIC32MX_ETH_FRMTXOKSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMTXOKSET_OFFSET)
|
||||
#define PIC32MX_ETH_FRMTXOKINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMTXOKINV_OFFSET)
|
||||
#define PIC32MX_ETH_SCOLFRM (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_SCOLFRM_OFFSET)
|
||||
#define PIC32MX_ETH_SCOLFRMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_SCOLFRMSET_OFFSET)
|
||||
#define PIC32MX_ETH_SCOLFRMCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_SCOLFRMCLR_OFFSET)
|
||||
#define PIC32MX_ETH_SCOLFRMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_SCOLFRMSET_OFFSET)
|
||||
#define PIC32MX_ETH_SCOLFRMINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_SCOLFRMINV_OFFSET)
|
||||
#define PIC32MX_ETH_MCOLFRM (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_MCOLFRM_OFFSET)
|
||||
#define PIC32MX_ETH_MCOLFRMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_MCOLFRMSET_OFFSET)
|
||||
#define PIC32MX_ETH_MCOLFRMCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_MCOLFRMCLR_OFFSET)
|
||||
#define PIC32MX_ETH_MCOLFRMSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_MCOLFRMSET_OFFSET)
|
||||
#define PIC32MX_ETH_MCOLFRMINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_MCOLFRMINV_OFFSET)
|
||||
#define PIC32MX_ETH_FRMRXOK (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMRXOK_OFFSET)
|
||||
#define PIC32MX_ETH_FRMRXOKSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMRXOKSET_OFFSET)
|
||||
#define PIC32MX_ETH_FRMRXOKCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMRXOKCLR_OFFSET)
|
||||
#define PIC32MX_ETH_FRMRXOKSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMRXOKSET_OFFSET)
|
||||
#define PIC32MX_ETH_FRMRXOKINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FRMRXOKINV_OFFSET)
|
||||
#define PIC32MX_ETH_FCSERR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FCSERR_OFFSET)
|
||||
#define PIC32MX_ETH_FCSERRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FCSERRSET_OFFSET)
|
||||
#define PIC32MX_ETH_FCSERRCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FCSERRCLR_OFFSET)
|
||||
#define PIC32MX_ETH_FCSERRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FCSERRSET_OFFSET)
|
||||
#define PIC32MX_ETH_FCSERRINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_FCSERRINV_OFFSET)
|
||||
#define PIC32MX_ETH_ALGNERR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_ALGNERR_OFFSET)
|
||||
#define PIC32MX_ETH_ALGNERRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_ALGNERRSET_OFFSET)
|
||||
#define PIC32MX_ETH_ALGNERRCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_ALGNERRCLR_OFFSET)
|
||||
#define PIC32MX_ETH_ALGNERRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_ALGNERRSET_OFFSET)
|
||||
#define PIC32MX_ETH_ALGNERRINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_ETH_ALGNERRINV_OFFSET)
|
||||
|
||||
/* MAC Configuration Registers */
|
||||
|
||||
#define PIC32MX_EMAC1_CFG1 (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG1_OFFSET)
|
||||
#define PIC32MX_EMAC1_CFG1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG1SET_OFFSET)
|
||||
#define PIC32MX_EMAC1_CFG1CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG1CLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_CFG1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG1SET_OFFSET)
|
||||
#define PIC32MX_EMAC1_CFG1INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG1INV_OFFSET)
|
||||
#define PIC32MX_EMAC1_CFG2 (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG2_OFFSET)
|
||||
#define PIC32MX_EMAC1_CFG2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG2SET_OFFSET)
|
||||
#define PIC32MX_EMAC1_CFG2CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG2CLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_CFG2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG2SET_OFFSET)
|
||||
#define PIC32MX_EMAC1_CFG2INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CFG2INV_OFFSET)
|
||||
#define PIC32MX_EMAC1_IPGT (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGT_OFFSET)
|
||||
#define PIC32MX_EMAC1_IPGTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGTSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_IPGTCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGTCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_IPGTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGTSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_IPGTINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGTINV_OFFSET)
|
||||
#define PIC32MX_EMAC1_IPGR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGR_OFFSET)
|
||||
#define PIC32MX_EMAC1_IPGRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGRSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_IPGRCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGRCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_IPGRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGRSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_IPGRINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_IPGRINV_OFFSET)
|
||||
#define PIC32MX_EMAC1_CLRT (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CLRT_OFFSET)
|
||||
#define PIC32MX_EMAC1_CLRTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CLRTSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_CLRTCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CLRTCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_CLRTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CLRTSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_CLRTINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_CLRTINV_OFFSET)
|
||||
#define PIC32MX_EMAC1_MAXF (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MAXF_OFFSET)
|
||||
#define PIC32MX_EMAC1_MAXFSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MAXFSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MAXFCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MAXFCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_MAXFSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MAXFSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MAXFINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MAXFINV_OFFSET)
|
||||
#define PIC32MX_EMAC1_SUPP (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SUPP_OFFSET)
|
||||
#define PIC32MX_EMAC1_SUPPSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SUPPSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_SUPPCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SUPPCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_SUPPSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SUPPSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_SUPPINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SUPPINV_OFFSET)
|
||||
#define PIC32MX_EMAC1_TEST (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_TEST_OFFSET)
|
||||
#define PIC32MX_EMAC1_TESTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_TESTSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_TESTCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_TESTCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_TESTSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_TESTSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_TESTINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_TESTINV_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA0 (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA0_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA0SET_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA0CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA0CLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA0SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA0SET_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA0INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA0INV_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA1 (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA1_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA1SET_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA1CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA1CLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA1SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA1SET_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA1INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA1INV_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA2 (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA2_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA2SET_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA2CLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA2CLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA2SET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA2SET_OFFSET)
|
||||
#define PIC32MX_EMAC1_SA2INV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_SA2INV_OFFSET)
|
||||
|
||||
/* MII Management Registers */
|
||||
|
||||
#define PIC32MX_EMAC1_MCFG (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCFG_OFFSET)
|
||||
#define PIC32MX_EMAC1_MCFGSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCFGSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MCFGCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCFGCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_MCFGSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCFGSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MCFGINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCFGINV_OFFSET)
|
||||
#define PIC32MX_EMAC1_MCMD (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCMD_OFFSET)
|
||||
#define PIC32MX_EMAC1_MCMDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCMDSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MCMDCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCMDCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_MCMDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCMDSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MCMDINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MCMDINV_OFFSET)
|
||||
#define PIC32MX_EMAC1_MADR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MADR_OFFSET)
|
||||
#define PIC32MX_EMAC1_MADRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MADRSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MADRCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MADRCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_MADRSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MADRSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MADRINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MADRINV_OFFSET)
|
||||
#define PIC32MX_EMAC1_MWTD (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MWTD_OFFSET)
|
||||
#define PIC32MX_EMAC1_MWTDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MWTDSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MWTDCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MWTDCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_MWTDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MWTDSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MWTDINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MWTDINV_OFFSET)
|
||||
#define PIC32MX_EMAC1_MRDD (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MRDD_OFFSET)
|
||||
#define PIC32MX_EMAC1_MRDDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MRDDSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MRDDCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MRDDCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_MRDDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MRDDSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MRDDINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MRDDINV_OFFSET )
|
||||
#define PIC32MX_EMAC1_MIND (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MIND_OFFSET)
|
||||
#define PIC32MX_EMAC1_MINDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MINDSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MINDCLR (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MINDCLR_OFFSET)
|
||||
#define PIC32MX_EMAC1_MINDSET (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MINDSET_OFFSET)
|
||||
#define PIC32MX_EMAC1_MINDINV (PIC32MX_ETHERNET_K1BASE+PIC32MX_EMAC1_MINDINV_OFFSET)
|
||||
|
||||
/* Register Bit-Field Definitions ***********************************************************/
|
||||
|
||||
+305
-305
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user