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Improvements for NRF52 (#37)
Author: Alan Carvalho de Assis <acassis@gmail.com> Fix long line comments in the header files Author: Mateusz Szafoni <raiden00pl@users.noreply.github.com> * arch/arm/src/nrf52: add GPIOTE and SAADC registers definitions * arch/arm/src/nrf52: update some registers definitions * arch/arm/src/nrf52: add basic I2C support * arch/arm/src/nrf52: add function to unconfigure GPIO * arch/arm/src/nrf52/nrf52_lowputc: add missing FAR
This commit is contained in:
Mateusz Szafoni
committed by
Alan Carvalho de Assis
Alan Carvalho de Assis
parent
d644567dff
commit
9e091d2027
@@ -89,6 +89,8 @@
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/* Register bit definitions *********************************************************/
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#define NRF52_GPIO_CNF_DIR (1 << 0) /* Bit 0: Pin direction */
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#define NRF52_GPIO_CNF_INPUT (1 << 1) /* Bit 1: Input buffer disconnect */
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#define NRF52_GPIO_CNF_PULL_SHIFT (2)
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#define NRF52_GPIO_CNF_PULL_MASK (0x3 << NRF52_GPIO_CNF_PULL_SHIFT)
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# define NRF52_GPIO_CNF_PULL_DISABLED (0 << NRF52_GPIO_CNF_PULL_SHIFT)
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@@ -0,0 +1,99 @@
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/****************************************************************************
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* arch/arm/src/nrf52/hardware/nrf52_gpiote.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
|
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* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIOTE_H
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#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIOTE_H
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/****************************************************************************
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* Included Files
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***************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/nrf52_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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***************************************************************************/
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/* Register offsets for GPIOTE *********************************************/
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#define NRF52_GPIOTE_TASKS_OUT_OFFSET(x) (0x0000 + (0x04 * x)) /* TASKS_OUT[x] */
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#define NRF52_GPIOTE_TASKS_SET_OFFSET(x) (0x0030 + (0x04 * x)) /* TASKS_SET[x] */
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#define NRF52_GPIOTE_TASKS_CLR_OFFSET(x) (0x0060 + (0x04 * x)) /* TASKS_CLR[x] */
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#define NRF52_GPIOTE_EVENTS_IN_OFFSET(x) (0x0100 + (0x04 * x)) /* EVENTS_IN[x] */
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#define NRF52_GPIOTE_EVENTS_PORT_OFFSET 0x017c /* EVENTS_PORT */
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#define NRF52_GPIOTE_INTENSET_OFFSET 0x0304 /* INTENSET */
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#define NRF52_GPIOTE_INTENCLR_OFFSET 0x0308 /* INTENCLR */
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#define NRF52_GPIOTE_CONFIG_OFFSET(x) (0x0510 + (0x04 * x)) /* CONFIG[x] */
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/* Register addresses for GPIOTE *******************************************/
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#define NRF52_GPIOTE_TASKS_OUT(x) (NRF52_GPIOTE_BASE + NRF52_GPIOTE_TASKS_OUT_OFFSET(x))
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#define NRF52_GPIOTE_TASKS_SET(x) (NRF52_GPIOTE_BASE + NRF52_GPIOTE_TASKS_SET_OFFSET(x))
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#define NRF52_GPIOTE_TASKS_CLR(x) (NRF52_GPIOTE_BASE + NRF52_GPIOTE_TASKS_CLR_OFFSET(x))
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#define NRF52_GPIOTE_EVENTS_IN(x) (NRF52_GPIOTE_BASE + NRF52_GPIOTE_EVENTS_IN_OFFSET(x))
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#define NRF52_GPIOTE_EVENTS_PORT (NRF52_GPIOTE_BASE + NRF52_GPIOTE_EVENTS_PORT_OFFSET)
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#define NRF52_GPIOTE_INTENSET (NRF52_GPIOTE_BASE + NRF52_GPIOTE_INTENSET_OFFSET)
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#define NRF52_GPIOTE_INTENCLR (NRF52_GPIOTE_BASE + NRF52_GPIOTE_INTENCLR_OFFSET)
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#define NRF52_GPIOTE_CONFIG(x) (NRF52_GPIOTE_BASE + NRF52_GPIOTE_CONFIG_OFFSET(x))
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/* Register offsets for GPIOTE *********************************************/
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/* INTENSET/INTENCLR Register */
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#define GPIOTE_INT_IN_SHIFT 0 /* Bits 0-7: Enable interrupt for event IN[i] */
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#define GPIOTE_INT_IN_MASK (0xff << GPIOTE_INT_IN_SHIFT)
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# define GPIOTE_INT_IN(i) ((1 << (i + GPIOTE_INT_IN_SHIFT)) & GPIOTE_INT_IN_MASK)
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#define GPIOTE_INT_PORT 31 /* Bit 31: Enable interrupt for event PORT */
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/* CONFIG Register */
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#define GPIOTE_CONFIG_MODE_SHIFT 0 /* Bits 0-1: Mode */
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#define GPIOTE_CONFIG_MODE_MASK (0x3 << GPIOTE_CONFIG_MODE_SHIFT)
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# define GPIOTE_CONFIG_MODE_DIS (0x0 << GPIOTE_CONFIG_MODE_SHIFT) /* 0: Disabled */
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# define GPIOTE_CONFIG_MODE_EV (0x0 << GPIOTE_CONFIG_MODE_SHIFT) /* 1: Event */
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# define GPIOTE_CONFIG_MODE_TS (0x0 << GPIOTE_CONFIG_MODE_SHIFT) /* 2: Task */
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#define GPIOTE_CONFIG_PSEL_SHIFT (8) /* Bits 8-12: GPIO number */
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#define GPIOTE_CONFIG_PSEL_MASK (0x1f << GPIOTE_CONFIG_PSEL_SHIFT)
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#define GPIOTE_CONFIG_PORT_SHIFT (13) /* Bit 13: GPIO port */
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#define GPIOTE_CONFIG_POL_SHIFT (16) /* Bits 16-17: Polarity */
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#define GPIOTE_CONFIG_POL_MASK (0x3 << GPIOTE_CONFIG_POL_SHIFT)
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# define GPIOTE_CONFIG_POL_NONE (0x0 << GPIOTE_CONFIG_POL_SHIFT) /* 0: None */
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# define GPIOTE_CONFIG_POL_LTH (0x1 << GPIOTE_CONFIG_POL_SHIFT) /* 1: LoToHi */
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# define GPIOTE_CONFIG_POL_HTL (0x2 << GPIOTE_CONFIG_POL_SHIFT) /* 2: HiToLo */
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# define GPIOTE_CONFIG_POL_TG (0x3 << GPIOTE_CONFIG_POL_SHIFT) /* 3: Toggle */
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#define GPIOTE_CONFIG_OUTINIT (20) /* Bit 20: Initial value */
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#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_GPIOTE_H */
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@@ -0,0 +1,221 @@
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/****************************************************************************
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* arch/arm/src/nrf52/hardware/nrf52_saadc.h
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*
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* Copyright (C) 2019 Gregory Nutt. All rights reserved.
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* Author: Mateusz Szafoni <raiden00@railab.me>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
|
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* 3. Neither the name NuttX nor the names of its contributors may be
|
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* used to endorse or promote products derived from this software
|
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* without specific prior written permission.
|
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
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* POSSIBILITY OF SUCH DAMAGE.
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*
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***************************************************************************/
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#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SAADC_H
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#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SAADC_H
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/****************************************************************************
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* Included Files
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***************************************************************************/
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#include <nuttx/config.h>
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#include "hardware/nrf52_memorymap.h"
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/****************************************************************************
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* Pre-processor Definitions
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***************************************************************************/
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/* Register offsets for SAADC **********************************************/
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#define NRF52_SAADC_TASKS_START 0x0000 /* Start the SAADCM */
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#define NRF52_SAADC_TASKS_SAMPLE 0x0004 /* Takes one SAADC sample */
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#define NRF52_SAADC_TASKS_STOP 0x0008 /* Stop the SAADC */
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#define NRF52_SAADC_TASKS_CALEOFFSET 0x000c /* Starts offset auto-calibration */
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#define NRF52_SAADC_EVENTS_STARTED 0x0100 /* The SAADC has started */
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#define NRF52_SAADC_EVENTS_END 0x0104 /* The SAADC has filled up the result buffer */
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#define NRF52_SAADC_EVENTS_DONE 0x0108 /* A conversio ntask has been completed */
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#define NRF52_SAADC_EVENTS_RESULTDONE 0x010c /* Result ready for transfer to RAM */
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#define NRF52_SAADC_EVENTS_CALDONE 0x0110 /* Calibration is complete */
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#define NRF52_SAADC_EVENTS_STOPPED 0x0110 /* The SAADC has stopped */
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#define NRF52_SAADC_EVENTS_CHLIMH(x) (0x118 + (x + 0x8)) /* Limit high event for channel x */
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#define NRF52_SAADC_EVENTS_CHLIML(x) (0x11c + (x + 0x8)) /* Limit low event for channel x */
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#define NRF52_SAADC_INTEN 0x0300 /* Enable or disable interrupt */
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#define NRF52_SAADC_INTENSET 0x0304 /* Enable interrupt */
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#define NRF52_SAADC_INTENCLR 0x0308 /* Disable interrupt */
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#define NRF52_SAADC_STATUS 0x0400 /* Status */
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#define NRF52_SAADC_ENABLE 0x0500 /* Enable or disable SAADC */
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#define NRF52_SAADC_CHPSELP(x) (0x510 + (x + 0x10)) /* Input positive pin for CH[x] */
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#define NRF52_SAADC_CHPSELN(x) (0x514 + (x + 0x10)) /* Input negative pin for CH[x] */
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#define NRF52_SAADC_CHCONFIG(x) (0x518 + (x + 0x10)) /* Input configuration for CH[x] */
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#define NRF52_SAADC_CHLIMIT(x) (0x51c + (x + 0x10)) /* High/low limits for event monitoring of a CH[x] */
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#define NRF52_SAADC_RESOLUTION 0x05f0 /* Resolution configuration */
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#define NRF52_SAADC_OVERSAMPLE 0x05f4 /* Oversampling configuration */
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#define NRF52_SAADC_SAMPLERATE 0x05f8 /* Controls normal or continous sample rate */
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#define NRF52_SAADC_PTR 0x062c /* Data pointer */
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#define NRF52_SAADC_MAXCNT 0x0630 /* Maximum number of 16-bit samples */
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#define NRF52_SAADC_AMOUNT 0x0634 /* Number of 16-bit samples written to buffer */
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/* Register Bitfield Definitions for SAADC *********************************/
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/* INTEN/INTENSET/INTENCLR Register */
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#define SAADC_INT_STARTED (1 << 0) /* Bit 0: Interrupt for event STARTED */
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#define SAADC_INT_END (1 << 1) /* Bit 1: Interrupt for event END */
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#define SAADC_INT_DONE (1 << 2) /* Bit 2: Interrupt for event DONE */
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#define SAADC_INT_RESULTDONE (1 << 3) /* Bit 3: Interrupt for event RESULTDONE */
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#define SAADC_INT_CALDONE (1 << 4) /* Bit 4: Interrupt for event CALIBRATEDONE */
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#define SAADC_INT_STOPPED (1 << 5) /* Bit 5: Interrupt for event STOPPED */
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#define SAADC_INT_CHXLIMH(x) (1 << (x + 0x6)) /* Bit (x+6): Interrupt for event CHxLIMITH */
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#define SAADC_INT_CHXLIML(x) (1 << (x + 0x7)) /* Bit (x+7): Interrupt for event CHxLIMITL */
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/* STATUS Register */
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#define SAADC_STATUS_READY (0) /* Bit 0: SAADC is ready */
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#define SAADC_STATUS_BUSY (1 << 0) /* Bit 0: SAADC is busy */
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/* ENABLE Register */
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#define SAADC_ENABLE_DIS (0) /* Bit 0: Disable SAADC */
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#define SAADC_ENABLE_EN (1 << 0) /* Bit 0: Enable SAADC */
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/* CH[n] PSELP Register */
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#define SAADC_CHPSELP_SHIFT (0) /* Bits 0-4: Intput positive pin selection for CH[x] */
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#define SAADC_CHPSELP_MASK (0xf << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_NC (0x0 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN0 (0x1 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN1 (0x2 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN2 (0x3 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN3 (0x4 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN4 (0x5 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN5 (0x6 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN6 (0x7 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_IN7 (0x8 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_VDD (0x9 << SAADC_CHPSELP_SHIFT)
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# define SAADC_CHPSELP_VDDHDIV5 (0xd << SAADC_CHPSELP_SHIFT)
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/* CH[n] PSELN Register */
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#define SAADC_CHPSELN_SHIFT (0) /* Bits 0-4: Intput negative pin selection for CH[x] */
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#define SAADC_CHPSELN_MASK (0xf << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_NC (0x0 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN0 (0x1 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN1 (0x2 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN2 (0x3 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN3 (0x4 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN4 (0x5 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN5 (0x6 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN6 (0x7 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_IN7 (0x8 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_VDD (0x9 << SAADC_CHPSELN_SHIFT)
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# define SAADC_CHPSELN_VDDHDIV5 (0xd << SAADC_CHPSELN_SHIFT)
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/* CH[n] CONFIG Register */
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#define SAADC_CONFIG_RESP_SHIFT (0) /* Bits 0-2: Positive channel resistor control */
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#define SAADC_CONFIG_RESP_MASK (0x3 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESN_NONE (0x0 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESN_PD (0x1 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESN_PU (0x2 << SAADC_CONFIG_RESP_SHIFT)
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# define SAADC_CONFIG_RESN_VDD1P2 (0x3 << SAADC_CONFIG_RESP_SHIFT)
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#define SAADC_CONFIG_RESN_SHIFT (4) /* Bits 4-5: Negative channel resistor control */
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#define SAADC_CONFIG_RESN_MASK (0x3 << SAADC_CONFIG_RESN_SHIFT)
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# define SAADC_CONFIG_RESN_NONE (0x0 << SAADC_CONFIG_RESN_SHIFT)
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# define SAADC_CONFIG_RESN_PD (0x1 << SAADC_CONFIG_RESN_SHIFT)
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# define SAADC_CONFIG_RESN_PU (0x2 << SAADC_CONFIG_RESN_SHIFT)
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# define SAADC_CONFIG_RESN_VDD1D2 (0x3 << SAADC_CONFIG_RESN_SHIFT)
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#define SAADC_CONFIG_GAIN_SHIFT (8) /* Bits 8-10: Gain control */
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#define SAADC_CONFIG_GAIN_MASK (0x7 << SAADC_CONFIG_GAIN_SHIFT)
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# define SAADC_CONFIG_GAIN_1P6 (0x0 << SAADC_CONFIG_GAIN_SHIFT)
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# define SAADC_CONFIG_GAIN_1P5 (0x1 << SAADC_CONFIG_GAIN_SHIFT)
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# define SAADC_CONFIG_GAIN_1P4 (0x2 << SAADC_CONFIG_GAIN_SHIFT)
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# define SAADC_CONFIG_GAIN_1P3 (0x3 << SAADC_CONFIG_GAIN_SHIFT)
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# define SAADC_CONFIG_GAIN_1P2 (0x4 << SAADC_CONFIG_GAIN_SHIFT)
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# define SAADC_CONFIG_GAIN_1 (0x5 << SAADC_CONFIG_GAIN_SHIFT)
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# define SAADC_CONFIG_GAIN_2 (0x6 << SAADC_CONFIG_GAIN_SHIFT)
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# define SAADC_CONFIG_GAIN_4 (0x7 << SAADC_CONFIG_GAIN_SHIFT)
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#define SAADC_REFSEL_INTERNAL (0 << 12) /* Bit 12: Internal reference (0.6V) */
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#define SAADC_REFSEL_VDD1P4 (1 << 12) /* Bit 12: VDD/4 as reference */
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#define SAADC_CONFIG_TACQ_SHIFT (16) /* Bits 16-18: Acquisition time */
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#define SAADC_CONFIG_TACQ_MASK (0x7 << SAADC_CONFIG_TACQ_SHIFT)
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# define SAADC_CONFIG_TACQ_3US (0x0 << SAADC_CONFIG_TACQ_SHIFT)
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# define SAADC_CONFIG_TACQ_5US (0x1 << SAADC_CONFIG_TACQ_SHIFT)
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# define SAADC_CONFIG_TACQ_10US (0x2 << SAADC_CONFIG_TACQ_SHIFT)
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# define SAADC_CONFIG_TACQ_15US (0x3 << SAADC_CONFIG_TACQ_SHIFT)
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# define SAADC_CONFIG_TACQ_20US (0x4 << SAADC_CONFIG_TACQ_SHIFT)
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# define SAADC_CONFIG_TACQ_40US (0x5 << SAADC_CONFIG_TACQ_SHIFT)
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#define SAADC_CONFIG_MODE_SE (0 << 20) /* Bit 20: Single-ended */
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#define SAADC_CONFIG_MODE_DIFF (1 << 20) /* Bit 20: Differential */
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#define SAADC_CONFIG_BURS_DIS (0 << 24) /* Bit 24: Burst mode is disabled */
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#define SAADC_CONFIG_BURS_EN (1 << 24) /* Bit 24: Burst mode is enabled */
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/* CH[n] LIMIT Register */
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#define SAADC_CHLIMIT_LOW_SHIFT (0) /* Bits 0-15: Low level limit */
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#define SAADC_CHLIMIT_LOW_MASK (0xffff << SAADC_CHLIMIT_LOW_SHIFT)
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#define SAADC_CHLIMIT_HIGH_SHIFT (16) /* Bits 0-15: High level limit */
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#define SAADC_CHLIMIT_HIGH_MASK (0xffff << SAADC_CHLIMIT_HIGH_SHIFT)
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/* RESOLUTION Register */
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#define SAADC_RESOLUTION_SHIFT (0) /* Bits 0-2: SAADC resolution */
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#define SAADC_RESOLUTION_MASK (0xf << SAADC_RESOLUTION_SHIFT)
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# define SAADC_RESOLUTION_8BIT (0x0 << SAADC_RESOLUTION_SHIFT)
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# define SAADC_RESOLUTION_10BIT (0x1 << SAADC_RESOLUTION_SHIFT)
|
||||
# define SAADC_RESOLUTION_12BIT (0x2 << SAADC_RESOLUTION_SHIFT)
|
||||
# define SAADC_RESOLUTION_14BIT (0x3 << SAADC_RESOLUTION_SHIFT)
|
||||
|
||||
/* OVERSAMPLE Register */
|
||||
|
||||
#define SAADC_OVERSAMPLE_SHIFT (0) /* Bit 0-3: Oversample control */
|
||||
#define SAADC_OVERSAMPLE_MASK (0xf << SAADC_OVERSAMPLE_SHIFT)
|
||||
# define SAADC_OVERSAMPLE_NONE (0x0 << SAADC_OVERSAMPLE_SHIFT)
|
||||
# define SAADC_OVERSAMPLE_2X (0x1 << SAADC_OVERSAMPLE_SHIFT)
|
||||
# define SAADC_OVERSAMPLE_4X (0x2 << SAADC_OVERSAMPLE_SHIFT)
|
||||
# define SAADC_OVERSAMPLE_8X (0x3 << SAADC_OVERSAMPLE_SHIFT)
|
||||
# define SAADC_OVERSAMPLE_16X (0x4 << SAADC_OVERSAMPLE_SHIFT)
|
||||
# define SAADC_OVERSAMPLE_32X (0x5 << SAADC_OVERSAMPLE_SHIFT)
|
||||
# define SAADC_OVERSAMPLE_64X (0x6 << SAADC_OVERSAMPLE_SHIFT)
|
||||
# define SAADC_OVERSAMPLE_128X (0x7 << SAADC_OVERSAMPLE_SHIFT)
|
||||
# define SAADC_OVERSAMPLE_256X (0x8 << SAADC_OVERSAMPLE_SHIFT)
|
||||
|
||||
/* SAMPLERATE Register */
|
||||
|
||||
#define SAADC_SAMPLERATE_CC_SHIFT (0) /* Bits 0-10: Capture and compare value */
|
||||
#define SAADC_SAMPLERATE_CC_MASK (0x7ff << SAADC_SAMPLERATE_CC_SHIFT)
|
||||
#define SAADC_SAMPLERATE_MODE_TASK (0 << 12) /* Bit 12: Rate is controlled from SAMPLE task */
|
||||
#define SAADC_SAMPLERATE_MODE_TIMERS (1 << 12) /* Bit 12: Rate is controlled from local timer */
|
||||
|
||||
/* MAXCNT Register */
|
||||
|
||||
#define SAADC_MAXCNT_SHIFT (0) /* Bits 0-14: Maximum of 16-bit samples written to output buffer */
|
||||
#define SAADC_MAXCNT_MASK (0x7fff)
|
||||
|
||||
/* AMOUNT Register */
|
||||
|
||||
#define SAADC_AMOUNT_SHIFT (0) /* Bits 0-14: Number of 16-bit samples written to output buffer */
|
||||
#define SAADC_AMOUNT_MASK (0x7fff)
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SAADC_H */
|
||||
@@ -1,4 +1,4 @@
|
||||
/************************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/arm/src/nrf52/hardware/nrf52_spi.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
@@ -31,23 +31,23 @@
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************************/
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SPI_H
|
||||
#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_SPI_H
|
||||
|
||||
/************************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************************/
|
||||
***************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/nrf52_memorymap.h"
|
||||
|
||||
/************************************************************************************************
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************************/
|
||||
***************************************************************************/
|
||||
|
||||
/* Register offsets for SPI master (SPIM) *******************************************************/
|
||||
/* Register offsets for SPI master (SPIM) **********************************/
|
||||
|
||||
#define NRF52_SPIM_TASK_START_OFFSET (0x0010) /* Start SPI transaction */
|
||||
#define NRF52_SPIM_TASK_STOP_OFFSET (0x0014) /* Stop SPI transaction */
|
||||
@@ -84,7 +84,7 @@
|
||||
#define NRF52_SPIM_DCXCNT_OFFSET (0x0570) /* DCX configuration */
|
||||
#define NRF52_SPIM_ORC_OFFSET (0x05c0) /* ORC */
|
||||
|
||||
/* Register offsets for SPI slave (SPIS) *******************************************************/
|
||||
/* Register offsets for SPI slave (SPIS) ***********************************/
|
||||
|
||||
#define NRF52_SPIS_SHORTS_OFFSET (0x0200) /* Shortcuts between local events and tasks */
|
||||
#define NRF52_SPIS_INTENSET_OFFSET (0x0304) /* Enable interrupt */
|
||||
@@ -108,7 +108,7 @@
|
||||
#define NRF52_SPIS_DEF_OFFSET (0x055c) /* Default character */
|
||||
#define NRF52_SPIS_ORC_OFFSET (0x05c0) /* Over-read character */
|
||||
|
||||
/* Register Bitfield Definitions for SPIM *******************************************************/
|
||||
/* Register Bitfield Definitions for SPIM **********************************/
|
||||
|
||||
/* TASKS_START Register */
|
||||
|
||||
@@ -160,13 +160,13 @@
|
||||
|
||||
/* STALLLSTAT Register */
|
||||
|
||||
#define SPIM_STALLSTAT_TX (1 << 0) /* Bit 0: Stall status for EasyDMA RAM reads */
|
||||
#define SPIM_STALLSTAT_RX (1 << 0) /* Bit 0: Stall status for EasyDMA RAM reads */
|
||||
#define SPIM_STALLSTAT_TX (1 << 1) /* Bit 1: Stall status for EasyDMA RAM writes */
|
||||
|
||||
/* ENABLE Register */
|
||||
|
||||
#define SPIM_ENABLE_DIS (0) /* Disable SPIM */
|
||||
#define SPIM_ENABLE_EN (0xf << 0) /* Enable SPIM */
|
||||
#define SPIM_ENABLE_EN (0x7 << 0) /* Enable SPIM */
|
||||
|
||||
/* PSELSCK Register */
|
||||
|
||||
@@ -175,6 +175,7 @@
|
||||
#define SPIM_PSELSCK_PORT_SHIFT (5) /* Bit 5: SCK port number */
|
||||
#define SPIM_PSELSCK_PORT_MASK (0x1 << SPIM_PSELSCK_PORT_SHIFT)
|
||||
#define SPIM_PSELSCK_CONNECTED (1 << 31) /* Bit 31: Connection */
|
||||
#define SPIM_PSELSCK_RESET (0xffffffff)
|
||||
|
||||
/* PSELMOSI Register */
|
||||
|
||||
@@ -183,6 +184,7 @@
|
||||
#define SPIM_PSELMOSI_PORT_SHIFT (5) /* Bit 5: MOSI port number */
|
||||
#define SPIM_PSELMOSI_PORT_MASK (0x1 << SPIM_PSELMOSI_PORT_SHIFT)
|
||||
#define SPIM_PSELMOSI_CONNECTED (1 << 31) /* Bit 31: Connection */
|
||||
#define SPIM_PSELMOSI_RESET (0xffffffff)
|
||||
|
||||
/* PSELMISO Register */
|
||||
|
||||
@@ -191,6 +193,7 @@
|
||||
#define SPIM_PSELMISO_PORT_SHIFT (5) /* Bit 5: MISO port number */
|
||||
#define SPIM_PSELMISO_PORT_MASK (0x1 << SPIM_PSELMISO_PORT_SHIFT)
|
||||
#define SPIM_PSELMISO_CONNECTED (1 << 31) /* Bit 31: Connection */
|
||||
#define SPIM_PSELMISO_RESET (0xffffffff)
|
||||
|
||||
/* PSELCSN Register */
|
||||
|
||||
@@ -199,6 +202,7 @@
|
||||
#define SPIM_PSELCSN_PORT_SHIFT (5) /* Bit 5: CSN port number */
|
||||
#define SPIM_PSELCSN_PORT_MASK (0x1 << SPIM_PSELCSN_PORT_SHIFT)
|
||||
#define SPIM_PSELCSN_CONNECTED (1 << 31) /* Bit 31: Connection */
|
||||
#define SPIM_PSELCSN_RESET (0xffffffff)
|
||||
|
||||
/* FREQUENCY Register */
|
||||
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
/************************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/arm/src/nrf52/hardware/nrf52_twi.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
@@ -31,23 +31,23 @@
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************************/
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TWI_H
|
||||
#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_TWI_H
|
||||
|
||||
/************************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************************/
|
||||
***************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/nrf52_memorymap.h"
|
||||
|
||||
/************************************************************************************************
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************************/
|
||||
***************************************************************************/
|
||||
|
||||
/* Register offsets for TWI master (TWIM) *******************************************************/
|
||||
/* Register offsets for TWI master (TWIM) **********************************/
|
||||
|
||||
#define NRF52_TWIM_TASKS_STARTRX_OFFSET 0x0000 /* Start TWIM receive sequence */
|
||||
#define NRF52_TWIM_TASKS_STARTTX_OFFSET 0x0008 /* Start TWIM transmit sequence */
|
||||
@@ -80,7 +80,7 @@
|
||||
#define NRF52_TWIM_TXLIST_OFFSET 0x0550 /* TX EasyDMA list type */
|
||||
#define NRF52_TWIM_ADDRESS_OFFSET 0x0588 /* TWIM address */
|
||||
|
||||
/* Register offsets for TWI slave (TWIS) ********************************************************/
|
||||
/* Register offsets for TWI slave (TWIS) ***********************************/
|
||||
|
||||
#define NRF52_TWIS_TASKS_STOP_OFFSET 0x0014 /* Stop TWIS transaction */
|
||||
#define NRF52_TWIS_TASKS_SUSPEND_OFFSET 0x001c /* Suspend TWIS transaction */
|
||||
@@ -115,7 +115,7 @@
|
||||
#define NRF52_TWIS_CONFIG_OFFSET 0x0594 /* Configuration register for the address match mechanism */
|
||||
#define NRF52_TWIS_ORC_OFFSET 0x05c0 /* Over-read character */
|
||||
|
||||
/* Register Bitfield Definitions for TWIM *******************************************************/
|
||||
/* Register Bitfield Definitions for TWIM **********************************/
|
||||
|
||||
/* SHORTS Register */
|
||||
|
||||
@@ -145,7 +145,7 @@
|
||||
/* ENABLE Register */
|
||||
|
||||
#define TWIM_ENABLE_DIS (0) /* Disable TWIM */
|
||||
#define TWIM_ENABLE_EN (0xf << 0) /* Disable TWIM */
|
||||
#define TWIM_ENABLE_EN (0x6 << 0) /* Disable TWIM */
|
||||
|
||||
/* PSELSCL Register */
|
||||
|
||||
@@ -154,6 +154,7 @@
|
||||
#define TWIM_PSELSCL_PORT_SHIFT (5) /* Bit 5: SCL port number */
|
||||
#define TWIM_PSELSCL_PORT_MASK (0x1 << TWIM_PSELSCL_PORT_SHIFT)
|
||||
#define TWIM_PSELSCL_CONNECTED (1 << 31) /* Bit 31: Connection */
|
||||
#define TWIM_PSELSCL_RESET (0xffffffff)
|
||||
|
||||
/* PSELSDA Register */
|
||||
|
||||
@@ -162,6 +163,7 @@
|
||||
#define TWIM_PSELSDA_PORT_SHIFT (5) /* Bit 5: SDA port number */
|
||||
#define TWIM_PSELSDA_PORT_MASK (0x1 << TWIM_PSELSDA_PORT_SHIFT)
|
||||
#define TWIM_PSELSDA_CONNECTED (1 << 31) /* Bit 31: Connection */
|
||||
#define TWIM_PSELSDA_RESET (0xffffffff)
|
||||
|
||||
/* FREQUENCY Register */
|
||||
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
/*****************************************************************************************************
|
||||
/****************************************************************************
|
||||
* arch/arm/src/nrf52/hardware/nrf52_uarte.h
|
||||
*
|
||||
* Copyright (C) 2018 Gregory Nutt. All rights reserved.
|
||||
@@ -31,23 +31,23 @@
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
*****************************************************************************************************/
|
||||
***************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UARTE_H
|
||||
#define __ARCH_ARM_SRC_NRF52_HARDWARE_NRF52_UARTE_H
|
||||
|
||||
/*****************************************************************************************************
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
*****************************************************************************************************/
|
||||
***************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "hardware/nrf52_memorymap.h"
|
||||
|
||||
/*****************************************************************************************************
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
*****************************************************************************************************/
|
||||
***************************************************************************/
|
||||
|
||||
/* UART/UARTE Register Offsets ***********************************************************************/
|
||||
/* UART/UARTE Register Offsets *********************************************/
|
||||
|
||||
#define NRF52_UARTE_TASKS_STARTRX_OFFSET 0x0000 /* Start UART receiver */
|
||||
#define NRF52_UARTE_TASKS_STOPRX_OFFSET 0x0004 /* Stop UART receiver */
|
||||
@@ -109,7 +109,7 @@
|
||||
#define NRF52_UART_BAUDRATE_OFFSET 0x0524 /* Baud rate */
|
||||
#define NRF52_UART_CONFIG_OFFSET 0x056c /* Configuration of parity and hardware flow control */
|
||||
|
||||
/* UART/UARTE Register Addresses *********************************************************************/
|
||||
/* UART/UARTE Register Addresses *******************************************/
|
||||
|
||||
#define NRF52_UARTE0_TASKS_STARTRX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STARTRX_OFFSET)
|
||||
#define NRF52_UARTE0_TASKS_STOPRX (NRF52_UARTE0_BASE + NRF52_UARTE_TASKS_STOPRX_OFFSET)
|
||||
@@ -233,7 +233,7 @@
|
||||
# define NRF52_UART1_CONFIG (NRF52_UART1_BASE + NRF52_UART_CONFIG_OFFSET)
|
||||
#endif
|
||||
|
||||
/* UART Register Bitfield Definitions ****************************************************************/
|
||||
/* UART Register Bitfield Definitions **************************************/
|
||||
|
||||
/* PSELRTS Register */
|
||||
|
||||
@@ -242,6 +242,7 @@
|
||||
#define UART_PSELRTS_PORT_SHIFT (5) /* Bit 5: Port number */
|
||||
#define UART_PSELRTS_PORT_MASK (0x1 << UART_PSELRTS_PORT_SHIFT)
|
||||
#define UART_PSELRTS_CONNECT (1 << 31) /* Bit 31: Connection */
|
||||
#define UART_PSELRTS_RESET (0xffffffff)
|
||||
|
||||
/* PSELTXD Register */
|
||||
|
||||
@@ -250,6 +251,7 @@
|
||||
#define UART_PSELTXD_PORT_SHIFT (5) /* Bit 5: Port number */
|
||||
#define UART_PSELTXD_PORT_MASK (0x1 << UART_PSELTXD_PORT_SHIFT)
|
||||
#define UART_PSELTXD_CONNECT (1 << 31) /* Bit 31: Connection */
|
||||
#define UART_PSELTXD_RESET (0xffffffff)
|
||||
|
||||
/* PSELCTS Register */
|
||||
|
||||
@@ -258,6 +260,7 @@
|
||||
#define UART_PSELCTS_PORT_SHIFT (5) /* Bit 5: Port number */
|
||||
#define UART_PSELCTS_PORT_MASK (0x1 << UART_PSELCTS_PORT_SHIFT)
|
||||
#define UART_PSELCTS_CONNECT (1 << 31) /* Bit 31: Connection */
|
||||
#define UART_PSELCTS_RESET (0xffffffff)
|
||||
|
||||
/* PSELRXD Register */
|
||||
|
||||
@@ -266,6 +269,7 @@
|
||||
#define UART_PSELRXD_PORT_SHIFT (5) /* Bit 5: Port number */
|
||||
#define UART_PSELRXD_PORT_MASK (0x1 << UART_PSELRXD_PORT_SHIFT)
|
||||
#define UART_PSELRXD_CONNECT (1 << 31) /* Bit 31: Connection */
|
||||
#define UART_PSELRXD_RESET (0xffffffff)
|
||||
|
||||
/* ENABLE Register */
|
||||
|
||||
|
||||
@@ -228,6 +228,36 @@ int nrf52_gpio_config(nrf52_pinset_t cfgset)
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_gpio_unconfig
|
||||
*
|
||||
* Description:
|
||||
* Unconfigure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int nrf52_gpio_unconfig(nrf52_pinset_t cfgset)
|
||||
{
|
||||
unsigned int pin;
|
||||
unsigned int port;
|
||||
uint32_t offset;
|
||||
|
||||
/* Get port and pin number */
|
||||
|
||||
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Get address offset */
|
||||
|
||||
offset = nrf52_gpio_regget(port, NRF52_GPIO_PIN_CNF_OFFSET(pin));
|
||||
|
||||
/* Configure as input and disconnect input buffer */
|
||||
|
||||
putreg32(NRF52_GPIO_CNF_INPUT, offset);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_gpio_write
|
||||
*
|
||||
|
||||
@@ -225,6 +225,16 @@ void nrf52_gpio_irqinitialize(void);
|
||||
|
||||
int nrf52_gpio_config(nrf52_pinset_t cfgset);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: nrf52_gpio_unconfig
|
||||
*
|
||||
* Description:
|
||||
* Unconfigure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int nrf52_gpio_unconfig(nrf52_pinset_t cfgset);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: nrf52_gpio_interrupt
|
||||
*
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,92 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/nrf52/nrf52_i2c.h
|
||||
*
|
||||
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
|
||||
* Author: Mateusz Szafoni <raiden00@railab.me>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_NRF52_NRF52_I2C_H
|
||||
#define __ARCH_ARM_SRC_NRF52_NRF52_I2C_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/i2c/i2c_master.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_i2cbus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected I2C port. And return a unique instance of struct
|
||||
* struct i2c_master_s. This function may be called to obtain multiple
|
||||
* instances of the interface, each of which may be set up with a
|
||||
* different frequency and slave address.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Port number (for hardware that has multiple TWI interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid I2C device structure reference on success; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct i2c_master_s *nrf52_i2cbus_initialize(int port);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: nrf52_i2cbus_uninitialize
|
||||
*
|
||||
* Description:
|
||||
* De-initialize the selected I2C port, and power down the device.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Device structure as returned by the nrf52_i2cbus_initialize()
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success, ERROR when internal reference count mismatch or dev
|
||||
* points to invalid hardware device.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int nrf52_i2cbus_uninitialize(FAR struct i2c_master_s *dev);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_NRF52_NRF52_I2C_H */
|
||||
@@ -114,7 +114,8 @@ static const struct uart_config_s g_console_config =
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
static void nrf52_setbaud(uintptr_t base, const struct uart_config_s *config)
|
||||
static void nrf52_setbaud(uintptr_t base,
|
||||
FAR const struct uart_config_s *config)
|
||||
{
|
||||
uint32_t br = 0;
|
||||
|
||||
@@ -163,7 +164,8 @@ void nrf52_lowsetup(void)
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
void nrf52_usart_configure(uintptr_t base, const struct uart_config_s *config)
|
||||
void nrf52_usart_configure(uintptr_t base,
|
||||
FAR const struct uart_config_s *config)
|
||||
{
|
||||
uint32_t pin = 0;
|
||||
uint32_t port = 0;
|
||||
@@ -216,7 +218,8 @@ void nrf52_usart_configure(uintptr_t base, const struct uart_config_s *config)
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
void nrf52_usart_disable(uintptr_t base)
|
||||
void nrf52_usart_disable(uintptr_t base,
|
||||
FAR const struct uart_config_s *config)
|
||||
{
|
||||
/* Disable interrupts */
|
||||
|
||||
@@ -228,6 +231,16 @@ void nrf52_usart_disable(uintptr_t base)
|
||||
|
||||
putreg32(0xffffffff, base + NRF52_UART_PSELTXD_OFFSET);
|
||||
putreg32(0xffffffff, base + NRF52_UART_PSELRXD_OFFSET);
|
||||
|
||||
/* Unconfigure GPIO */
|
||||
|
||||
nrf52_gpio_unconfig(config->rxpin);
|
||||
nrf52_gpio_unconfig(config->txpin);
|
||||
|
||||
/* Deatach TWI from GPIO */
|
||||
|
||||
putreg32(UART_PSELTXD_RESET, base + NRF52_UART_PSELTXD_OFFSET);
|
||||
putreg32(UART_PSELRXD_RESET, base + NRF52_UART_PSELRXD_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
@@ -96,7 +96,8 @@ void nrf52_lowsetup(void);
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
void nrf52_usart_configure(uintptr_t base, FAR const struct uart_config_s *config);
|
||||
void nrf52_usart_configure(uintptr_t base,
|
||||
FAR const struct uart_config_s *config);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
@@ -109,7 +110,8 @@ void nrf52_usart_configure(uintptr_t base, FAR const struct uart_config_s *confi
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef HAVE_UART_DEVICE
|
||||
void nrf52_usart_disable(uintptr_t base);
|
||||
void nrf52_usart_disable(uintptr_t base,
|
||||
FAR const struct uart_config_s *config);
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_NRF52_NRF52_LOWPUTC_H */
|
||||
|
||||
@@ -319,13 +319,11 @@ static void nrf52_shutdown(struct uart_dev_s *dev)
|
||||
{
|
||||
struct nrf52_dev_s *priv = (struct nrf52_dev_s *)dev->priv;
|
||||
|
||||
/* TODO: release uart pins */
|
||||
|
||||
/* Disable interrupts */
|
||||
|
||||
/* Reset hardware and disable Rx and Tx */
|
||||
|
||||
nrf52_usart_disable(priv->uartbase);
|
||||
nrf52_usart_disable(priv->uartbase, &priv->config);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
|
||||
Reference in New Issue
Block a user