mpfs/mpfs_corespi: Several speed optimizations to the FPGA driver

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This is a collection of tweaks / optimizations to the driver to limit
CPU usage as well as interrupt processing times.

The changes are as follows:
- setfrequency is now no-op if the frequency does not change. Accessing
  MPFS_SPI_CONTROL requires synchronization to the FIC domain, which
  takes unnecessary time if nothing changes
- load/unload FIFO loops optimized so !buffer, priv->nbits and i==last are
  only tested once (instead of for every word written in loop).
- Disable the RX interrupt only once (again, FIC domain access is slow)
- In case a spurious MPFS_SPI_DATA_RX interrupt arrives, just wipe the
  whole RX FIFO, instead of trying to read it byte-by-byte

...

This commit is contained in:

Ville Juven

2023-09-28 09:36:07 +08:00

committed by Xiang Xiao

parent ded321a515

commit 9be93addea

1 changed files with 59 additions and 84 deletions

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arch/risc-v/src/mpfs/mpfs_corespi.c

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