mirror of
https://github.com/apache/nuttx.git
synced 2026-06-07 09:18:00 +08:00
Merged nuttx/nuttx into master
This commit is contained in:
Pascal Speck
@@ -3130,7 +3130,7 @@
|
||||
point numbers.
|
||||
* lib/stdio/lib_libdtoa.c and lib_libvsprintf.c: Correct some floating
|
||||
point options.
|
||||
* arch/arm/lpc43xx/lpc32_usb0dev.c: Add framework for development of
|
||||
* arch/arm/lpc43xx/lpc43_usb0dev.c: Add framework for development of
|
||||
an USB0, device-side driver for the LPC43XX. The initial check-in,
|
||||
however, is simply for the LPC31xx driver with name changes. The
|
||||
LPC31xx has the same USB IP, but will require some additional initialization
|
||||
@@ -4440,7 +4440,7 @@
|
||||
* binfmt/binfmt_execmodule.c: Here is a place where I forget
|
||||
to update the call to sched_releasetcb() to pass the thread
|
||||
type as the second parameter (2013-03-23).
|
||||
* arch/arm/src/lm, kinetis, lpc32, and nuc1xx: Add kernel build
|
||||
* arch/arm/src/lm, kinetis, lpc43, and nuc1xx: Add kernel build
|
||||
support to all ARMv7-M and ARMv6-M chips. There are no
|
||||
configurations in place to to verify these additions!
|
||||
(2013-03-24).
|
||||
@@ -10964,7 +10964,7 @@
|
||||
(2015-09-09).
|
||||
* configs/nucleo-f303re: Support for the STMicro Nucleo F303RE board
|
||||
from Paul Alexander Patience (2015-09-10).
|
||||
* arch/arm/src/lpc43xx/lpc32_ehci.c and .h: LPC43xx EHCI driver from
|
||||
* arch/arm/src/lpc43xx/lpc43_ehci.c and .h: LPC43xx EHCI driver from
|
||||
Ilya Averyanov (2015-09-10).
|
||||
* ARMv7-M, all "lazy" interrupt stack logic. Assembly instruction
|
||||
that fetches the saved value is incorrect; replace with more
|
||||
@@ -12348,7 +12348,7 @@
|
||||
adds DEBUGASSERT for invalid geometry and additional memory debug
|
||||
logic. Also fixes the dangling pointer on error bug. From Ken
|
||||
Pettit (2016-07-14).
|
||||
* arch/arm/src/lpc32xx: Extend LPC43xx EMC code to support SDRAM on a
|
||||
* arch/arm/src/lpc43xx: Extend LPC43xx EMC code to support SDRAM on a
|
||||
dynamic memory interface. From Vytautas Lukenskas (2016-07-19).
|
||||
* arch/sim/src: Add the simulated QSPI (N25Q) flash to the simulation
|
||||
and modify sim up_spiflash.c to enable it to run with different MTD
|
||||
@@ -12772,6 +12772,9 @@
|
||||
* STM32 DMA2D: fix an error in up_dma2dcreatelayer where an invalid
|
||||
pointer was returned when a certain underlying function failed. From
|
||||
Jens Gräf (2016-10-07).
|
||||
|
||||
7.19 2016-12-26 Gregory Nutt <gnutt@nuttx.org>
|
||||
|
||||
* include/nuttx/fs/nxffs.h: Needs forward reference to struct mtd_dev_s
|
||||
and needs to include stdbool.h (2016-10-09).
|
||||
* STM32F103 Minimum: Note in Kconfig that the board supports buttons.
|
||||
@@ -12844,16 +12847,16 @@
|
||||
(2016-10-19).
|
||||
* libc/locale: Allows c++ code to compile with or without
|
||||
CONFIG_LIBC_LOCALE and will generate a link error if CONFIG_LIBC_LOCALE
|
||||
is not defined and setlocale is referneced. With CONFIG_LIBC_LOCALE
|
||||
is not defined and setlocale is referenced. With CONFIG_LIBC_LOCALE
|
||||
defined setlocale will act as if MB string is not supported and return
|
||||
"C" for POSIX. C and "". From David Sidrane (2016-10-19).
|
||||
* Add vectors for interrupt levels 2-6 (2016-10-20).
|
||||
* strtof: Add strtof() as simply a copy of strtod with types and
|
||||
* Xtensa ESP32: Add vectors for interrupt levels 2-6 (2016-10-20).
|
||||
* strtof(): Add strtof() as simply a copy of strtod with types and
|
||||
limits changed (2016-10-20).
|
||||
* arch/arm/src/stm32v7: Register the watchdog device at the configured
|
||||
device path CONFIG_WATCHDOG_DEVPATH vs. hard-coded /dev/wdt. From Frank
|
||||
Benkert (2016-10-21).
|
||||
* configs/*/defdonf The buttons example was changed to archbuttons. As
|
||||
* configs/*/defconfig: The buttons example was changed to archbuttons. As
|
||||
a result all of the button configurations are broken and need some
|
||||
renaming in the defconfig files. Noted by Frank Berkert (2016-10-21).
|
||||
* configs/stm32f103-minimum: Add support to PWM on STM32F103-Minimum
|
||||
@@ -12909,7 +12912,7 @@
|
||||
found in the F4. From David Sidrane (2016-10-26).
|
||||
* arch/arm/src/stm32f7: stm32f76xx77xx_pinmap.h Missed one. From
|
||||
David Sidrane (2016-10-26).
|
||||
* LPC32xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. From Vytautas
|
||||
* LPC43xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. From Vytautas
|
||||
Lukenskas (2016-10-27).
|
||||
* sched/clock: Correct clock initialization. The correct range for
|
||||
the month is 0-11 but is entered as 1-12 in the .config file
|
||||
@@ -12919,7 +12922,7 @@
|
||||
* sched/Kconfig: Add ranges to START_YEAR, MONTH, and DAY (2016-10-28).
|
||||
* configs/nucleo-f303re: Add STM32 F303RE hello configuration; remove
|
||||
duplicate setting from board.h. From Marc Rechté (2016-10-18).
|
||||
* arch/arm/src/lpc32xx: Restore RS485 mode on serial port open (if
|
||||
* arch/arm/src/lpc43xx: Restore RS485 mode on serial port open (if
|
||||
RS485 is enabled via menuconfig). From Vytautas Lukenskas (2016-10-28).
|
||||
* arch/arm/src/stm32f7: otgdev fixed typo. From David Sidrane
|
||||
(2016-10-28).
|
||||
@@ -12949,14 +12952,12 @@
|
||||
From Paul A. Patience (2016-11-02).
|
||||
* drivers/ and drivers/spi: Fix Kconfig warning. This commit moves the
|
||||
ARCH_HAVE_SPI options outside the check for SPI. Those options don't
|
||||
depend on SPI, and Kconfig files in arch/ enable them even if SPI isn't
|
||||
enabled.
|
||||
|
||||
Sourcing the driver's Kconfig in drivers/Kconfig only if support for
|
||||
the driver is enabled prevents us from defining these ARCH_HAVE options
|
||||
in the driver's Kconfig. We should probably remove the other checks in
|
||||
drivers/Kconfig and check if the drivers are enabled only in their
|
||||
Kconfig. From Paul A. Patience (2016-11-02).
|
||||
depend on SPI, and Kconfig files in arch/ enable them even if SPI
|
||||
isn't enabled. Source the driver's Kconfig in drivers/Kconfig only
|
||||
if support for the driver is enabled prevents us from defining these
|
||||
ARCH_HAVE options in the driver's Kconfig. We should probably remove
|
||||
the other checks in drivers/Kconfig and check if the drivers are
|
||||
enabled only in their Kconfig. From Paul A. Patience (2016-11-02).
|
||||
* Move protoypes for the non-standard include/semaphore.h file to the
|
||||
non-standard include/nuttx/semaphore.h with the other non-standard
|
||||
semaphore interfaces (2016-11-02).
|
||||
@@ -13100,7 +13101,7 @@
|
||||
argument so that there can be additional usage. From Sebastien Lorquet
|
||||
(2016-11-17).
|
||||
* All timer lower half drivers. Port Sebastien's changes to all all
|
||||
other implementations of the timer lower half. Very many just and
|
||||
other implementations of the timer lower half. Many changes and
|
||||
untested. Expect some problems. (2016-11-17).
|
||||
* sched/irq: irq_csection() has a bad assumption in the SMP case. It
|
||||
assumed that the state of certain variables. That was true on entry
|
||||
@@ -13130,5 +13131,348 @@
|
||||
So this change adds locking (via enter_critical section) to wdog
|
||||
expiration logic for the the case if the SMP configuration
|
||||
(2016-11-18).
|
||||
* SAM3/4: Add delay between setting and clearing the endpoint RESET bit
|
||||
in sam_ep_resume(). We need to add a delay between setting and
|
||||
clearing the endpoint reset bit in SAM_UDP_RSTEP. Without the delay the
|
||||
USB controller will (may?) not reset the endpoint. If the endpoint is
|
||||
not being reset, the Data Toggle (DTGLE) bit will not to be cleared
|
||||
which will cause the next transaction to fail if DTGLE is 1. If that
|
||||
happens the host will time-out and reset the bus. Adding this delay
|
||||
may also fix the USBMSC_STALL_RACEWAR in usbmsc_scsi.c, however this
|
||||
has not been verified yet. From Wolfgang Reißnegger (2016-11-18).
|
||||
* SAM3/4: Remove unused 'halted' flag in UDP driver. From Wolfgang
|
||||
Reißnegger (2016-11-18).
|
||||
* SAM3/4: Remove 'stalled' flag in UDP driver. The flag is not necessary.
|
||||
The state of the endpoint can be determined using 'epstate' instead.
|
||||
From Wolfgang Reißnegger (2016-11-18).
|
||||
* USBMSC: Fix length of mode6 sense reply packet. From Wolfgang
|
||||
Reißnegger (2016-11-18).
|
||||
* configs/dk-tm4c129x: Typo fix. From Wolfgang Reißnegger (2016-11-18).
|
||||
* Typo fix in sam_udp.c. From Wolfgang Reißnegger (2016-11-18).
|
||||
* STM32: STM32F303xB and STM32F303xC chips have 4 ADCs. From Paul A.
|
||||
Patience (2016-11-19).
|
||||
* vfork(): Fix a race condition in the SMP case. Existing logic
|
||||
depended on the fact that the child would not run until waitpid was
|
||||
called because the child had the same priority as the parent. BUT
|
||||
in the SMP case that is not true... the child may run immediately on
|
||||
a different CPU (2016-11-19).
|
||||
* arch/: Add option to use low-priority work queue to all Ethernet
|
||||
drivers in arch that support CONFIG_NET_NOINTS (2016-11-19).
|
||||
* sched/clock: Correct calculation for the case of Tickless mode with
|
||||
a 32-bit timer. In that case, the calculation was returning
|
||||
millisecond accuracy. That is not good when the timer accuracy is < 1
|
||||
msec. From Rajan Gill (2016-11-19).
|
||||
* sched/task: task_restart() test not supported on SMP systems. This is
|
||||
not fully implemented (2016-11-19).
|
||||
* This commit adds a new internal interfaces and fixes a problem with
|
||||
three APIs in the SMP configuration. The new internal interface is
|
||||
sched_cpu_pause(tcb). This function will pause a CPU if the task
|
||||
associated with 'tcb' is running on that CPU. This allows a different
|
||||
CPU to modify that OS data stuctures associated with the CPU. When the
|
||||
other CPU is resumed, those modifications can safely take place. The
|
||||
three fixes are to handle cases in the SMP configuration where one CPU
|
||||
does need to make modifications to TCB and data structures on a task
|
||||
that could be running running on another CPU. Those three cases are
|
||||
task_delete(), task_restart(), and execution of signal handles. In
|
||||
all three cases the solutions is basically the same: (1) Call
|
||||
sched_cpu_pause(tcb) to pause the CPU on which the task is running,
|
||||
(2) perform the necessary operations, then (3) call up_cpu_resume() to
|
||||
restart the paused CPU (2016-11-20).
|
||||
* task_restart: Make sure new task starts with pre-emption disabled and
|
||||
not in a critical section (2016-11-21).
|
||||
* Fix a typo in a spinlock macro (2016-11-21).
|
||||
* Spinlocks: Added capability to provide architecture-specific memory
|
||||
barriers. This was for i.MX6 but does not help with the SMP problems.
|
||||
It is still a good feature (2016-11-21).
|
||||
* Remove a assertion condition that appears to rarely cause false-alarm
|
||||
assertions. Teported by Petteri Aimonen (2016-11-21).
|
||||
* The examples/qencoder app was trying to init the encoder by a direct
|
||||
call into the board, cheating in a local header to declare the normally
|
||||
unavailable function prototype. From Sebastien Lorquet (2016-11-22).
|
||||
* configs: All QE encoder files. Last change made timer hard-coded to 3.
|
||||
Make configurable (2016-11-22).
|
||||
* configs: Remove all traces of the no-longer existent ARCHBUTTONS
|
||||
example. Remove all button configurations that depended on the
|
||||
obsoleted ARCHBUTTON example (2016-11-22).
|
||||
* nucleo-l476rg: Add better selection of timer (2016-11-22).
|
||||
* implementation of dumpgpio for stm32l4, was required for pwm debug.
|
||||
From Sebastien Lorquet (2016-11-22).
|
||||
* SMP: Add logic to avoid a deadlock condition when CPU1 is hung waiting
|
||||
for g_cpu_irqlock and CPU0 is waitin for g_cpu_paused (2016-11-22).
|
||||
* Misoc: Add timer driver. From Ramtin Amin (2016-11-22).
|
||||
* Misoc: Add commits and warnings about missing caculation of the timer
|
||||
reload value (2016-11-22).
|
||||
* SAM3/4: Name of method is now setcallback, not sethandler (2016-11-22).
|
||||
* sam4s-xplained-pro/nsh: Configuration uses old, improper timer interface.
|
||||
CONFIG_TIMER disabled in configuration. (2016-11-22).
|
||||
* sam4s-xplained-pro: Remove obsolete timer initialization logic
|
||||
(2016-11-22).
|
||||
* Misoc LM32: Make system timer configurable via CONFIG_USEC_PER_TICK.
|
||||
From Ramtin Amin (2016-11-23).
|
||||
* LPC43xx: Add timer driver; configs/bambino-200e: Add support for timer
|
||||
driver. From Alan Carvalho de Assis (2016-11-23).
|
||||
* SMP: Fix backward condition in test (2016-11-23).
|
||||
* ARMv7-A SMP: Add a little logic to signal handling (2016-11-24).
|
||||
* Misoc LM32: Add signal handling logic. From Ramtin Amin (2016-11-24).
|
||||
* SMP: Add spin_trylock(). Use this in conditions where other CPUs need
|
||||
to stopped but we cannot call enter_critical_section (2016-11-24).
|
||||
* Fix for F1 RTC Clock, tested on F103. From Maciej Wójcik (2016-11-25).
|
||||
* SMP: Fix yet another potential deadlock (2016-11-25).
|
||||
* Enable CONFIG_RTC in the hymini-stm32v/nsh2 (kitchensink) config.
|
||||
From Maciej Wójcik (2016-11-26).
|
||||
* This adds support for keeping i.MX6 inter-processor communication data
|
||||
in a non-cached address region (2016-11-26).
|
||||
* i.MX6: Disable non-cached region support. Add SCU register definitions
|
||||
(2016-11-26).
|
||||
* i.MX6: Add some controls to enable SMP cache coherency in SMP mode
|
||||
(2016-11-26).
|
||||
* ARMv7-A: Fix some SCU SMP logic (2016-11-26).
|
||||
* ARMv7-A/i.MX6: Modify handling of the SMP cache coherency
|
||||
configuration so that it is identical to the steps from the TRM.
|
||||
Makes no differenct, however (2016-11-27).
|
||||
* The Smoothie project needs to compile C++ inside config/boardname/src/
|
||||
to use with High Priority Interruption, then I modified the board
|
||||
configs Makefile to support it. It works fine for the first time
|
||||
compilation, but if we execute "touch config/boardname/src/Pin.cxx"
|
||||
and execute "make" it will not detect that Pin.cxx was modified. I
|
||||
think there is some other place I should modify, but I didn't find
|
||||
it. From Alan Carvalho de Assis (2016-11-27).
|
||||
* ARMv7-A/i.MX6 SMP: Move SMP coherent cache setup to earlier in
|
||||
initialization of CPUn, n>0 (2016-11-27).
|
||||
* ARMv7 GIC: SGIs are non-maskable but go through the same path as other,
|
||||
maskable interrupts. Added logic to serialize SGI processing when
|
||||
necessary (2016-11-27).
|
||||
* sched_note: Extend OS instrumentation to include some SMP events
|
||||
(2016-11-27).
|
||||
* sched_note: Add spinlock instrumentation; In SMP configurations,
|
||||
select to log only notes from certain CPUs (2016-11-28).
|
||||
* Misoc LM3: Add Misoc Ethernet driver. Integrate network support into
|
||||
configs/misoc/hello. Remove configs/misoc/include/generated directory.
|
||||
I suppose the the intent now is that this is a symbolic link? DANGER!
|
||||
This means that you cannot compile this code with first generating
|
||||
these files a providing a symbolic link to this location! From Ramtin
|
||||
Amin (2016-11-28).
|
||||
* Add tools/showsize.sh (2016-11-28).
|
||||
* configs/misoc: Add a sample directory containing generated sources.
|
||||
This is really only useful for performing test builds. You really
|
||||
must generate the Misoc architecture for a real-life build. From
|
||||
Ramtin Amin (2016-11-28).
|
||||
* sched_note: Permit spinlock and critical section notes in in-memory
|
||||
buffer iff sched_not_get() interfaces is disabled (2016-11-28).
|
||||
* STM32 DAC: Fix shift value whenever there are is a DAC2 and, hence,
|
||||
up to three interfaces. From Marc Rechté (2016-11-29).
|
||||
* Back out a debug change that was included in commit (2016-11-29).
|
||||
* i.MX6: Don't output the alphabet if CONFIG_DEBUG_FEATURES is not set
|
||||
(2016-11-29).
|
||||
* Misoc LM32: Add logic to flush/invalidate caches. From Ramtin Amin
|
||||
(2016-11-29).
|
||||
* drivers/net/: Adapt all Ethernet drivers to work as though
|
||||
CONFIG_NET_MULTIBUFFER were set. Remove all references to
|
||||
CONFIG_NET_MULTIBUFFER (2016-11-29).
|
||||
* stm32_otghshost: if STM32F446 increase number of channels to 16. From
|
||||
Janne Rosberg (2016-11-30).
|
||||
* usbhost_composite: fix end offset in usbhost_copyinterface(). From
|
||||
Janne Rosberg (2016-11-30).
|
||||
* usbhost_cdcacm: add CDC_SUBCLASS_ACM and CDC_PROTO_ATM to supported
|
||||
class and proto. From Janne Rosberg (2016-11-30).
|
||||
* LPC43 SD/MMC: Correct some git definitions on SMMC control register
|
||||
in lpc43_sdmmc.h. From Alan Carvalho de Assis (2016-11-30).
|
||||
* STM32L4: Correct USART1/2 definitions. Use default mbed UART4
|
||||
settings. From Sebastien Lorquet (2016-12-01).
|
||||
* boardctl: Add new boardctl() command ,BOARDIOC_NX_START, to start the
|
||||
NX server as a kernel thread (2016-12-01).
|
||||
* GPDMA driver for the LPC43xx. The GPDMA block is basically the same
|
||||
as the LPC17xx. Only the clock configuration is different and LPC43xx
|
||||
has four different DMA request sources, where LPC17xx has only two.
|
||||
From Alan Carvalho de Assis (2016-12-01).
|
||||
* Remove RGMP and RGMP drivers (2016-12-02).
|
||||
* i.MX6: Add an untested SPI driver taken directly from the i.MX1 port
|
||||
(2016-12-02).
|
||||
* Eliminate CONFIG_NO_NOINTS. There is no longer any support for
|
||||
interrupt level processing of the network stack. Lots of files changed
|
||||
-> lots of testing needed (2016-12-03).
|
||||
* Fix DEBUGASSERT() in group_signal.c. From Masayuki Ishikawa
|
||||
(2016-12-04).
|
||||
* Add support for the SAM5CMP-DB board. From Masayuki Ishikawa
|
||||
(2016-12-04).
|
||||
* SAM3/4: Add SMP support for the dual-core SAM4CM. From Masayuki
|
||||
Ishikawa (2016-12-04).
|
||||
* C Library: Allow option to enable IP address conversions even when the
|
||||
IP address family is not supported (2016-12-04).
|
||||
* SSD1306: Fix errors in SPI mode configuration. From Gong Darcy
|
||||
(2016-12-04).
|
||||
* SAMA5 does not build when executing from SDRAM before board
|
||||
frequencies are not constant. Rather, the bootloader configures the
|
||||
clocking and we must derive the clocking from the MCK left by the
|
||||
bootloader. This means lots more computations. This is untested on
|
||||
initial commit because I don't have a good PWM test setup right now
|
||||
(2016-12-04).
|
||||
* Olimex-LPC1766-STK: Enable procfs in NSH configuration. Automount
|
||||
/proc on startup (2016-12-05).
|
||||
* SAM4CMP-DB: Add hooks to auto-mount the procfs file system on startup
|
||||
in board bring-up logic (2016-12-05).
|
||||
* Remove all references to BOARDIOC_PWMSETUP and board_pwm_setup()
|
||||
(2016-12-05).
|
||||
* Remove all references to BOARDIOC_ADCSETUP and board_adc_setup()
|
||||
(2016-12-05).
|
||||
* Added Timers 2-5 and control of SAI and I2S PLLs. From David Sidrane
|
||||
(2016-12-05).
|
||||
* Added support for stmf469 SAI and I2S PLL configuration and STM446
|
||||
fixes. From David Sidrane (2016-12-05).
|
||||
* Expanded otgfs support to stm32F469 and stm32f446. Added missing bits
|
||||
definitions, Used stm32F469 and stm32f446 bit definitions, Removed
|
||||
unsed header file. From David Sidrane (2016-12-05).
|
||||
* Remove BOARDIOC_CAN_INITIALIZE. CAN initialization is now done in the
|
||||
board initialization logic just like every other device driver
|
||||
(2016-12-06).
|
||||
* STM32F7: Allow the config to override the clock edge setting. From
|
||||
David Sidrane (2016-12-06).
|
||||
* For Cortex-A9, should also set ACTLR.FW in SMP mode to enble TLB and
|
||||
cache broadcasts. Does not fix SMP cache problem (2016-12-07).
|
||||
* sched notes: Add additional note to see if/when CPU is started in SMP
|
||||
mode (2016-12-07).
|
||||
* EFM32: Fix a compilation error. From Pierre-noel Bouteville
|
||||
(2016-12-07).
|
||||
* pthreads: Add pthread_cleanup_push() and pthread_cleanup_pop()
|
||||
(2016-12-08).
|
||||
* BUGFIX:STM32F427 was rebooting. Over reached family. From David
|
||||
Sidrane (2016-12-08).
|
||||
* Add pthread_setcanceltype() and pthread_testcancel() (2016-12-09).
|
||||
* Added STM32F469 RAM size and deliberated STM32F446 size. From David
|
||||
Sidrane (2016-12-09).
|
||||
* Typo in stm32f76xx77xx_pinmap.h edited online with Bitbucket. From
|
||||
David Sidrane (2016-12-09).
|
||||
* stm32_allocateheap.c edited online with Bitbucket. From David Sidrane
|
||||
(2016-12-09).
|
||||
* LPC43xx SD card: Correct pin configuration options needed for SD card
|
||||
pins. From Alan Carvalho de Assis (2016-12-09).
|
||||
* pthread_mutex_destroy(): Fix an error in destroying a mutex which can
|
||||
occur after a pthread has been canceled while holding the mutex
|
||||
(2016-12-09).
|
||||
* Add support for cancellation points (2016-12-09).
|
||||
* Forgot to add some files in the last commit (2016-12-10).
|
||||
* Correct some default font IDs. From Pierre-Noel Bouteville
|
||||
(2016-12-10).
|
||||
* task_delete() now obeys all cancellation point semantics (2016-12-10).
|
||||
* Add task_setcancelstate(), task_setcanceltype(), and task_testcancel().
|
||||
These are non-standard interfaces analogous to the correponding pthread_
|
||||
interfaces that provide cancellation controls for tasks (2016-12-10).
|
||||
* i.MX6 interrupt handling: Additional logic needed to handle nested
|
||||
interrupts when an interrupt stack is used (2016-12-13).
|
||||
* SAMV7 MCAN: Prevent Interrupt-Flooding of ACKE when not connected to
|
||||
CAN-BUS. An Acknowledge-Error will occur every time no other CAN Node
|
||||
acknowledges the message sent. This will also occur if the device is
|
||||
not connected to the can-bus. The CAN-Standard declares, that the Chip
|
||||
has to retry a given message as long as it is not sent successfully (or
|
||||
it is not cancelled by the application). Every time the chip tries to
|
||||
resend the message an Acknowledge-Error-Interrupt is generated. At high
|
||||
baud rates this can lead in extremely high CPU load just for handling
|
||||
the interrupts (and possibly the error handling in the application). To
|
||||
prevent this Interrupt-Flooding we disable the ACKE once it is seen as
|
||||
long we didn't transfer at least one message successfully. From Frank
|
||||
Benkert (2016-12-13).
|
||||
* i.MX6: Remove non-cached, inter-cpu memory region. Not a useful
|
||||
concept (2016-12-13).
|
||||
* minnsh Configurations: Remove minnsh configurations and support logic:
|
||||
up_getc() and lowinstream. This was an interesting exercise to see
|
||||
just how small you could get NuttX, but otherwise it was not useful:
|
||||
(1) the NSH code violated the OS interface layer by callup up_getc and
|
||||
up_putc directly, and (2) while waiting for character input, NSH would
|
||||
call up_getc() which would hog all of the CPU. Not a reasonable
|
||||
solution other than as a proof of concept (2016-12-13).
|
||||
* Calypso Boards: Remove all Calypso board configurations (2016-12-13).
|
||||
* Calypso: Remove Calypso architecture support and support for Calypso
|
||||
SERCOMM driver (2016-12-13).
|
||||
* ESP32 core v2: Two changes (1) flushes the UART TX buffer in the esp32
|
||||
serial shutdown routine. The ROM bootloader does not flush the FIFO
|
||||
before handing over to user code, so some of this output is not
|
||||
currently seen when the UART is reconfigured in early stages of
|
||||
startup. And changes the openocd config file's default flash voltage
|
||||
from 1.8V to 3.3V. This is not necessary right now, but may save some
|
||||
hard-to-debug moments down the track (3.3V-only flash running at 1.8V
|
||||
often half-works and does weird things...). From Angus Gratton
|
||||
(2016-12-14).
|
||||
* Xtensa ESP32: Add missing ENTRY() and RET() macros in C callable
|
||||
assembly language. At one time I though the that the ESP32 support the
|
||||
CALL0 ABI. I was mistaken so there may be a few more like this
|
||||
(2016-12-14).
|
||||
* Xtensa ESP32: Fix a couple of bugs associated with handling of CPU
|
||||
interrupts (2016-12-14).
|
||||
* Xtensa ESP32: Fix several build-related issues associated with vector
|
||||
section (2016-12-15).
|
||||
* Xtensa ESP32: Fix missing CALL0 ABI condition (2016-12-15).
|
||||
* Xtensa EPS32: Make sure that all C callable assembly functions includes
|
||||
ENTRY prologue and RET epilogue (2016-12-15).
|
||||
* Xtensa ESP32: Fix windowspill register handling + Use r6, not r2 when
|
||||
passing paramters with call4 (2016-12-16).
|
||||
* Xtensa ESP32: Use r6, not r2 when passing paramters with call4
|
||||
(2016-12-16).
|
||||
* Xtensa ESP32: Correct a logic problem the prevented dumping the IDLE
|
||||
thread's stack on an assertion (2016-12-16).
|
||||
* Xtensa ESP32: Fix some missing SMP logic (2016-12-16).
|
||||
* Xtensa ESP32: Basically a redesign of the interrupt dispatch logic
|
||||
(2016-12-16).
|
||||
* Xtensa ESP32: Level 1 interrupts should return via RFE (2016-12-17).
|
||||
* Xtensa ESP32: One register getting clobber on context save (2016-12-17).
|
||||
* STM32 F7: Fix some STM32F7 copy paste errors. From David Sidrane
|
||||
(2016-12-17).
|
||||
* CDC/ACM Device Class: uart_ops_s portion of cdcacm will not be
|
||||
initalized with correct functions if CONFIG_SERIAL_DMA is lit
|
||||
(2016-12-17).
|
||||
* Xtensa ESP32: Using wrong register to disable interrupts (2016-12-17).
|
||||
* Xtensa ESP32: Fix clobbered a9 in co-processor context save/restore
|
||||
(2016-12-17).
|
||||
* Xtensa ESP32: Need to clone some logic for synchronous context switch.
|
||||
Window spill logic in the conmon restores logic is inappropriate in
|
||||
this context (2016-12-17).
|
||||
* sscanf(): Add scansets to the scanf function. Enabled
|
||||
CONFIG_LIBC_SCANSET option. From Aleksandr Vyhovanec (2016-12-17).
|
||||
* Xtensa ESP32: Fix context save logic when called in window ABI
|
||||
configuration. Add an IDLE stack. Don't depend on the mystery stack
|
||||
received from the bootloader (2016-12-18).
|
||||
* Xtensa ESP32: Need to spill registers to memory as the last dying
|
||||
action before switching to a new thread (2016-12-18).
|
||||
* ESP32 Serial: Add logic to prevent infinite loops in interrupt handler
|
||||
(2016-12-18).
|
||||
* Xtensa ESP32: Automatically mount /proc at start-up (2016-12-19).
|
||||
* Xtensa ESP32: Corrects timer initialization and timer input frequency
|
||||
(2016-12-19).
|
||||
* Tiva PWM: Support PWM_PULSECOUNT feature for TI tiva. From Young.Mu
|
||||
(2016-12-20).
|
||||
* Xtensa ESP32: Missing prologue/epilogue macros on C callable function
|
||||
(2016-12-20).
|
||||
* Xtensa ESP32: Update APP CPU startup logic to match current Expressif
|
||||
example code. Fix errors APP CPU startup (2016-12-20).
|
||||
* fs/procfs: Fix procfs status for SMP case (2016-12-20).
|
||||
* Xtensa ESP32: Clock frequency is different if running from IRAM or is
|
||||
booting from FLASH. This is a booltloader issue (2016-12-20).
|
||||
* Xtensa ESP32: Basic port is function in both single CPU and dual CPU
|
||||
SMP configurations. There is an NSH configuration for each CPU
|
||||
configuration (2016-12-21).
|
||||
* STM32 F4: Merge in support for the Olimex STM32 P407 board (2016-12-21).
|
||||
* Xtensa ESP32: Add an OS test to verify the port (2016-12-22).
|
||||
* Xtensa ESP32: Corrects a problem with dispatching to signal handlers:
|
||||
Cannot vector directly to the signal handling function as in other ABIs
|
||||
under the Xtensa Window ABI. In that case, we need to go through a
|
||||
tiny hook when performs the correct window call (call4) otherwise
|
||||
registers will be scrambled in the signal handler (2016-12-22).
|
||||
* SAMV7 CAN: Make delete_filter functions more robust. From Frank
|
||||
Benkert (2016-12-23).
|
||||
* Xtensa ESP32: Add stack checking logic (2016-12-23).
|
||||
* sched note: record ID enumeration now results on constant values; ID
|
||||
values do not change with configuration. This makes writing
|
||||
post-processing software much easier (2016-12-24).
|
||||
* STM32 F3: Forgot to update chip.h for STM32F303x[BC]'s 4 ADCs
|
||||
(2016-12-24).
|
||||
* STM32 F4: Allow dma in 1 bit mode in STM32F4xxx. From David Sidrane
|
||||
(2016-12-24).
|
||||
* termios.h: Fix CRTSCTS define to include input and output flow.
|
||||
From Lorenz Meier (2016-12-26).
|
||||
* SMP: Enforce this rule: Tasks which are normally restored when
|
||||
sched_unlock() is called must remain pending (1) if we are in a
|
||||
critical section, i.e., g_cpu_irqlock is locked , or (2) other CPUs
|
||||
still have pre-emption disabled, i.e., g_cpu_schedlock is locked. In
|
||||
those cases, the release of the pending tasks must be deferred until
|
||||
those conditions are met (2016-12-26).
|
||||
|
||||
7.19 2016-xx-xx Gregory Nutt <gnutt@nuttx.org>
|
||||
7.20 2017-xx-xx Gregory Nutt <gnutt@nuttx.org>
|
||||
|
||||
+118
-70
@@ -8,7 +8,7 @@
|
||||
<tr align="center" bgcolor="#e4e4e4">
|
||||
<td>
|
||||
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
|
||||
<p>Last Updated: October 8, 2016</p>
|
||||
<p>Last Updated: December 26, 2016</p>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
@@ -317,7 +317,7 @@
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<li>POSIX/ANSI-like task controls, named message queues, counting semaphores, clocks/timers, signals, pthreads, environment variables, filesystem.</li>
|
||||
<li>POSIX/ANSI-like task controls, named message queues, counting semaphores, clocks/timers, signals, pthreads, cancellation points, environment variables, filesystem.</li>
|
||||
</p>
|
||||
</tr>
|
||||
|
||||
@@ -1339,11 +1339,11 @@
|
||||
<h2>Released Versions</h2>
|
||||
<p>
|
||||
In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available.
|
||||
The current release is NuttX 7.18.
|
||||
NuttX 7.18 is the 118<sup>th</sup> release of NuttX.
|
||||
It was released on October 8, 2016, and is available for download from the
|
||||
The current release is NuttX 7.19.
|
||||
NuttX 7.19 is the 119<sup>th</sup> release of NuttX.
|
||||
It was released on December 26, 2016, and is available for download from the
|
||||
<a href="https://bitbucket.org/nuttx/nuttx/downloads/">Bitbucket.org</a> website.
|
||||
Note that the release consists of two tarballs: <code>nuttx-7.18.tar.gz</code> and <code>apps-7.18.tar.gz</code>.
|
||||
Note that the release consists of two tarballs: <code>nuttx-7.19.tar.gz</code> and <code>apps-7.19.tar.gz</code>.
|
||||
Both may be needed (see the top-level <code>nuttx/README.txt</code> file for build information).
|
||||
</p>
|
||||
|
||||
@@ -1352,7 +1352,7 @@
|
||||
<ul>
|
||||
<li><b>nuttx</b>.
|
||||
<ul><p>
|
||||
Release notes for NuttX 7.18 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
|
||||
Release notes for NuttX 7.19 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
|
||||
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>.
|
||||
The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ChangeLog" target="_blank">Bitbucket GIT</a>.
|
||||
The ChangeLog for the current release is at the bottom of that file.
|
||||
@@ -1360,7 +1360,7 @@
|
||||
</li></ul>
|
||||
<li><b>apps</b>.
|
||||
<ul><p>
|
||||
Release notes for NuttX 7.18 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
|
||||
Release notes for NuttX 7.19 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
|
||||
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>
|
||||
The ChangeLog for the all releases of <code>apps/</code> is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/apps/src/master/ChangeLog.txt" target="_blank">Bitbucket GIT</a>.
|
||||
The ChangeLog for the current release is at the bottom of that file.
|
||||
@@ -1408,7 +1408,7 @@
|
||||
<li><a href="#linuxusermode">Linux/Cygwin user mode simulation</a> (1)</li>
|
||||
<li>ARM
|
||||
<ul>
|
||||
<li><a href="#arm7tdmi">ARM7TDMI</b></a> (5)</li>
|
||||
<li><a href="#arm7tdmi">ARM7TDMI</b></a> (4)</li>
|
||||
<li><a href="#arm920t">ARM920T</a> (1)</li>
|
||||
<li><a href="#arm926ejs">ARM926EJS</a> (4)</li>
|
||||
<li><a href="#armv4">Other ARMv4</a> (1)</li>
|
||||
@@ -1418,7 +1418,7 @@
|
||||
<li><a href="#armcortexr4">ARM Cortex-R4</a> (1)</li>
|
||||
<li><a href="#armcortexm0">ARM Cortex-M0/M0+</a> (7)</li>
|
||||
<li><a href="#armcortexm3">ARM Cortex-M3</a> (35)</li>
|
||||
<li><a href="#armcortexm4">ARM Cortex-M4</a> (31)</li>
|
||||
<li><a href="#armcortexm4">ARM Cortex-M4</a> (32)</li>
|
||||
<li><a href="#armcortexm7">ARM Cortex-M7</a> (7)</li>
|
||||
</ul>
|
||||
<li>Atmel AVR
|
||||
@@ -1445,6 +1445,10 @@
|
||||
<li><a href="#pic32mzmips">PIC32MZ</a> (MIPS M14K) (1)</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Misoc
|
||||
<ul>
|
||||
<li><a href="#misoclm32">LM32</a> (1)</li>
|
||||
</ul>
|
||||
<li>Renesas/Hitachi:
|
||||
<ul>
|
||||
<li><a href="#superh">Renesas/Hitachi SuperH</a> (1/2)</li>
|
||||
@@ -1453,6 +1457,15 @@
|
||||
</li>
|
||||
</td>
|
||||
<td bgcolor="#e4e4e4" valign="top" width="33%">
|
||||
<li><a href="#riscv">RISC-V</a> (1)
|
||||
<ul>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Xtensa LX6:
|
||||
<ul>
|
||||
<li><a href="#esp32">ESP32</a> (1)</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>ZiLOG
|
||||
<ul>
|
||||
<li><a href="#zilogz16f">ZiLOG ZNEO Z16F</a> (2)</li>
|
||||
@@ -1502,6 +1515,11 @@
|
||||
<li><a href="#at91sama5d4">Atmel SAMA5D4</a> <small>(ARM Cortex-A5)</small></li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Expressif
|
||||
<ul>
|
||||
<li><a href="#esp32">ESP32</a> <small>(Dual Xtensa LX6)</small</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Freescale
|
||||
<ul>
|
||||
<li><a href="#m68hcs12">M68HCS12</a></li>
|
||||
@@ -1533,13 +1551,13 @@
|
||||
<li><a href="#pic32mzec">PIC32MZEC Family</a> <small>(MIPS32 M14K)</small></li>
|
||||
</ul>
|
||||
</li>
|
||||
</td>
|
||||
<td bgcolor="#e4e4e4" valign="top" width="33%">
|
||||
<li>Moxa
|
||||
<ul>
|
||||
<li><a href="#moxart">Moxa NP51x0</a> <small>(ARMv4)</small></li>
|
||||
</ul>
|
||||
</li>
|
||||
</td>
|
||||
<td bgcolor="#e4e4e4" valign="top" width="33%">
|
||||
<li>nuvoTon
|
||||
<ul>
|
||||
<li><a href="#nuvotonnu120">nuvoTon NUC120</a> <small>(ARM Cortex-M0)</small></li>
|
||||
@@ -1604,7 +1622,6 @@
|
||||
<li>Texas Instruments (some formerly Luminary)
|
||||
<ul>
|
||||
<li><a href="#tms320c5471">TI TMS320-C5471</a> <small>(ARM7TDMI)</small></li>
|
||||
<li><a href="#ticalypso">TI Calypso</a> <small>(ARM7TDMI)</small></li>
|
||||
<li><a href="#titms320dm320">TI TMS320-DM320</a> <small>(ARM9E6JS)</small></li>
|
||||
<li><a href="#tilms6432">TI/Stellaris LM3S6432</a> <small>(ARM Cortex-M3)</small></li>
|
||||
<li><a href="#tilm3s6432s2e">TI/Stellaris LM3S6432S2E</a> <small>(ARM Cortex-M3)</small></li>
|
||||
@@ -1695,31 +1712,6 @@
|
||||
<td><br></td>
|
||||
<td><hr></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<a name="ticalypso"><b>TI Calypso</b>.</a>
|
||||
This port supports the TI "Calypso" MCU used in various cell phones (and, in particular,
|
||||
by the <a href="http://bb.osmocom.org/trac/">Osmocom-bb project</a>).
|
||||
Like the c5471, NuttX operates on the ARM7 of this dual core processor.
|
||||
Board support is available for the Motorola C139, C155 and W220 phones and for the Pirelli DP-L10 phone.
|
||||
</p>
|
||||
<ul>
|
||||
<p>
|
||||
<b>STATUS:</b>
|
||||
This port was contributed by Denis Carilki and includes the work of Denis Carikli, Alan Carvalho de Assis, and Stefan Richter.
|
||||
Calypso support first appeared in NuttX-6.17 with LCD drivers.
|
||||
Support for the Calypso keyboard was added in NuttX-6.24 by Denis Carilki.
|
||||
Refer to the NuttX board README files for the <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/compal_e88/README.txt" target="_blank">Compal E88</a>, <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/compal_e99/README.txt" target="_blank">Compal E99</a> and <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pirelli_dpl10/README.txt" target="_blank">Pirelli DP-L10</a> phones for further information.
|
||||
</p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td><hr></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
@@ -3160,7 +3152,7 @@ nsh>
|
||||
<li>
|
||||
<p>
|
||||
<b>Kamami STM32 Butterfly 2</b>
|
||||
Support for the <a href="https://kamami.pl/zestawy-uruchomieniowe-stm32/178507-stm32butterfly2.html">Kamami STM32 Butterfly 2</a> was contributed by Michał Łyszczek in NuttX-7/18. That port features the STMicro STM32F107VC MCU.
|
||||
Support for the <a href="https://kamami.pl/zestawy-uruchomieniowe-stm32/178507-stm32butterfly2.html">Kamami STM32 Butterfly 2</a> was contributed by Michał Łyszczek in NuttX-7.18. That port features the STMicro STM32F107VC MCU.
|
||||
</p>
|
||||
<p>
|
||||
<b>STATUS:</b>
|
||||
@@ -3743,11 +3735,14 @@ nsh>
|
||||
<li><b>NuttX-7.3</b>
|
||||
Support for the Olimex STM32 H405 board was added in NuttX-7.3.
|
||||
</li>
|
||||
<li>
|
||||
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/stm3240g-eval/README.txt" target="_blank">README</a> file for further information.
|
||||
<li><b>NuttX-7.19</b>
|
||||
Support for the Olimex STM32 P405 board was added in NuttX-7.19.
|
||||
</li>
|
||||
</ul>
|
||||
</p>
|
||||
<p>
|
||||
Refer to the STM3240G-EVAL board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/stm3240g-eval/README.txt" target="_blank">README</a> file for further information.
|
||||
</p>
|
||||
<p>
|
||||
<b>STMicro STM32F4-Discovery</b>.
|
||||
This port uses the STMicro STM32F4-Discovery board featuring the STM32F407VGT6 MCU.
|
||||
@@ -3817,6 +3812,11 @@ nsh>
|
||||
Networking configurations were added in NuttX-7.18.
|
||||
See the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-e407/README.txt" target="_blank">README</a> file for further information about the NuttX port.
|
||||
</p>
|
||||
<p>
|
||||
<b>Olimex STM32 P407</b>.
|
||||
Support for the Olimex STM32 P407 development board appeared in NuttX-7.19.
|
||||
See the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-p407/README.txt" target="_blank">README</a> file for further information about the NuttX port.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@@ -4332,7 +4332,7 @@ Mem: 29232 5920 23312 23312
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<a name="at91sam4c"><b>Atmel SAM4C</b>.</a>
|
||||
<a name="at91sam4c"><b>Atmel SAM4CM</b>.</a>
|
||||
General architectural support was provided for SAM4CM family in NuttX 7.3
|
||||
This was <i>architecture-only</i> support, meaning that support for the boards with these chips is available, but no support for any publicly available boards was included.
|
||||
The SAM4CM port should be compatible with most of the SAM3/4 drivers (like HSMCI, DMAC, etc.) but those have not be verified on hardware as of this writing.
|
||||
@@ -4340,6 +4340,18 @@ Mem: 29232 5920 23312 23312
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>Atmel SAM4CMP-DB</b>.
|
||||
Support for the SAM4CMP-DB board was contributed to NuttX by Masayuki Ishikawa in NuttX-7.19.
|
||||
The SAM4CM is a dual-CPU part and SMP was included for the ARMv7-M and SAM3/4 families.
|
||||
The SAM4CMP-DB board support includes an NSH configuration that operates in an SMP configuration.
|
||||
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/sam4cmp-db/README.txt" target="_blank">README</a> file for further information.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td><hr></td>
|
||||
@@ -4856,6 +4868,23 @@ Mem: 29232 5920 23312 23312
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
<a name="misoclm32"><b>Misoc LM32</b>.</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>Misoc LM32 Architectural Support</b>.
|
||||
Architectural support for the Misoc LM32 was contributed by Ramtin Amin in NuttX 7.19. Driver support is basic in this initial release: Serial, Timer, and Ethernet. "Board" support is a available for developing with Misoc LM32 under Qemu or on your custom FPGA.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
@@ -4920,34 +4949,6 @@ Mem: 29232 5920 23312 23312
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td><hr></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>RGMP</b>.
|
||||
RGMP stands for RTOS and GPOS on Multi-Processor.
|
||||
RGMP is a project for running GPOS and RTOS simultaneously on multi-processor platforms
|
||||
You can port your favorite RTOS to RGMP together with an unmodified Linux to form a hybrid operating system.
|
||||
This makes your application able to use both RTOS and GPOS features.
|
||||
</p>
|
||||
<p>
|
||||
See the <a href="http://rgmp.sourceforge.net/wiki/index.php/Main_Page">RGMP Wiki</a> for further information about RGMP.
|
||||
</p>
|
||||
<ul>
|
||||
<p>
|
||||
<b>STATUS:</b>
|
||||
This initial port of NuttX to RGMP was provided in NuttX-6.3.
|
||||
This initial RGP port provides only minimal driver support and does not use the native NuttX interrupt system.
|
||||
This is a great, stable starting point for anyone interest in working with NuttX under RGMP!
|
||||
Refer to the NuttX <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/rgmp/README.txt" target="_blank">README</a> file for further information.
|
||||
</p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
@@ -5250,6 +5251,53 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1);
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
<a name="riscv"><b>RISC-V</b>.</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>RISC-V Architectural Support</b>.
|
||||
Basic support for the RISC-V architecture was contributed by Ken Pettit in NuttX-7.19. The initial release is <i>thin</i> but a great starting point for anyone interested in RISC-V development with NuttX.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
<a name="esp32"><b>ESP32 <small>(Dual Xtensa LX6)</small></b>.</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>Xtensa LX6 ESP32 Architectural Support</b>.
|
||||
Basic architectural support for Xtensa LX6 processors and the port for the Expressif ESP32 were added in NuttX-7.19.
|
||||
The basic ESP32 port is function in both single CPU and dual CPU SMP configurations.
|
||||
</p>
|
||||
<p>
|
||||
<b>Expressif ESP32 Core v2 Board</b>
|
||||
The NuttX release includes support for Expressif ESP32 Core v2 board.
|
||||
There is an NSH configuration for each CPU configuration and an OS test configuration for verificatin of the port.
|
||||
</p>
|
||||
<p>
|
||||
<b>STATUS</b>.
|
||||
ESP32 support in NuttX-7.19 is functional, but very preliminary.
|
||||
There is little yet in the way of device driver support.
|
||||
Outstanding issues include missing clock configuration logic, missing partition tables to support correct configuration from FLASH, and some serial driver pin configuration issues.
|
||||
The configuration is usable despite these limitations.
|
||||
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/esp32-core/README.txt" target="_blank">README</a> file for further information.
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
|
||||
@@ -1008,10 +1008,6 @@ drivers/
|
||||
| |-- Kconfig
|
||||
| |-- Make.defs
|
||||
| `-- <i>(Common sensor driver source files)</i>
|
||||
|-- sercomm/
|
||||
| |-- Kconfig
|
||||
| |-- Make.defs
|
||||
| `-- <i>(Files for the Calypso SERCOMM driver)</i>
|
||||
|-- serial/
|
||||
| |-- Kconfig
|
||||
| |-- Make.defs
|
||||
@@ -1170,8 +1166,6 @@ include/
|
||||
| | `-- <i>(Power management header files)</i>
|
||||
| |-sensors/
|
||||
| | `-- <i>(Sensor device driver header files)</i>
|
||||
| |-sercomm/
|
||||
| | `-- <i>(SERCOMM driver header files)</i>
|
||||
| |-serial/
|
||||
| | `-- <i>(Serial driver header files)</i>
|
||||
| |-spi/
|
||||
|
||||
+601
-179
File diff suppressed because it is too large
Load Diff
@@ -8,7 +8,7 @@
|
||||
<tr align="center" bgcolor="#e4e4e4">
|
||||
<td>
|
||||
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
|
||||
<p>Last Updated: November 14, 2016</p>
|
||||
<p>Last Updated: December 21, 2016</p>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
@@ -70,12 +70,6 @@ nuttx/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/cc3200-launchpad/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- cloudctrl/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/cloudctrl/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- compal_e86/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/compal_e86/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- compal_e88/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/compal_e88/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- compal_e99/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/compal_e99/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- demo9s12ne64/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/demo9s12ne64/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- dk-tm4c129x/
|
||||
@@ -183,6 +177,8 @@ nuttx/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-p107/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- olimex-stm32-p207/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-p207/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- olimex-stm32-p407/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-p407/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- olimex-strp711/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-strp711/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- open1788/
|
||||
@@ -199,12 +195,8 @@ nuttx/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pic32mx7mmb/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- pic32mz-starterkit/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pic32mz-starterkit/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- pirelli_dpl10/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pirelli_dpl10/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- qemu-i486/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/qemu-i486/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- rgmp/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/rgmp/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- sabre-6quad/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/sabre-6quad/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- sama5d2-xult/
|
||||
@@ -223,6 +215,8 @@ nuttx/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/saml21-xplained/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- sam3u-ek/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/sam3u-ek/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- sam4cmp-db
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/sam4cmp-d/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- sam4e-ek/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/sam4e-ek/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- sam4l-xplained/
|
||||
@@ -328,8 +322,6 @@ nuttx/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/mtd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- sensors/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/sensors/README.txt" target="_blank">README.txt</a>
|
||||
| |- sercomm/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/sercomm/README.txt" target="_blank">README.txt</a>
|
||||
| |- syslog/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/syslog/README.txt" target="_blank">README.txt</a>
|
||||
| `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
|
||||
@@ -45,6 +45,14 @@ config HOST_OTHER
|
||||
|
||||
endchoice
|
||||
|
||||
config TOOLCHAIN_WINDOWS
|
||||
bool
|
||||
default n
|
||||
depends on HOST_WINDOWS
|
||||
---help---
|
||||
Selected internally if the selected Windows environment is compatible
|
||||
with the use of Windows native toolchains.
|
||||
|
||||
choice
|
||||
prompt "Windows Build Environment"
|
||||
default WINDOWS_CYGWIN
|
||||
@@ -52,24 +60,34 @@ choice
|
||||
|
||||
config WINDOWS_NATIVE
|
||||
bool "Windows Native"
|
||||
select TOOLCHAIN_WINDOWS
|
||||
---help---
|
||||
Build natively in a CMD.exe environment with Windows style paths
|
||||
(like C:\cgywin\home)
|
||||
|
||||
config WINDOWS_CYGWIN
|
||||
bool "Cygwin"
|
||||
select TOOLCHAIN_WINDOWS
|
||||
---help---
|
||||
Build natively in a Cygwin environment with POSIX style paths (like
|
||||
/cygdrive/c/cgywin/home)
|
||||
/cygdrive/c/Program Files)
|
||||
|
||||
config WINDOWS_UBUNTU
|
||||
bool "Ubuntu under Windows 10"
|
||||
---help---
|
||||
Build natively in an Unbuntu shell under Windoes 10 environment with
|
||||
POSIX style paths (like /mnt/c/Program Files)
|
||||
|
||||
config WINDOWS_MSYS
|
||||
bool "MSYS"
|
||||
select TOOLCHAIN_WINDOWS
|
||||
---help---
|
||||
Build natively in a Cygwin environment with POSIX style paths (like
|
||||
/cygdrive/c/cgywin/home)
|
||||
|
||||
config WINDOWS_OTHER
|
||||
bool "Windows POSIX-like environment"
|
||||
select TOOLCHAIN_WINDOWS
|
||||
---help---
|
||||
Build natively in another POSIX-like environment. Additional
|
||||
support may be necessary
|
||||
|
||||
+184
-24
@@ -1,8 +1,10 @@
|
||||
README
|
||||
^^^^^^
|
||||
|
||||
o Installation
|
||||
o Environments
|
||||
- Installing Cygwin
|
||||
- Ubuntu Bash under Windows 10
|
||||
o Installation
|
||||
- Download and Unpack
|
||||
- Semi-Optional apps/ Package
|
||||
- Installation Directories with Spaces in the Path
|
||||
@@ -34,21 +36,49 @@ README
|
||||
- Window Native Toolchain Issues
|
||||
o Documentation
|
||||
|
||||
INSTALLATION
|
||||
ENVIRONMENTS
|
||||
^^^^^^^^^^^^
|
||||
|
||||
NuttX may be installed and built on a Linux system or on a Windows
|
||||
system if Cygwin is installed. The MSYS environment is an option
|
||||
to Cygwin on the Windows platform. However, I have little experience
|
||||
that that configuration and it will not be discussed in this README
|
||||
file.
|
||||
NuttX requires a POSIX development environment such as you would find under
|
||||
Linux or OSX. NuttX may be also be installed and built on Windows system
|
||||
if you also provde such a POSIX development environment. Options for a
|
||||
POSIX development environment under Windows include:
|
||||
|
||||
Instructions for installation of Cygwin on Windows system are provided
|
||||
in the following paragraph.
|
||||
- An installation of Linux on a virtual machine (VM) in Windows. I have
|
||||
not been happy using a VM myself. I have had stability problems with
|
||||
open source VMs and commercial VMs cost more than I want to spend.
|
||||
Sharing files with Linux running in a VM is awkward; sharing devices
|
||||
connected to the Windows box with Linux in a VM is, at the very least,
|
||||
confusing; Using Windows tools (such as Segger J-Link) with files
|
||||
built under the Linux VM is not a possibility.
|
||||
|
||||
NuttX can also be installed and built on a native Windows system, but
|
||||
with some potential tool-related issues (see the discussion "Native
|
||||
Windows Build" below).
|
||||
- The Cygwin environment. Instructions for installation of Cygwin on a
|
||||
Windows system are provided in the following paragraph, "Installing
|
||||
Cygwin". Cygwin is a mature, well-tested, and very convenient
|
||||
environment. It is especially expecially convenient if you need to
|
||||
integrate with Windows tools and files. Downsides are that the
|
||||
installation time is very long and the compile times are slow.
|
||||
|
||||
- Ubuntu/Bash shell under Windows 10. This is a new option under
|
||||
Windows 10. See the section "Ubuntu Bash under Windows 10" below.
|
||||
This is an improvement over Cygwin if your concern is compile time;
|
||||
its build performance is comparable to native Linux, certainly better
|
||||
than the Cygwin build time. It also installs in a tiny fraction of
|
||||
the time as Cygwin, perhaps 20 minutes for the basic Ubuntu install
|
||||
(vs. more than a day for the complete Cygwin install).
|
||||
|
||||
- The MSYS environment. I have no experience using the MSYS environment
|
||||
and that configuration will not be discussed in this README file.
|
||||
See http://www.mingw.org/wiki/MSYS if you are interested in
|
||||
using MSYS. People report to me that they have used MSYS
|
||||
successfully. I suppose that the advantages of the MSYS environemnt
|
||||
is that it is closer to a native Windows environment and uses only a
|
||||
minimal of add-on POSIX-land tools.
|
||||
|
||||
- NuttX can also be installed and built on a native Windows system, but
|
||||
with some potential tool-related issues (see the discussion "Native
|
||||
Windows Build" under "Building NuttX" below). GNUWin32 is used to
|
||||
provide compatible native windows tools.
|
||||
|
||||
Installing Cygwin
|
||||
-----------------
|
||||
@@ -84,6 +114,9 @@ Installing Cygwin
|
||||
"Publishing". You can try omitting KDE, Gnome, GTK, and other
|
||||
graphics packages if you don't plan to use them.
|
||||
|
||||
Perhaps a minimum set would be those packages listed below for the
|
||||
"Ubuntu Bash under Windows 10" installation?
|
||||
|
||||
After installing Cygwin, you will get lots of links for installed
|
||||
tools and shells. I use the RXVT native shell. It is fast and reliable
|
||||
and does not require you to run the Cygwin X server (which is neither
|
||||
@@ -95,6 +128,136 @@ Installing Cygwin
|
||||
about 5GiB. The server I selected was also very slow so it took
|
||||
over a day to do the whole install!
|
||||
|
||||
Ubuntu Bash under Windows 10
|
||||
----------------------------
|
||||
|
||||
A better version of a command-line only Ubuntu under Windows 10 (beta)
|
||||
has recently been made available from Microsoft.
|
||||
|
||||
Installation
|
||||
------------
|
||||
Installation instructions abound on the Internet complete with screen
|
||||
shots. I will attempt to duplicate those instructions in full here.
|
||||
Here are the simplified installation steps:
|
||||
|
||||
- Open "Settings".
|
||||
- Click on "Update & security".
|
||||
- Click on "For Developers".
|
||||
- Under "Use developer features", select the "Developer mode" option to
|
||||
setup the environment to install Bash.
|
||||
- A message box should pop up. Click "Yes" to turn on developer mode.
|
||||
- After the necessary components install, you'll need to restart your
|
||||
computer.
|
||||
|
||||
Once your computer reboots:
|
||||
|
||||
- Open "Control Panel".
|
||||
- Click on "Programs".
|
||||
- Click on "Turn Windows features on or off".
|
||||
- A list of features will pop up, check the "Windows Subsystem for Linux
|
||||
(beta)" option.
|
||||
- Click OK.
|
||||
- Once the components installed on your computer, click the "Restart
|
||||
now" button to complete the task.
|
||||
|
||||
After your computer restarts, you will notice that Bash will not appear in
|
||||
the "Recently added" list of apps, this is because Bash isn't actually
|
||||
installed yet. Now that you have setup the necessary components, use the
|
||||
following steps to complete the installation of Bash:
|
||||
|
||||
- Open "Start", do a search for bash.exe, and press "Enter".
|
||||
- On the command prompt, type y and press Enter to download and install
|
||||
Bash from the Windows Store. This will take awhile.
|
||||
- Then you'll need to create a default UNIX user account. This account
|
||||
doesn't have to be the same as your Windows account. Enter the
|
||||
username in the required field and press Enter (you can't use the
|
||||
username "admin").
|
||||
- Close the "bash.exe" command prompt.
|
||||
|
||||
Now that you completed the installation and setup, you can open the Bash
|
||||
tool from the Start menu like you would with any other app.
|
||||
|
||||
Accessing Windows Files from Ubuntu
|
||||
-----------------------------------
|
||||
File sysems will be mounted under "/mnt" so for example "C:\Program Files"
|
||||
appears at "/mnt/c/Program Files". This is as opposed to Cgwin where
|
||||
the same directory would appear at "/cygdrive/c/Program Files".
|
||||
|
||||
With these differences (perhaps a few other Windows quirks) the Ubuntu
|
||||
install works just like Ubuntu running natively on your PC.
|
||||
|
||||
Accessing Ubuntu Files From Windows
|
||||
-----------------------------------
|
||||
In Ubuntu Userspace for Windows, the Ubuntu file system root directory is
|
||||
at:
|
||||
|
||||
%localappdata%\lxss\rootfs
|
||||
|
||||
Or
|
||||
|
||||
C:\Users\Username\AppData\Local\lxss\rootfs
|
||||
|
||||
Install Linux Software.
|
||||
-----------------------
|
||||
Use "sudo apt-get install <package name>". As examples, this is how
|
||||
you would get GIT:
|
||||
|
||||
$ sudo apt-get install git
|
||||
|
||||
This will get you a compiler for your host PC:
|
||||
|
||||
$ sudo apt-get install gcc
|
||||
|
||||
This will get you an ARM compiler for your target:
|
||||
|
||||
$ sudo apt-get install gcc-arm-none-eabi
|
||||
|
||||
NOTE: That is just an example. I am not sure if apt-get will give you a
|
||||
current or usable compiler. You should carefully select your toolchain
|
||||
for the needs of your project.]
|
||||
|
||||
You will also need to the get the kconfig-frontends configuration as
|
||||
described below under "NuttX Configuration tool". In order build the
|
||||
kconfig-frontends configuration tool you will also need: make, gperf,
|
||||
flex, bison, and libncurses-dev.
|
||||
|
||||
That is enough to do a basic NuttX build.
|
||||
|
||||
Integrating with Windows Tools
|
||||
------------------------------
|
||||
If you want to integrate with Windows native tools, then you would need
|
||||
deal with the same kind of craziness as with integrating Cygwin with
|
||||
native toolchains, see the section "Cygwin Build Problems" below.
|
||||
|
||||
However, there is currently no build support for using Windows native
|
||||
tools with Ubuntu under Windows. This tool combination is made to work
|
||||
with Cygwin through the use of the 'cygpath -w' tool that converts paths
|
||||
from say '/cydrive/c/Program Files' to 'C:\Program Files'. There is,
|
||||
however, no corresponding tool to convert '/mnt/c/Program Files' in the
|
||||
Ubuntu environment.
|
||||
|
||||
Graphics Support
|
||||
----------------
|
||||
The Ubuntu version support by Microsoft is a command-line only version.
|
||||
There is no support for Linux graphics utilities.
|
||||
|
||||
This limititation is not a limitation of Ubuntu, however, only in what
|
||||
Microsoft is willing to support. If you install a X-Server, then you
|
||||
can also use basic graphics utilities. See for example:
|
||||
|
||||
http://www.howtogeek.com/261575/how-to-run-graphical-linux-desktop-applications-from-windows-10s-bash-shell/
|
||||
|
||||
Many Linux graphics programs would, however, also require a graphics
|
||||
framework like GTK or Qt. So this might be a trip down the rabbit hole.
|
||||
|
||||
INSTALLATION
|
||||
^^^^^^^^^^^^
|
||||
|
||||
There are two ways to get NuttX: You may download released, stable
|
||||
tarballs from wither the Bitbucket or Sourceforge download locations.
|
||||
Or you may get NuttX by cloning the Bitbucket GIT repositories. Let's
|
||||
consider the released tarballs first:
|
||||
|
||||
Download and Unpack
|
||||
-------------------
|
||||
|
||||
@@ -105,6 +268,11 @@ Download and Unpack
|
||||
match the various instructions in the documentation and some scripts
|
||||
in the source tree.
|
||||
|
||||
Download locations:
|
||||
|
||||
https://bitbucket.org/nuttx/nuttx/downloads
|
||||
https://sourceforge.net/projects/nuttx/files/nuttx/
|
||||
|
||||
Semi-Optional apps/ Package
|
||||
---------------------------
|
||||
|
||||
@@ -1287,12 +1455,6 @@ nuttx/
|
||||
| | `- README.txt
|
||||
| |- cloudctrl
|
||||
| | `- README.txt
|
||||
| |- compal_e86
|
||||
| | `- README.txt
|
||||
| |- compal_e88
|
||||
| | `- README.txt
|
||||
| |- compal_e99
|
||||
| | `- README.txt
|
||||
| |- demo0s12ne64/
|
||||
| | `- README.txt
|
||||
| |- dk-tm4c129x/
|
||||
@@ -1399,6 +1561,8 @@ nuttx/
|
||||
| | `- README.txt
|
||||
| |- olimex-stm32-p207/
|
||||
| | `- README.txt
|
||||
| |- olimex-stm32-p407/
|
||||
| | `- README.txt
|
||||
| |- olimex-strp711/
|
||||
| | `- README.txt
|
||||
| |- open1788/
|
||||
@@ -1415,12 +1579,8 @@ nuttx/
|
||||
| | `- README.txt
|
||||
| |- pic32mz-starterkit/
|
||||
| | `- README.txt
|
||||
| |- pirelli_dpl10/
|
||||
| | `- README.txt
|
||||
| |- qemu-i486/
|
||||
| | `- README.txt
|
||||
| |- rgmp/
|
||||
| | `- README.txt
|
||||
| |- sabre-6quad/
|
||||
| | `- README.txt
|
||||
| |- sama5d2-xult/
|
||||
@@ -1439,6 +1599,8 @@ nuttx/
|
||||
| | `- README.txt
|
||||
| |- sam3u-ek/
|
||||
| | `- README.txt
|
||||
| |- sam4cmp-db
|
||||
| | `- README.txt
|
||||
| |- sam4e-ek/
|
||||
| | `- README.txt
|
||||
| |- sam4l-xplained/
|
||||
@@ -1544,8 +1706,6 @@ nuttx/
|
||||
| | `- README.txt
|
||||
| |- sensors/
|
||||
| | `- README.txt
|
||||
| |- sercomm/
|
||||
| | `- README.txt
|
||||
| |- syslog/
|
||||
| | `- README.txt
|
||||
| `- README.txt
|
||||
|
||||
+791
File diff suppressed because it is too large
Load Diff
@@ -1,4 +1,4 @@
|
||||
NuttX TODO List (Last updated November 19, 2016)
|
||||
NuttX TODO List (Last updated January 10, 2017)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
This file summarizes known NuttX bugs, limitations, inconsistencies with
|
||||
@@ -9,8 +9,8 @@ issues related to each board port.
|
||||
|
||||
nuttx/:
|
||||
|
||||
(13) Task/Scheduler (sched/)
|
||||
(2) SMP
|
||||
(12) Task/Scheduler (sched/)
|
||||
(1) SMP
|
||||
(1) Memory Management (mm/)
|
||||
(1) Power Management (drivers/pm)
|
||||
(3) Signals (sched/signal, arch/)
|
||||
@@ -22,7 +22,7 @@ nuttx/:
|
||||
(12) Network (net/, drivers/net)
|
||||
(4) USB (drivers/usbdev, drivers/usbhost)
|
||||
(0) Other drivers (drivers/)
|
||||
(11) Libraries (libc/, libm/)
|
||||
(12) Libraries (libc/, libm/)
|
||||
(11) File system/Generic drivers (fs/, drivers/)
|
||||
(9) Graphics Subsystem (graphics/)
|
||||
(2) Build system / Toolchains
|
||||
@@ -31,8 +31,8 @@ nuttx/:
|
||||
|
||||
apps/ and other Add-Ons:
|
||||
|
||||
(3) Network Utilities (apps/netutils/)
|
||||
(2) NuttShell (NSH) (apps/nshlib)
|
||||
(2) Network Utilities (apps/netutils/)
|
||||
(1) NuttShell (NSH) (apps/nshlib)
|
||||
(1) System libraries apps/system (apps/system)
|
||||
(1) Pascal add-on (pcode/)
|
||||
(4) Other Applications & Tests (apps/examples/)
|
||||
@@ -101,16 +101,37 @@ o Task/Scheduler (sched/)
|
||||
Status: Open
|
||||
Priority: Medium Low for now
|
||||
|
||||
Title: ISSUES WITH atexit() AND on_exit()
|
||||
Title: ISSUES WITH atexit(), on_exit(), AND pthread_cleanup_pop()
|
||||
Description: These functions execute with the following bad properties:
|
||||
|
||||
1. They run with interrupts disabled,
|
||||
2. They run in supervisor mode (if applicable), and
|
||||
3. They do not obey any setup of PIC or address
|
||||
environments. Do they need to?
|
||||
4. In the case of task_delete() and pthread_cancel(), these
|
||||
callbacks will run on the thread of execution and address
|
||||
context of the caller of task. That is very bad!
|
||||
|
||||
The fix for all of these issues it to have the callbacks
|
||||
run on the caller's thread (as with signal handlers).
|
||||
run on the caller's thread as is currently done with
|
||||
signal handlers. Signals are delivered differently in
|
||||
PROTECTED and KERNEL modes: The deliver is involes a
|
||||
signal handling trampoline function in the user address
|
||||
space and two signal handlers: One to call the signal
|
||||
handler trampoline in user mode (SYS_signal_handler) and
|
||||
on in with the signal handler trampoline to return to
|
||||
supervisor mode (SYS_signal_handler_return)
|
||||
|
||||
The primary difference is in the location of the signal
|
||||
handling trampoline:
|
||||
|
||||
- In PROTECTED mode, there is on a single user space blob
|
||||
with a header at the beginning of the block (at a well-
|
||||
known location. There is a pointer to the signal handler
|
||||
trampoline function in that header.
|
||||
- In the KERNEL mode, a special process signal handler
|
||||
trampoline is used at a well-known location in every
|
||||
process address space (ARCH_DATA_RESERVE->ar_sigtramp).
|
||||
Status: Open
|
||||
Priority: Medium Low. This is an important change to some less
|
||||
important interfaces. For the average user, these
|
||||
@@ -144,20 +165,6 @@ o Task/Scheduler (sched/)
|
||||
incompatibilities could show up in porting some code).
|
||||
Priority: Low
|
||||
|
||||
Title: REMOVE TASK_DELETE
|
||||
Description: Need to remove or fix task delete. This interface is non-
|
||||
standard and not safe. Arbitrary deleting tasks can cause
|
||||
serious problems such as memory leaks. Better to remove it
|
||||
than to retain it as a latent bug.
|
||||
|
||||
Currently used within the OS and also part of the
|
||||
implementation of pthread_cancel() and task_restart() (which
|
||||
should also go for the same reasons). It is used in
|
||||
NxWM::CNxConsole to terminate console tasks and also in
|
||||
apps/netutils/thttpd to kill CGI tasks that timeout.
|
||||
Status: Open
|
||||
Priority: Low and not easily removable.
|
||||
|
||||
Title: RELEASE SEMAPHORES HELD BY CANCELED THREADS:
|
||||
Description: Commit: fecb9040d0e54baf14b729e556a832febfe8229e: "In
|
||||
case a thread is doing a blocking operation (e.g. read())
|
||||
@@ -308,70 +315,33 @@ o Task/Scheduler (sched/)
|
||||
o SMP
|
||||
^^^
|
||||
|
||||
Title: SPINLOCKS AND DATA CACHES
|
||||
Description: If spinlocks are used in a system with a data cache, then there
|
||||
may be a problem with cache coherency in some CPU architectures:
|
||||
When one CPU modifies the spinlock, the changes may not be
|
||||
visible to another CPU if it does not share the data cache.
|
||||
That would cause failure in the spinlock logic.
|
||||
Title: SMP AND DATA CACHES
|
||||
Description: When spinlocks, semaphores, etc. are used in an SMP system with
|
||||
a data cache, then there may be problems with cache coherency
|
||||
in some CPU architectures: When one CPU modifies the shared
|
||||
object, the changes may not be visible to another CPU if it
|
||||
does not share the data cache. That would cause failure in
|
||||
the IPC logic.
|
||||
|
||||
Flushing the D-cache on writes and invalidating before a read is
|
||||
not really an option. spinlocks are normally 8-bits in size and
|
||||
cache lines are typically 32-bytes so that would have side effects
|
||||
unless the spinlocks were made to be the same size as one cache
|
||||
line.
|
||||
not really an option. That would essentially effect every memory
|
||||
access and there may be side-effects due to cache line sizes
|
||||
and alignment.
|
||||
|
||||
This might be doable if a write-through cache is used. Then you
|
||||
could always safely invalidate the cache line before reading the
|
||||
spinlock because there should never be any dirty cache lines in
|
||||
this case.
|
||||
For the same reason a separate, non-cacheable memory region is
|
||||
not an option. Essentially all data would have to go in the
|
||||
non-cached region and you would have no benefit from the data
|
||||
cache.
|
||||
|
||||
The better option is to add compiler independent "ornamentation"
|
||||
to the spinlock so that the spinlocks are all linked together
|
||||
into a separate, non-cacheable memory regions. Because of
|
||||
region alignment and minimum region mapping sizes this could
|
||||
still be wasteful of memory. This would work in systems that
|
||||
have both data cache and either an MPU or an MMU.
|
||||
Status: Open
|
||||
Priority: High. spinlocks, and hence SMP, will not work on such systems
|
||||
without this change.
|
||||
On ARM Cortex-A, each CPU has a separate data cache. However,
|
||||
the MPCore's Snoop Controller Unit supports coherency among
|
||||
the different caches. The SCU is enabled by the SCU control
|
||||
register and each CPU participates in the SMP coherency by
|
||||
setting the ACTLR_SMP bit in the auxiliary control register
|
||||
(ACTLR).
|
||||
|
||||
Title: DEADLOCK SCENARIO WITH up_cpu_pause().
|
||||
Description: I think there is a possibilty for a hang in up_cpu_pause().
|
||||
Suppose this situation:
|
||||
|
||||
- CPU1 is in a critical section and has the g_cpu_irqlock
|
||||
spinlock.
|
||||
- CPU0 takes an interrupt and attempts to enter the critical
|
||||
section. It spins waiting on g_cpu_irqlock with interrupt
|
||||
disabled.
|
||||
- CPU1 calls up_cpu_pause() to pause operation on CPU1. This
|
||||
will issue an inter-CPU interrupt to CPU0
|
||||
- But interrupts are disabled. What will happen? I think
|
||||
that this is a deadlock: Interrupts will stay disabled on
|
||||
CPU0 because it is spinning in the interrupt handler;
|
||||
up_cpu_pause() will hang becuase the inter-CPU interrupt
|
||||
is pending.
|
||||
|
||||
Are inter-CPU interrupts maskable in the same way as other
|
||||
interrupts? If the are not-maskable, then we must also handle
|
||||
them as nested interrupts in some fashion.
|
||||
|
||||
A work-around might be to check the state of other-CPU
|
||||
interrupt handler inside the spin loop of up_cpu_pause().
|
||||
Having the other CPU spinning and waiting for up_cpu_pause()
|
||||
provided that (1) the pending interrupt can be cleared, and
|
||||
(2) leave_critical_section() is not called prior to the point
|
||||
where up_cpu_resume() is called, and (3) up_cpu_resume() is
|
||||
smart enough to know that it should not attempt to resume a
|
||||
non-paused CPU.
|
||||
|
||||
This would require some kind of information about each
|
||||
interrupt handler: In an interrupt, waiting for spinlock,
|
||||
have spinlock, etc.
|
||||
|
||||
Status: Open
|
||||
Priority: Medium-High. I don't know for certain that this is a problem but it seems like it could
|
||||
Status: Closed
|
||||
Priority: High on platforms that may have the issue.
|
||||
|
||||
o Memory Management (mm/)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^
|
||||
@@ -444,7 +414,7 @@ o Memory Management (mm/)
|
||||
|
||||
So in this case, NuttX work just link Linux or or *nix systems:
|
||||
All memory allocated by processes or threads in processes will
|
||||
be recovered when the process exists.
|
||||
be recovered when the process exits.
|
||||
|
||||
But not for the flat memory build. In that case, the issues
|
||||
above do apply. There is no safe way to recover the memory in
|
||||
@@ -457,7 +427,9 @@ o Memory Management (mm/)
|
||||
it is inherently unsafe, I would never incorporate anything
|
||||
like that into NuttX.
|
||||
|
||||
Status: Open. No changes are planned.
|
||||
Status: Open. No changes are planned. NOTE: This applies to the FLAT
|
||||
and PROTECTED builds only. There is no such leaking of memory
|
||||
in the KERNEL build mode.
|
||||
Priority: Medium/Low, a good feature to prevent memory leaks but would
|
||||
have negative impact on memory usage and code size.
|
||||
|
||||
@@ -528,12 +500,6 @@ o Signals (sched/signal, arch/)
|
||||
o pthreads (sched/pthreads)
|
||||
^^^^^^^^^^^^^^^^^
|
||||
|
||||
Title: CANCELLATION POINTS
|
||||
Description: pthread_cancel(): Should implement cancellation points and
|
||||
pthread_testcancel()
|
||||
Status: Open. No changes are planned.
|
||||
Priority: Low, probably not that useful
|
||||
|
||||
Title: PTHREAD_PRIO_PROTECT
|
||||
Description: Extend pthread_mutexattr_setprotocol() support PTHREAD_PRIO_PROTECT:
|
||||
|
||||
@@ -594,6 +560,44 @@ o pthreads (sched/pthreads)
|
||||
solution. So I discarded a few hours of programming. Not a
|
||||
big loss from the experience I gained."
|
||||
|
||||
Title: ISSUES WITH CANCELLATION POINTS
|
||||
Description: According to POIX cancellation points must occur when a thread is executing
|
||||
the following functions. There are some execptions as noted:
|
||||
|
||||
accept() mq_timedsend() NA putpmsg() sigtimedwait()
|
||||
04 aio_suspend() NA msgrcv() pwrite() NA sigwait()
|
||||
NA clock_nanosleep() NA msgsnd() read() sigwaitinfo()
|
||||
close() NA msync() NA readv() 01 sleep()
|
||||
connect() nanosleep() recv() 02 system()
|
||||
-- creat() open() recvfrom() NA tcdrain()
|
||||
fcntl() pause() NA recvmsg() 01 usleep()
|
||||
NA fdatasync() poll() select() -- wait()
|
||||
fsync() pread() sem_timedwait() waitid()
|
||||
NA getmsg() NA pselect() sem_wait() waitpid()
|
||||
NA getpmsg() pthread_cond_timedwait() send() write()
|
||||
NA lockf() pthread_cond_wait() NA sendmsg() NA writev()
|
||||
mq_receive() pthread_join() sendto()
|
||||
mq_send() pthread_testcancel() 03 sigpause()
|
||||
mq_timedreceive() NA putmsg() sigsuspend()
|
||||
|
||||
NA Not supported
|
||||
-- Doesn't need instrumentation. Handled by lower level calls.
|
||||
nn See note nn
|
||||
|
||||
NOTE 01: sleep() and usleep() are user-space functions in the C library and cannot
|
||||
serve as cancellation points. They are, however, simple wrappers around nanosleep
|
||||
which is a true cancellation point.
|
||||
NOTE 02: system() is actually implemented in apps/ as part of NSH. It cannot be
|
||||
a cancellation point either.
|
||||
NOTE 03: sigpause() is a user-space function in the C library and cannot serve as
|
||||
cancellation points. It is, however, a simple wrapper around sigsuspend()
|
||||
which is a true cancellation point.
|
||||
NOTE 04: aio_suspend() is a user-space function in the C library and cannot serve as
|
||||
cancellation points. It does call around sigtimedwait() which is a true cancellation
|
||||
point.
|
||||
Status: Not really open. This is just the way it is.
|
||||
Priority: Nothing additional is planned.
|
||||
|
||||
o Message Queues (sched/mqueue)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
@@ -1080,41 +1084,18 @@ o Network (net/, drivers/net)
|
||||
Priority: Medium. Important on slow applications that will not accept
|
||||
connections promptly.
|
||||
|
||||
Title: INTERRUPT LEVEL PROCESSING IN ETHERNET DRIVERS
|
||||
Description: Too many Ethernet drivers do interrupt-level processing with
|
||||
the network stack. The network stack supports either interrupt
|
||||
level processing or normal task level processing (depending on
|
||||
CONFIG_NET_NOINTS). This is really a very bad use of CPU
|
||||
resources; All of the network stack processing should be
|
||||
modified to use a work queue (and, all use of CONFIG_NET_NOINTS=n
|
||||
should be eliminated). This applies to many Ethernet drivers:
|
||||
Title: IPv6 REQUIRES ADDRESS FILTER SUPPORT
|
||||
Description: IPv6 requires that the Ethernet driver support NuttX address
|
||||
filter interfaces. Several Ethernet drivers do support there,
|
||||
however. Others support the address filtering interfaces but
|
||||
have never been verifed:
|
||||
|
||||
ARCHITECTURE CONFIG_NET_NOINTS? ADDRESS FILTER SUPPORT?
|
||||
C5471 NO NO
|
||||
STM32 YES YES
|
||||
STM32F7 YES YES
|
||||
TIVA ----------------------- ------
|
||||
LM3S NO NO
|
||||
TM4C YES YES
|
||||
eZ80 NO NO
|
||||
Kinetis YES YES (not tested)
|
||||
LPC17xx YES YES (not tested)
|
||||
LPC43xx YES YES (not tested)
|
||||
DMxxx NIC NO NO
|
||||
PIC32 NO NO
|
||||
RGMP ??? ???
|
||||
SAM3/4 YES YES
|
||||
SAMA5D ----------------------- ------
|
||||
EMACA NO YES (not tested)
|
||||
EMACB YES YES
|
||||
GMAC NO YES (not tested)
|
||||
SAMV7 YES YES
|
||||
SIM N/A (No interrupts) NO
|
||||
C5471, LM3X, ez80, DM0x90 NIC, PIC: Do not support address
|
||||
filteringing.
|
||||
Kinetis, LPC17xx, LPC43xx: Untested address filter support
|
||||
|
||||
The general outline of how this might be done is included in
|
||||
drivers/net/skeleton.c
|
||||
Status: Open
|
||||
Priority: Pretty high if you want a well behaved system.
|
||||
Priority: Pretty high if you want a to use IPv6 on these platforms.
|
||||
|
||||
Title: UDP MULTICAST RECEPTION
|
||||
Description: The logic in udp_input() expects either a single receive socket or
|
||||
@@ -1511,10 +1492,28 @@ o Libraries (libc/, libm/)
|
||||
2016-07-30: Numerous fixes and performance improvements from
|
||||
David Alessio.
|
||||
|
||||
Status: Open
|
||||
Priority: Low for casual users but clearly high if you need care about
|
||||
Status: Open
|
||||
Priority: Low for casual users but clearly high if you need care about
|
||||
these incorrect corner case behaviors in the math libraries.
|
||||
|
||||
Title: Repartition libc functionality.
|
||||
Description: There are many things implemented within the kernel (for example
|
||||
under sched/pthread) that probably should be migrated in the
|
||||
C library where it belongs.
|
||||
|
||||
I would really like to see a little flavor of a micro-kernel
|
||||
at the OS interface: I would like to see more primitive OS
|
||||
system calls with more higher level logic in the C library.
|
||||
|
||||
One awkward thing is the incompatibility of KERNEL vs FLAT
|
||||
builds: In the kernel build, it would be nice to move many
|
||||
of the thread-specific data items out of the TCB and into
|
||||
the process address environment where they belong. It is
|
||||
difficult to make this compatible with the FLAT build,
|
||||
however.
|
||||
Status: Open
|
||||
Priority: Low
|
||||
|
||||
o File system / Generic drivers (fs/, drivers/)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
@@ -1713,18 +1712,6 @@ o Graphics Subsystem (graphics/)
|
||||
Status: Open
|
||||
Priority: Medium low
|
||||
|
||||
Title: IMPROVED NxTERM FONT CACHING
|
||||
Description: Now each NxTerm instance has its own private font cache
|
||||
whose size is determined by CONFIG_NXTERM_MXCHARS. If there
|
||||
are multiple NxTerm instances using the same font, each will
|
||||
have a separate font cache. This is inefficient and wasteful
|
||||
of memory: Each NxTerm instance should share a common font
|
||||
cache.
|
||||
Status: Open
|
||||
Priority: Medium. Not important for day-to-day testing but would be
|
||||
a critical improvement if NxTerm were to be used in a
|
||||
product.
|
||||
|
||||
Title: NxTERM VT100 SUPPORT
|
||||
Description: If the NxTerm will be used with the Emacs-like command line
|
||||
editor (CLE), then it will need to support VT100 cursor control
|
||||
@@ -1761,6 +1748,37 @@ o Graphics Subsystem (graphics/)
|
||||
Priority: Low, not a serious issue but worth noting. There is no plan
|
||||
to change this behavior.
|
||||
|
||||
Title: REMOVE SINGLE USER MODE
|
||||
Description: NX graphics supports two modes: A simple single user mode and
|
||||
more complex multi-user mode selected with CONFIG_NX_MULTIUSER=y.
|
||||
In this configuration, an application can start the NX server
|
||||
with boardctrl(BOARDIOC_NX_START); After that, all graphic
|
||||
interactions are via a thin layer in libnx/. The OS
|
||||
interface is only via messages sent and received using POSIX
|
||||
message queues. So this is good code and respects all of the
|
||||
POSIX interfacing rules. Hence, it works well in all build
|
||||
modes (FLAT, PROTECTED, and KERNEL builds).
|
||||
|
||||
But without CONFIG_NX_MULTIUSER, the single user applications
|
||||
violate all of the rules and calls internal NX functions
|
||||
directly. This includes all calls to internal OSfunctions
|
||||
with names like, nx_open, up_fbinitialize, board_lcd_*, and
|
||||
others. This is a violation of interfacing standard in all
|
||||
cases and can only be made to work in the FLAT build mode.
|
||||
|
||||
The single user mode does have some desirable properties: It
|
||||
is lighter weight and so more suitable for very resource limited
|
||||
platforms. But I think that in the long run the only reasonable
|
||||
solution is to eliminate the single user mode and provide only
|
||||
the multi-user mode with the message queue interface.
|
||||
Status: Open
|
||||
Priority: Low-Medium, not a serious issue but worth noting. Single user
|
||||
mode is a blemish on the OS and not compatible with the RTOS
|
||||
roadmap. But neither is there any critical necessity to
|
||||
remove the offending code immediately. Be aware: If you use
|
||||
the single user mode, it will be yanked out from under your
|
||||
feet in the not-so-distant future.
|
||||
|
||||
o Build system
|
||||
^^^^^^^^^^^^
|
||||
|
||||
@@ -1790,21 +1808,6 @@ o Build system
|
||||
Priority: Low, since I am not aware of anyone using the Windows Native build.
|
||||
But, of course, very high if you want to use it.
|
||||
|
||||
Title: REMOVE SINGLE USER MODE
|
||||
Description: The graphics sub-system can operate in either a single-user mode or
|
||||
in a multi-user mode. In the multiple-user mode, a kernel thread
|
||||
is used to support a graphics server. Multiple applications may then
|
||||
communicate with the server using a message queue. This users only
|
||||
standard POSIX interfaces and works in all build modes (FLAT,
|
||||
PROTECTED, and KERNEL builds).
|
||||
|
||||
The single-user mode, on the hand, uses inappropriate calls directly
|
||||
into the OS. This violates the POSIX interface and must, eventually,
|
||||
be eliminated. These inappropriate calls can only be supported in
|
||||
the FLAT build mode.
|
||||
Status: Open
|
||||
Priority: Medium-High
|
||||
|
||||
o Other drivers (drivers/)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
@@ -1997,13 +2000,6 @@ o Network Utilities (apps/netutils/)
|
||||
Status: Open
|
||||
Priority: Medium
|
||||
|
||||
Title: THTTPD WARNINGS
|
||||
Description: If the network is enabled, but THTTPD is not configured, it spews out lots
|
||||
of pointless warnings. This is kind of annoying and unprofessional; needs to
|
||||
be fixed someday.
|
||||
Status: Open. An annoyance, but not a real problem.
|
||||
Priority: Low
|
||||
|
||||
Title: NETWORK MONITOR NOT GENERALLY AVAILABLE
|
||||
Description: The NSH network management logic has general applicability
|
||||
but is currently useful only because it is embedded in the NSH
|
||||
@@ -2023,11 +2019,6 @@ o NuttShell (NSH) (apps/nshlib)
|
||||
Status: Open
|
||||
Priority: Low
|
||||
|
||||
Title: ARPPING COMMAND
|
||||
Description: Add an arping command
|
||||
Status: Open
|
||||
Priority: Low (enhancement)
|
||||
|
||||
o System libraries apps/system (apps/system)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
@@ -2083,7 +2074,12 @@ o Other Applications & Tests (apps/examples/)
|
||||
it stops rendering. This is not a problem for the examples/nx
|
||||
code because it uses so few fonts, but if the logic were
|
||||
leveraged for more general purposes, it would be a problem.
|
||||
|
||||
Update: see examples/nxtext for some improved font cache handling.
|
||||
Update: The NXTERM font cache has been generalized and is now
|
||||
offered as the standard, common font cache for all applications.
|
||||
both the nx and nxtext examples should be modified to use this
|
||||
common font cache. See interfaces defined in nxfonts.h.
|
||||
Status: Open
|
||||
Priority: Low. This is not really a problem because examples/nx works
|
||||
fine with its bogus font caching.
|
||||
|
||||
+2
-8
@@ -46,12 +46,6 @@ config ARCH_MISOC
|
||||
---help---
|
||||
MISOC
|
||||
|
||||
config ARCH_RGMP
|
||||
bool "RGMP"
|
||||
---help---
|
||||
RTOS and GPOS on Multi-Processor (RGMP) architecture. See
|
||||
http://rgmp.sourceforge.net/wiki/index.php/Main_Page.
|
||||
|
||||
config ARCH_RENESAS
|
||||
bool "Renesas"
|
||||
select ARCH_NOINTC
|
||||
@@ -83,6 +77,8 @@ config ARCH_X86
|
||||
|
||||
config ARCH_XTENSA
|
||||
bool "Xtensa"
|
||||
select ARCH_HAVE_STACKCHECK
|
||||
select ARCH_HAVE_CUSTOMOPT
|
||||
---help---
|
||||
Cadence® Tensilica® Xtensa® actictures.
|
||||
|
||||
@@ -107,7 +103,6 @@ config ARCH
|
||||
default "hc" if ARCH_HC
|
||||
default "mips" if ARCH_MIPS
|
||||
default "misoc" if ARCH_MISOC
|
||||
default "rgmp" if ARCH_RGMP
|
||||
default "renesas" if ARCH_RENESAS
|
||||
default "risc-v" if ARCH_RISCV
|
||||
default "sim" if ARCH_SIM
|
||||
@@ -121,7 +116,6 @@ source arch/avr/Kconfig
|
||||
source arch/hc/Kconfig
|
||||
source arch/mips/Kconfig
|
||||
source arch/misoc/Kconfig
|
||||
source arch/rgmp/Kconfig
|
||||
source arch/renesas/Kconfig
|
||||
source arch/risc-v/Kconfig
|
||||
source arch/sim/Kconfig
|
||||
|
||||
@@ -158,7 +158,6 @@ arch/arm - ARM-based micro-controllers
|
||||
MCU support
|
||||
arch/arm/include/a1x and arch/arm/src/a1x
|
||||
arch/arm/include/c5471 and arch/arm/src/c5471
|
||||
arch/arm/include/calypso and arch/arm/src/calypso
|
||||
arch/arm/include/dm320 and arch/arm/src/dm320
|
||||
arch/arm/include/efm32 and arch/arm/src/efm32
|
||||
arch/arm/include/imx1 and arch/arm/src/imx1
|
||||
@@ -222,17 +221,6 @@ arch/renesas - Support for Renesas and legacy Hitachi microcontrollers.
|
||||
arch/renesas/include/m16c and arch/renesas/src/m16c
|
||||
arch/renesas/include/sh1 and arch/renesas/src/sh1
|
||||
|
||||
arch/rgmp
|
||||
|
||||
RGMP stands for RTOS and GPOS on Multi-Processor. RGMP is a project
|
||||
for running GPOS and RTOS simultaneously on multi-processor platforms.
|
||||
You can port your favorite RTOS to RGMP together with an unmodified
|
||||
Linux to form a hybrid operating system. This makes your application
|
||||
able to use both RTOS and GPOS features.
|
||||
|
||||
See http://rgmp.sourceforge.net/wiki/index.php/Main_Page for further
|
||||
information about RGMP.
|
||||
|
||||
arch/risc-v
|
||||
This directory is dedicated to ports to the RISC-V family.
|
||||
|
||||
|
||||
@@ -31,16 +31,6 @@ config ARCH_CHIP_C5471
|
||||
---help---
|
||||
TI TMS320 C5471, A180, or DA180 (ARM7TDMI)
|
||||
|
||||
config ARCH_CHIP_CALYPSO
|
||||
bool "Calypso"
|
||||
select ARCH_ARM7TDMI
|
||||
select ARCH_HAVE_HEAP2
|
||||
select ARCH_HAVE_LOWVECTORS
|
||||
select OTHER_UART_SERIALDRIVER
|
||||
select ARCH_HAVE_POWEROFF
|
||||
---help---
|
||||
TI Calypso-based cell phones (ARM7TDMI)
|
||||
|
||||
config ARCH_CHIP_DM320
|
||||
bool "TMS320 DM320"
|
||||
select ARCH_ARM926EJS
|
||||
@@ -409,7 +399,6 @@ config ARCH_CHIP
|
||||
string
|
||||
default "a1x" if ARCH_CHIP_A1X
|
||||
default "c5471" if ARCH_CHIP_C5471
|
||||
default "calypso" if ARCH_CHIP_CALYPSO
|
||||
default "dm320" if ARCH_CHIP_DM320
|
||||
default "efm32" if ARCH_CHIP_EFM32
|
||||
default "imx1" if ARCH_CHIP_IMX1
|
||||
@@ -625,9 +614,6 @@ endif
|
||||
if ARCH_CHIP_C5471
|
||||
source arch/arm/src/c5471/Kconfig
|
||||
endif
|
||||
if ARCH_CHIP_CALYPSO
|
||||
source arch/arm/src/calypso/Kconfig
|
||||
endif
|
||||
if ARCH_CHIP_DM320
|
||||
source arch/arm/src/dm320/Kconfig
|
||||
endif
|
||||
|
||||
@@ -1,12 +1,8 @@
|
||||
/****************************************************************************
|
||||
* arch/rgmp/src/arm/sigentry.S
|
||||
* arch/arm/include/armv7-a/spinlock.h
|
||||
*
|
||||
* Copyright (C) 2011 Yu Qiang. All rights reserved.
|
||||
* Author: Yu Qiang <yuq825@gmail.com>
|
||||
*
|
||||
* This file is a part of NuttX:
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -37,13 +33,7 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl up_sigentry
|
||||
up_sigentry:
|
||||
sub sp, sp, #68 @ 68 is the size of Trapframe
|
||||
mov r0, sp
|
||||
bl up_sigdeliver
|
||||
add sp, sp, #4 @ skip current_task
|
||||
pop {r0-r12, lr}
|
||||
rfefd sp!
|
||||
#ifndef __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H
|
||||
#define __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H
|
||||
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_ARM_SPINLOCK_H */
|
||||
@@ -1,5 +1,5 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_getc.h
|
||||
/****************************************************************************
|
||||
* arch/arm/include/armv7-a/spinlock.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
@@ -31,17 +31,9 @@
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_GETC_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_GETC_H
|
||||
#ifndef __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H
|
||||
#define __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_GETC_H */
|
||||
#endif /* __ARCH_ARM_INCLUDE_ARMV6_M_SPINLOCK_H */
|
||||
@@ -1,12 +1,8 @@
|
||||
/****************************************************************************
|
||||
* arch/rgmp/include/arm/arch/subarch/arch.h
|
||||
* arch/arm/include/armv7-a/spinlock.h
|
||||
*
|
||||
* Copyright (C) 2011 Yu Qiang. All rights reserved.
|
||||
* Author: Yu Qiang <yuq825@gmail.com>
|
||||
*
|
||||
* This file is a part of NuttX:
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -37,22 +33,7 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __RGMP_ARCH_SUBARCH_ARCH_H
|
||||
#define __RGMP_ARCH_SUBARCH_ARCH_H
|
||||
#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H
|
||||
#define __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
|
||||
static inline void up_mdelay(uint32_t msec)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
static inline void up_udelay(uint32_t usec)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
#endif /* !__ASSEMBLY__ */
|
||||
|
||||
#endif
|
||||
#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H */
|
||||
@@ -1,8 +1,8 @@
|
||||
/****************************************************************************
|
||||
* configs/misoc/include/generated/common.h
|
||||
* arch/arm/include/armv7-a/spinlock.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Ramtin Amin <keytwo@gmail.com>
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
@@ -33,17 +33,7 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H
|
||||
#define __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H
|
||||
#ifndef __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H
|
||||
#define __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __ASSEMBLER__
|
||||
# define MMPTR(x) x
|
||||
#else
|
||||
# define MMPTR(x) (*((volatile unsigned int *)(x)))
|
||||
#endif
|
||||
|
||||
#endif /* __CONFIGS_MISOC_INCLUDE_GENERATED_COMMON_H */
|
||||
#endif /* __ARCH_ARM_INCLUDE_ARMV7_M_SPINLOCK_H */
|
||||
@@ -0,0 +1,39 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/include/armv7-r/spinlock.h
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H
|
||||
#define __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_ARMV7_R_SPINLOCK_H */
|
||||
@@ -1,67 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define CALYPSO_PLL26_52_MHZ ((2 << 8) | 0)
|
||||
#define CALYPSO_PLL26_86_7_MHZ ((10 << 8) | 2)
|
||||
#define CALYPSO_PLL26_87_MHZ ((3 << 8) | 0)
|
||||
#define CALYPSO_PLL13_104_MHZ ((8 << 8) | 0)
|
||||
|
||||
enum mclk_div {
|
||||
_ARM_MCLK_DIV_1 = 0,
|
||||
ARM_MCLK_DIV_1 = 1,
|
||||
ARM_MCLK_DIV_2 = 2,
|
||||
ARM_MCLK_DIV_3 = 3,
|
||||
ARM_MCLK_DIV_4 = 4,
|
||||
ARM_MCLK_DIV_5 = 5,
|
||||
ARM_MCLK_DIV_6 = 6,
|
||||
ARM_MCLK_DIV_7 = 7,
|
||||
ARM_MCLK_DIV_1_5 = 0x80 | 1,
|
||||
ARM_MCLK_DIV_2_5 = 0x80 | 2,
|
||||
};
|
||||
|
||||
void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div);
|
||||
void calypso_pll_set(uint16_t inp);
|
||||
void calypso_clk_dump(void);
|
||||
|
||||
/* CNTL_RST */
|
||||
enum calypso_rst {
|
||||
RESET_DSP = (1 << 1),
|
||||
RESET_EXT = (1 << 2),
|
||||
RESET_WDOG = (1 << 3),
|
||||
};
|
||||
|
||||
void calypso_reset_set(enum calypso_rst calypso_rst, int active);
|
||||
int calypso_reset_get(enum calypso_rst);
|
||||
|
||||
enum calypso_bank {
|
||||
CALYPSO_nCS0 = 0,
|
||||
CALYPSO_nCS1 = 2,
|
||||
CALYPSO_nCS2 = 4,
|
||||
CALYPSO_nCS3 = 6,
|
||||
CALYPSO_nCS7 = 8,
|
||||
CALYPSO_CS4 = 0xa,
|
||||
CALYPSO_nCS6 = 0xc,
|
||||
};
|
||||
|
||||
enum calypso_mem_width {
|
||||
CALYPSO_MEM_8bit = 0,
|
||||
CALYPSO_MEM_16bit = 1,
|
||||
CALYPSO_MEM_32bit = 2,
|
||||
};
|
||||
|
||||
void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws,
|
||||
enum calypso_mem_width width, int we);
|
||||
|
||||
/* Enable or disable the internal bootrom mapped to 0x0000'0000 */
|
||||
void calypso_bootrom(int enable);
|
||||
|
||||
/* Enable or disable the debug unit */
|
||||
void calypso_debugunit(int enable);
|
||||
|
||||
/* configure the RHEA bus bridge[s] */
|
||||
void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
|
||||
uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1);
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H */
|
||||
@@ -1,31 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
|
||||
|
||||
#ifndef ARRAY_SIZE
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check at compile time that something is of a particular type.
|
||||
* Always evaluates to 1 so you may use it easily in comparisons.
|
||||
*/
|
||||
#define typecheck(type,x) \
|
||||
({ type __dummy; \
|
||||
typeof(x) __dummy2; \
|
||||
(void)(&__dummy == &__dummy2); \
|
||||
1; \
|
||||
})
|
||||
|
||||
#ifdef DEBUG
|
||||
#define dputchar(x) putchar(x)
|
||||
#define dputs(x) puts(x)
|
||||
#define dphex(x,y) phex(x,y)
|
||||
#define printd(x, ...) printf(x, ##__VA_ARGS__)
|
||||
#else
|
||||
#define dputchar(x)
|
||||
#define dputs(x)
|
||||
#define dphex(x,y)
|
||||
#define printd(x, args ...)
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H */
|
||||
@@ -1,17 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
|
||||
|
||||
#define __attribute_const__ __attribute__((__const__))
|
||||
|
||||
/* type properties */
|
||||
#define __packed __attribute__((packed))
|
||||
#define __aligned(alignment) __attribute__((aligned(alignment)))
|
||||
#define __unused __attribute__((unused))
|
||||
|
||||
/* linkage */
|
||||
#define __section(name) __attribute__((section(name)))
|
||||
|
||||
/* force placement in zero-waitstate memory */
|
||||
#define __ramtext __section(".ramtext")
|
||||
|
||||
#endif /* !__ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H */
|
||||
@@ -1,81 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/include/calypso/irq.h
|
||||
* Driver for Calypso IRQ controller
|
||||
*
|
||||
* (C) 2010 by Harald Welte <laforge@gnumonks.org>
|
||||
* (C) 2011 by Stefan Richter <ichgeh@l--putt.de>
|
||||
*
|
||||
* This source code is derivated from Osmocom-BB project and was
|
||||
* relicensed as BSD with permission from original authors.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __INCLUDE_NUTTX_IRQ_H
|
||||
#error "This file should never be included directly! Use <nuttx/irq.h>"
|
||||
#endif
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
enum irq_nr {
|
||||
IRQ_WATCHDOG = 0,
|
||||
IRQ_TIMER1 = 1,
|
||||
IRQ_TIMER2 = 2,
|
||||
IRQ_TSP_RX = 3,
|
||||
IRQ_TPU_FRAME = 4,
|
||||
IRQ_TPU_PAGE = 5,
|
||||
IRQ_SIMCARD = 6,
|
||||
IRQ_UART_MODEM = 7,
|
||||
IRQ_KEYPAD_GPIO = 8,
|
||||
IRQ_RTC_TIMER = 9,
|
||||
IRQ_RTC_ALARM_I2C = 10,
|
||||
IRQ_ULPD_GAUGING = 11,
|
||||
IRQ_EXTERNAL = 12,
|
||||
IRQ_SPI = 13,
|
||||
IRQ_DMA = 14,
|
||||
IRQ_API = 15,
|
||||
IRQ_SIM_DETECT = 16,
|
||||
IRQ_EXTERNAL_FIQ = 17,
|
||||
IRQ_UART_IRDA = 18,
|
||||
IRQ_ULPD_GSM_TIMER = 19,
|
||||
IRQ_GEA = 20,
|
||||
_NR_IRQS
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* Don't use _NR_IRQS!!! Won't work in preprocessor... */
|
||||
#define NR_IRQS 21
|
||||
|
||||
#define IRQ_SYSTIMER IRQ_TIMER2
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H */
|
||||
@@ -1,28 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
|
||||
|
||||
#define __arch_getb(a) (*(volatile unsigned char *)(a))
|
||||
#define __arch_getw(a) (*(volatile unsigned short *)(a))
|
||||
#define __arch_getl(a) (*(volatile unsigned int *)(a))
|
||||
|
||||
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
|
||||
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
|
||||
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
|
||||
|
||||
#define __raw_writeb(v,a) __arch_putb(v,a)
|
||||
#define __raw_writew(v,a) __arch_putw(v,a)
|
||||
#define __raw_writel(v,a) __arch_putl(v,a)
|
||||
|
||||
#define __raw_readb(a) __arch_getb(a)
|
||||
#define __raw_readw(a) __arch_getw(a)
|
||||
#define __raw_readl(a) __arch_getl(a)
|
||||
|
||||
#define writeb(v,a) __arch_putb(v,a)
|
||||
#define writew(v,a) __arch_putw(v,a)
|
||||
#define writel(v,a) __arch_putl(v,a)
|
||||
|
||||
#define readb(a) __arch_getb(a)
|
||||
#define readw(a) __arch_getw(a)
|
||||
#define readl(a) __arch_getl(a)
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H */
|
||||
@@ -1,25 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
|
||||
|
||||
/* Enable or Disable a timer */
|
||||
void hwtimer_enable(int num, int on);
|
||||
|
||||
/* Configure pre-scaler and if timer is auto-reload */
|
||||
void hwtimer_config(int num, uint8_t pre_scale, int auto_reload);
|
||||
|
||||
/* Load a timer with the given value */
|
||||
void hwtimer_load(int num, uint16_t val);
|
||||
|
||||
/* Read the current timer value */
|
||||
uint16_t hwtimer_read(int num);
|
||||
|
||||
/* Enable or disable the watchdog */
|
||||
void wdog_enable(int on);
|
||||
|
||||
/* Reset cpu using watchdog */
|
||||
void wdog_reset(void);
|
||||
|
||||
/* power up the timers */
|
||||
void hwtimer_init(void);
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H */
|
||||
@@ -1,6 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
|
||||
void uwire_init(void);
|
||||
int uwire_xfer(int cs, int bitlen, const void *dout, void *din);
|
||||
#endif
|
||||
|
||||
+846
-805
File diff suppressed because it is too large
Load Diff
@@ -44,13 +44,59 @@
|
||||
# include <stdint.h>
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* Include ARM architecture-specific IRQ definitions (including register
|
||||
* save structure and up_irq_save()/up_irq_restore() functions)
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_CORTEXA5) || defined(CONFIG_ARCH_CORTEXA8) || \
|
||||
defined(CONFIG_ARCH_CORTEXA9)
|
||||
# include <arch/armv7-a/spinlock.h>
|
||||
#elif defined(CONFIG_ARCH_CORTEXR4) || defined(CONFIG_ARCH_CORTEXR4F) || \
|
||||
defined(CONFIG_ARCH_CORTEXR5) || defined(CONFIG_ARCH_CORTEXR5F) || \
|
||||
defined(CONFIG_ARCH_CORTEXR7) || defined(CONFIG_ARCH_CORTEXR7F)
|
||||
# include <arch/armv7-r/spinlock.h>
|
||||
#elif defined(CONFIG_ARCH_CORTEXM3) || defined(CONFIG_ARCH_CORTEXM4) || \
|
||||
defined(CONFIG_ARCH_CORTEXM7)
|
||||
# include <arch/armv7-m/spinlock.h>
|
||||
#elif defined(CONFIG_ARCH_CORTEXM0)
|
||||
# include <arch/armv6-m/spinlock.h>
|
||||
#else
|
||||
# include <arch/arm/spinlock.h>
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Spinlock states */
|
||||
|
||||
#define SP_UNLOCKED 0 /* The Un-locked state */
|
||||
#define SP_LOCKED 1 /* The Locked state */
|
||||
|
||||
/* Memory barriers for use with NuttX spinlock logic
|
||||
*
|
||||
* Data Memory Barrier (DMB) acts as a memory barrier. It ensures that all
|
||||
* explicit memory accesses that appear in program order before the DMB
|
||||
* instruction are observed before any explicit memory accesses that appear
|
||||
* in program order after the DMB instruction. It does not affect the
|
||||
* ordering of any other instructions executing on the processor
|
||||
*
|
||||
* dmb st - Data memory barrier. Wait for stores to complete.
|
||||
*
|
||||
* Data Synchronization Barrier (DSB) acts as a special kind of memory
|
||||
* barrier. No instruction in program order after this instruction executes
|
||||
* until this instruction completes. This instruction completes when: (1) All
|
||||
* explicit memory accesses before this instruction complete, and (2) all
|
||||
* Cache, Branch predictor and TLB maintenance operations before this
|
||||
* instruction complete.
|
||||
*
|
||||
* dsb sy - Data syncrhonization barrier. Assures that the CPU waits until
|
||||
* all memory accesses are complete
|
||||
*/
|
||||
|
||||
#define SP_DSB(n) __asm__ __volatile__ ("dsb sy" : : : "memory")
|
||||
#define SP_DMB(n) __asm__ __volatile__ ("dmb st" : : : "memory")
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
@@ -1374,7 +1374,7 @@
|
||||
# define STM32_NLCD 0 /* (0) No LCD */
|
||||
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
|
||||
# define STM32_NGPIO 37 /* GPIOA-F */
|
||||
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
|
||||
# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */
|
||||
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
|
||||
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* (1) CRC calculation unit */
|
||||
@@ -1414,7 +1414,7 @@
|
||||
# define STM32_NLCD 0 /* (0) No LCD */
|
||||
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
|
||||
# define STM32_NGPIO 52 /* GPIOA-F */
|
||||
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
|
||||
# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */
|
||||
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
|
||||
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* (1) CRC calculation unit */
|
||||
@@ -1494,7 +1494,7 @@
|
||||
# define STM32_NLCD 0 /* (0) No LCD */
|
||||
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
|
||||
# define STM32_NGPIO 87 /* GPIOA-F */
|
||||
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
|
||||
# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */
|
||||
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
|
||||
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* (1) CRC calculation unit */
|
||||
|
||||
@@ -77,7 +77,7 @@
|
||||
# define STM32L4_NBTIM 2 /* Two basic timers, TIM6-7 */
|
||||
# define STM32L4_NLPTIM 2 /* Two low-power timers, LPTIM1-2 */
|
||||
# define STM32L4_NRNG 1 /* Random number generator (RNG) */
|
||||
# define STM32L4_NUART 4 /* UART 4-5 */
|
||||
# define STM32L4_NUART 2 /* UART 4-5 */
|
||||
# define STM32L4_NUSART 3 /* USART 1-3 */
|
||||
# define STM32L4_NLPUART 1 /* LPUART 1 */
|
||||
# define STM32L4_NSPI 3 /* SPI1-3 */
|
||||
|
||||
@@ -7,8 +7,8 @@ comment "ARM Configuration Options"
|
||||
|
||||
choice
|
||||
prompt "Toolchain Selection"
|
||||
default ARM_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
|
||||
default ARM_TOOLCHAIN_GNU_EABIL if !HOST_WINDOWS
|
||||
default ARM_TOOLCHAIN_GNU_EABIW if TOOLCHAIN_WINDOWS
|
||||
default ARM_TOOLCHAIN_GNU_EABIL if !TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARM_TOOLCHAIN_BUILDROOT
|
||||
bool "Buildroot (Cygwin or Linux)"
|
||||
@@ -24,11 +24,11 @@ config ARM_TOOLCHAIN_CODESOURCERYL
|
||||
|
||||
config ARM_TOOLCHAIN_CODESOURCERYW
|
||||
bool "CodeSourcery GNU toolchain under Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARM_TOOLCHAIN_DEVKITARM
|
||||
bool "devkitARM GNU toolchain"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARM_TOOLCHAIN_GNU_EABIL
|
||||
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
|
||||
@@ -38,7 +38,7 @@ config ARM_TOOLCHAIN_GNU_EABIL
|
||||
|
||||
config ARM_TOOLCHAIN_GNU_EABIW
|
||||
bool "Generic GNU EABI toolchain under Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
---help---
|
||||
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
|
||||
configured for arm-none-eabi-.
|
||||
|
||||
@@ -7,12 +7,12 @@ comment "ARMV6M Configuration Options"
|
||||
|
||||
choice
|
||||
prompt "Toolchain Selection"
|
||||
default ARMV6M_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
|
||||
default ARMV6M_TOOLCHAIN_GNU_EABIL if !HOST_WINDOWS
|
||||
default ARMV6M_TOOLCHAIN_GNU_EABIW if TOOLCHAIN_WINDOWS
|
||||
default ARMV6M_TOOLCHAIN_GNU_EABIL if !TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARMV6M_TOOLCHAIN_ATOLLIC
|
||||
bool "Atollic Lite/Pro for Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARMV6M_TOOLCHAIN_BUILDROOT
|
||||
bool "Buildroot (Cygwin or Linux)"
|
||||
@@ -24,7 +24,7 @@ config ARMV6M_TOOLCHAIN_CODEREDL
|
||||
|
||||
config ARMV6M_TOOLCHAIN_CODEREDW
|
||||
bool "CodeRed for Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARMV6M_TOOLCHAIN_CODESOURCERYL
|
||||
bool "CodeSourcery GNU toolchain under Linux"
|
||||
@@ -32,11 +32,11 @@ config ARMV6M_TOOLCHAIN_CODESOURCERYL
|
||||
|
||||
config ARMV6M_TOOLCHAIN_CODESOURCERYW
|
||||
bool "CodeSourcery GNU toolchain under Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARMV6M_TOOLCHAIN_DEVKITARM
|
||||
bool "devkitARM GNU toolchain"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARMV6M_TOOLCHAIN_GNU_EABIL
|
||||
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
|
||||
@@ -46,7 +46,7 @@ config ARMV6M_TOOLCHAIN_GNU_EABIL
|
||||
|
||||
config ARMV6M_TOOLCHAIN_GNU_EABIW
|
||||
bool "Generic GNU EABI toolchain under Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
---help---
|
||||
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
|
||||
configured for arm-none-eabi.
|
||||
|
||||
@@ -128,8 +128,8 @@ endif # ARMV7A_HAVE_L2CC
|
||||
|
||||
choice
|
||||
prompt "Toolchain Selection"
|
||||
default ARMV7A_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
|
||||
default ARMV7A_TOOLCHAIN_GNU_EABIL if !HOST_WINDOWS
|
||||
default ARMV7A_TOOLCHAIN_GNU_EABIW if TOOLCHAIN_WINDOWS
|
||||
default ARMV7A_TOOLCHAIN_GNU_EABIL if !TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARMV7A_TOOLCHAIN_BUILDROOT
|
||||
bool "Buildroot (Cygwin or Linux)"
|
||||
@@ -145,11 +145,11 @@ config ARMV7A_TOOLCHAIN_CODESOURCERYL
|
||||
|
||||
config ARMV7A_TOOLCHAIN_CODESOURCERYW
|
||||
bool "CodeSourcery GNU toolchain under Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARMV7A_TOOLCHAIN_DEVKITARM
|
||||
bool "devkitARM GNU toolchain"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARMV7A_TOOLCHAIN_GNU_EABIL
|
||||
bool "Generic GNU EABI toolchain under Linux (or other POSIX environment)"
|
||||
@@ -159,7 +159,7 @@ config ARMV7A_TOOLCHAIN_GNU_EABIL
|
||||
|
||||
config ARMV7A_TOOLCHAIN_GNU_EABIW
|
||||
bool "Generic GNU EABI toolchain under Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
---help---
|
||||
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
|
||||
configured for arm-none-eabi-.
|
||||
|
||||
@@ -53,6 +53,7 @@
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "sched/sched.h"
|
||||
#include "irq/irq.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
@@ -345,10 +346,21 @@ static void _up_assert(int errorcode)
|
||||
|
||||
if (CURRENT_REGS || this_task()->pid == 0)
|
||||
{
|
||||
/* Disable interrupts on this CPU */
|
||||
|
||||
(void)up_irq_save();
|
||||
|
||||
for (; ; )
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
/* Try (again) to stop activity on other CPUs */
|
||||
|
||||
(void)spin_trylock(&g_cpu_irqlock);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
/* FLASH LEDs a 2Hz */
|
||||
|
||||
board_autoled_on(LED_PANIC);
|
||||
up_mdelay(250);
|
||||
board_autoled_off(LED_PANIC);
|
||||
|
||||
@@ -308,7 +308,11 @@ __cpu3_start:
|
||||
orr r0, r0, #(SCTLR_RR)
|
||||
#endif
|
||||
|
||||
#ifndef CPU_DCACHE_DISABLE
|
||||
/* In SMP configurations, the data cache will not be enabled until later
|
||||
* after SMP cache coherency has been setup.
|
||||
*/
|
||||
|
||||
#if 0 /* !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP) */
|
||||
/* Dcache enable
|
||||
*
|
||||
* SCTLR_C Bit 2: DCache enable
|
||||
|
||||
@@ -44,6 +44,7 @@
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/sched.h>
|
||||
#include <nuttx/spinlock.h>
|
||||
#include <nuttx/sched_note.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "gic.h"
|
||||
@@ -55,13 +56,132 @@
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS];
|
||||
static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS];
|
||||
/* These spinlocks are used in the SMP configuration in order to implement
|
||||
* up_cpu_pause(). The protocol for CPUn to pause CPUm is as follows
|
||||
*
|
||||
* 1. The up_cpu_pause() implementation on CPUn locks both g_cpu_wait[m]
|
||||
* and g_cpu_paused[m]. CPUn then waits spinning on g_cpu_paused[m].
|
||||
* 2. CPUm receives the interrupt it (1) unlocks g_cpu_paused[m] and
|
||||
* (2) locks g_cpu_wait[m]. The first unblocks CPUn and the second
|
||||
* blocks CPUm in the interrupt handler.
|
||||
*
|
||||
* When CPUm resumes, CPUn unlocks g_cpu_wait[m] and the interrupt handler
|
||||
* on CPUm continues. CPUm must, of course, also then unlock g_cpu_wait[m]
|
||||
* so that it will be ready for the next pause operation.
|
||||
*/
|
||||
|
||||
static volatile spinlock_t g_cpu_wait[CONFIG_SMP_NCPUS] SP_SECTION;
|
||||
static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS] SP_SECTION;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_cpu_pausereq
|
||||
*
|
||||
* Description:
|
||||
* Return true if a pause request is pending for this CPU.
|
||||
*
|
||||
* Input Parameters:
|
||||
* cpu - The index of the CPU to be queried
|
||||
*
|
||||
* Returned Value:
|
||||
* true = a pause request is pending.
|
||||
* false = no pasue request is pending.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool up_cpu_pausereq(int cpu)
|
||||
{
|
||||
return spin_islocked(&g_cpu_paused[cpu]);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_cpu_paused
|
||||
*
|
||||
* Description:
|
||||
* Handle a pause request from another CPU. Normally, this logic is
|
||||
* executed from interrupt handling logic within the architecture-specific
|
||||
* However, it is sometimes necessary necessary to perform the pending
|
||||
* pause operation in other contexts where the interrupt cannot be taken
|
||||
* in order to avoid deadlocks.
|
||||
*
|
||||
* This function performs the following operations:
|
||||
*
|
||||
* 1. It saves the current task state at the head of the current assigned
|
||||
* task list.
|
||||
* 2. It waits on a spinlock, then
|
||||
* 3. Returns from interrupt, restoring the state of the new task at the
|
||||
* head of the ready to run list.
|
||||
*
|
||||
* Input Parameters:
|
||||
* cpu - The index of the CPU to be paused
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, OK is returned. Otherwise, a negated errno value indicating
|
||||
* the nature of the failure is returned.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_cpu_paused(int cpu)
|
||||
{
|
||||
FAR struct tcb_s *tcb = this_task();
|
||||
|
||||
/* Update scheduler parameters */
|
||||
|
||||
sched_suspend_scheduler(tcb);
|
||||
|
||||
#ifdef CONFIG_SCHED_INSTRUMENTATION
|
||||
/* Notify that we are paused */
|
||||
|
||||
sched_note_cpu_paused(tcb);
|
||||
#endif
|
||||
|
||||
/* Save the current context at CURRENT_REGS into the TCB at the head
|
||||
* of the assigned task list for this CPU.
|
||||
*/
|
||||
|
||||
up_savestate(tcb->xcp.regs);
|
||||
|
||||
/* Release the g_cpu_puased spinlock to synchronize with the
|
||||
* requesting CPU.
|
||||
*/
|
||||
|
||||
spin_unlock(&g_cpu_paused[cpu]);
|
||||
|
||||
/* Wait for the spinlock to be released. The requesting CPU will release
|
||||
* the spinlcok when the CPU is resumed.
|
||||
*/
|
||||
|
||||
spin_lock(&g_cpu_wait[cpu]);
|
||||
|
||||
/* This CPU has been resumed. Restore the exception context of the TCB at
|
||||
* the (new) head of the assigned task list.
|
||||
*/
|
||||
|
||||
tcb = this_task();
|
||||
|
||||
#ifdef CONFIG_SCHED_INSTRUMENTATION
|
||||
/* Notify that we have resumed */
|
||||
|
||||
sched_note_cpu_resumed(tcb);
|
||||
#endif
|
||||
|
||||
/* Reset scheduler parameters */
|
||||
|
||||
sched_resume_scheduler(tcb);
|
||||
|
||||
/* Then switch contexts. Any necessary address environment changes
|
||||
* will be made when the interrupt returns.
|
||||
*/
|
||||
|
||||
up_restorestate(tcb->xcp.regs);
|
||||
spin_unlock(&g_cpu_wait[cpu]);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_pause_handler
|
||||
*
|
||||
@@ -84,40 +204,19 @@ static volatile spinlock_t g_cpu_paused[CONFIG_SMP_NCPUS];
|
||||
|
||||
int arm_pause_handler(int irq, FAR void *context)
|
||||
{
|
||||
FAR struct tcb_s *tcb = this_task();
|
||||
int cpu = up_cpu_index();
|
||||
int cpu = this_cpu();
|
||||
|
||||
/* Update scheduler parameters */
|
||||
|
||||
sched_suspend_scheduler(tcb);
|
||||
|
||||
/* Save the current context at CURRENT_REGS into the TCB at the head of the
|
||||
* assigned task list for this CPU.
|
||||
/* Check for false alarms. Such false could occur as a consequence of
|
||||
* some deadlock breaking logic that might have already serviced the SG2
|
||||
* interrupt by calling up_cpu_paused(). If the pause event has already
|
||||
* been processed then g_cpu_paused[cpu] will not be locked.
|
||||
*/
|
||||
|
||||
up_savestate(tcb->xcp.regs);
|
||||
if (spin_islocked(&g_cpu_paused[cpu]))
|
||||
{
|
||||
return up_cpu_paused(cpu);
|
||||
}
|
||||
|
||||
/* Wait for the spinlock to be released */
|
||||
|
||||
spin_unlock(&g_cpu_paused[cpu]);
|
||||
spin_lock(&g_cpu_wait[cpu]);
|
||||
|
||||
/* Restore the exception context of the tcb at the (new) head of the
|
||||
* assigned task list.
|
||||
*/
|
||||
|
||||
tcb = this_task();
|
||||
|
||||
/* Reset scheduler parameters */
|
||||
|
||||
sched_resume_scheduler(tcb);
|
||||
|
||||
/* Then switch contexts. Any necessary address environment changes will
|
||||
* be made when the interrupt returns.
|
||||
*/
|
||||
|
||||
up_restorestate(tcb->xcp.regs);
|
||||
spin_unlock(&g_cpu_wait[cpu]);
|
||||
return OK;
|
||||
}
|
||||
|
||||
@@ -134,7 +233,7 @@ int arm_pause_handler(int irq, FAR void *context)
|
||||
* CPU.
|
||||
*
|
||||
* Input Parameters:
|
||||
* cpu - The index of the CPU to be stopped/
|
||||
* cpu - The index of the CPU to be stopped
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure.
|
||||
@@ -145,6 +244,12 @@ int up_cpu_pause(int cpu)
|
||||
{
|
||||
int ret;
|
||||
|
||||
#ifdef CONFIG_SCHED_INSTRUMENTATION
|
||||
/* Notify of the pause event */
|
||||
|
||||
sched_note_cpu_pause(this_task(), cpu);
|
||||
#endif
|
||||
|
||||
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
|
||||
|
||||
/* Take the both spinlocks. The g_cpu_wait spinlock will prevent the SGI2
|
||||
@@ -208,6 +313,12 @@ int up_cpu_pause(int cpu)
|
||||
|
||||
int up_cpu_resume(int cpu)
|
||||
{
|
||||
#ifdef CONFIG_SCHED_INSTRUMENTATION
|
||||
/* Notify of the resume event */
|
||||
|
||||
sched_note_cpu_resume(this_task(), cpu);
|
||||
#endif
|
||||
|
||||
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
|
||||
|
||||
/* Release the spinlock. Releasing the spinlock will cause the SGI2
|
||||
|
||||
@@ -43,10 +43,11 @@
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/sched.h>
|
||||
#include <nuttx/sched_note.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "gic.h"
|
||||
#include "cp15_cacheops.h"
|
||||
#include "gic.h"
|
||||
#include "sched/sched.h"
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
@@ -104,13 +105,18 @@ static inline void arm_registerdump(FAR struct tcb_s *tcb)
|
||||
|
||||
int arm_start_handler(int irq, FAR void *context)
|
||||
{
|
||||
FAR struct tcb_s *tcb;
|
||||
FAR struct tcb_s *tcb = this_task();
|
||||
|
||||
sinfo("CPU%d Started\n", up_cpu_index());
|
||||
sinfo("CPU%d Started\n", this_cpu());
|
||||
|
||||
#ifdef CONFIG_SCHED_INSTRUMENTATION
|
||||
/* Notify that this CPU has started */
|
||||
|
||||
sched_note_cpu_started(tcb);
|
||||
#endif
|
||||
|
||||
/* Reset scheduler parameters */
|
||||
|
||||
tcb = this_task();
|
||||
sched_resume_scheduler(tcb);
|
||||
|
||||
/* Dump registers so that we can see what is going to happen on return */
|
||||
@@ -159,6 +165,12 @@ int up_cpu_start(int cpu)
|
||||
|
||||
DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS && cpu != this_cpu());
|
||||
|
||||
#ifdef CONFIG_SCHED_INSTRUMENTATION
|
||||
/* Notify of the start event */
|
||||
|
||||
sched_note_cpu_start(this_task(), cpu);
|
||||
#endif
|
||||
|
||||
/* Make the content of CPU0 L1 cache has been written to coherent L2 */
|
||||
|
||||
cp15_clean_dcache(CONFIG_RAM_START, CONFIG_RAM_END - 1);
|
||||
|
||||
@@ -40,10 +40,10 @@
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
@@ -51,21 +51,40 @@
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "group/group.h"
|
||||
#include "gic.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* A bit set of pending, non-maskable SGI interrupts, on bit set for each
|
||||
* supported CPU.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARMV7A_HAVE_GICv2
|
||||
#ifdef CONFIG_SMP
|
||||
static uint16_t g_sgi_pending[CONFIG_SMP_NCPUS];
|
||||
#else
|
||||
static uint16_t g_sgi_pending[1];
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t *arm_doirq(int irq, uint32_t *regs)
|
||||
/****************************************************************************
|
||||
* Name: _arm_doirq
|
||||
*
|
||||
* Description:
|
||||
* Receives the one decoded interrupt and dispatches control to the
|
||||
* attached interrupt handler.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
static inline uint32_t *_arm_doirq(int irq, uint32_t *regs)
|
||||
{
|
||||
board_autoled_on(LED_INIRQ);
|
||||
#ifdef CONFIG_SUPPRESS_INTERRUPTS
|
||||
PANIC();
|
||||
#else
|
||||
/* Nested interrupts are not supported */
|
||||
|
||||
DEBUGASSERT(CURRENT_REGS == NULL);
|
||||
|
||||
/* Current regs non-zero indicates that we are processing an interrupt;
|
||||
* CURRENT_REGS is also used to manage interrupt level context switches.
|
||||
*/
|
||||
@@ -110,8 +129,131 @@ uint32_t *arm_doirq(int irq, uint32_t *regs)
|
||||
|
||||
regs = (uint32_t *)CURRENT_REGS;
|
||||
CURRENT_REGS = NULL;
|
||||
|
||||
return regs;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_doirq
|
||||
*
|
||||
* Description:
|
||||
* Receives the decoded GIC interrupt information and dispatches control
|
||||
* to the attached interrupt handler. There are two versions:
|
||||
*
|
||||
* 1) For the simple case where all interrupts are maskable. In that
|
||||
* simple case, arm_doirq() is simply a wrapper for the inlined
|
||||
* _arm_do_irq() that does the real work.
|
||||
*
|
||||
* 2) With the GICv2, there are 16 non-maskable software generated
|
||||
* interrupts (SGIs) that also come through arm_doirq(). In that case,
|
||||
* we must avoid nesting interrupt handling and serial the processing.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARMV7A_HAVE_GICv2
|
||||
uint32_t *arm_doirq(int irq, uint32_t *regs)
|
||||
{
|
||||
board_autoled_on(LED_INIRQ);
|
||||
#ifdef CONFIG_SUPPRESS_INTERRUPTS
|
||||
PANIC();
|
||||
#else
|
||||
/* Nested interrupts are not supported */
|
||||
|
||||
DEBUGASSERT(CURRENT_REGS == NULL);
|
||||
|
||||
/* Dispatch the interrupt to its attached handler */
|
||||
|
||||
regs = _arm_doirq(irq, regs);
|
||||
#endif
|
||||
|
||||
board_autoled_off(LED_INIRQ);
|
||||
return regs;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARMV7A_HAVE_GICv2
|
||||
uint32_t *arm_doirq(int irq, uint32_t *regs)
|
||||
{
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
uint32_t bit;
|
||||
int cpu;
|
||||
int i;
|
||||
#endif
|
||||
|
||||
board_autoled_on(LED_INIRQ);
|
||||
#ifdef CONFIG_SUPPRESS_INTERRUPTS
|
||||
PANIC();
|
||||
|
||||
#else
|
||||
/* Get the CPU processing the interrupt */
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
cpu = up_cpu_index();
|
||||
#else
|
||||
cpu = 0;
|
||||
#endif
|
||||
|
||||
/* Non-zero CURRENT_REGS indicates that we are already processing an
|
||||
* interrupt. This could be a normal event for the case of the GICv2;
|
||||
* Software generated interrupts are non-maskable.
|
||||
*
|
||||
* REVISIT: There is no support for nested SGIs! That will cause an
|
||||
* assertion below. There is also no protection for concurrent access
|
||||
* to g_sgi_pending for that case.
|
||||
*/
|
||||
|
||||
if (CURRENT_REGS != NULL)
|
||||
{
|
||||
int ndx = irq - GIC_IRQ_SGI0;
|
||||
bit = (1 << (ndx));
|
||||
|
||||
/* Only an SGI should cause this event. We also cannot support
|
||||
* multiple pending SGI interrupts.
|
||||
*/
|
||||
|
||||
ASSERT((unsigned int)irq <= GIC_IRQ_SGI15 &&
|
||||
(g_sgi_pending[cpu] & bit) == 0);
|
||||
|
||||
/* Mare the SGI as pending and return immediately */
|
||||
|
||||
sinfo("SGI%d pending\n", ndx);
|
||||
g_sgi_pending[cpu] |= bit;
|
||||
return regs;
|
||||
}
|
||||
|
||||
/* Dispatch the interrupt to its attached handler */
|
||||
|
||||
regs = _arm_doirq(irq, regs);
|
||||
|
||||
/* Then loop dispatching any pending SGI interrupts that occcurred during
|
||||
* processing of the interrupts.
|
||||
*/
|
||||
|
||||
for (i = 0; i < 16 && g_sgi_pending[cpu] != 0; i++)
|
||||
{
|
||||
/* Check if this SGI is pending */
|
||||
|
||||
bit = (1 << i);
|
||||
if ((g_sgi_pending[cpu] & bit) != 0)
|
||||
{
|
||||
/* Clear the pending bit */
|
||||
|
||||
g_sgi_pending[cpu] &= ~bit;
|
||||
|
||||
/* And dispatch the SGI */
|
||||
|
||||
sinfo("Dispatching pending SGI%d\n", i + GIC_IRQ_SGI0);
|
||||
regs = _arm_doirq(i + GIC_IRQ_SGI0, regs);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
board_autoled_off(LED_INIRQ);
|
||||
return regs;
|
||||
}
|
||||
#endif
|
||||
|
||||
@@ -122,7 +122,7 @@ void arm_gic0_initialize(void)
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/* Attach SGI interrupt handlers */
|
||||
/* Attach SGI interrupt handlers. This attaches the handler for all CPUs. */
|
||||
|
||||
DEBUGVERIFY(irq_attach(GIC_IRQ_SGI1, arm_start_handler));
|
||||
DEBUGVERIFY(irq_attach(GIC_IRQ_SGI2, arm_pause_handler));
|
||||
@@ -574,5 +574,4 @@ int arm_gic_irq_trigger(int irq, bool edge)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
|
||||
#endif /* CONFIG_ARMV7A_HAVE_GICv2 */
|
||||
|
||||
@@ -450,7 +450,11 @@ __start:
|
||||
orr r0, r0, #(SCTLR_RR)
|
||||
#endif
|
||||
|
||||
#ifndef CPU_DCACHE_DISABLE
|
||||
/* In SMP configurations, the data cache will not be enabled until later
|
||||
* after SMP cache coherency has been setup.
|
||||
*/
|
||||
|
||||
#if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP)
|
||||
/* Dcache enable
|
||||
*
|
||||
* SCTLR_C Bit 2: DCache enable
|
||||
@@ -638,7 +642,7 @@ __start:
|
||||
#endif
|
||||
|
||||
/* Perform early C-level, platform-specific initialization. Logic
|
||||
* within arm_boot() must configure SDRAM and call arm_ram_initailize.
|
||||
* within arm_boot() must configure SDRAM and call arm_data_initialize().
|
||||
*/
|
||||
|
||||
bl arm_boot
|
||||
|
||||
@@ -434,7 +434,11 @@ __start:
|
||||
orr r0, r0, #(SCTLR_RR)
|
||||
#endif
|
||||
|
||||
#ifndef CPU_DCACHE_DISABLE
|
||||
/* In SMP configurations, the data cache will not be enabled until later
|
||||
* after SMP cache coherency has been setup.
|
||||
*/
|
||||
|
||||
#if !defined(CPU_DCACHE_DISABLE) && !defined(CONFIG_SMP)
|
||||
/* Dcache enable
|
||||
*
|
||||
* SCTLR_C Bit 2: DCache enable
|
||||
@@ -670,7 +674,7 @@ __start:
|
||||
#endif
|
||||
|
||||
/* Perform early C-level, platform-specific initialization. Logic
|
||||
* within arm_boot() must configure SDRAM and call arm_ram_initailize.
|
||||
* within arm_boot() must configure SDRAM and call arm_data_initialize().
|
||||
*/
|
||||
|
||||
bl arm_boot
|
||||
|
||||
@@ -1,7 +1,7 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-a/arm_schedulesigaction.c
|
||||
*
|
||||
* Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2013, 2015-2017 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -51,6 +51,8 @@
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "irq/irq.h"
|
||||
|
||||
#ifndef CONFIG_DISABLE_SIGNALS
|
||||
|
||||
/****************************************************************************
|
||||
@@ -90,6 +92,7 @@
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_SMP
|
||||
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
{
|
||||
irqstate_t flags;
|
||||
@@ -105,7 +108,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
if (!tcb->xcp.sigdeliver)
|
||||
{
|
||||
/* First, handle some special cases when the signal is being delivered
|
||||
* to the currently executing task.
|
||||
* to task that is currently executing on this CPU.
|
||||
*/
|
||||
|
||||
sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
|
||||
@@ -142,16 +145,16 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
* the signals have been delivered.
|
||||
*/
|
||||
|
||||
tcb->xcp.sigdeliver = sigdeliver;
|
||||
tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
|
||||
tcb->xcp.saved_cpsr = CURRENT_REGS[REG_CPSR];
|
||||
tcb->xcp.sigdeliver = sigdeliver;
|
||||
tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
|
||||
tcb->xcp.saved_cpsr = CURRENT_REGS[REG_CPSR];
|
||||
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled
|
||||
*/
|
||||
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
|
||||
/* And make sure that the saved context in the TCB is the same
|
||||
* as the interrupt return context.
|
||||
@@ -163,7 +166,7 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
|
||||
/* Otherwise, we are (1) signaling a task is not running from an
|
||||
* interrupt handler or (2) we are not in an interrupt handler and the
|
||||
* running task is signalling some non-running task.
|
||||
* running task is signalling some other non-running task.
|
||||
*/
|
||||
|
||||
else
|
||||
@@ -173,20 +176,189 @@ void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
* have been delivered.
|
||||
*/
|
||||
|
||||
tcb->xcp.sigdeliver = sigdeliver;
|
||||
tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
|
||||
tcb->xcp.saved_cpsr = tcb->xcp.regs[REG_CPSR];
|
||||
tcb->xcp.sigdeliver = sigdeliver;
|
||||
tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
|
||||
tcb->xcp.saved_cpsr = tcb->xcp.regs[REG_CPSR];
|
||||
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#endif /* !CONFIG_SMP */
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver)
|
||||
{
|
||||
irqstate_t flags;
|
||||
int cpu;
|
||||
int me;
|
||||
|
||||
sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver);
|
||||
|
||||
/* Make sure that interrupts are disabled */
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
/* Refuse to handle nested signal actions */
|
||||
|
||||
if (!tcb->xcp.sigdeliver)
|
||||
{
|
||||
/* First, handle some special cases when the signal is being delivered
|
||||
* to task that is currently executing on any CPU.
|
||||
*/
|
||||
|
||||
sinfo("rtcb=0x%p CURRENT_REGS=0x%p\n", this_task(), CURRENT_REGS);
|
||||
|
||||
if (tcb->task_state == TSTATE_TASK_RUNNING)
|
||||
{
|
||||
me = this_cpu();
|
||||
cpu = tcb->cpu;
|
||||
|
||||
/* CASE 1: We are not in an interrupt handler and a task is
|
||||
* signalling itself for some reason.
|
||||
*/
|
||||
|
||||
if (cpu == me && !CURRENT_REGS)
|
||||
{
|
||||
/* In this case just deliver the signal now. */
|
||||
|
||||
sigdeliver(tcb);
|
||||
}
|
||||
|
||||
/* CASE 2: The task that needs to receive the signal is running.
|
||||
* This could happen if the task is running on another CPU OR if
|
||||
* we are in an interrupt handler and the task is running on this
|
||||
* CPU. In the former case, we will have to PAUSE the other CPU
|
||||
* first. But in either case, we will have to modify the return
|
||||
* state as well as the state in the TCB.
|
||||
*
|
||||
* Hmmm... there looks like a latent bug here: The following logic
|
||||
* would fail in the strange case where we are in an interrupt
|
||||
* handler, the thread is signalling itself, but a context switch
|
||||
* to another task has occurred so that CURRENT_REGS does not
|
||||
* refer to the thread of this_task()!
|
||||
*/
|
||||
|
||||
else
|
||||
{
|
||||
/* If we signalling a task running on the other CPU, we have
|
||||
* to PAUSE the other CPU.
|
||||
*/
|
||||
|
||||
if (cpu != me)
|
||||
{
|
||||
up_cpu_pause(cpu);
|
||||
}
|
||||
|
||||
/* Save the return lr and cpsr and one scratch register
|
||||
* These will be restored by the signal trampoline after
|
||||
* the signals have been delivered.
|
||||
*/
|
||||
|
||||
tcb->xcp.sigdeliver = sigdeliver;
|
||||
tcb->xcp.saved_pc = CURRENT_REGS[REG_PC];
|
||||
tcb->xcp.saved_cpsr = CURRENT_REGS[REG_CPSR];
|
||||
|
||||
/* Increment the IRQ lock count so that when the task is restarted,
|
||||
* it will hold the IRQ spinlock.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(tcb->irqcount < INT16_MAX);
|
||||
tcb->irqcount++;
|
||||
|
||||
/* Handle a possible race condition where the TCB was suspended
|
||||
* just before we paused the other CPU. The critical section
|
||||
* established above will prevent new threads from running on
|
||||
* that CPU, but it will not guarantee that the running thread
|
||||
* did not suspend itself (allowing any threads "assigned" to
|
||||
* the CPU to run).
|
||||
*/
|
||||
|
||||
if (tcb->task_state != TSTATE_TASK_RUNNING)
|
||||
{
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled
|
||||
*/
|
||||
|
||||
CURRENT_REGS[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
CURRENT_REGS[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
|
||||
/* In an SMP configuration, the interrupt disable logic also
|
||||
* involves spinlocks that are configured per the TCB irqcount
|
||||
* field. This is logically equivalent to enter_critical_section().
|
||||
* The matching call to leave_critical_section() will be
|
||||
* performed in up_sigdeliver().
|
||||
*/
|
||||
|
||||
spin_setbit(&g_cpu_irqset, cpu, &g_cpu_irqsetlock,
|
||||
&g_cpu_irqlock);
|
||||
|
||||
/* And make sure that the saved context in the TCB is the same
|
||||
* as the interrupt return context.
|
||||
*/
|
||||
|
||||
up_savestate(tcb->xcp.regs);
|
||||
}
|
||||
|
||||
/* RESUME the other CPU if it was PAUSED */
|
||||
|
||||
if (cpu != me)
|
||||
{
|
||||
up_cpu_resume(cpu);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Otherwise, we are (1) signaling a task is not running from an
|
||||
* interrupt handler or (2) we are not in an interrupt handler and the
|
||||
* running task is signalling some other non-running task.
|
||||
*/
|
||||
|
||||
else
|
||||
{
|
||||
/* Save the return lr and cpsr and one scratch register. These
|
||||
* will be restored by the signal trampoline after the signals
|
||||
* have been delivered.
|
||||
*/
|
||||
|
||||
tcb->xcp.sigdeliver = sigdeliver;
|
||||
tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC];
|
||||
tcb->xcp.saved_cpsr = tcb->xcp.regs[REG_CPSR];
|
||||
|
||||
/* Increment the IRQ lock count so that when the task is restarted,
|
||||
* it will hold the IRQ spinlock.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(tcb->irqcount < INT16_MAX);
|
||||
tcb->irqcount++;
|
||||
|
||||
/* Then set up to vector to the trampoline with interrupts
|
||||
* disabled
|
||||
*/
|
||||
|
||||
tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver;
|
||||
tcb->xcp.regs[REG_CPSR] = (PSR_MODE_SVC | PSR_I_BIT | PSR_F_BIT);
|
||||
}
|
||||
}
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#endif /* CONFIG_SMP */
|
||||
|
||||
#endif /* !CONFIG_DISABLE_SIGNALS */
|
||||
|
||||
@@ -0,0 +1,227 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-a/arm_scu.c
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "cp15_cacheops.h"
|
||||
#include "sctlr.h"
|
||||
#include "cache.h"
|
||||
#include "scu.h"
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_get_sctlr
|
||||
*
|
||||
* Description:
|
||||
* Get the contents of the SCTLR register
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline uint32_t arm_get_sctlr(void)
|
||||
{
|
||||
uint32_t sctlr;
|
||||
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmrc p15, 0, %0, c1, c0, 0\n" /* Read SCTLR */
|
||||
: "=r"(sctlr)
|
||||
:
|
||||
:
|
||||
);
|
||||
|
||||
return sctlr;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_set_sctlr
|
||||
*
|
||||
* Description:
|
||||
* Set the contents of the SCTLR register
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void arm_set_sctlr(uint32_t sctlr)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmcr p15, 0, %0, c1, c0, 0\n" /* Write SCTLR */
|
||||
:
|
||||
: "r"(sctlr)
|
||||
:
|
||||
);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_get_actlr
|
||||
*
|
||||
* Description:
|
||||
* Get the contents of the ACTLR register
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline uint32_t arm_get_actlr(void)
|
||||
{
|
||||
uint32_t actlr;
|
||||
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmrc p15, 0, %0, c1, c0, 1\n" /* Read ACTLR */
|
||||
: "=r"(actlr)
|
||||
:
|
||||
:
|
||||
);
|
||||
|
||||
return actlr;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_set_actlr
|
||||
*
|
||||
* Description:
|
||||
* Set the contents of the ACTLR register
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void arm_set_actlr(uint32_t actlr)
|
||||
{
|
||||
__asm__ __volatile__
|
||||
(
|
||||
"\tmcr p15, 0, %0, c1, c0, 1\n" /* Write ACTLR */
|
||||
:
|
||||
: "r"(actlr)
|
||||
:
|
||||
);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_enable_smp
|
||||
*
|
||||
* Description:
|
||||
* Enable the SCU and make certain that current CPU is participating in
|
||||
* the SMP cache coherency.
|
||||
*
|
||||
* Assumption:
|
||||
* Called early in the CPU start-up. No special critical sections are
|
||||
* needed if only CPU-private registers are modified.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void arm_enable_smp(int cpu)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Handle actions unique to CPU0 which comes up first */
|
||||
|
||||
if (cpu == 0)
|
||||
{
|
||||
/* Invalidate the SCU duplicate tags for all processors */
|
||||
|
||||
putreg32((SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU0_SHIFT) |
|
||||
(SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU1_SHIFT) |
|
||||
(SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU2_SHIFT) |
|
||||
(SCU_INVALIDATE_ALL_WAYS << SCU_INVALIDATE_CPU3_SHIFT),
|
||||
SCU_INVALIDATE);
|
||||
|
||||
/* Invalidate CPUn L1 data cache so that is will we be reloaded from
|
||||
* coherent L2.
|
||||
*/
|
||||
|
||||
cp15_invalidate_dcache_all();
|
||||
ARM_DSB();
|
||||
|
||||
/* Invalidate the L2C-310 -- Missing logic. */
|
||||
|
||||
/* Enable the SCU */
|
||||
|
||||
regval = getreg32(SCU_CTRL);
|
||||
regval |= SCU_CTRL_ENABLE;
|
||||
putreg32(regval, SCU_CTRL);
|
||||
}
|
||||
|
||||
/* Actions for other CPUs */
|
||||
|
||||
else
|
||||
{
|
||||
/* Invalidate CPUn L1 data cache so that is will we be reloaded from
|
||||
* coherent L2.
|
||||
*/
|
||||
|
||||
cp15_invalidate_dcache_all();
|
||||
ARM_DSB();
|
||||
|
||||
/* Wait for the SCU to be enabled by the primary processor -- should
|
||||
* not be necessary.
|
||||
*/
|
||||
}
|
||||
|
||||
/* Enable the data cache, set the SMP mode with ACTLR.SMP=1.
|
||||
*
|
||||
* SMP - Sgnals if the Cortex-A9 processor is taking part in coherency
|
||||
* or not.
|
||||
*
|
||||
* Cortex-A9 also needs ACTLR.FW=1
|
||||
*
|
||||
* FW - Cache and TLB maintenance broadcast.
|
||||
*/
|
||||
|
||||
regval = arm_get_actlr();
|
||||
regval |= ACTLR_SMP;
|
||||
#ifdef CONFIG_ARCH_CORTEXA9
|
||||
regval |= ACTLR_FW;
|
||||
#endif
|
||||
arm_set_actlr(regval);
|
||||
|
||||
regval = arm_get_sctlr();
|
||||
regval |= SCTLR_C;
|
||||
arm_set_sctlr(regval);
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -1,7 +1,7 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-a/arm_sigdeliver.c
|
||||
*
|
||||
* Copyright (C) 2013, 2015 Gregory Nutt. All rights reserved.
|
||||
* Copyright (C) 2013, 2015-2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
@@ -103,18 +103,27 @@ void up_sigdeliver(void)
|
||||
|
||||
/* Then restore the task interrupt state */
|
||||
|
||||
up_irq_restore(regs[REG_CPSR]);
|
||||
leave_critical_section(regs[REG_CPSR]);
|
||||
|
||||
/* Deliver the signals */
|
||||
/* Deliver the signal */
|
||||
|
||||
sigdeliver(rtcb);
|
||||
|
||||
/* Output any debug messages BEFORE restoring errno (because they may
|
||||
* alter errno), then disable interrupts again and restore the original
|
||||
* errno that is needed by the user logic (it is probably EINTR).
|
||||
*
|
||||
* REVISIT: In SMP mode up_irq_save() probably only disables interrupts
|
||||
* on the local CPU. We do not want to call enter_critical_section()
|
||||
* here, however, because we don't want this state to stick after the
|
||||
* call to up_fullcontextrestore().
|
||||
*
|
||||
* I would prefer that all interrupts are disabled when
|
||||
* up_fullcontextrestore() is called, but that may not be necessary.
|
||||
*/
|
||||
|
||||
sinfo("Resuming\n");
|
||||
|
||||
(void)up_irq_save();
|
||||
rtcb->pterrno = saved_errno;
|
||||
|
||||
|
||||
@@ -75,7 +75,7 @@
|
||||
* This function must be provided via the architecture-specific logoic.
|
||||
*
|
||||
* Input Parameters:
|
||||
* lock - The address of spinlock object.
|
||||
* lock - The address of spinlock object (r0).
|
||||
*
|
||||
* Returned Value:
|
||||
* The spinlock is always locked upon return. The value of previous value
|
||||
@@ -84,6 +84,8 @@
|
||||
* obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
|
||||
* (meaning that we successfully obtained the lock)
|
||||
*
|
||||
* Modifies: r1, r2, and lr
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl up_testset
|
||||
@@ -98,7 +100,7 @@ up_testset:
|
||||
1:
|
||||
ldrexb r2, [r0] /* Test if spinlock is locked or not */
|
||||
cmp r2, r1 /* Already locked? */
|
||||
beq 2f /* If alrady locked, return SP_LOCKED */
|
||||
beq 2f /* If already locked, return SP_LOCKED */
|
||||
|
||||
/* Not locked ... attempt to lock it */
|
||||
|
||||
|
||||
@@ -64,6 +64,10 @@ g_fiqtmp:
|
||||
.word 0 /* Saved lr */
|
||||
.word 0 /* Saved spsr */
|
||||
#endif
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3 && defined(CONFIG_ARMV7A_HAVE_GICv2)
|
||||
g_nestlevel:
|
||||
.word 0 /* Interrupt nesting level */
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
@@ -172,13 +176,53 @@ arm_vectorirq:
|
||||
mov r0, sp /* Get r0=xcp */
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
#ifdef CONFIG_ARMV7A_HAVE_GICv2
|
||||
/* We will switch to the interrupt stack, UNLESS we are processing a
|
||||
* nested interrupt in which case we are already using the interrupt
|
||||
* stack. SGI interrupts may be nested because they are non-maskable.
|
||||
*/
|
||||
|
||||
ldr r5, .Lirqnestlevel /* r1=Points to interrupt nesting level */
|
||||
ldr r1, [r5] /* Get r1= nesting level */
|
||||
add r1, r1, #1 /* Increment nesting level */
|
||||
str r1, [r5] /* Save r1= nesting level */
|
||||
|
||||
cmp r1, #1 /* r1>1 if nested */
|
||||
bgt .Lintnested /* Use current SP if nested */
|
||||
#endif
|
||||
|
||||
/* Call arm_decodeirq() on the interrupt stack */
|
||||
|
||||
ldr sp, .Lirqstackbase /* SP = interrupt stack base */
|
||||
str r0, [sp] /* Save the user stack pointer */
|
||||
mov r4, sp /* Save the SP in a preserved register */
|
||||
bic sp, sp, #7 /* Force 8-byte alignment */
|
||||
bl arm_decodeirq /* Call the handler */
|
||||
ldr sp, [r4] /* Restore the user stack pointer */
|
||||
|
||||
#ifdef CONFIG_ARMV7A_HAVE_GICv2
|
||||
b .Lintreturn
|
||||
|
||||
/* Call arm_decodeirq() on whatever stack is in place */
|
||||
|
||||
.Lintnested:
|
||||
mov r4, sp /* Save the SP in a preserved register */
|
||||
bic sp, sp, #7 /* Force 8-byte alignment */
|
||||
bl arm_decodeirq /* Call the handler */
|
||||
mov sp, r4 /* Restore the possibly unaligned stack pointer */
|
||||
|
||||
/* Decrement the nesting level (r5 should be preserved) */
|
||||
|
||||
.Lintreturn:
|
||||
ldr r1, [r5] /* Get r1= nesting level */
|
||||
cmp r1, #0 /* A sanity check*/
|
||||
subgt r1, r1, #1 /* Decrement nesting level */
|
||||
strgt r1, [r5] /* Save r1= nesting level */
|
||||
#endif
|
||||
|
||||
#else
|
||||
/* Call arm_decodeirq() on the user stack */
|
||||
|
||||
mov r4, sp /* Save the SP in a preserved register */
|
||||
bic sp, sp, #7 /* Force 8-byte alignment */
|
||||
bl arm_decodeirq /* Call the handler */
|
||||
@@ -227,6 +271,10 @@ arm_vectorirq:
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
.Lirqstackbase:
|
||||
.word g_intstackbase
|
||||
#ifdef CONFIG_ARMV7A_HAVE_GICv2
|
||||
.Lirqnestlevel:
|
||||
.word g_nestlevel
|
||||
#endif
|
||||
#endif
|
||||
.size arm_vectorirq, . - arm_vectorirq
|
||||
.align 5
|
||||
@@ -937,7 +985,7 @@ arm_vectorfiq:
|
||||
.word g_fiqtmp
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
.Lfiqstackbase:
|
||||
.word g_intstackbase
|
||||
.word g_fiqstackbase
|
||||
#endif
|
||||
|
||||
#else
|
||||
@@ -965,5 +1013,21 @@ g_intstackbase:
|
||||
.size g_intstackbase, 4
|
||||
.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
|
||||
|
||||
.globl g_fiqstackalloc
|
||||
.type g_fiqstackalloc, object
|
||||
.globl g_fiqstackbase
|
||||
.type g_fiqstackbase, object
|
||||
|
||||
/************************************************************************************
|
||||
* Name: g_fiqstackalloc/g_fiqstackbase
|
||||
************************************************************************************/
|
||||
|
||||
g_fiqstackalloc:
|
||||
.skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
|
||||
g_fiqstackbase:
|
||||
.skip 4
|
||||
.size g_fiqstackbase, 4
|
||||
.size g_fiqstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
|
||||
|
||||
#endif /* CONFIG_ARCH_INTERRUPTSTACK > 3 */
|
||||
.end
|
||||
|
||||
@@ -50,6 +50,16 @@
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Intrinsics are used in these inline functions */
|
||||
|
||||
#define arm_isb(n) __asm__ __volatile__ ("isb " #n : : : "memory")
|
||||
#define arm_dsb(n) __asm__ __volatile__ ("dsb " #n : : : "memory")
|
||||
#define arm_dmb(n) __asm__ __volatile__ ("dmb " #n : : : "memory")
|
||||
|
||||
#define ARM_DSB() arm_dsb(15)
|
||||
#define ARM_ISB() arm_isb(15)
|
||||
#define ARM_DMB() arm_dmb(15)
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
@@ -513,7 +513,6 @@
|
||||
* NMRR registers. For the simple case where TEX[2:0] = 0b000, the control
|
||||
* is as follows:
|
||||
*
|
||||
*
|
||||
* MEMORY INNER OUTER OUTER SHAREABLE
|
||||
* C B TYPE CACHEABILITY CACHEABILITY ATTRIBUTE
|
||||
* - - ---------- ------------- ------------ -----------------
|
||||
@@ -602,7 +601,6 @@
|
||||
#define MMU_L2_PGTABFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_RW1)
|
||||
|
||||
#define MMU_L1_VECTORFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_PTE_DOM(0))
|
||||
|
||||
#define MMU_L2_VECTRWFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_RW1)
|
||||
#define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_R1)
|
||||
#define MMU_L2_VECTORFLAGS MMU_L2_VECTRWFLAGS
|
||||
@@ -1424,6 +1422,28 @@ void mmu_l1_restore(uintptr_t vaddr, uint32_t l1entry);
|
||||
# define mmu_l1_clrentry(v) mmu_l1_restore(v,0)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: mmu_l2_setentry
|
||||
*
|
||||
* Description:
|
||||
* Set one small (4096B) entry in a level2 translation table.
|
||||
*
|
||||
* Input Parameters:
|
||||
* l2vaddr - the virtual address of the beginning of the L2 translation
|
||||
* table.
|
||||
* paddr - The physical address to be mapped. Must be aligned to a 4KB
|
||||
* address boundary
|
||||
* vaddr - The virtual address to be mapped. Must be aligned to a 4KB
|
||||
* address boundary
|
||||
* mmuflags - The MMU flags to use in the mapping.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARCH_ROMPGTABLE
|
||||
void mmu_l2_setentry(uint32_t l2vaddr, uint32_t paddr, uint32_t vaddr,
|
||||
uint32_t mmuflags);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: mmu_l1_map_region
|
||||
*
|
||||
|
||||
@@ -0,0 +1,176 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/armv7-a/scu.h
|
||||
* Generic Interrupt Controller Definitions
|
||||
*
|
||||
* Copyright (C) 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Reference:
|
||||
* Cortex™-A9 MPCore, Revision: r4p1, Technical Reference Manual, ARM DDI
|
||||
* 0407I (ID091612).
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_ARMV7_A_SCU_H
|
||||
#define __ARCH_ARM_SRC_ARMV7_A_SCU_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include "mpcore.h" /* For MPCORE_SCU_VBASE */
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#define SCU_CTRL_OFFSET 0x0000 /* SCU Control Register (Implementation defined) */
|
||||
#define SCU_CONFIG_OFFSET 0x0004 /* SCU Configuration Register (Implementation defined) */
|
||||
#define SCU_PWRSTATUS_OFFSET 0x0008 /* SCU CPU Power Status Register */
|
||||
#define SCU_INVALIDATE_OFFSET 0x000c /* SCU Invalidate All Registers in Secure State */
|
||||
#define SCU_FILTERSTART_OFFSET 0x0040 /* Filtering Start Address Register Defined by FILTERSTART input */
|
||||
#define SCU_FILTEREND_OFFSET 0x0044 /* Filtering End Address Register Defined by FILTEREND input */
|
||||
#define SCU_SAC_OFFSET 0x0050 /* SCU Access Control (SAC) Register */
|
||||
#define SCU_SNSAC_OFFSET 0x0054 /* SCU Non-secure Access Control (SNSAC) Register */
|
||||
|
||||
/* Register addresses *******************************************************/
|
||||
|
||||
#define SCU_CTRL (MPCORE_SCU_VBASE+SCU_CTRL_OFFSET)
|
||||
#define SCU_CONFIG (MPCORE_SCU_VBASE+SCU_CONFIG_OFFSET)
|
||||
#define SCU_PWRSTATUS (MPCORE_SCU_VBASE+SCU_PWRSTATUS_OFFSET)
|
||||
#define SCU_INVALIDATE (MPCORE_SCU_VBASE+SCU_INVALIDATE_OFFSET)
|
||||
#define SCU_FILTERSTART (MPCORE_SCU_VBASE+SCU_FILTERSTART_OFFSET)
|
||||
#define SCU_FILTEREND (MPCORE_SCU_VBASE+SCU_FILTEREND_OFFSET)
|
||||
#define SCU_SAC (MPCORE_SCU_VBASE+SCU_SAC_OFFSET)
|
||||
#define SCU_SNSAC (MPCORE_SCU_VBASE+SCU_SNSAC_OFFSET)
|
||||
|
||||
/* Register bit-field definitions *******************************************/
|
||||
|
||||
/* SCU Control Register (Implementation defined) */
|
||||
|
||||
#define SCU_CTRL_ENABLE (1 << 0) /* SCU enable */
|
||||
#define SCU_CTRL_ADDRFILTER (1 << 1) /* Address filtering enable */
|
||||
#define SCU_CTRL_RAMPARITY (1 << 2) /* SCU RAMs parity enable */
|
||||
#define SCU_CTRL_LINFILL (1 << 3) /* SCU speculative linefill enable */
|
||||
#define SCU_CTRL_PORT0 (1 << 4) /* Force all device to port0 enable */
|
||||
#define SCU_CTRL_STANDBY (1 << 5) /* SCU standby enable */
|
||||
#define SCU_CTRL_ICSTANDBY (1 << 6) /* IC standby enable */
|
||||
|
||||
/* SCU Configuration Register (Implementation defined) */
|
||||
|
||||
#define SCU_CONFIG_NCPUS_SHIFT 0 /* CPU number Number of CPUs present */
|
||||
#define SCU_CONFIG_NCPUS_MASK (3 << SCU_CONFIG_NCPUS_SHIFT)
|
||||
# define SCU_CONFIG_NCPUS(r) ((((uint32_t)(r) & SCU_CONFIG_NCPUS_MASK) >> SCU_CONFIG_NCPUS_SHIFT) + 1)
|
||||
#define SCU_CONFIG_SMPCPUS_SHIFT 4 /* Processors that are in SMP or AMP mode */
|
||||
#define SCU_CONFIG_SMPCPUS_MASK (15 << SCU_CONFIG_SMPCPUS_SHIFT)
|
||||
# define SCU_CONFIG_CPU_SMP(n) (1 << ((n)+4))
|
||||
# define SCU_CONFIG_CPU0_SMP (1 << 4)
|
||||
# define SCU_CONFIG_CPU1_SMP (1 << 5)
|
||||
# define SCU_CONFIG_CPU2_SMP (1 << 6)
|
||||
# define SCU_CONFIG_CPU3_SMP (1 << 7)
|
||||
|
||||
#define SCU_CONFIG_TAGRAM_16KB 0
|
||||
#define SCU_CONFIG_TAGRAM_32KB 1
|
||||
#define SCU_CONFIG_TAGRAM_64KB 2
|
||||
|
||||
#define SCU_CONFIG_CPU0_TAGRAM_SHIFT 8 /* CPU 0 tag RAM size */
|
||||
#define SCU_CONFIG_CPU0_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT)
|
||||
#define SCU_CONFIG_CPU1_TAGRAM_SHIFT 10 /* CPU 1 tag RAM size */
|
||||
#define SCU_CONFIG_CPU1_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT)
|
||||
#define SCU_CONFIG_CPU2_TAGRAM_SHIFT 12 /* CPU 1 tag RAM size */
|
||||
#define SCU_CONFIG_CPU2_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT)
|
||||
#define SCU_CONFIG_CPU3_TAGRAM_SHIFT 14 /* CPU 1 tag RAM size */
|
||||
#define SCU_CONFIG_CPU3_TAGRAM_MASK (3 << SCU_CONFIG_CPU0_TAGRAM_SHIFT)
|
||||
|
||||
/* SCU CPU Power Status Register */
|
||||
|
||||
#define SCU_PWRSTATUS_NORMAL 0
|
||||
#define SCU_PWRSTATUS_DORMANT 2
|
||||
#define SCU_PWRSTATUS_PWROFF 3
|
||||
|
||||
#define SCU_PWRSTATUS_CPU0_SHIFT 0 /* CPU0 status Power status */
|
||||
#define SCU_PWRSTATUS_CPU0_MASK (3 << SCU_PWRSTATUS_CPU0_SHIFT)
|
||||
#define SCU_PWRSTATUS_CPU1_SHIFT 8 /* CPU1 status Power status */
|
||||
#define SCU_PWRSTATUS_CPU1_MASK (3 << SCU_PWRSTATUS_CPU1_SHIFT)
|
||||
#define SCU_PWRSTATUS_CPU2_SHIFT 16 /* CPU2 status Power status */
|
||||
#define SCU_PWRSTATUS_CPU2_MASK (3 << SCU_PWRSTATUS_CPU2_SHIFT)
|
||||
#define SCU_PWRSTATUS_CPU3_SHIFT 24 /* CPU3 status Power status */
|
||||
#define SCU_PWRSTATUS_CPU3_MASK (3 << SCU_PWRSTATUS_CPU3_SHIFT)
|
||||
|
||||
/* SCU Invalidate All Registers in Secure State */
|
||||
|
||||
#define SCU_INVALIDATE_ALL_WAYS 15
|
||||
#define SCU_INVALIDATE_CPU0_SHIFT 0 /* Ways that must be invalidated for CPU0 */
|
||||
#define SCU_INVALIDATE_CPU0_MASK (15 << SCU_INVALIDATE_CPU0_SHIFT)
|
||||
#define SCU_INVALIDATE_CPU1_SHIFT 4 /* Ways that must be invalidated for CPU1 */
|
||||
#define SCU_INVALIDATE_CPU1_MASK (15 << SCU_INVALIDATE_CPU1_SHIFT)
|
||||
#define SCU_INVALIDATE_CPU2_SHIFT 8 /* Ways that must be invalidated for CPU2 */
|
||||
#define SCU_INVALIDATE_CPU2_MASK (15 << SCU_INVALIDATE_CPU2_SHIFT)
|
||||
#define SCU_INVALIDATE_CPU3_SHIFT 12 /* Ways that must be invalidated for CPU3 */
|
||||
#define SCU_INVALIDATE_CPU3_MASK (15 << SCU_INVALIDATE_CPU3_SHIFT)
|
||||
|
||||
/* Filtering Start Address Register Defined by FILTERSTART input */
|
||||
|
||||
#define SCU_FILTERSTART_SHIFT 10 /* Filtering start address */
|
||||
#define SCU_FILTERSTART_MASK (0xfff << SCU_FILTERSTART_SHIFT)
|
||||
|
||||
/* Filtering End Address Register Defined by FILTEREND input */
|
||||
|
||||
#define SCU_FILTEREND_SHIFT 10 /* Filtering start address */
|
||||
#define SCU_FILTEREND_MASK (0xfff << SCU_FILTEREND_SHIFT)
|
||||
|
||||
/* SCU Access Control (SAC) Register */
|
||||
|
||||
#define SCU_SAC_CPU(n) (1 << (n)) /* CPUn may access components */
|
||||
|
||||
/* SCU Non-secure Access Control (SNSAC) Register */
|
||||
|
||||
#define SCU_SNSAC_COMP_CPU(n) (1 << (n)) /* CPUn has non-secure access to components */
|
||||
#define SCU_SNSAC_PTIM_CPU(n) (1 << ((n)+4)) /* CPUn has non-secure access to private timers */
|
||||
#define SCU_SNSAC_GTIM_CPU(n) (1 << ((n)+8)) /* CPUn has non-secure access to global timer */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_enable_smp
|
||||
*
|
||||
* Description:
|
||||
* Enable the SCU and make certain that current CPU is participating in
|
||||
* the SMP cache coherency.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void arm_enable_smp(int cpu);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_ARMV7_A_SCU_H */
|
||||
@@ -48,12 +48,12 @@ config ARMV7M_DTCM
|
||||
|
||||
choice
|
||||
prompt "Toolchain Selection"
|
||||
default ARMV7M_TOOLCHAIN_GNU_EABIW if HOST_WINDOWS
|
||||
default ARMV7M_TOOLCHAIN_GNU_EABIL if !HOST_WINDOWS
|
||||
default ARMV7M_TOOLCHAIN_GNU_EABIW if TOOLCHAIN_WINDOWS
|
||||
default ARMV7M_TOOLCHAIN_GNU_EABIL if !TOOLCHAIN_WINDOWS
|
||||
|
||||
config ARMV7M_TOOLCHAIN_IARW
|
||||
bool "IAR for Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
select ARM_TOOLCHAIN_IAR
|
||||
|
||||
config ARMV7M_TOOLCHAIN_IARL
|
||||
@@ -63,7 +63,7 @@ config ARMV7M_TOOLCHAIN_IARL
|
||||
|
||||
config ARMV7M_TOOLCHAIN_ATOLLIC
|
||||
bool "Atollic Lite/Pro for Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
select ARM_TOOLCHAIN_GNU
|
||||
|
||||
config ARMV7M_TOOLCHAIN_BUILDROOT
|
||||
@@ -78,7 +78,7 @@ config ARMV7M_TOOLCHAIN_CODEREDL
|
||||
|
||||
config ARMV7M_TOOLCHAIN_CODEREDW
|
||||
bool "CodeRed for Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
select ARM_TOOLCHAIN_GNU
|
||||
|
||||
config ARMV7M_TOOLCHAIN_CODESOURCERYL
|
||||
@@ -88,12 +88,12 @@ config ARMV7M_TOOLCHAIN_CODESOURCERYL
|
||||
|
||||
config ARMV7M_TOOLCHAIN_CODESOURCERYW
|
||||
bool "CodeSourcery GNU toolchain under Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
select ARM_TOOLCHAIN_GNU
|
||||
|
||||
config ARMV7M_TOOLCHAIN_DEVKITARM
|
||||
bool "devkitARM GNU toolchain"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
select ARM_TOOLCHAIN_GNU
|
||||
|
||||
config ARMV7M_TOOLCHAIN_GNU_EABIL
|
||||
@@ -106,7 +106,7 @@ config ARMV7M_TOOLCHAIN_GNU_EABIL
|
||||
|
||||
config ARMV7M_TOOLCHAIN_GNU_EABIW
|
||||
bool "Generic GNU EABI toolchain under Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
select ARM_TOOLCHAIN_GNU
|
||||
---help---
|
||||
This option should work for any modern GNU toolchain (GCC 4.5 or newer)
|
||||
@@ -114,7 +114,7 @@ config ARMV7M_TOOLCHAIN_GNU_EABIW
|
||||
|
||||
config ARMV7M_TOOLCHAIN_RAISONANCE
|
||||
bool "STMicro Raisonance for Windows"
|
||||
depends on HOST_WINDOWS
|
||||
depends on TOOLCHAIN_WINDOWS
|
||||
select ARM_TOOLCHAIN_GNU
|
||||
|
||||
endchoice
|
||||
|
||||
@@ -53,6 +53,7 @@
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "sched/sched.h"
|
||||
#include "irq/irq.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
@@ -319,6 +320,12 @@ static void up_dumpstate(void)
|
||||
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
/* Show the CPU number */
|
||||
|
||||
_alert("CPU%d:\n", up_cpu_index());
|
||||
#endif
|
||||
|
||||
/* Then dump the registers (if available) */
|
||||
|
||||
up_registerdump();
|
||||
@@ -351,6 +358,12 @@ static void _up_assert(int errorcode)
|
||||
(void)up_irq_save();
|
||||
for (; ; )
|
||||
{
|
||||
#ifdef CONFIG_SMP
|
||||
/* Try (again) to stop activity on other CPUs */
|
||||
|
||||
(void)spin_trylock(&g_cpu_irqlock);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
board_autoled_on(LED_PANIC);
|
||||
up_mdelay(250);
|
||||
|
||||
@@ -50,22 +50,6 @@
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user