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https://github.com/apache/nuttx.git
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Initial STM32H5 Timers Commit
Used the STM32H7 as a reference. Removed APB enabling from stm32h5xx_rcc.c. This is done in timer initialization, like STM32H7. Also removed LPTIM. Will add later. tim_lowerhalf: Timers 9, 10, and 11 removed. Timers 15,16, and 17 added. Removed low-power timers from Kconfig. Not implemented yet. Style Updates Added stm32_tim_enable and stm32_tim_disable to Timer operations.
This commit is contained in:
Kyle Wilson
committed by
Mateusz Szafoni
Mateusz Szafoni
parent
e5e9032ea0
commit
9783c88425
+3110
-1
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Load Diff
@@ -43,7 +43,7 @@ CHIP_CSRCS += stm32_idle.c
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endif
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ifeq ($(CONFIG_TIMER),y)
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CHIP_CSRCS += stm32h5_tim_lowerhalf.c
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CHIP_CSRCS += stm32_tim_lowerhalf.c
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endif
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ifeq ($(CONFIG_STM32H5_I2C),y)
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@@ -66,6 +66,10 @@ ifeq ($(CONFIG_STM32H5_QSPI1),y)
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CHIP_CSRCS += stm32_qspi.c
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endif
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ifeq ($(CONFIG_STM32H5_TIM),y)
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CHIP_CSRCS += stm32_tim.c
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endif
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# Required chip type specific files
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ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y)
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@@ -0,0 +1,223 @@
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/****************************************************************************
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* arch/arm/src/stm32h5/stm32_tim.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H5_STM32_TIM_H
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#define __ARCH_ARM_SRC_STM32H5_STM32_TIM_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "hardware/stm32_tim.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Helpers ******************************************************************/
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#define STM32_TIM_ENABLE(d) ((d)->ops->enable(d))
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#define STM32_TIM_DISABLE(d) ((d)->ops->disable(d))
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#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
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#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
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#define STM32_TIM_SETPERIOD(d,period) ((d)->ops->setperiod(d,period))
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#define STM32_TIM_GETCOUNTER(d) ((d)->ops->getcounter(d))
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#define STM32_TIM_SETCOUNTER(d,c) ((d)->ops->setcounter(d,c))
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#define STM32_TIM_GETWIDTH(d) ((d)->ops->getwidth(d))
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#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode))
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#define STM32_TIM_SETCOMPARE(d,ch,comp) ((d)->ops->setcompare(d,ch,comp))
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#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch))
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#define STM32_TIM_SETISR(d,hnd,arg,s) ((d)->ops->setisr(d,hnd,arg,s))
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#define STM32_TIM_ENABLEINT(d,s) ((d)->ops->enableint(d,s))
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#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
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#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
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#define STM32_TIM_CHECKINT(d,s) ((d)->ops->checkint(d,s))
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/****************************************************************************
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* Public Types
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/* TIM Device Structure */
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struct stm32_tim_dev_s
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{
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struct stm32_tim_ops_s *ops;
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};
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/* TIM Modes of Operation */
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typedef enum
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{
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STM32_TIM_MODE_UNUSED = -1,
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/* One of the following */
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STM32_TIM_MODE_MASK = 0x0310,
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STM32_TIM_MODE_DISABLED = 0x0000,
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STM32_TIM_MODE_UP = 0x0100,
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STM32_TIM_MODE_DOWN = 0x0110,
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STM32_TIM_MODE_UPDOWN = 0x0200,
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STM32_TIM_MODE_PULSE = 0x0300,
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/* One of the following */
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STM32_TIM_MODE_CK_INT = 0x0000,
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#if 0
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STM32_TIM_MODE_CK_INT_TRIG = 0x0400,
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STM32_TIM_MODE_CK_EXT = 0x0800,
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STM32_TIM_MODE_CK_EXT_TRIG = 0x0c00,
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/* Clock sources, OR'ed with CK_EXT */
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STM32_TIM_MODE_CK_CHINVALID = 0x0000,
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STM32_TIM_MODE_CK_CH1 = 0x0001,
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STM32_TIM_MODE_CK_CH2 = 0x0002,
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STM32_TIM_MODE_CK_CH3 = 0x0003,
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STM32_TIM_MODE_CK_CH4 = 0x0004
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#endif
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/* Todo: external trigger block */
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} stm32_tim_mode_t;
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/* TIM Channel Modes */
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typedef enum
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{
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STM32_TIM_CH_DISABLED = 0x00,
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/* Common configuration */
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STM32_TIM_CH_POLARITY_POS = 0x00,
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STM32_TIM_CH_POLARITY_NEG = 0x01,
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/* MODES: */
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STM32_TIM_CH_MODE_MASK = 0x0e,
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/* Output Compare Modes */
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/* Enable standard PWM mode, active high when counter < compare */
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STM32_TIM_CH_OUTPWM = 0x04,
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/* Toggle TIM_CHx output on UEV */
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STM32_TIM_CH_OUTTOGGLE = 0x08,
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#if 0
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STM32_TIM_CH_OUTCOMPARE = 0x06,
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/* TODO other modes ... as PWM capture, ENCODER and Hall Sensor */
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STM32_TIM_CH_INCAPTURE = 0x10,
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STM32_TIM_CH_INPWM = 0x20
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STM32_TIM_CH_DRIVE_OC - open collector mode
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#endif
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} stm32_tim_channel_t;
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/* TIM Operations */
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struct stm32_tim_ops_s
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{
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/* Basic Timers */
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void (*enable)(struct stm32_tim_dev_s *dev);
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void (*disable)(struct stm32_tim_dev_s *dev);
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int (*setmode)(struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
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int (*setclock)(struct stm32_tim_dev_s *dev, uint32_t freq);
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void (*setperiod)(struct stm32_tim_dev_s *dev, uint32_t period);
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uint32_t (*getcounter)(struct stm32_tim_dev_s *dev);
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void (*setcounter)(struct stm32_tim_dev_s *dev, uint32_t count);
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/* General and Advanced Timers Adds */
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int (*getwidth)(struct stm32_tim_dev_s *dev);
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int (*setchannel)(struct stm32_tim_dev_s *dev, uint8_t channel,
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stm32_tim_channel_t mode);
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int (*setcompare)(struct stm32_tim_dev_s *dev, uint8_t channel,
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uint32_t compare);
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int (*getcapture)(struct stm32_tim_dev_s *dev, uint8_t channel);
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/* Timer interrupts */
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int (*setisr)(struct stm32_tim_dev_s *dev, xcpt_t handler, void *arg,
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int source);
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void (*enableint)(struct stm32_tim_dev_s *dev, int source);
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void (*disableint)(struct stm32_tim_dev_s *dev, int source);
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void (*ackint)(struct stm32_tim_dev_s *dev, int source);
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int (*checkint)(struct stm32_tim_dev_s *dev, int source);
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};
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/* Power-up timer and get its structure */
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struct stm32_tim_dev_s *stm32_tim_init(int timer);
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/* Power-down timer, mark it as unused */
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int stm32_tim_deinit(struct stm32_tim_dev_s *dev);
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/****************************************************************************
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* Name: stm32_timer_initialize
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*
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* Description:
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* Bind the configuration timer to a timer lower half instance and
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* register the timer drivers at 'devpath'
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*
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* Input Parameters:
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* devpath - The full path to the timer device. This should be of the
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* form /dev/timer0
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* timer - the timer number.
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*
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* Returned Values:
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* Zero (OK) is returned on success; A negated errno value is returned
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* to indicate the nature of any failure.
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*
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****************************************************************************/
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#ifdef CONFIG_TIMER
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int stm32_timer_initialize(const char *devpath, int timer);
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#endif
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM_SRC_STM32H5_STM32_TIM_H */
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File diff suppressed because it is too large
Load Diff
@@ -355,60 +355,6 @@ static inline void rcc_enableapb1l(void)
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regval = getreg32(STM32_RCC_APB1LENR);
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#ifdef CONFIG_STM32H5_TIM2
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/* Bit 0: TIM2 clock enable */
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regval |= RCC_APB1LENR_TIM2EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM3
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/* Bit 1: TIM3 clock enable */
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regval |= RCC_APB1LENR_TIM3EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM4
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/* Bit 2: TIM4 clock enable */
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regval |= RCC_APB1LENR_TIM4EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM5
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/* Bit 3: TIM5 clock enable */
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regval |= RCC_APB1LENR_TIM5EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM6
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/* Bit 4: TIM6 clock enable */
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regval |= RCC_APB1LENR_TIM6EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM7
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/* Bit 5: TIM7 clock enable */
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regval |= RCC_APB1LENR_TIM7EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM12
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/* Bit 5: TIM12 clock enable */
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regval |= RCC_APB1LENR_TIM12EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM13
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/* Bit 5: TIM13 clock enable */
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regval |= RCC_APB1LENR_TIM13EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM14
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/* Bit 5: TIM14 clock enable */
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regval |= RCC_APB1LENR_TIM14EN;
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#endif
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#ifdef CONFIG_STM32H5_SPI2
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/* Bit 14: SPI2 clock enable */
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@@ -588,48 +534,18 @@ static inline void rcc_enableapb2(void)
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regval = getreg32(STM32_RCC_APB2ENR);
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#ifdef CONFIG_STM32H5_TIM1
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/* TIM1 clock enable */
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regval |= RCC_APB2ENR_TIM1EN;
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#endif
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#ifdef CONFIG_STM32H5_SPI1
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/* SPI1 clock enable */
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regval |= RCC_APB2ENR_SPI1EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM8
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/* TIM8 clock enable */
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regval |= RCC_APB2ENR_TIM8EN;
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#endif
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#ifdef CONFIG_STM32H5_USART1
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/* USART1 clock enable */
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regval |= RCC_APB2ENR_USART1EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM15
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/* TIM15 clock enable */
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regval |= RCC_APB2ENR_TIM15EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM16
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/* TIM16 clock enable */
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regval |= RCC_APB2ENR_TIM16EN;
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#endif
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#ifdef CONFIG_STM32H5_TIM17
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/* TIM17 clock enable */
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regval |= RCC_APB2ENR_TIM17EN;
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#endif
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#ifdef CONFIG_STM32H5_SPI4
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/* SPI4 clock enable */
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