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Change naming of all Stellaris pre-processor symbols from LM3S_ to LM_ to make room in the namespace for LM4F

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git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5498 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
2013-01-09 18:15:02 +00:00
parent da5ed36c5b
commit 97548511f6
59 changed files with 2282 additions and 2280 deletions
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arch/arm/include/lm/chip.h
+52 -52
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@@ -49,63 +49,63 @@
/* Get customizations for each supported chip (only the LM3S6918 and 65 right now) */
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
# define LM3S_NTIMERS 4 /* Four general purpose timers */
# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM3S_ETHTS /* No timestamp register */
# define LM3S_NSSI 2 /* Two SSI modules */
# define LM3S_NUARTS 2 /* Two UART modules */
# define LM3S_NI2C 2 /* Two I2C modules */
# define LM3S_NADC 1 /* One ADC module */
# define LM2S_NPWM 0 /* No PWM generator modules */
# define LM3S_NQEI 0 /* No quadrature encoders */
# define LM3S_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
# define LM_NTIMERS 4 /* Four general purpose timers */
# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM_ETHTS /* No timestamp register */
# define LM_NSSI 2 /* Two SSI modules */
# define LM_NUARTS 2 /* Two UART modules */
# define LM_NI2C 2 /* Two I2C modules */
# define LM_NADC 1 /* One ADC module */
# define LM_NPWM 0 /* No PWM generator modules */
# define LM_NQEI 0 /* No quadrature encoders */
# define LM_NPORTS 8 /* 8 Ports (GPIOA-H) 5-38 GPIOs */
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
# define LM3S_NTIMERS 3 /* Three general purpose timers */
# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM3S_ETHTS /* No timestamp register */
# define LM3S_NSSI 1 /* One SSI module */
# define LM3S_NUARTS 2 /* Two UART modules */
# define LM3S_NI2C 1 /* Two I2C modules */
# define LM3S_NADC 1 /* One ADC module */
# define LM2S_NPWM 1 /* One PWM generator module */
# define LM3S_NQEI 0 /* No quadrature encoders */
# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
# define LM_NTIMERS 3 /* Three general purpose timers */
# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM_ETHTS /* No timestamp register */
# define LM_NSSI 1 /* One SSI module */
# define LM_NUARTS 2 /* Two UART modules */
# define LM_NI2C 1 /* Two I2C modules */
# define LM_NADC 1 /* One ADC module */
# define LM_NPWM 1 /* One PWM generator module */
# define LM_NQEI 0 /* No quadrature encoders */
# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
# define LM3S_NTIMERS 4 /* Four general purpose timers */
# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM3S_ETHTS /* No timestamp register */
# define LM3S_NSSI 1 /* One SSI module */
# define LM3S_NUARTS 3 /* Three UART modules */
# define LM3S_NI2C 2 /* Two I2C modules */
# define LM3S_NADC 1 /* One ADC module */
# define LM2S_NPWM 3 /* Three PWM generator modules */
# define LM3S_NQEI 2 /* Two quadrature encoders */
# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
# define LM_NTIMERS 4 /* Four general purpose timers */
# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM_ETHTS /* No timestamp register */
# define LM_NSSI 1 /* One SSI module */
# define LM_NUARTS 3 /* Three UART modules */
# define LM_NI2C 2 /* Two I2C modules */
# define LM_NADC 1 /* One ADC module */
# define LM_NPWM 3 /* Three PWM generator modules */
# define LM_NQEI 2 /* Two quadrature encoders */
# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 0-42 GPIOs */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
# define LM3S_NTIMERS 4 /* Four general purpose timers */
# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM3S_ETHTS /* No timestamp register */
# define LM3S_NSSI 2 /* Two SSI modules */
# define LM3S_NUARTS 3 /* Three UART modules */
# define LM3S_NI2C 2 /* Two I2C modules */
# define LM3S_NADC 2 /* Two ADC module */
# define LM3S_CAN 2 /* Two CAN module */
# define LM3S_NPWM 4 /* Four PWM generator modules */
# define LM3S_NQEI 2 /* Two quadrature encoders */
# define LM3S_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
# define LM_NTIMERS 4 /* Four general purpose timers */
# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
# undef LM_ETHTS /* No timestamp register */
# define LM_NSSI 2 /* Two SSI modules */
# define LM_NUARTS 3 /* Three UART modules */
# define LM_NI2C 2 /* Two I2C modules */
# define LM_NADC 2 /* Two ADC module */
# define LM_CAN 2 /* Two CAN module */
# define LM_NPWM 4 /* Four PWM generator modules */
# define LM_NQEI 2 /* Two quadrature encoders */
# define LM_NPORTS 9 /* 9 Ports (GPIOA-H,J) 0-65 GPIOs */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
# define LM3S_NTIMERS 4 /* Four general purpose timers */
# define LM3S_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LM3S_NSSI 1 /* One SSI module */
# define LM3S_NUARTS 3 /* Two UART modules */
# define LM3S_NI2C 2 /* One I2C module */
# define LM3S_NADC 1 /* One ADC module */
# define LM2S_NPWM 3 /* Three PWM generator modules */
# define LM3S_NQEI 2 /* Two quadrature encoders */
# define LM3S_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
# define LC3S_CANCONTROLLER 1 /* One CAN controller */
# define LM_NTIMERS 4 /* Four general purpose timers */
# define LM_NETHCONTROLLERS 1 /* One Ethernet controller */
# define LM_NSSI 1 /* One SSI module */
# define LM_NUARTS 3 /* Two UART modules */
# define LM_NI2C 2 /* One I2C module */
# define LM_NADC 1 /* One ADC module */
# define LM_NPWM 3 /* Three PWM generator modules */
# define LM_NQEI 2 /* Two quadrature encoders */
# define LM_NPORTS 7 /* 7 Ports (GPIOA-G), 5-42 GPIOs */
# define LM_CANCONTROLLER 1 /* One CAN controller */
#else
# error "Capabilities not specified for this LM3S chip"
# error "Capabilities not specified for this Stellaris chip"
#endif
/************************************************************************************
arch/arm/include/lm/irq.h
+325 -325
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arch/arm/src/lm/chip/lm3s_memorymap.h
+253 -253
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arch/arm/src/lm/chip/lm3s_pinmap.h
+1 -1
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@@ -263,7 +263,7 @@
# define GPIO_ETHPHY_LED0 (GPIO_FUNC_PFOUTPUT | GPIO_PORTF | 3) /* PF3: LED0 */
# define GPIO_PWM0_1 (GPIO_FUNC_PFOUTPUT | GPIO_PORTG | 1) /* PG1:PWM Generator 0, PWM1 */
#else
# error "Unknown LM3S chip"
# error "Unknown Stellaris chip"
#endif
/************************************************************************************
arch/arm/src/lm/chip/lm_epi.h
+13 -13
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@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H
#define __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H
/************************************************************************************
* Included Files
@@ -46,19 +46,19 @@
/* External Peripheral Interface Register Offsets ***********************************/
#define LM3S_EPI_CFG_OFFSET 0x000
#define LM3S_EPI_SDRAMCFG_OFFSET 0x010
#define LM3S_EPI_ADDRMAP_OFFSET 0x01C
#define LM3S_EPI_STAT_OFFSET 0x060
#define LM3S_EPI_BAUD_OFFSET 0x004
#define LM_EPI_CFG_OFFSET 0x000
#define LM_EPI_SDRAMCFG_OFFSET 0x010
#define LM_EPI_ADDRMAP_OFFSET 0x01C
#define LM_EPI_STAT_OFFSET 0x060
#define LM_EPI_BAUD_OFFSET 0x004
/* External Peripheral Interface Register Addresses *********************************/
#define LM3S_EPI0_CFG (LM3S_EPI0_BASE + LM3S_EPI_CFG_OFFSET)
#define LM3S_EPI0_SDRAMCFG (LM3S_EPI0_BASE + LM3S_EPI_SDRAMCFG_OFFSET)
#define LM3S_EPI0_ADDRMAP (LM3S_EPI0_BASE + LM3S_EPI_ADDRMAP_OFFSET)
#define LM3S_EPI0_STAT (LM3S_EPI0_BASE + LM3S_EPI_STAT_OFFSET)
#define LM3S_EPI0_BAUD (LM3S_EPI0_BASE + LM3S_EPI_BAUD_OFFSET)
#define LM_EPI0_CFG (LM_EPI0_BASE + LM_EPI_CFG_OFFSET)
#define LM_EPI0_SDRAMCFG (LM_EPI0_BASE + LM_EPI_SDRAMCFG_OFFSET)
#define LM_EPI0_ADDRMAP (LM_EPI0_BASE + LM_EPI_ADDRMAP_OFFSET)
#define LM_EPI0_STAT (LM_EPI0_BASE + LM_EPI_STAT_OFFSET)
#define LM_EPI0_BAUD (LM_EPI0_BASE + LM_EPI_BAUD_OFFSET)
/* External Peripheral Interface Register Bit Definitions ***************************/
@@ -110,4 +110,4 @@
#define EPI_BAUD_COUNT0_MASK (0xFFFF << EPI_BAUD_COUNT0_SHIFT)
# define EPI_BAUD_COUNT0(n) ((n) << EPI_BAUD_COUNT0_SHIFT)
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_EPI_H */
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_EPI_H */
arch/arm/src/lm/chip/lm_ethernet.h
+50 -50
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@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H
#define __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H
/************************************************************************************
* Included Files
@@ -53,63 +53,63 @@
/* Ethernet MAC Register Offsets */
#define LM3S_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */
#define LM3S_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */
#define LM3S_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */
#define LM3S_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */
#define LM3S_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */
#define LM3S_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */
#define LM3S_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */
#define LM3S_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */
#define LM3S_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */
#define LM3S_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */
#define LM3S_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */
#define LM3S_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */
#define LM3S_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
#define LM3S_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
#define LM3S_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
#ifdef LM3S_ETHTS
# define LM3S_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
#define LM_MAC_RIS_OFFSET 0x000 /* Ethernet MAC Raw Interrupt Status */
#define LM_MAC_IACK_OFFSET 0x000 /* Ethernet MAC Acknowledge */
#define LM_MAC_IM_OFFSET 0x004 /* Ethernet MAC Interrupt Mask */
#define LM_MAC_RCTL_OFFSET 0x008 /* Ethernet MAC Receive Control */
#define LM_MAC_TCTL_OFFSET 0x00c /* Ethernet MAC Transmit Control */
#define LM_MAC_DATA_OFFSET 0x010 /* Ethernet MAC Data */
#define LM_MAC_IA0_OFFSET 0x014 /* Ethernet MAC Individual Address 0 */
#define LM_MAC_IA1_OFFSET 0x018 /* Ethernet MAC Individual Address 1 */
#define LM_MAC_THR_OFFSET 0x01c /* Ethernet MAC Threshold */
#define LM_MAC_MCTL_OFFSET 0x020 /* Ethernet MAC Management Control */
#define LM_MAC_MDV_OFFSET 0x024 /* Ethernet MAC Management Divider */
#define LM_MAC_MTXD_OFFSET 0x02c /* Ethernet MAC Management Transmit Data */
#define LM_MAC_MRXD_OFFSET 0x030 /* Ethernet MAC Management Receive Data */
#define LM_MAC_NP_OFFSET 0x034 /* Ethernet MAC Number of Packets */
#define LM_MAC_TR_OFFSET 0x038 /* Ethernet MAC Transmission Request */
#ifdef LM_ETHTS
# define LM_MAC_TS_OFFSET 0x03c /* Ethernet MAC Time Stamp Configuration */
#endif
/* MII Management Register Offsets (see include/nuttx/net/mii.h) */
/* Ethernet Controller Register Addresses *******************************************/
#define LM3S_MAC_RIS (LM3S_ETHCON_BASE + LM3S_MAC_RIS_OFFSET)
#define LM3S_MAC_IACK (LM3S_ETHCON_BASE + LM3S_MAC_IACK_OFFSET)
#define LM3S_MAC_IM (LM3S_ETHCON_BASE + LM3S_MAC_IM_OFFSET)
#define LM3S_MAC_RCTL (LM3S_ETHCON_BASE + LM3S_MAC_RCTL_OFFSET)
#define LM3S_MAC_TCTL (LM3S_ETHCON_BASE + LM3S_MAC_TCTL_OFFSET)
#define LM3S_MAC_DATA (LM3S_ETHCON_BASE + LM3S_MAC_DATA_OFFSET)
#define LM3S_MAC_IA0 (LM3S_ETHCON_BASE + LM3S_MAC_IA0_OFFSET)
#define LM3S_MAC_IA1 (LM3S_ETHCON_BASE + LM3S_MAC_IA1_OFFSET)
#define LM3S_MAC_THR (LM3S_ETHCON_BASE + LM3S_MAC_THR_OFFSET)
#define LM3S_MAC_MCTL (LM3S_ETHCON_BASE + LM3S_MAC_MCTL_OFFSET)
#define LM3S_MAC_MDV (LM3S_ETHCON_BASE + LM3S_MAC_MDV_OFFSET)
#define LM3S_MAC_MTXD (LM3S_ETHCON_BASE + LM3S_MAC_MTXD_OFFSET)
#define LM3S_MAC_MRXD (LM3S_ETHCON_BASE + LM3S_MAC_MRXD_OFFSET)
#define LM3S_MAC_NP (LM3S_ETHCON_BASE + LM3S_MAC_NP_OFFSET)
#define LM3S_MAC_TR (LM3S_ETHCON_BASE + LM3S_MAC_TR_OFFSET)
#ifdef LM3S_ETHTS
# define LM3S_MAC_TS (LM3S_ETHCON_BASE + LM3S_MAC_TS_OFFSET)
#define LM_MAC_RIS (LM_ETHCON_BASE + LM_MAC_RIS_OFFSET)
#define LM_MAC_IACK (LM_ETHCON_BASE + LM_MAC_IACK_OFFSET)
#define LM_MAC_IM (LM_ETHCON_BASE + LM_MAC_IM_OFFSET)
#define LM_MAC_RCTL (LM_ETHCON_BASE + LM_MAC_RCTL_OFFSET)
#define LM_MAC_TCTL (LM_ETHCON_BASE + LM_MAC_TCTL_OFFSET)
#define LM_MAC_DATA (LM_ETHCON_BASE + LM_MAC_DATA_OFFSET)
#define LM_MAC_IA0 (LM_ETHCON_BASE + LM_MAC_IA0_OFFSET)
#define LM_MAC_IA1 (LM_ETHCON_BASE + LM_MAC_IA1_OFFSET)
#define LM_MAC_THR (LM_ETHCON_BASE + LM_MAC_THR_OFFSET)
#define LM_MAC_MCTL (LM_ETHCON_BASE + LM_MAC_MCTL_OFFSET)
#define LM_MAC_MDV (LM_ETHCON_BASE + LM_MAC_MDV_OFFSET)
#define LM_MAC_MTXD (LM_ETHCON_BASE + LM_MAC_MTXD_OFFSET)
#define LM_MAC_MRXD (LM_ETHCON_BASE + LM_MAC_MRXD_OFFSET)
#define LM_MAC_NP (LM_ETHCON_BASE + LM_MAC_NP_OFFSET)
#define LM_MAC_TR (LM_ETHCON_BASE + LM_MAC_TR_OFFSET)
#ifdef LM_ETHTS
# define LM_MAC_TS (LM_ETHCON_BASE + LM_MAC_TS_OFFSET)
#endif
/* Memory Mapped MII Management Registers */
#define MAC_MII_MCR (LM3S_ETHCON_BASE + MII_MCR)
#define MAC_MII_MSR (LM3S_ETHCON_BASE + MII_MSR)
#define MAC_MII_PHYID1 (LM3S_ETHCON_BASE + MII_PHYID1)
#define MAC_MII_PHYID2 (LM3S_ETHCON_BASE + MII_PHYID2)
#define MAC_MII_ADVERTISE (LM3S_ETHCON_BASE + MII_ADVERTISE)
#define MAC_MII_LPA (LM3S_ETHCON_BASE + MII_LPA)
#define MAC_MII_EXPANSION (LM3S_ETHCON_BASE + MII_EXPANSION)
#define MAC_MII_VSPECIFIC (LM3S_ETHCON_BASE + MII_LM3S_VSPECIFIC)
#define MAC_MII_INTCS (LM3S_ETHCON_BASE + MII_LM3S_INTCS)
#define MAC_MII_DIAGNOSTIC (LM3S_ETHCON_BASE + MII_LM3S_DIAGNOSTIC)
#define MAC_MII_XCVRCONTROL (LM3S_ETHCON_BASE + MII_LM3S_XCVRCONTROL)
#define MAC_MII_LEDCONFIG (LM3S_ETHCON_BASE + MII_LM3S_LEDCONFIG)
#define MAC_MII_MDICONTROL (LM3S_ETHCON_BASE + MII_LM3S_MDICONTROL)
#define MAC_MII_MCR (LM_ETHCON_BASE + MII_MCR)
#define MAC_MII_MSR (LM_ETHCON_BASE + MII_MSR)
#define MAC_MII_PHYID1 (LM_ETHCON_BASE + MII_PHYID1)
#define MAC_MII_PHYID2 (LM_ETHCON_BASE + MII_PHYID2)
#define MAC_MII_ADVERTISE (LM_ETHCON_BASE + MII_ADVERTISE)
#define MAC_MII_LPA (LM_ETHCON_BASE + MII_LPA)
#define MAC_MII_EXPANSION (LM_ETHCON_BASE + MII_EXPANSION)
#define MAC_MII_VSPECIFIC (LM_ETHCON_BASE + MII_LM_VSPECIFIC)
#define MAC_MII_INTCS (LM_ETHCON_BASE + MII_LM_INTCS)
#define MAC_MII_DIAGNOSTIC (LM_ETHCON_BASE + MII_LM_DIAGNOSTIC)
#define MAC_MII_XCVRCONTROL (LM_ETHCON_BASE + MII_LM_XCVRCONTROL)
#define MAC_MII_LEDCONFIG (LM_ETHCON_BASE + MII_LM_LEDCONFIG)
#define MAC_MII_MDICONTROL (LM_ETHCON_BASE + MII_LM_MDICONTROL)
/* Ethernet Controller Register Bit Definitions *************************************/
@@ -200,4 +200,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_ETHERNET_H */
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_ETHERNET_H */
arch/arm/src/lm/chip/lm_flash.h
+47 -47
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@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H
#define __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H
/************************************************************************************
* Included Files
@@ -49,66 +49,66 @@
/* FLASH register offsets ***********************************************************/
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
* control base address of LM3S_FLASHCON_BASE.
* control base address of LM_FLASHCON_BASE.
*/
#define LM3S_FLASH_FMA_OFFSET 0x000 /* Flash memory address */
#define LM3S_FLASH_FMD_OFFSET 0x004 /* Flash memory data */
#define LM3S_FLASH_FMC_OFFSET 0x008 /* Flash memory control */
#define LM3S_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */
#define LM3S_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */
#define LM3S_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */ */
#define LM_FLASH_FMA_OFFSET 0x000 /* Flash memory address */
#define LM_FLASH_FMD_OFFSET 0x004 /* Flash memory data */
#define LM_FLASH_FMC_OFFSET 0x008 /* Flash memory control */
#define LM_FLASH_FCRIS_OFFSET 0x00c /* Flash controller raw interrupt status */
#define LM_FLASH_FCIM_OFFSET 0x010 /* Flash controller interrupt mask */
#define LM_FLASH_FCMISC_OFFSET 0x014 /* Flash controller masked interrupt status and clear */
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
* System Control base address of LM3S_SYSCON_BASE
* System Control base address of LM_SYSCON_BASE
*/
#define LM3S_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */
#define LM3S_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */
#define LM3S_FLASH_USECRL_OFFSET 0x140 /* USec Reload */
#define LM3S_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */
#define LM3S_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */
#define LM3S_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */
#define LM3S_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */
#define LM3S_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */
#define LM3S_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */
#define LM3S_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */
#define LM3S_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */
#define LM3S_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */
#define LM3S_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */
#define LM3S_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */
#define LM_FLASH_FMPRE_OFFSET 0x130 /* Flash memory protection read enable */
#define LM_FLASH_FMPPE_OFFSET 0x134 /* Flash memory protection program enable */
#define LM_FLASH_USECRL_OFFSET 0x140 /* USec Reload */
#define LM_FLASH_USERDBG_OFFSET 0x1d0 /* User Debug */
#define LM_FLASH_USERREG0_OFFSET 0x1e0 /* User Register 0 */
#define LM_FLASH_USERREG1_OFFSET 0x1e4 /* User Register 1 */
#define LM_FLASH_FMPRE0_OFFSET 0x200 /* Flash Memory Protection Read Enable 0 */
#define LM_FLASH_FMPRE1_OFFSET 0x204 /* Flash Memory Protection Read Enable 1 */
#define LM_FLASH_FMPRE2_OFFSET 0x208 /* Flash Memory Protection Read Enable 2 */
#define LM_FLASH_FMPRE3_OFFSET 0x20c /* Flash Memory Protection Read Enable 3 */
#define LM_FLASH_FMPPE0_OFFSET 0x400 /* Flash Memory Protection Program Enable 0 */
#define LM_FLASH_FMPPE1_OFFSET 0x404 /* Flash Memory Protection Program Enable 1 */
#define LM_FLASH_FMPPE2_OFFSET 0x408 /* Flash Memory Protection Program Enable 2 */
#define LM_FLASH_FMPPE3_OFFSET 0x40c /* Flash Memory Protection Program Enable 3 */
/* FLASH register addresses *********************************************************/
/* The FMA, FMD, FMC, FCRIS, FCIM, and FCMISC registers are relative to the Flash
* control base address of LM3S_FLASHCON_BASE.
* control base address of LM_FLASHCON_BASE.
*/
#define LM3S_FLASH_FMA (LM3S_FLASHCON_BASE + LM3S_FLASH_FMA_OFFSET)
#define LM3S_FLASH_FMD (LM3S_FLASHCON_BASE + LM3S_FLASH_FMD_OFFSET)
#define LM3S_FLASH_FMC (LM3S_FLASHCON_BASE + LM3S_FLASH_FMC_OFFSET)
#define LM3S_FLASH_FCRIS (LM3S_FLASHCON_BASE + LM3S_FLASH_FCRIS_OFFSET)
#define LM3S_FLASH_FCIM (LM3S_FLASHCON_BASE + LM3S_FLASH_FCIM_OFFSET)
#define LM3S_FLASH_FCMISC (LM3S_FLASHCON_BASE + LM3S_FLASH_FCMISC_OFFSET)
#define LM_FLASH_FMA (LM_FLASHCON_BASE + LM_FLASH_FMA_OFFSET)
#define LM_FLASH_FMD (LM_FLASHCON_BASE + LM_FLASH_FMD_OFFSET)
#define LM_FLASH_FMC (LM_FLASHCON_BASE + LM_FLASH_FMC_OFFSET)
#define LM_FLASH_FCRIS (LM_FLASHCON_BASE + LM_FLASH_FCRIS_OFFSET)
#define LM_FLASH_FCIM (LM_FLASHCON_BASE + LM_FLASH_FCIM_OFFSET)
#define LM_FLASH_FCMISC (LM_FLASHCON_BASE + LM_FLASH_FCMISC_OFFSET)
/* The FMPREn, FMPPEn, USECRL, USER_DBG, and USER_REGn registers are relative to the
* System Control base address of LM3S_SYSCON_BASE
* System Control base address of LM_SYSCON_BASE
*/
#define LM3S_FLASH_FMPRE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE_OFFSET)
#define LM3S_FLASH_FMPPE (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE_OFFSET)
#define LM3S_FLASH_USECRL (LM3S_SYSCON_BASE + LM3S_FLASH_USECRL_OFFSET)
#define LM3S_FLASH_USERDBG (LM3S_SYSCON_BASE + LM3S_FLASH_USERDBG_OFFSET)
#define LM3S_FLASH_USERREG0 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG0_OFFSET)
#define LM3S_FLASH_USERREG1 (LM3S_SYSCON_BASE + LM3S_FLASH_USERREG1_OFFSET)
#define LM3S_FLASH_FMPRE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE0_OFFSET)
#define LM3S_FLASH_FMPRE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE1_OFFSET)
#define LM3S_FLASH_FMPRE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE2_OFFSET)
#define LM3S_FLASH_FMPRE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPRE3_OFFSET)
#define LM3S_FLASH_FMPPE0 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE0_OFFSET)
#define LM3S_FLASH_FMPPE1 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE1_OFFSET)
#define LM3S_FLASH_FMPPE2 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE2_OFFSET)
#define LM3S_FLASH_FMPPE3 (LM3S_SYSCON_BASE + LM3S_FLASH_FMPPE3_OFFSET)
#define LM_FLASH_FMPRE (LM_SYSCON_BASE + LM_FLASH_FMPRE_OFFSET)
#define LM_FLASH_FMPPE (LM_SYSCON_BASE + LM_FLASH_FMPPE_OFFSET)
#define LM_FLASH_USECRL (LM_SYSCON_BASE + LM_FLASH_USECRL_OFFSET)
#define LM_FLASH_USERDBG (LM_SYSCON_BASE + LM_FLASH_USERDBG_OFFSET)
#define LM_FLASH_USERREG0 (LM_SYSCON_BASE + LM_FLASH_USERREG0_OFFSET)
#define LM_FLASH_USERREG1 (LM_SYSCON_BASE + LM_FLASH_USERREG1_OFFSET)
#define LM_FLASH_FMPRE0 (LM_SYSCON_BASE + LM_FLASH_FMPRE0_OFFSET)
#define LM_FLASH_FMPRE1 (LM_SYSCON_BASE + LM_FLASH_FMPRE1_OFFSET)
#define LM_FLASH_FMPRE2 (LM_SYSCON_BASE + LM_FLASH_FMPRE2_OFFSET)
#define LM_FLASH_FMPRE3 (LM_SYSCON_BASE + LM_FLASH_FMPRE3_OFFSET)
#define LM_FLASH_FMPPE0 (LM_SYSCON_BASE + LM_FLASH_FMPPE0_OFFSET)
#define LM_FLASH_FMPPE1 (LM_SYSCON_BASE + LM_FLASH_FMPPE1_OFFSET)
#define LM_FLASH_FMPPE2 (LM_SYSCON_BASE + LM_FLASH_FMPPE2_OFFSET)
#define LM_FLASH_FMPPE3 (LM_SYSCON_BASE + LM_FLASH_FMPPE3_OFFSET)
/* FLASH register bit defitiions ****************************************************/
/* To be provided */
@@ -125,4 +125,4 @@
* Public Function Prototypes
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_FLASH_H */
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_FLASH_H */
arch/arm/src/lm/chip/lm_gpio.h
+323 -323
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File diff suppressed because it is too large Load Diff
arch/arm/src/lm/chip/lm_i2c.h
+71 -71
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H
#define __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H
/************************************************************************************
* Included Files
@@ -50,99 +50,99 @@
/* I2C Master */
#define LM3S_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */
#define LM3S_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */
#define LM3S_I2CM_DR_OFFSET 0x008 /* I2C Master Data */
#define LM3S_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
#define LM3S_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
#define LM3S_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
#define LM3S_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
#define LM3S_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
#define LM3S_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */
#define LM_I2CM_SA_OFFSET 0x000 /* I2C Master Slave Address */
#define LM_I2CM_CS_OFFSET 0x004 /* I2C Master Control/Status */
#define LM_I2CM_DR_OFFSET 0x008 /* I2C Master Data */
#define LM_I2CM_TPR_OFFSET 0x00c /* I2C Master Timer Period */
#define LM_I2CM_IMR_OFFSET 0x010 /* I2C Master Interrupt Mask */
#define LM_I2CM_RIS_OFFSET 0x014 /* I2C Master Raw Interrupt Status */
#define LM_I2CM_MIS_OFFSET 0x018 /* I2C Master Masked Interrupt Status */
#define LM_I2CM_ICR_OFFSET 0x01c /* I2C Master Interrupt Clear */
#define LM_I2CM_CR_OFFSET 0x020 /* I2C Master Configuration */
/* I2C Slave */
#define LM3S_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
#define LM3S_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
#define LM3S_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */
#define LM3S_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
#define LM3S_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
#define LM3S_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
#define LM3S_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
#define LM_I2CS_OAR_OFFSET 0x000 /* I2C Slave Own Address */
#define LM_I2CS_CSR_OFFSET 0x004 /* I2C Slave Control/Status */
#define LM_I2CS_DR_OFFSET 0x008 /* I2C Slave Data */
#define LM_I2CS_IMR_OFFSET 0x00c /* I2C Slave Interrupt Mask */
#define LM_I2CS_RIS_OFFSET 0x010 /* I2C Slave Raw Interrupt Status */
#define LM_I2CS_MIS_OFFSET 0x014 /* I2C Slave Masked Interrupt Status */
#define LM_I2CS_ICR_OFFSET 0x018 /* I2C Slave Interrupt Clear */
/* I2C Register Addresses ***********************************************************/
#if LM3S_NI2C > 0
#if LM_NI2C > 0
/* I2C Master */
#define LM3S_I2CM_BASE(n) (LM3S_I2CM0_BASE + (n)*0x1000)
#define LM3S_I2CM_SA(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_SA_OFFSET)
#define LM3S_I2CM_CS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CS_OFFSET)
#define LM3S_I2CM_DR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_DR_OFFSET)
#define LM3S_I2CM_TPR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_TPR_OFFSET)
#define LM3S_I2CM_IMR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_IMR_OFFSET)
#define LM3S_I2CM_RIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_RIS_OFFSET)
#define LM3S_I2CM_MIS(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_MIS_OFFSET)
#define LM3S_I2CM_ICR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_ICR_OFFSET)
#define LM3S_I2CM_CR(n) (LM3S_I2CM_BASE(n) + LM3S_I2CM_CR_OFFSET)
#define LM_I2CM_BASE(n) (LM_I2CM0_BASE + (n)*0x1000)
#define LM_I2CM_SA(n) (LM_I2CM_BASE(n) + LM_I2CM_SA_OFFSET)
#define LM_I2CM_CS(n) (LM_I2CM_BASE(n) + LM_I2CM_CS_OFFSET)
#define LM_I2CM_DR(n) (LM_I2CM_BASE(n) + LM_I2CM_DR_OFFSET)
#define LM_I2CM_TPR(n) (LM_I2CM_BASE(n) + LM_I2CM_TPR_OFFSET)
#define LM_I2CM_IMR(n) (LM_I2CM_BASE(n) + LM_I2CM_IMR_OFFSET)
#define LM_I2CM_RIS(n) (LM_I2CM_BASE(n) + LM_I2CM_RIS_OFFSET)
#define LM_I2CM_MIS(n) (LM_I2CM_BASE(n) + LM_I2CM_MIS_OFFSET)
#define LM_I2CM_ICR(n) (LM_I2CM_BASE(n) + LM_I2CM_ICR_OFFSET)
#define LM_I2CM_CR(n) (LM_I2CM_BASE(n) + LM_I2CM_CR_OFFSET)
/* I2C Slave */
#define LM3S_I2CS_BASE(n) (LM3S_I2CS0_BASE + (n)*0x1000)
#define LM3S_I2CS_OAR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_OAR_OFFSET)
#define LM3S_I2CS_CSR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_CSR_OFFSET)
#define LM3S_I2CS_DR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_DR_OFFSET)
#define LM3S_I2CS_IMR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_IMR_OFFSET)
#define LM3S_I2CS_RIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_RIS_OFFSET)
#define LM3S_I2CS_MIS(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_MIS_OFFSET)
#define LM3S_I2CS_ICR(n) (LM3S_I2CS_BASE(n) + LM3S_I2CS_ICR_OFFSET)
#define LM_I2CS_BASE(n) (LM_I2CS0_BASE + (n)*0x1000)
#define LM_I2CS_OAR(n) (LM_I2CS_BASE(n) + LM_I2CS_OAR_OFFSET)
#define LM_I2CS_CSR(n) (LM_I2CS_BASE(n) + LM_I2CS_CSR_OFFSET)
#define LM_I2CS_DR(n) (LM_I2CS_BASE(n) + LM_I2CS_DR_OFFSET)
#define LM_I2CS_IMR(n) (LM_I2CS_BASE(n) + LM_I2CS_IMR_OFFSET)
#define LM_I2CS_RIS(n) (LM_I2CS_BASE(n) + LM_I2CS_RIS_OFFSET)
#define LM_I2CS_MIS(n) (LM_I2CS_BASE(n) + LM_I2CS_MIS_OFFSET)
#define LM_I2CS_ICR(n) (LM_I2CS_BASE(n) + LM_I2CS_ICR_OFFSET)
/* I2C0 Master */
#define LM3S_I2CM0_SA (LM3S_I2CM0_BASE + LM3S_I2CM_SA_OFFSET)
#define LM3S_I2CM0_CS (LM3S_I2CM0_BASE + LM3S_I2CM_CS_OFFSET)
#define LM3S_I2CM0_DR (LM3S_I2CM0_BASE + LM3S_I2CM_DR_OFFSET)
#define LM3S_I2CM0_TPR (LM3S_I2CM0_BASE + LM3S_I2CM_TPR_OFFSET)
#define LM3S_I2CM0_IMR (LM3S_I2CM0_BASE + LM3S_I2CM_IMR_OFFSET)
#define LM3S_I2CM0_RIS (LM3S_I2CM0_BASE + LM3S_I2CM_RIS_OFFSET)
#define LM3S_I2CM0_MIS (LM3S_I2CM0_BASE + LM3S_I2CM_MIS_OFFSET)
#define LM3S_I2CM0_ICR (LM3S_I2CM0_BASE + LM3S_I2CM_ICR_OFFSET)
#define LM3S_I2CM0_CR (LM3S_I2CM0_BASE + LM3S_I2CM_CR_OFFSET)
#define LM_I2CM0_SA (LM_I2CM0_BASE + LM_I2CM_SA_OFFSET)
#define LM_I2CM0_CS (LM_I2CM0_BASE + LM_I2CM_CS_OFFSET)
#define LM_I2CM0_DR (LM_I2CM0_BASE + LM_I2CM_DR_OFFSET)
#define LM_I2CM0_TPR (LM_I2CM0_BASE + LM_I2CM_TPR_OFFSET)
#define LM_I2CM0_IMR (LM_I2CM0_BASE + LM_I2CM_IMR_OFFSET)
#define LM_I2CM0_RIS (LM_I2CM0_BASE + LM_I2CM_RIS_OFFSET)
#define LM_I2CM0_MIS (LM_I2CM0_BASE + LM_I2CM_MIS_OFFSET)
#define LM_I2CM0_ICR (LM_I2CM0_BASE + LM_I2CM_ICR_OFFSET)
#define LM_I2CM0_CR (LM_I2CM0_BASE + LM_I2CM_CR_OFFSET)
/* I2C0 Slave */
#define LM3S_I2CS0_OAR (LM3S_I2CS0_BASE + LM3S_I2CS_OAR_OFFSET)
#define LM3S_I2CS0_CSR (LM3S_I2CS0_BASE + LM3S_I2CS_CSR_OFFSET)
#define LM3S_I2CS0_DR (LM3S_I2CS0_BASE + LM3S_I2CS_DR_OFFSET)
#define LM3S_I2CS0_IMR (LM3S_I2CS0_BASE + LM3S_I2CS_IMR_OFFSET)
#define LM3S_I2CS0_RIS (LM3S_I2CS0_BASE + LM3S_I2CS_RIS_OFFSET)
#define LM3S_I2CS0_MIS (LM3S_I2CS0_BASE + LM3S_I2CS_MIS_OFFSET)
#define LM3S_I2CS0_ICR (LM3S_I2CS0_BASE + LM3S_I2CS_ICR_OFFSET)
#define LM_I2CS0_OAR (LM_I2CS0_BASE + LM_I2CS_OAR_OFFSET)
#define LM_I2CS0_CSR (LM_I2CS0_BASE + LM_I2CS_CSR_OFFSET)
#define LM_I2CS0_DR (LM_I2CS0_BASE + LM_I2CS_DR_OFFSET)
#define LM_I2CS0_IMR (LM_I2CS0_BASE + LM_I2CS_IMR_OFFSET)
#define LM_I2CS0_RIS (LM_I2CS0_BASE + LM_I2CS_RIS_OFFSET)
#define LM_I2CS0_MIS (LM_I2CS0_BASE + LM_I2CS_MIS_OFFSET)
#define LM_I2CS0_ICR (LM_I2CS0_BASE + LM_I2CS_ICR_OFFSET)
#if LM3S_NI2C > 1
#if LM_NI2C > 1
/* I2C1 Master */
#define LM3S_I2CM1_SA (LM3S_I2CM1_BASE + LM3S_I2CM_SA_OFFSET)
#define LM3S_I2CM1_CS (LM3S_I2CM1_BASE + LM3S_I2CM_CS_OFFSET)
#define LM3S_I2CM1_DR (LM3S_I2CM1_BASE + LM3S_I2CM_DR_OFFSET)
#define LM3S_I2CM1_TPR (LM3S_I2CM1_BASE + LM3S_I2CM_TPR_OFFSET)
#define LM3S_I2CM1_IMR (LM3S_I2CM1_BASE + LM3S_I2CM_IMR_OFFSET)
#define LM3S_I2CM1_RIS (LM3S_I2CM1_BASE + LM3S_I2CM_RIS_OFFSET)
#define LM3S_I2CM1_MIS (LM3S_I2CM1_BASE + LM3S_I2CM_MIS_OFFSET)
#define LM3S_I2CM1_ICR (LM3S_I2CM1_BASE + LM3S_I2CM_ICR_OFFSET)
#define LM3S_I2CM1_CR (LM3S_I2CM1_BASE + LM3S_I2CM_CR_OFFSET)
#define LM_I2CM1_SA (LM_I2CM1_BASE + LM_I2CM_SA_OFFSET)
#define LM_I2CM1_CS (LM_I2CM1_BASE + LM_I2CM_CS_OFFSET)
#define LM_I2CM1_DR (LM_I2CM1_BASE + LM_I2CM_DR_OFFSET)
#define LM_I2CM1_TPR (LM_I2CM1_BASE + LM_I2CM_TPR_OFFSET)
#define LM_I2CM1_IMR (LM_I2CM1_BASE + LM_I2CM_IMR_OFFSET)
#define LM_I2CM1_RIS (LM_I2CM1_BASE + LM_I2CM_RIS_OFFSET)
#define LM_I2CM1_MIS (LM_I2CM1_BASE + LM_I2CM_MIS_OFFSET)
#define LM_I2CM1_ICR (LM_I2CM1_BASE + LM_I2CM_ICR_OFFSET)
#define LM_I2CM1_CR (LM_I2CM1_BASE + LM_I2CM_CR_OFFSET)
/* I2C1 Slave */
#define LM3S_I2CS1_OAR (LM3S_I2CS1_BASE + LM3S_I2CS_OAR_OFFSET)
#define LM3S_I2CS1_CSR (LM3S_I2CS1_BASE + LM3S_I2CS_CSR_OFFSET)
#define LM3S_I2CS1_DR (LM3S_I2CS1_BASE + LM3S_I2CS_DR_OFFSET)
#define LM3S_I2CS1_IMR (LM3S_I2CS1_BASE + LM3S_I2CS_IMR_OFFSET)
#define LM3S_I2CS1_RIS (LM3S_I2CS1_BASE + LM3S_I2CS_RIS_OFFSET)
#define LM3S_I2CS1_MIS (LM3S_I2CS1_BASE + LM3S_I2CS_MIS_OFFSET)
#define LM3S_I2CS1_ICR (LM3S_I2CS1_BASE + LM3S_I2CS_ICR_OFFSET)
#define LM_I2CS1_OAR (LM_I2CS1_BASE + LM_I2CS_OAR_OFFSET)
#define LM_I2CS1_CSR (LM_I2CS1_BASE + LM_I2CS_CSR_OFFSET)
#define LM_I2CS1_DR (LM_I2CS1_BASE + LM_I2CS_DR_OFFSET)
#define LM_I2CS1_IMR (LM_I2CS1_BASE + LM_I2CS_IMR_OFFSET)
#define LM_I2CS1_RIS (LM_I2CS1_BASE + LM_I2CS_RIS_OFFSET)
#define LM_I2CS1_MIS (LM_I2CS1_BASE + LM_I2CS_MIS_OFFSET)
#define LM_I2CS1_ICR (LM_I2CS1_BASE + LM_I2CS_ICR_OFFSET)
#endif
#endif
@@ -244,4 +244,4 @@
* Public Function Prototypes
****************************************************************************/
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_I2C_H */
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_I2C_H */
arch/arm/src/lm/chip/lm_pinmap.h
+1 -1
View File
@@ -42,7 +42,7 @@
#include <nuttx/config.h>
/* Include the memory map file for the specific Stellaris chip */
/* Include the pin mapping file for the specific Stellaris chip */
#ifdef CONFIG_ARCH_CHIP_LM3S
# include "chip/lm3s_pinmap.h"
arch/arm/src/lm/chip/lm_ssi.h
+131 -131
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H
#define __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H
/************************************************************************************
* Included Files
@@ -43,7 +43,7 @@
#include <nuttx/config.h>
#include <sys/types.h>
#if LM3S_NSSI > 0
#if LM_NSSI > 0
/************************************************************************************
* Definitions
@@ -51,173 +51,173 @@
/* SSI register offsets *************************************************************/
#define LM3S_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */
#define LM3S_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */
#define LM3S_SSI_DR_OFFSET 0x008 /* SSI Data */
#define LM3S_SSI_SR_OFFSET 0x00c /* SSI Status */
#define LM3S_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */
#define LM3S_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */
#define LM3S_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */
#define LM3S_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */
#define LM3S_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */
#define LM3S_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
#define LM3S_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
#define LM3S_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
#define LM3S_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
#define LM3S_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
#define LM3S_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
#define LM3S_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
#define LM3S_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
#define LM3S_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */
#define LM3S_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */
#define LM3S_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */
#define LM3S_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */
#define LM_SSI_CR0_OFFSET 0x000 /* SSI Control 0 */
#define LM_SSI_CR1_OFFSET 0x004 /* SSI Control 1 */
#define LM_SSI_DR_OFFSET 0x008 /* SSI Data */
#define LM_SSI_SR_OFFSET 0x00c /* SSI Status */
#define LM_SSI_CPSR_OFFSET 0x010 /* SSI Clock Prescale */
#define LM_SSI_IM_OFFSET 0x014 /* SSI Interrupt Mask */
#define LM_SSI_RIS_OFFSET 0x018 /* SSI Raw Interrupt Status */
#define LM_SSI_MIS_OFFSET 0x01c /* SSI Masked Interrupt Status */
#define LM_SSI_ICR_OFFSET 0x020 /* SSI Interrupt Clear */
#define LM_SSI_PERIPHID4_OFFSET 0xfd0 /* SSI Peripheral Identification 4 */
#define LM_SSI_PERIPHID5_OFFSET 0xfd4 /* SSI Peripheral Identification 5 */
#define LM_SSI_PERIPHID6_OFFSET 0xfd8 /* SSI Peripheral Identification 6 */
#define LM_SSI_PERIPHID7_OFFSET 0xfdc /* SSI Peripheral Identification 7 */
#define LM_SSI_PERIPHID0_OFFSET 0xfe0 /* SSI Peripheral Identification 0 */
#define LM_SSI_PERIPHID1_OFFSET 0xfe4 /* SSI Peripheral Identification 1 */
#define LM_SSI_PERIPHID2_OFFSET 0xfe8 /* SSI Peripheral Identification 2 */
#define LM_SSI_PERIPHID3_OFFSET 0xfec /* SSI Peripheral Identification 3 */
#define LM_SSI_PCELLID0_OFFSET 0xff0 /* SSI PrimeCell Identification 0 */
#define LM_SSI_PCELLID1_OFFSET 0xff4 /* SSI PrimeCell Identification 1 */
#define LM_SSI_PCELLID2_OFFSET 0xff8 /* SSI PrimeCell Identification 2 */
#define LM_SSI_PCELLID3_OFFSET 0xffc /* SSI PrimeCell Identification 3 */
/* SSI register addresses ***********************************************************/
#define LM3S_SSI0_CR0 (LM3S_SSI0_BASE + LM3S_SSI_CR0_OFFSET)
#define LM3S_SSI0_CR1 (LM3S_SSI0_BASE + LM3S_SSI_CR1_OFFSET)
#define LM3S_SSI0_DR (LM3S_SSI0_BASE + LM3S_SSI_DR_OFFSET)
#define LM3S_SSI0_SR (LM3S_SSI0_BASE + LM3S_SSI_SR_OFFSET)
#define LM3S_SSI0_CPSR (LM3S_SSI0_BASE + LM3S_SSI_CPSR_OFFSET)
#define LM3S_SSI0_IM (LM3S_SSI0_BASE + LM3S_SSI_IM_OFFSET)
#define LM3S_SSI0_RIS (LM3S_SSI0_BASE + LM3S_SSI_RIS_OFFSET)
#define LM3S_SSI0_MIS (LM3S_SSI0_BASE + LM3S_SSI_MIS_OFFSET)
#define LM3S_SSI0_ICR (LM3S_SSI0_BASE + LM3S_SSI_ICR_OFFSET)
#define LM3S_SSI0_PERIPHID4 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID4_OFFSET)
#define LM3S_SSI0_PERIPHID5 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID5_OFFSET)
#define LM3S_SSI0_PERIPHID6 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID6_OFFSET)
#define LM3S_SSI0_PERIPHID7 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID7_OFFSET)
#define LM3S_SSI0_PERIPHID0 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID0_OFFSET)
#define LM3S_SSI0_PERIPHID1 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID1_OFFSET)
#define LM3S_SSI0_PERIPHID2 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID2_OFFSET)
#define LM3S_SSI0_PERIPHID3 (LM3S_SSI0_BASE + LM3S_SSI_PERIPHID3_OFFSET)
#define LM3S_SSI0_PCELLID0 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID0_OFFSET)
#define LM3S_SSI0_PCELLID1 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID1_OFFSET)
#define LM3S_SSI0_PCELLID2 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID2_OFFSET)
#define LM3S_SSI0_PCELLID3 (LM3S_SSI0_BASE + LM3S_SSI_PCELLID3_OFFSET)
#define LM_SSI0_CR0 (LM_SSI0_BASE + LM_SSI_CR0_OFFSET)
#define LM_SSI0_CR1 (LM_SSI0_BASE + LM_SSI_CR1_OFFSET)
#define LM_SSI0_DR (LM_SSI0_BASE + LM_SSI_DR_OFFSET)
#define LM_SSI0_SR (LM_SSI0_BASE + LM_SSI_SR_OFFSET)
#define LM_SSI0_CPSR (LM_SSI0_BASE + LM_SSI_CPSR_OFFSET)
#define LM_SSI0_IM (LM_SSI0_BASE + LM_SSI_IM_OFFSET)
#define LM_SSI0_RIS (LM_SSI0_BASE + LM_SSI_RIS_OFFSET)
#define LM_SSI0_MIS (LM_SSI0_BASE + LM_SSI_MIS_OFFSET)
#define LM_SSI0_ICR (LM_SSI0_BASE + LM_SSI_ICR_OFFSET)
#define LM_SSI0_PERIPHID4 (LM_SSI0_BASE + LM_SSI_PERIPHID4_OFFSET)
#define LM_SSI0_PERIPHID5 (LM_SSI0_BASE + LM_SSI_PERIPHID5_OFFSET)
#define LM_SSI0_PERIPHID6 (LM_SSI0_BASE + LM_SSI_PERIPHID6_OFFSET)
#define LM_SSI0_PERIPHID7 (LM_SSI0_BASE + LM_SSI_PERIPHID7_OFFSET)
#define LM_SSI0_PERIPHID0 (LM_SSI0_BASE + LM_SSI_PERIPHID0_OFFSET)
#define LM_SSI0_PERIPHID1 (LM_SSI0_BASE + LM_SSI_PERIPHID1_OFFSET)
#define LM_SSI0_PERIPHID2 (LM_SSI0_BASE + LM_SSI_PERIPHID2_OFFSET)
#define LM_SSI0_PERIPHID3 (LM_SSI0_BASE + LM_SSI_PERIPHID3_OFFSET)
#define LM_SSI0_PCELLID0 (LM_SSI0_BASE + LM_SSI_PCELLID0_OFFSET)
#define LM_SSI0_PCELLID1 (LM_SSI0_BASE + LM_SSI_PCELLID1_OFFSET)
#define LM_SSI0_PCELLID2 (LM_SSI0_BASE + LM_SSI_PCELLID2_OFFSET)
#define LM_SSI0_PCELLID3 (LM_SSI0_BASE + LM_SSI_PCELLID3_OFFSET)
#if LM3S_NSSI > 1
#define LM3S_SSI1_CR0 (LM3S_SSI1_BASE + LM3S_SSI_CR0_OFFSET)
#define LM3S_SSI1_CR1 (LM3S_SSI1_BASE + LM3S_SSI_CR1_OFFSET)
#define LM3S_SSI1_DR (LM3S_SSI1_BASE + LM3S_SSI_DR_OFFSET)
#define LM3S_SSI1_SR (LM3S_SSI1_BASE + LM3S_SSI_SR_OFFSET)
#define LM3S_SSI1_CPSR (LM3S_SSI1_BASE + LM3S_SSI_CPSR_OFFSET)
#define LM3S_SSI1_IM (LM3S_SSI1_BASE + LM3S_SSI_IM_OFFSET)
#define LM3S_SSI1_RIS (LM3S_SSI1_BASE + LM3S_SSI_RIS_OFFSET)
#define LM3S_SSI1_MIS (LM3S_SSI1_BASE + LM3S_SSI_MIS_OFFSET)
#define LM3S_SSI1_ICR (LM3S_SSI1_BASE + LM3S_SSI_ICR_OFFSET)
#define LM3S_SSI1_PERIPHID4 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID4_OFFSET)
#define LM3S_SSI1_PERIPHID5 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID5_OFFSET)
#define LM3S_SSI1_PERIPHID6 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID6_OFFSET)
#define LM3S_SSI1_PERIPHID7 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID7_OFFSET)
#define LM3S_SSI1_PERIPHID0 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID0_OFFSET)
#define LM3S_SSI1_PERIPHID1 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID1_OFFSET)
#define LM3S_SSI1_PERIPHID2 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID2_OFFSET)
#define LM3S_SSI1_PERIPHID3 (LM3S_SSI1_BASE + LM3S_SSI_PERIPHID3_OFFSET)
#define LM3S_SSI1_PCELLID0 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID0_OFFSET)
#define LM3S_SSI1_PCELLID1 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID1_OFFSET)
#define LM3S_SSI1_PCELLID2 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID2_OFFSET)
#define LM3S_SSI1_PCELLID3 (LM3S_SSI1_BASE + LM3S_SSI_PCELLID3_OFFSET)
#if LM_NSSI > 1
#define LM_SSI1_CR0 (LM_SSI1_BASE + LM_SSI_CR0_OFFSET)
#define LM_SSI1_CR1 (LM_SSI1_BASE + LM_SSI_CR1_OFFSET)
#define LM_SSI1_DR (LM_SSI1_BASE + LM_SSI_DR_OFFSET)
#define LM_SSI1_SR (LM_SSI1_BASE + LM_SSI_SR_OFFSET)
#define LM_SSI1_CPSR (LM_SSI1_BASE + LM_SSI_CPSR_OFFSET)
#define LM_SSI1_IM (LM_SSI1_BASE + LM_SSI_IM_OFFSET)
#define LM_SSI1_RIS (LM_SSI1_BASE + LM_SSI_RIS_OFFSET)
#define LM_SSI1_MIS (LM_SSI1_BASE + LM_SSI_MIS_OFFSET)
#define LM_SSI1_ICR (LM_SSI1_BASE + LM_SSI_ICR_OFFSET)
#define LM_SSI1_PERIPHID4 (LM_SSI1_BASE + LM_SSI_PERIPHID4_OFFSET)
#define LM_SSI1_PERIPHID5 (LM_SSI1_BASE + LM_SSI_PERIPHID5_OFFSET)
#define LM_SSI1_PERIPHID6 (LM_SSI1_BASE + LM_SSI_PERIPHID6_OFFSET)
#define LM_SSI1_PERIPHID7 (LM_SSI1_BASE + LM_SSI_PERIPHID7_OFFSET)
#define LM_SSI1_PERIPHID0 (LM_SSI1_BASE + LM_SSI_PERIPHID0_OFFSET)
#define LM_SSI1_PERIPHID1 (LM_SSI1_BASE + LM_SSI_PERIPHID1_OFFSET)
#define LM_SSI1_PERIPHID2 (LM_SSI1_BASE + LM_SSI_PERIPHID2_OFFSET)
#define LM_SSI1_PERIPHID3 (LM_SSI1_BASE + LM_SSI_PERIPHID3_OFFSET)
#define LM_SSI1_PCELLID0 (LM_SSI1_BASE + LM_SSI_PCELLID0_OFFSET)
#define LM_SSI1_PCELLID1 (LM_SSI1_BASE + LM_SSI_PCELLID1_OFFSET)
#define LM_SSI1_PCELLID2 (LM_SSI1_BASE + LM_SSI_PCELLID2_OFFSET)
#define LM_SSI1_PCELLID3 (LM_SSI1_BASE + LM_SSI_PCELLID3_OFFSET)
#define LM3S_SSI_BASE(n) (LM3S_SSI0_BASE + (n)*0x01000)
#define LM_SSI_BASE(n) (LM_SSI0_BASE + (n)*0x01000)
#define LM3S_SSI_CR0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR0_OFFSET)
#define LM3S_SSI_CR1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CR1_OFFSET)
#define LM3S_SSI_DR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_DR_OFFSET)
#define LM3S_SSI_SR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_SR_OFFSET)
#define LM3S_SSI_CPSR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_CPSR_OFFSET)
#define LM3S_SSI_IM(n) (LM3S_SSI_BASE(n) + LM3S_SSI_IM_OFFSET)
#define LM3S_SSI_RIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_RIS_OFFSET)
#define LM3S_SSI_MIS(n) (LM3S_SSI_BASE(n) + LM3S_SSI_MIS_OFFSET)
#define LM3S_SSI_ICR(n) (LM3S_SSI_BASE(n) + LM3S_SSI_ICR_OFFSET)
#define LM3S_SSI_PERIPHID4(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID4_OFFSET)
#define LM3S_SSI_PERIPHID5(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID5_OFFSET)
#define LM3S_SSI_PERIPHID6(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID6_OFFSET)
#define LM3S_SSI_PERIPHID7(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID7_OFFSET)
#define LM3S_SSI_PERIPHID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID0_OFFSET)
#define LM3S_SSI_PERIPHID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID1_OFFSET)
#define LM3S_SSI_PERIPHID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID2_OFFSET)
#define LM3S_SSI_PERIPHID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PERIPHID3_OFFSET)
#define LM3S_SSI_PCELLID0(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID0_OFFSET)
#define LM3S_SSI_PCELLID1(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID1_OFFSET)
#define LM3S_SSI_PCELLID2(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID2_OFFSET)
#define LM3S_SSI_PCELLID3(n) (LM3S_SSI_BASE(n) + LM3S_SSI_PCELLID3_OFFSET)
#endif /* LM3S_NSSI > 1 */
#define LM_SSI_CR0(n) (LM_SSI_BASE(n) + LM_SSI_CR0_OFFSET)
#define LM_SSI_CR1(n) (LM_SSI_BASE(n) + LM_SSI_CR1_OFFSET)
#define LM_SSI_DR(n) (LM_SSI_BASE(n) + LM_SSI_DR_OFFSET)
#define LM_SSI_SR(n) (LM_SSI_BASE(n) + LM_SSI_SR_OFFSET)
#define LM_SSI_CPSR(n) (LM_SSI_BASE(n) + LM_SSI_CPSR_OFFSET)
#define LM_SSI_IM(n) (LM_SSI_BASE(n) + LM_SSI_IM_OFFSET)
#define LM_SSI_RIS(n) (LM_SSI_BASE(n) + LM_SSI_RIS_OFFSET)
#define LM_SSI_MIS(n) (LM_SSI_BASE(n) + LM_SSI_MIS_OFFSET)
#define LM_SSI_ICR(n) (LM_SSI_BASE(n) + LM_SSI_ICR_OFFSET)
#define LM_SSI_PERIPHID4(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID4_OFFSET)
#define LM_SSI_PERIPHID5(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID5_OFFSET)
#define LM_SSI_PERIPHID6(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID6_OFFSET)
#define LM_SSI_PERIPHID7(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID7_OFFSET)
#define LM_SSI_PERIPHID0(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID0_OFFSET)
#define LM_SSI_PERIPHID1(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID1_OFFSET)
#define LM_SSI_PERIPHID2(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID2_OFFSET)
#define LM_SSI_PERIPHID3(n) (LM_SSI_BASE(n) + LM_SSI_PERIPHID3_OFFSET)
#define LM_SSI_PCELLID0(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID0_OFFSET)
#define LM_SSI_PCELLID1(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID1_OFFSET)
#define LM_SSI_PCELLID2(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID2_OFFSET)
#define LM_SSI_PCELLID3(n) (LM_SSI_BASE(n) + LM_SSI_PCELLID3_OFFSET)
#endif /* LM_NSSI > 1 */
/* SSI register bit defitiions ******************************************************/
/* SSI Control 0 (SSICR0), offset 0x000 */
#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */
#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT)
#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */
#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT)
#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */
#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */
#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */
#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */
#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */
#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */
#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT)
#define SSI_CR0_DSS_SHIFT 0 /* Bits 3-0: SSI Data Size Select */
#define SSI_CR0_DSS_MASK (0x0f << SSI_CR0_DSS_SHIFT)
#define SSI_CR0_DSS(n) ((n-1) << SSI_CR0_DSS_SHIFT) /* n={4,5,..16} */
#define SSI_CR0_FRF_SHIFT 4 /* Bits 5-4: SSI Frame Format Select */
#define SSI_CR0_FRF_MASK (3 << SSI_CR0_FRF_SHIFT)
#define SSI_CR0_FRF_SPI (0 << SSI_CR0_FRF_SHIFT) /* Freescale SPI format */
#define SSI_CR0_FRF_SSFF (1 << SSI_CR0_FRF_SHIFT) /* TI synchronous serial fram format */
#define SSI_CR0_FRF_UWIRE (2 << SSI_CR0_FRF_SHIFT) /* MICROWIRE frame format */
#define SSI_CR0_SPO (1 << 6) /* Bit 6: SSI Serial Clock Polarity */
#define SSI_CR0_SPH (1 << 7) /* Bit 7: SSI Serial Clock Phase */
#define SSI_CR0_SCR_SHIFT 8 /* Bits 15-8: SSI Serial Clock Rate */
#define SSI_CR0_SCR_MASK (0xff << SSI_CR0_SCR_SHIFT)
/* SSI Control 1 (SSICR1), offset 0x004 */
#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */
#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */
#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */
#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */
#define SSI_CR1_LBM (1 << 0) /* Bit 0: SSI Loopback Mode */
#define SSI_CR1_SSE (1 << 1) /* Bit 1: SSI Synchronous Serial Port Enable */
#define SSI_CR1_MS (1 << 2) /* Bit 2: SSI Master/Slave Select slave */
#define SSI_CR1_SOD (1 << 3) /* Bit 3: SSI Slave Mode Output Disable */
/* SSI Data (SSIDR), offset 0x008 */
#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */
#define SSI_DR_MASK 0xffff /* Bits 15-0: SSI data */
/* SSI Status (SSISR), offset 0x00c */
#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */
#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */
#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */
#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */
#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */
#define SSI_SR_TFE (1 << 0) /* Bit 0: SSI Transmit FIFO Empty */
#define SSI_SR_TNF (1 << 1) /* Bit 1: SSI Transmit FIFO Not Full */
#define SSI_SR_RNE (1 << 2) /* Bit 2: SSI Receive FIFO Not Empty */
#define SSI_SR_RFF (1 << 3) /* Bit 3: SSI Receive FIFO Full */
#define SSI_SR_BSY (1 << 4) /* Bit 4: SSI Busy Bit */
/* SSI Clock Prescale (SSICPSR), offset 0x010 */
#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */
#define SSI_CPSR_DIV_MASK 0xff /* Bits 7-0: SSI Clock Prescale Divisor */
/* SSI Interrupt Mask (SSIIM), offset 0x014 */
#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */
#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */
#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */
#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */
#define SSI_IM_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Mask */
#define SSI_IM_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Mask */
#define SSI_IM_RX (1 << 2) /* Bit 2: SSI Receive FIFO Interrupt Mask */
#define SSI_IM_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Interrupt Mask */
/* SSI Raw Interrupt Status (SSIRIS), offset 0x018 */
#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */
#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */
#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */
#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */
#define SSI_RIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Raw Interrupt Status */
#define SSI_RIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Raw Interrupt Status */
#define SSI_RIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Raw Interrupt Status */
#define SSI_RIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Raw Interrupt Status */
/* SSI Masked Interrupt Status (SSIMIS), offset 0x01c */
#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */
#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */
#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */
#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */
#define SSI_MIS_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Masked Interrupt Status */
#define SSI_MIS_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Masked Interrupt Status */
#define SSI_MIS_RX (1 << 2) /* Bit 2: SSI Receive FIFO Masked Interrupt Status */
#define SSI_MIS_TX (1 << 3) /* Bit 3: SSI Transmit FIFO Masked Interrupt Status */
/* SSI Interrupt Clear (SSIICR), offset 0x020 */
#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */
#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */
#define SSI_ICR_ROR (1 << 0) /* Bit 0: SSI Receive Overrun Interrupt Clear */
#define SSI_ICR_RT (1 << 1) /* Bit 1: SSI Receive Time-Out Interrupt Clear */
/* SSI Peripheral Identification n (SSIPERIPHIDn), offset 0xfd0-0xfec */
#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */
#define SSI_PERIPHID_MASK 0xff /* Bits 7-0: SSI Peripheral ID n */
/* SSI PrimeCell Identification n (SSIPCELLIDn), offset 0xff0-0xffc */
#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */
#define SSI_PCELLID_MASK 0xff /* Bits 7-0: SSI Prime cell ID */
/************************************************************************************
* Public Types
@@ -231,5 +231,5 @@
* Public Function Prototypes
************************************************************************************/
#endif /* LM3S_NSSI > 0 */
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SSI_H */
#endif /* LM_NSSI > 0 */
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_SSI_H */
arch/arm/src/lm/chip/lm_syscontrol.h
+61 -61
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H
#define __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H
/************************************************************************************
* Included Files
@@ -48,67 +48,67 @@
/* System Control Register Offsets **************************************************/
#define LM3S_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
#define LM3S_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
#define LM3S_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
#define LM3S_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
#define LM3S_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
#define LM3S_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
#define LM3S_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
#define LM3S_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */
#define LM3S_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */
#define LM3S_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
#define LM3S_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
#define LM3S_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/
#define LM3S_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */
#define LM3S_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */
#define LM3S_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */
#define LM3S_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */
#define LM3S_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */
#define LM3S_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */
#define LM3S_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */
#define LM3S_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
#define LM3S_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
#define LM3S_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
#define LM3S_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
#define LM3S_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
#define LM3S_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
#define LM3S_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
#define LM3S_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
#define LM3S_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
#define LM3S_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
#define LM_SYSCON_DID0_OFFSET 0x000 /* Device Identification 0 */
#define LM_SYSCON_DID1_OFFSET 0x004 /* Device Identification 1 */
#define LM_SYSCON_DC0_OFFSET 0x008 /* Device Capabilities 0 */
#define LM_SYSCON_DC1_OFFSET 0x010 /* Device Capabilities 1 */
#define LM_SYSCON_DC2_OFFSET 0x014 /* Device Capabilities 2 */
#define LM_SYSCON_DC3_OFFSET 0x018 /* Device Capabilities 3 */
#define LM_SYSCON_DC4_OFFSET 0x01c /* Device Capabilities 4 */
#define LM_SYSCON_PBORCTL_OFFSET 0x030 /* Brown-Out Reset Control */
#define LM_SYSCON_LDOPCTL_OFFSET 0x034 /* LDO Power Control */
#define LM_SYSCON_SRCR0_OFFSET 0x040 /* Software Reset Control 0 */
#define LM_SYSCON_SRCR1_OFFSET 0x044 /* Software Reset Control 1 */
#define LM_SYSCON_SRCR2_OFFSET 0x048 /* Software Reset Control 2*/
#define LM_SYSCON_RIS_OFFSET 0x050 /* Raw Interrupt Status */
#define LM_SYSCON_IMC_OFFSET 0x054 /* Interrupt Mask Control */
#define LM_SYSCON_MISC_OFFSET 0x058 /* Masked Interrupt Status and Clear */
#define LM_SYSCON_RESC_OFFSET 0x05c /* Reset Cause */
#define LM_SYSCON_RCC_OFFSET 0x060 /* Run-Mode Clock Configuration */
#define LM_SYSCON_PLLCFG_OFFSET 0x064 /* XTAL to PLL Translation */
#define LM_SYSCON_RCC2_OFFSET 0x070 /* Run-Mode Clock Configuration 2 */
#define LM_SYSCON_RCGC0_OFFSET 0x100 /* Run Mode Clock Gating Control Register 0 */
#define LM_SYSCON_RCGC1_OFFSET 0x104 /* Run Mode Clock Gating Control Register 1 */
#define LM_SYSCON_RCGC2_OFFSET 0x108 /* Run Mode Clock Gating Control Register 2 */
#define LM_SYSCON_SCGC0_OFFSET 0x110 /* Sleep Mode Clock Gating Control Register 0 */
#define LM_SYSCON_SCGC1_OFFSET 0x114 /* Sleep Mode Clock Gating Control Register 1 */
#define LM_SYSCON_SCGC2_OFFSET 0x118 /* Sleep Mode Clock Gating Control Register 2 */
#define LM_SYSCON_DCGC0_OFFSET 0x120 /* Deep Sleep Mode Clock Gating Control Register 0 */
#define LM_SYSCON_DCGC1_OFFSET 0x124 /* Deep Sleep Mode Clock Gating Control Register 1 */
#define LM_SYSCON_DCGC2_OFFSET 0x128 /* Deep Sleep Mode Clock Gating Control Register 2 */
#define LM_SYSCON_DSLPCLKCFG_OFFSET 0x144 /* Deep Sleep Clock Configuration*/
/* System Control Register Addresses ************************************************/
#define LM3S_SYSCON_DID0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID0_OFFSET)
#define LM3S_SYSCON_DID1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DID1_OFFSET)
#define LM3S_SYSCON_DC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC0_OFFSET)
#define LM3S_SYSCON_DC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC1_OFFSET)
#define LM3S_SYSCON_DC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC2_OFFSET)
#define LM3S_SYSCON_DC3 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC3_OFFSET)
#define LM3S_SYSCON_DC4 (LM3S_SYSCON_BASE + LM3S_SYSCON_DC4_OFFSET)
#define LM3S_SYSCON_PBORCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_PBORCTL_OFFSET)
#define LM3S_SYSCON_LDOPCTL (LM3S_SYSCON_BASE + LM3S_SYSCON_LDOPCTL_OFFSET)
#define LM3S_SYSCON_SRCR0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR0_OFFSET)
#define LM3S_SYSCON_SRCR1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR1_OFFSET)
#define LM3S_SYSCON_SRCR2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SRCR2_OFFSET)
#define LM3S_SYSCON_RIS (LM3S_SYSCON_BASE + LM3S_SYSCON_RIS_OFFSET)
#define LM3S_SYSCON_IMC (LM3S_SYSCON_BASE + LM3S_SYSCON_IMC_OFFSET)
#define LM3S_SYSCON_MISC (LM3S_SYSCON_BASE + LM3S_SYSCON_MISC_OFFSET)
#define LM3S_SYSCON_RESC (LM3S_SYSCON_BASE + LM3S_SYSCON_RESC_OFFSET)
#define LM3S_SYSCON_RCC (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC_OFFSET)
#define LM3S_SYSCON_PLLCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_PLLCFG_OFFSET)
#define LM3S_SYSCON_RCC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCC2_OFFSET)
#define LM3S_SYSCON_RCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC0_OFFSET)
#define LM3S_SYSCON_RCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC1_OFFSET)
#define LM3S_SYSCON_RCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_RCGC2_OFFSET)
#define LM3S_SYSCON_SCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC0_OFFSET)
#define LM3S_SYSCON_SCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC1_OFFSET)
#define LM3S_SYSCON_SCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_SCGC2_OFFSET)
#define LM3S_SYSCON_DCGC0 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC0_OFFSET)
#define LM3S_SYSCON_DCGC1 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC1_OFFSET)
#define LM3S_SYSCON_DCGC2 (LM3S_SYSCON_BASE + LM3S_SYSCON_DCGC2_OFFSET)
#define LM3S_SYSCON_DSLPCLKCFG (LM3S_SYSCON_BASE + LM3S_SYSCON_DSLPCLKCFG_OFFSET)
#define LM_SYSCON_DID0 (LM_SYSCON_BASE + LM_SYSCON_DID0_OFFSET)
#define LM_SYSCON_DID1 (LM_SYSCON_BASE + LM_SYSCON_DID1_OFFSET)
#define LM_SYSCON_DC0 (LM_SYSCON_BASE + LM_SYSCON_DC0_OFFSET)
#define LM_SYSCON_DC1 (LM_SYSCON_BASE + LM_SYSCON_DC1_OFFSET)
#define LM_SYSCON_DC2 (LM_SYSCON_BASE + LM_SYSCON_DC2_OFFSET)
#define LM_SYSCON_DC3 (LM_SYSCON_BASE + LM_SYSCON_DC3_OFFSET)
#define LM_SYSCON_DC4 (LM_SYSCON_BASE + LM_SYSCON_DC4_OFFSET)
#define LM_SYSCON_PBORCTL (LM_SYSCON_BASE + LM_SYSCON_PBORCTL_OFFSET)
#define LM_SYSCON_LDOPCTL (LM_SYSCON_BASE + LM_SYSCON_LDOPCTL_OFFSET)
#define LM_SYSCON_SRCR0 (LM_SYSCON_BASE + LM_SYSCON_SRCR0_OFFSET)
#define LM_SYSCON_SRCR1 (LM_SYSCON_BASE + LM_SYSCON_SRCR1_OFFSET)
#define LM_SYSCON_SRCR2 (LM_SYSCON_BASE + LM_SYSCON_SRCR2_OFFSET)
#define LM_SYSCON_RIS (LM_SYSCON_BASE + LM_SYSCON_RIS_OFFSET)
#define LM_SYSCON_IMC (LM_SYSCON_BASE + LM_SYSCON_IMC_OFFSET)
#define LM_SYSCON_MISC (LM_SYSCON_BASE + LM_SYSCON_MISC_OFFSET)
#define LM_SYSCON_RESC (LM_SYSCON_BASE + LM_SYSCON_RESC_OFFSET)
#define LM_SYSCON_RCC (LM_SYSCON_BASE + LM_SYSCON_RCC_OFFSET)
#define LM_SYSCON_PLLCFG (LM_SYSCON_BASE + LM_SYSCON_PLLCFG_OFFSET)
#define LM_SYSCON_RCC2 (LM_SYSCON_BASE + LM_SYSCON_RCC2_OFFSET)
#define LM_SYSCON_RCGC0 (LM_SYSCON_BASE + LM_SYSCON_RCGC0_OFFSET)
#define LM_SYSCON_RCGC1 (LM_SYSCON_BASE + LM_SYSCON_RCGC1_OFFSET)
#define LM_SYSCON_RCGC2 (LM_SYSCON_BASE + LM_SYSCON_RCGC2_OFFSET)
#define LM_SYSCON_SCGC0 (LM_SYSCON_BASE + LM_SYSCON_SCGC0_OFFSET)
#define LM_SYSCON_SCGC1 (LM_SYSCON_BASE + LM_SYSCON_SCGC1_OFFSET)
#define LM_SYSCON_SCGC2 (LM_SYSCON_BASE + LM_SYSCON_SCGC2_OFFSET)
#define LM_SYSCON_DCGC0 (LM_SYSCON_BASE + LM_SYSCON_DCGC0_OFFSET)
#define LM_SYSCON_DCGC1 (LM_SYSCON_BASE + LM_SYSCON_DCGC1_OFFSET)
#define LM_SYSCON_DCGC2 (LM_SYSCON_BASE + LM_SYSCON_DCGC2_OFFSET)
#define LM_SYSCON_DSLPCLKCFG (LM_SYSCON_BASE + LM_SYSCON_DSLPCLKCFG_OFFSET)
/* System Control Register Bit Definitions ******************************************/
@@ -492,4 +492,4 @@
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_SYSCONTROL_H */
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_SYSCONTROL_H */
arch/arm/src/lm/chip/lm_timer.h
+20 -20
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H
#define __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H
/************************************************************************************
* Included Files
@@ -46,27 +46,27 @@
/* Timer register offsets ***********************************************************/
#define TIMER_GPTMCFG_OFFSET 0x000
#define TIMER_GPTMTAMR_OFFSET 0x004
#define TIMER_GPTMCTL_OFFSET 0x00C
#define TIMER_GPTMIMR_OFFSET 0x018
#define TIMER_GPTMRIS_OFFSET 0x01C
#define TIMER_GPTMICR_OFFSET 0x024
#define TIMER_GPTMTAILR_OFFSET 0x028
#define TIMER_GPTMTAR_OFFSET 0x048
#define LM_TIMER_GPTMCFG_OFFSET 0x000
#define LM_TIMER_GPTMTAMR_OFFSET 0x004
#define LM_TIMER_GPTMCTL_OFFSET 0x00c
#define LM_TIMER_GPTMIMR_OFFSET 0x018
#define LM_TIMER_GPTMRIS_OFFSET 0x01c
#define LM_TIMER_GPTMICR_OFFSET 0x024
#define LM_TIMER_GPTMTAILR_OFFSET 0x028
#define LM_TIMER_GPTMTAR_OFFSET 0x048
/* SSI register addresses ***********************************************************/
#define LM3S_TIMER_BASE(n) (LM3S_TIMER0_BASE + (n)*0x01000)
#define LM_TIMER_BASE(n) (LM_TIMER0_BASE + (n)*0x01000)
#define LM3S_TIMER_GPTMCFG(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCFG_OFFSET)
#define LM3S_TIMER_GPTMTAMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAMR_OFFSET)
#define LM3S_TIMER_GPTMCTL(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMCTL_OFFSET)
#define LM3S_TIMER_GPTMIMR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMIMR_OFFSET)
#define LM3S_TIMER_GPTMRIS(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMRIS_OFFSET)
#define LM3S_TIMER_GPTMICR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMICR_OFFSET)
#define LM3S_TIMER_GPTMTAILR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAILR_OFFSET)
#define LM3S_TIMER_GPTMTAR(n) (LM3S_TIMER_BASE(n) + TIMER_GPTMTAR_OFFSET)
#define LM_TIMER_GPTMCFG(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCFG_OFFSET)
#define LM_TIMER_GPTMTAMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAMR_OFFSET)
#define LM_TIMER_GPTMCTL(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMCTL_OFFSET)
#define LM_TIMER_GPTMIMR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMIMR_OFFSET)
#define LM_TIMER_GPTMRIS(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMRIS_OFFSET)
#define LM_TIMER_GPTMICR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMICR_OFFSET)
#define LM_TIMER_GPTMTAILR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAILR_OFFSET)
#define LM_TIMER_GPTMTAR(n) (LM_TIMER_BASE(n) + LM_TIMER_GPTMTAR_OFFSET)
/* SSI register bit defitiions ******************************************************/
@@ -122,4 +122,4 @@
#define TIMER_GPTMICR_TATOCINT_SHIFT 0 /* Bits 0: GPTM Timer A Time-Out Raw Interrupt Clear*/
#define TIMER_GPTMICR_TATOCINT_MASK (0x01 << TIMER_GPTMICR_TATOCINT_SHIFT)
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_TIMER_H */
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_TIMER_H */
arch/arm/src/lm/chip/lm_uart.h
+127 -127
View File
@@ -33,8 +33,8 @@
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
#define __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H
#ifndef __ARCH_ARM_SRC_LM_CHIP_LM_UART_H
#define __ARCH_ARM_SRC_LM_CHIP_LM_UART_H
/************************************************************************************
* Included Files
@@ -48,117 +48,117 @@
/* UART register offsets ************************************************************/
#define LM3S_UART_DR_OFFSET 0x000 /* UART Data */
#define LM3S_UART_RSR_OFFSET 0x004 /* UART Receive Status */
#define LM3S_UART_ECR_OFFSET 0x004 /* UART Error Clear */
#define LM3S_UART_FR_OFFSET 0x018 /* UART Flag */
#define LM3S_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */
#define LM3S_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/
#define LM3S_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */
#define LM3S_UART_LCRH_OFFSET 0x02c /* UART Line Control */
#define LM3S_UART_CTL_OFFSET 0x030 /* UART Control */
#define LM3S_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */
#define LM3S_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */
#define LM3S_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */
#define LM3S_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */
#define LM3S_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */
#define LM3S_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
#define LM3S_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
#define LM3S_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
#define LM3S_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
#define LM3S_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
#define LM3S_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
#define LM3S_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
#define LM3S_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
#define LM3S_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */
#define LM3S_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */
#define LM3S_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */
#define LM3S_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */
#define LM_UART_DR_OFFSET 0x000 /* UART Data */
#define LM_UART_RSR_OFFSET 0x004 /* UART Receive Status */
#define LM_UART_ECR_OFFSET 0x004 /* UART Error Clear */
#define LM_UART_FR_OFFSET 0x018 /* UART Flag */
#define LM_UART_ILPR_OFFSET 0x020 /* UART IrDA Low-Power Register */
#define LM_UART_IBRD_OFFSET 0x024 /* UART Integer Baud-Rate Divisor*/
#define LM_UART_FBRD_OFFSET 0x028 /* UART Fractional Baud-Rate Divisor */
#define LM_UART_LCRH_OFFSET 0x02c /* UART Line Control */
#define LM_UART_CTL_OFFSET 0x030 /* UART Control */
#define LM_UART_IFLS_OFFSET 0x034 /* UART Interrupt FIFO Level Select */
#define LM_UART_IM_OFFSET 0x038 /* UART Interrupt Mask */
#define LM_UART_RIS_OFFSET 0x03c /* UART Raw Interrupt Status */
#define LM_UART_MIS_OFFSET 0x040 /* UART Masked Interrupt Status */
#define LM_UART_ICR_OFFSET 0x044 /* UART Interrupt Clear */
#define LM_UART_PERIPHID4_OFFSET 0xfd0 /* UART Peripheral Identification 4 */
#define LM_UART_PERIPHID5_OFFSET 0xfd4 /* UART Peripheral Identification 5 */
#define LM_UART_PERIPHID6_OFFSET 0xfd8 /* UART Peripheral Identification 6 */
#define LM_UART_PERIPHID7_OFFSET 0xfdc /* UART Peripheral Identification 7 */
#define LM_UART_PERIPHID0_OFFSET 0xfe0 /* UART Peripheral Identification 0 */
#define LM_UART_PERIPHID1_OFFSET 0xfe4 /* UART Peripheral Identification 1 */
#define LM_UART_PERIPHID2_OFFSET 0xfe8 /* UART Peripheral Identification 2 */
#define LM_UART_PERIPHID3_OFFSET 0xfec /* UART Peripheral Identification 3 */
#define LM_UART_PCELLID0_OFFSET 0xff0 /* UART PrimeCell Identification 0 */
#define LM_UART_PCELLID1_OFFSET 0xff4 /* UART PrimeCell Identification 1 */
#define LM_UART_PCELLID2_OFFSET 0xff8 /* UART PrimeCell Identification 2 */
#define LM_UART_PCELLID3_OFFSET 0xffc /* UART PrimeCell Identification 3 */
/* UART register addresses **********************************************************/
#define LM3S_UART_BASE(n) (LM3S_UART0_BASE + (n)*0x01000)
#define LM_UART_BASE(n) (LM_UART0_BASE + (n)*0x01000)
#define LM3S_UART_DR(n) (LM3S_UART_BASE(n) + LM3S_UART_DR_OFFSET)
#define LM3S_UART_RSR(n) (LM3S_UART_BASE(n) + LM3S_UART_RSR_OFFSET)
#define LM3S_UART_ECR(n) (LM3S_UART_BASE(n) + LM3S_UART_ECR_OFFSET)
#define LM3S_UART_FR(n) (LM3S_UART_BASE(n) + LM3S_UART_FR_OFFSET)
#define LM3S_UART_ILPR(n) (LM3S_UART_BASE(n) + LM3S_UART_ILPR_OFFSET)
#define LM3S_UART_IBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_IBRD_OFFSET)
#define LM3S_UART_FBRD(n) (LM3S_UART_BASE(n) + LM3S_UART_FBRD_OFFSET)
#define LM3S_UART_LCRH(n) (LM3S_UART_BASE(n) + LM3S_UART_LCRH_OFFSET)
#define LM3S_UART_CTL(n) (LM3S_UART_BASE(n) + LM3S_UART_CTL_OFFSET)
#define LM3S_UART_IFLS(n) (LM3S_UART_BASE(n) + LM3S_UART_IFLS_OFFSET)
#define LM3S_UART_IM(n) (LM3S_UART_BASE(n) + LM3S_UART_IM_OFFSET)
#define LM3S_UART_RIS(n) (LM3S_UART_BASE(n) + LM3S_UART_RIS_OFFSET)
#define LM3S_UART_MIS(n) (LM3S_UART_BASE(n) + LM3S_UART_MIS_OFFSET)
#define LM3S_UART_ICR(n) (LM3S_UART_BASE(n) + LM3S_UART_ICR_OFFSET)
#define LM3S_UART_PERIPHID4(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID4_OFFSET)
#define LM3S_UART_PERIPHID5(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID5_OFFSET)
#define LM3S_UART_PERIPHID6(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID6_OFFSET)
#define LM3S_UART_PERIPHID7(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID7_OFFSET)
#define LM3S_UART_PERIPHID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID0_OFFSET)
#define LM3S_UART_PERIPHID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID1_OFFSET)
#define LM3S_UART_PERIPHID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID2_OFFSET)
#define LM3S_UART_PERIPHID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PERIPHID3_OFFSET)
#define LM3S_UART_PCELLID0(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID0_OFFSET)
#define LM3S_UART_PCELLID1(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID1_OFFSET)
#define LM3S_UART_PCELLID2(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID2_OFFSET)
#define LM3S_UART_PCELLID3(n) (LM3S_UART_BASE(n) + LM3S_UART_PCELLID3_OFFSET)
#define LM_UART_DR(n) (LM_UART_BASE(n) + LM_UART_DR_OFFSET)
#define LM_UART_RSR(n) (LM_UART_BASE(n) + LM_UART_RSR_OFFSET)
#define LM_UART_ECR(n) (LM_UART_BASE(n) + LM_UART_ECR_OFFSET)
#define LM_UART_FR(n) (LM_UART_BASE(n) + LM_UART_FR_OFFSET)
#define LM_UART_ILPR(n) (LM_UART_BASE(n) + LM_UART_ILPR_OFFSET)
#define LM_UART_IBRD(n) (LM_UART_BASE(n) + LM_UART_IBRD_OFFSET)
#define LM_UART_FBRD(n) (LM_UART_BASE(n) + LM_UART_FBRD_OFFSET)
#define LM_UART_LCRH(n) (LM_UART_BASE(n) + LM_UART_LCRH_OFFSET)
#define LM_UART_CTL(n) (LM_UART_BASE(n) + LM_UART_CTL_OFFSET)
#define LM_UART_IFLS(n) (LM_UART_BASE(n) + LM_UART_IFLS_OFFSET)
#define LM_UART_IM(n) (LM_UART_BASE(n) + LM_UART_IM_OFFSET)
#define LM_UART_RIS(n) (LM_UART_BASE(n) + LM_UART_RIS_OFFSET)
#define LM_UART_MIS(n) (LM_UART_BASE(n) + LM_UART_MIS_OFFSET)
#define LM_UART_ICR(n) (LM_UART_BASE(n) + LM_UART_ICR_OFFSET)
#define LM_UART_PERIPHID4(n) (LM_UART_BASE(n) + LM_UART_PERIPHID4_OFFSET)
#define LM_UART_PERIPHID5(n) (LM_UART_BASE(n) + LM_UART_PERIPHID5_OFFSET)
#define LM_UART_PERIPHID6(n) (LM_UART_BASE(n) + LM_UART_PERIPHID6_OFFSET)
#define LM_UART_PERIPHID7(n) (LM_UART_BASE(n) + LM_UART_PERIPHID7_OFFSET)
#define LM_UART_PERIPHID0(n) (LM_UART_BASE(n) + LM_UART_PERIPHID0_OFFSET)
#define LM_UART_PERIPHID1(n) (LM_UART_BASE(n) + LM_UART_PERIPHID1_OFFSET)
#define LM_UART_PERIPHID2(n) (LM_UART_BASE(n) + LM_UART_PERIPHID2_OFFSET)
#define LM_UART_PERIPHID3(n) (LM_UART_BASE(n) + LM_UART_PERIPHID3_OFFSET)
#define LM_UART_PCELLID0(n) (LM_UART_BASE(n) + LM_UART_PCELLID0_OFFSET)
#define LM_UART_PCELLID1(n) (LM_UART_BASE(n) + LM_UART_PCELLID1_OFFSET)
#define LM_UART_PCELLID2(n) (LM_UART_BASE(n) + LM_UART_PCELLID2_OFFSET)
#define LM_UART_PCELLID3(n) (LM_UART_BASE(n) + LM_UART_PCELLID3_OFFSET)
#define LM3S_UART0_DR (LM3S_UART0_BASE + LM3S_UART_TDR_OFFSET)
#define LM3S_UART0_RSR (LM3S_UART0_BASE + LM3S_UART_RSR_OFFSET)
#define LM3S_UART0_ECR (LM3S_UART0_BASE + LM3S_UART_ECR_OFFSET)
#define LM3S_UART0_FR (LM3S_UART0_BASE + LM3S_UART_FR_OFFSET)
#define LM3S_UART0_ILPR (LM3S_UART0_BASE + LM3S_UART_ILPR_OFFSET)
#define LM3S_UART0_IBRD (LM3S_UART0_BASE + LM3S_UART_IBRD_OFFSET)
#define LM3S_UART0_FBRD (LM3S_UART0_BASE + LM3S_UART_FBRD_OFFSET)
#define LM3S_UART0_LCRH (LM3S_UART0_BASE + LM3S_UART_LCRH_OFFSET)
#define LM3S_UART0_CTL (LM3S_UART0_BASE + LM3S_UART_CTL_OFFSET)
#define LM3S_UART0_IFLS (LM3S_UART0_BASE + LM3S_UART_IFLS_OFFSET)
#define LM3S_UART0_IM (LM3S_UART0_BASE + LM3S_UART_IM_OFFSET)
#define LM3S_UART0_RIS (LM3S_UART0_BASE + LM3S_UART_RIS_OFFSET)
#define LM3S_UART0_MIS (LM3S_UART0_BASE + LM3S_UART_MIS_OFFSET)
#define LM3S_UART0_ICR (LM3S_UART0_BASE + LM3S_UART_ICR_OFFSET)
#define LM3S_UART0_PERIPHID4 (LM3S_UART0_BASE + LM3S_UART_PERIPHID4_OFFSET)
#define LM3S_UART0_PERIPHID5 (LM3S_UART0_BASE + LM3S_UART_PERIPHID5_OFFSET)
#define LM3S_UART0_PERIPHID6 (LM3S_UART0_BASE + LM3S_UART_PERIPHID6_OFFSET)
#define LM3S_UART0_PERIPHID7 (LM3S_UART0_BASE + LM3S_UART_PERIPHID7_OFFSET)
#define LM3S_UART0_PERIPHID0 (LM3S_UART0_BASE + LM3S_UART_PERIPHID0_OFFSET)
#define LM3S_UART0_PERIPHID1 (LM3S_UART0_BASE + LM3S_UART_PERIPHID1_OFFSET)
#define LM3S_UART0_PERIPHID2 (LM3S_UART0_BASE + LM3S_UART_PERIPHID2_OFFSET)
#define LM3S_UART0_PERIPHID3 (LM3S_UART0_BASE + LM3S_UART_PERIPHID3_OFFSET)
#define LM3S_UART0_PCELLID0 (LM3S_UART0_BASE + LM3S_UART_PCELLID0_OFFSET)
#define LM3S_UART0_PCELLID1 (LM3S_UART0_BASE + LM3S_UART_PCELLID1_OFFSET)
#define LM3S_UART0_PCELLID2 (LM3S_UART0_BASE + LM3S_UART_PCELLID2_OFFSET)
#define LM3S_UART0_PCELLID3 (LM3S_UART0_BASE + LM3S_UART_PCELLID3_OFFSET)
#define LM_UART0_DR (LM_UART0_BASE + LM_UART_TDR_OFFSET)
#define LM_UART0_RSR (LM_UART0_BASE + LM_UART_RSR_OFFSET)
#define LM_UART0_ECR (LM_UART0_BASE + LM_UART_ECR_OFFSET)
#define LM_UART0_FR (LM_UART0_BASE + LM_UART_FR_OFFSET)
#define LM_UART0_ILPR (LM_UART0_BASE + LM_UART_ILPR_OFFSET)
#define LM_UART0_IBRD (LM_UART0_BASE + LM_UART_IBRD_OFFSET)
#define LM_UART0_FBRD (LM_UART0_BASE + LM_UART_FBRD_OFFSET)
#define LM_UART0_LCRH (LM_UART0_BASE + LM_UART_LCRH_OFFSET)
#define LM_UART0_CTL (LM_UART0_BASE + LM_UART_CTL_OFFSET)
#define LM_UART0_IFLS (LM_UART0_BASE + LM_UART_IFLS_OFFSET)
#define LM_UART0_IM (LM_UART0_BASE + LM_UART_IM_OFFSET)
#define LM_UART0_RIS (LM_UART0_BASE + LM_UART_RIS_OFFSET)
#define LM_UART0_MIS (LM_UART0_BASE + LM_UART_MIS_OFFSET)
#define LM_UART0_ICR (LM_UART0_BASE + LM_UART_ICR_OFFSET)
#define LM_UART0_PERIPHID4 (LM_UART0_BASE + LM_UART_PERIPHID4_OFFSET)
#define LM_UART0_PERIPHID5 (LM_UART0_BASE + LM_UART_PERIPHID5_OFFSET)
#define LM_UART0_PERIPHID6 (LM_UART0_BASE + LM_UART_PERIPHID6_OFFSET)
#define LM_UART0_PERIPHID7 (LM_UART0_BASE + LM_UART_PERIPHID7_OFFSET)
#define LM_UART0_PERIPHID0 (LM_UART0_BASE + LM_UART_PERIPHID0_OFFSET)
#define LM_UART0_PERIPHID1 (LM_UART0_BASE + LM_UART_PERIPHID1_OFFSET)
#define LM_UART0_PERIPHID2 (LM_UART0_BASE + LM_UART_PERIPHID2_OFFSET)
#define LM_UART0_PERIPHID3 (LM_UART0_BASE + LM_UART_PERIPHID3_OFFSET)
#define LM_UART0_PCELLID0 (LM_UART0_BASE + LM_UART_PCELLID0_OFFSET)
#define LM_UART0_PCELLID1 (LM_UART0_BASE + LM_UART_PCELLID1_OFFSET)
#define LM_UART0_PCELLID2 (LM_UART0_BASE + LM_UART_PCELLID2_OFFSET)
#define LM_UART0_PCELLID3 (LM_UART0_BASE + LM_UART_PCELLID3_OFFSET)
#define LM3S_UART1_DR (LM3S_UART1_BASE + LM3S_UART_DR_OFFSET)
#define LM3S_UART1_RSR (LM3S_UART1_BASE + LM3S_UART_RSR_OFFSET)
#define LM3S_UART1_ECR (LM3S_UART1_BASE + LM3S_UART_ECR_OFFSET)
#define LM3S_UART1_FR (LM3S_UART1_BASE + LM3S_UART_FR_OFFSET)
#define LM3S_UART1_ILPR (LM3S_UART1_BASE + LM3S_UART_ILPR_OFFSET)
#define LM3S_UART1_IBRD (LM3S_UART1_BASE + LM3S_UART_IBRD_OFFSET)
#define LM3S_UART1_FBRD (LM3S_UART1_BASE + LM3S_UART_FBRD_OFFSET)
#define LM3S_UART1_LCRH (LM3S_UART1_BASE + LM3S_UART_LCRH_OFFSET)
#define LM3S_UART1_CTL (LM3S_UART1_BASE + LM3S_UART_CTL_OFFSET)
#define LM3S_UART1_IFLS (LM3S_UART1_BASE + LM3S_UART_IFLS_OFFSET)
#define LM3S_UART1_IM (LM3S_UART1_BASE + LM3S_UART_IM_OFFSET)
#define LM3S_UART1_RIS (LM3S_UART1_BASE + LM3S_UART_RIS_OFFSET)
#define LM3S_UART1_MIS (LM3S_UART1_BASE + LM3S_UART_MIS_OFFSET)
#define LM3S_UART1_ICR (LM3S_UART1_BASE + LM3S_UART_ICR_OFFSET)
#define LM3S_UART1_PERIPHID4 (LM3S_UART1_BASE + LM3S_UART_PERIPHID4_OFFSET)
#define LM3S_UART1_PERIPHID5 (LM3S_UART1_BASE + LM3S_UART_PERIPHID5_OFFSET)
#define LM3S_UART1_PERIPHID6 (LM3S_UART1_BASE + LM3S_UART_PERIPHID6_OFFSET)
#define LM3S_UART1_PERIPHID7 (LM3S_UART1_BASE + LM3S_UART_PERIPHID7_OFFSET)
#define LM3S_UART1_PERIPHID0 (LM3S_UART1_BASE + LM3S_UART_PERIPHID0_OFFSET)
#define LM3S_UART1_PERIPHID1 (LM3S_UART1_BASE + LM3S_UART_PERIPHID1_OFFSET)
#define LM3S_UART1_PERIPHID2 (LM3S_UART1_BASE + LM3S_UART_PERIPHID2_OFFSET)
#define LM3S_UART1_PERIPHID3 (LM3S_UART1_BASE + LM3S_UART_PERIPHID3_OFFSET)
#define LM3S_UART1_PCELLID0 (LM3S_UART1_BASE + LM3S_UART_PCELLID0_OFFSET)
#define LM3S_UART1_PCELLID1 (LM3S_UART1_BASE + LM3S_UART_PCELLID1_OFFSET)
#define LM3S_UART1_PCELLID2 (LM3S_UART1_BASE + LM3S_UART_PCELLID2_OFFSET)
#define LM3S_UART1_PCELLID3 (LM3S_UART1_BASE + LM3S_UART_PCELLID3_OFFSET)
#define LM_UART1_DR (LM_UART1_BASE + LM_UART_DR_OFFSET)
#define LM_UART1_RSR (LM_UART1_BASE + LM_UART_RSR_OFFSET)
#define LM_UART1_ECR (LM_UART1_BASE + LM_UART_ECR_OFFSET)
#define LM_UART1_FR (LM_UART1_BASE + LM_UART_FR_OFFSET)
#define LM_UART1_ILPR (LM_UART1_BASE + LM_UART_ILPR_OFFSET)
#define LM_UART1_IBRD (LM_UART1_BASE + LM_UART_IBRD_OFFSET)
#define LM_UART1_FBRD (LM_UART1_BASE + LM_UART_FBRD_OFFSET)
#define LM_UART1_LCRH (LM_UART1_BASE + LM_UART_LCRH_OFFSET)
#define LM_UART1_CTL (LM_UART1_BASE + LM_UART_CTL_OFFSET)
#define LM_UART1_IFLS (LM_UART1_BASE + LM_UART_IFLS_OFFSET)
#define LM_UART1_IM (LM_UART1_BASE + LM_UART_IM_OFFSET)
#define LM_UART1_RIS (LM_UART1_BASE + LM_UART_RIS_OFFSET)
#define LM_UART1_MIS (LM_UART1_BASE + LM_UART_MIS_OFFSET)
#define LM_UART1_ICR (LM_UART1_BASE + LM_UART_ICR_OFFSET)
#define LM_UART1_PERIPHID4 (LM_UART1_BASE + LM_UART_PERIPHID4_OFFSET)
#define LM_UART1_PERIPHID5 (LM_UART1_BASE + LM_UART_PERIPHID5_OFFSET)
#define LM_UART1_PERIPHID6 (LM_UART1_BASE + LM_UART_PERIPHID6_OFFSET)
#define LM_UART1_PERIPHID7 (LM_UART1_BASE + LM_UART_PERIPHID7_OFFSET)
#define LM_UART1_PERIPHID0 (LM_UART1_BASE + LM_UART_PERIPHID0_OFFSET)
#define LM_UART1_PERIPHID1 (LM_UART1_BASE + LM_UART_PERIPHID1_OFFSET)
#define LM_UART1_PERIPHID2 (LM_UART1_BASE + LM_UART_PERIPHID2_OFFSET)
#define LM_UART1_PERIPHID3 (LM_UART1_BASE + LM_UART_PERIPHID3_OFFSET)
#define LM_UART1_PCELLID0 (LM_UART1_BASE + LM_UART_PCELLID0_OFFSET)
#define LM_UART1_PCELLID1 (LM_UART1_BASE + LM_UART_PCELLID1_OFFSET)
#define LM_UART1_PCELLID2 (LM_UART1_BASE + LM_UART_PCELLID2_OFFSET)
#define LM_UART1_PCELLID3 (LM_UART1_BASE + LM_UART_PCELLID3_OFFSET)
/* UART register bit settings *******************************************************/
@@ -275,62 +275,62 @@
/* UART Interrupt Clear (ICR), offset 0x044 */
#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */
#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */
#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */
#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */
#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */
#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */
#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
#define UART_ICR_RXIC (1 << 4) /* Bit 4: Receive Interrupt Clear */
#define UART_ICR_TXIC (1 << 5) /* Bit 5: Transmit Interrupt Clear */
#define UART_ICR_RTIC (1 << 6) /* Bit 6: Receive Time-Out Interrupt Clear */
#define UART_ICR_FEIC (1 << 7) /* Bit 7: Framing Error Interrupt Clear */
#define UART_ICR_PEIC (1 << 8) /* Bit 8: Parity Error Interrupt Clear */
#define UART_ICR_BEIC (1 << 9) /* Bit 9: Break Error Interrupt Clear */
#define UART_ICR_OEIC (1 << 10) /* Bit 10: Overrun Error Interrupt Clear
*/
/* UART Peripheral Identification 4 (PERIPHID4), offset 0xfd0 */
#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */
#define UART_PERIPHID4_MASK (0xff) /* UART Peripheral ID Register[7:0] */
/* UART Peripheral Identification 5 (UARTPERIPHID5), offset 0xfd4 */
#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */
#define UART_PERIPHID5_MASK (0xff) /* UART Peripheral ID Register[15:8] */
/* UART Peripheral Identification 6 (UARTPERIPHID6), offset 0xfd8 */
#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */
#define UART_PERIPHID6_MASK (0xff) /* UART Peripheral ID Register[23:16] */
/* UART Peripheral Identification 7 (UARTPERIPHID7), offset 0xfdc */
#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */
#define UART_PERIPHID7_MASK (0xff) /* UART Peripheral ID Register[31:24] */
/* UART Peripheral Identification 0 (UARTPERIPHID0), offset 0xfe0 */
#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */
#define UART_PERIPHID0_MASK (0xff) /* UART Peripheral ID Register[7:0] */
/* UART Peripheral Identification 1 (UARTPERIPHID1), offset 0xfe4 */
#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */
#define UART_PERIPHID1_MASK (0xff) /* UART Peripheral ID Register[15:8] */
/* UART Peripheral Identification 2 (UARTPERIPHID2), offset 0xfe8 */
#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */
#define UART_PERIPHID2_MASK (0xff) /* UART Peripheral ID Register[23:16] */
/* UART Peripheral Identification 3 (UARTPERIPHID3), offset 0xfec */
#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */
#define UART_PERIPHID3_MASK (0xff) /* UART Peripheral ID Register[31:24] */
/* UART PrimeCell Identification 0 (CELLID0), offset 0xff0 */
#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */
#define UART_CELLID0_MASK (0xff) /* UART PrimeCell ID Register[7:0] */
/* UART PrimeCell Identification 1 (UARTPCELLID1), offset 0xff4 */
#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */
#define UART_CELLID1_MASK (0xff) /* UART PrimeCell ID Register[15:8] */
/* UART PrimeCell Identification 2 (UARTPCELLID2), offset 0xff8 */
#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */
#define UART_CELLID02MASK (0xff) /* UART PrimeCell ID Register[23:16] */
/* UART PrimeCell Identification 3 (UARTPCELLID3), offset 0xffc */
#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */
#define UART_CELLID3_MASK (0xff) /* UART PrimeCell ID Register[31:24] */
/************************************************************************************
* Public Types
@@ -344,4 +344,4 @@
* Public Functions
************************************************************************************/
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM3S_UART_H */
#endif /* __ARCH_ARM_SRC_LM_CHIP_LM_UART_H */
arch/arm/src/lm/lm_dumpgpio.c
+14 -14
View File
@@ -60,19 +60,19 @@
/* NOTE: this is duplicated in lm_gpio.c */
#ifdef LM3S_GPIOH_BASE
#ifdef LM_GPIOH_BASE
static const uint32_t g_gpiobase[8] =
{
LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, LM3S_GPIOH_BASE,
LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE, LM_GPIOH_BASE,
};
static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H' };
#else
static const uint32_t g_gpiobase[8] =
{
LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE, 0,
LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE, 0,
};
static const char g_portchar[8] = { 'A', 'B', 'C', 'D', 'E', 'F', 'G', '?' };
@@ -138,7 +138,7 @@ int lm_dumpgpio(uint32_t pinset, const char *msg)
/* The following requires exclusive access to the GPIO registers */
flags = irqsave();
rcgc2 = getreg32(LM3S_SYSCON_RCGC2);
rcgc2 = getreg32(LM_SYSCON_RCGC2);
enabled = ((rcgc2 & SYSCON_RCGC2_GPIO(port)) != 0);
lldbg("GPIO%c pinset: %08x base: %08x -- %s\n",
@@ -151,16 +151,16 @@ int lm_dumpgpio(uint32_t pinset, const char *msg)
if (enabled)
{
lldbg(" AFSEL: %02x DEN: %02x DIR: %02x DATA: %02x\n",
getreg32(base + LM3S_GPIO_AFSEL_OFFSET), getreg32(base + LM3S_GPIO_DEN_OFFSET),
getreg32(base + LM3S_GPIO_DIR_OFFSET), getreg32(base + LM3S_GPIO_DATA_OFFSET + 0x3fc));
getreg32(base + LM_GPIO_AFSEL_OFFSET), getreg32(base + LM_GPIO_DEN_OFFSET),
getreg32(base + LM_GPIO_DIR_OFFSET), getreg32(base + LM_GPIO_DATA_OFFSET + 0x3fc));
lldbg(" IS: %02x IBE: %02x IEV: %02x IM: %02x RIS: %08x MIS: %08x\n",
getreg32(base + LM3S_GPIO_IEV_OFFSET), getreg32(base + LM3S_GPIO_IM_OFFSET),
getreg32(base + LM3S_GPIO_RIS_OFFSET), getreg32(base + LM3S_GPIO_MIS_OFFSET));
getreg32(base + LM_GPIO_IEV_OFFSET), getreg32(base + LM_GPIO_IM_OFFSET),
getreg32(base + LM_GPIO_RIS_OFFSET), getreg32(base + LM_GPIO_MIS_OFFSET));
lldbg(" 2MA: %02x 4MA: %02x 8MA: %02x ODR: %02x PUR %02x PDR: %02x SLR: %02x\n",
getreg32(base + LM3S_GPIO_DR2R_OFFSET), getreg32(base + LM3S_GPIO_DR4R_OFFSET),
getreg32(base + LM3S_GPIO_DR8R_OFFSET), getreg32(base + LM3S_GPIO_ODR_OFFSET),
getreg32(base + LM3S_GPIO_PUR_OFFSET), getreg32(base + LM3S_GPIO_PDR_OFFSET),
getreg32(base + LM3S_GPIO_SLR_OFFSET));
getreg32(base + LM_GPIO_DR2R_OFFSET), getreg32(base + LM_GPIO_DR4R_OFFSET),
getreg32(base + LM_GPIO_DR8R_OFFSET), getreg32(base + LM_GPIO_ODR_OFFSET),
getreg32(base + LM_GPIO_PUR_OFFSET), getreg32(base + LM_GPIO_PDR_OFFSET),
getreg32(base + LM_GPIO_SLR_OFFSET));
}
irqrestore(flags);
return OK;
arch/arm/src/lm/lm_ethernet.c
+126 -126
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/lm/lm_ethernet.h
+3 -3
View File
@@ -44,7 +44,7 @@
#include "chip.h"
#if LM3S_NETHCONTROLLERS > 1
#if LM_NETHCONTROLLERS > 1
/************************************************************************************
* Pre-processor Definitions
@@ -77,7 +77,7 @@ extern "C"
* Function: lm_ethinitialize
*
* Description:
* Initialize the Ethernet driver for one interface. If the LM3S chip
* Initialize the Ethernet driver for one interface. If the Stellaris chip
* supports multiple Ethernet controllers, then bould specific logic
* must implement up_netinitialize() and call this function to initialize
* the desiresed interfaces.
@@ -99,5 +99,5 @@ int lm_ethinitialize(int intf);
#endif
#endif /* __ASSEMBLY__ */
#endif /* LM3S_NETHCONTROLLERS > 1 */
#endif /* LM_NETHCONTROLLERS > 1 */
#endif /* __ARCH_ARM_SRC_LM_LM_ETHERNET_H */
arch/arm/src/lm/lm_gpio.c
+48 -48
View File
@@ -140,23 +140,23 @@ static const struct gpio_func_s g_funcbits[] =
{GPIO_INTERRUPT_SETBITS, GPIO_INTERRUPT_CLRBITS}, /* GPIO_FUNC_INTERRUPT */
};
static const uint32_t g_gpiobase[LM3S_NPORTS] =
static const uint32_t g_gpiobase[LM_NPORTS] =
{
/* All support LM3S parts have at least 7 ports, GPIOA-G */
/* All support Stellaris parts have at least 7 ports, GPIOA-G */
LM3S_GPIOA_BASE, LM3S_GPIOB_BASE, LM3S_GPIOC_BASE, LM3S_GPIOD_BASE,
LM3S_GPIOE_BASE, LM3S_GPIOF_BASE, LM3S_GPIOG_BASE,
LM_GPIOA_BASE, LM_GPIOB_BASE, LM_GPIOC_BASE, LM_GPIOD_BASE,
LM_GPIOE_BASE, LM_GPIOF_BASE, LM_GPIOG_BASE,
/* GPIOH exists on the LM3S6918 and th LM3S6B96, but not on the LM3S6965 or LM3S8962*/
#if LM3S_NPORTS > 7
LM3S_GPIOH_BASE,
#if LM_NPORTS > 7
LM_GPIOH_BASE,
#endif
/* GPIOJ exists on the LM3S6B96, but not on the LM3S6918 or LM3S6965 or LM3S8962*/
#if LM3S_NPORTS > 8
LM3S_GPIOJ_BASE,
#if LM_NPORTS > 8
LM_GPIOJ_BASE,
#endif
};
@@ -180,7 +180,7 @@ static const uint32_t g_gpiobase[LM3S_NPORTS] =
static uint32_t lm_gpiobaseaddress(unsigned int port)
{
uint32_t gpiobase = 0;
if (port < LM3S_NPORTS)
if (port < LM_NPORTS)
{
gpiobase = g_gpiobase[port];
}
@@ -215,10 +215,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
setbit = (((uint32_t)func->setbits >> ODR_SHIFT) & 1) << pinno;
clrbit = (((uint32_t)func->clrbits >> ODR_SHIFT) & 1) << pinno;
regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
regval = getreg32(base + LM_GPIO_ODR_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
putreg32(regval, base + LM_GPIO_ODR_OFFSET);
/* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
* register. When a bit is set to 1, it enables a weak pull-up resistor on the
@@ -231,10 +231,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
if (setbit || clrbit)
{
regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
regval = getreg32(base + LM_GPIO_PUR_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
putreg32(regval, base + LM_GPIO_PUR_OFFSET);
}
/* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
@@ -248,10 +248,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
if (setbit || clrbit)
{
regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
regval = getreg32(base + LM_GPIO_PDR_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
putreg32(regval, base + LM_GPIO_PDR_OFFSET);
}
/* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
@@ -266,10 +266,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
setbit = (((uint32_t)func->setbits >> DEN_SHIFT) & 1) << pinno;
clrbit = (((uint32_t)func->clrbits >> DEN_SHIFT) & 1) << pinno;
regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
regval = getreg32(base + LM_GPIO_DEN_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
putreg32(regval, base + LM_GPIO_DEN_OFFSET);
/* Set/clear/ignore the GPIO DIR bit. "The GPIODIR register is the data
* direction register. Bits set to 1 in the GPIODIR register configure
@@ -281,10 +281,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
setbit = (((uint32_t)func->setbits >> DIR_SHIFT) & 1) << pinno;
clrbit = (((uint32_t)func->clrbits >> DIR_SHIFT) & 1) << pinno;
regval = getreg32(base + LM3S_GPIO_DIR_OFFSET);
regval = getreg32(base + LM_GPIO_DIR_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM3S_GPIO_DIR_OFFSET);
putreg32(regval, base + LM_GPIO_DIR_OFFSET);
/* Set/clear/ignore the GPIO AFSEL bit. "The GPIOAFSEL register is the mode
* control select register. Writing a 1 to any bit in this register selects
@@ -298,10 +298,10 @@ static void lm_gpiofunc(uint32_t base, uint32_t pinno, const struct gpio_func_s
setbit = (((uint32_t)func->setbits >> AFSEL_SHIFT) & 1) << pinno;
clrbit = (((uint32_t)func->clrbits >> AFSEL_SHIFT) & 1) << pinno;
regval = getreg32(base + LM3S_GPIO_AFSEL_OFFSET);
regval = getreg32(base + LM_GPIO_AFSEL_OFFSET);
regval &= ~clrbit;
regval |= setbit;
putreg32(regval, base + LM3S_GPIO_AFSEL_OFFSET);
putreg32(regval, base + LM_GPIO_AFSEL_OFFSET);
}
/****************************************************************************
@@ -336,7 +336,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
* DRV8 bit in the GPIODR8R register are automatically cleared by hardware."
*/
regoffset = LM3S_GPIO_DR2R_OFFSET;
regoffset = LM_GPIO_DR2R_OFFSET;
}
break;
@@ -349,7 +349,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
* in the GPIO DR8R register are automatically cleared by hardware."
*/
regoffset = LM3S_GPIO_DR4R_OFFSET;
regoffset = LM_GPIO_DR4R_OFFSET;
}
break;
@@ -374,7 +374,7 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
* DRV4 bit in the GPIO DR4R register are automatically cleared by hardware."
*/
regoffset = LM3S_GPIO_DR8R_OFFSET;
regoffset = LM_GPIO_DR8R_OFFSET;
}
break;
}
@@ -385,10 +385,10 @@ static inline void lm_gpiopadstrength(uint32_t base, uint32_t pin, uint32_t cfgs
regval |= pin;
putreg32(regval, base + regoffset);
regval = getreg32(base + LM3S_GPIO_SLR_OFFSET);
regval = getreg32(base + LM_GPIO_SLR_OFFSET);
regval &= slrclr;
regval |= slrset;
putreg32(regval, base + LM3S_GPIO_SLR_OFFSET);
putreg32(regval, base + LM_GPIO_SLR_OFFSET);
}
/****************************************************************************
@@ -503,10 +503,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
*/
#if 0 /* always overwritten by lm_gpiofunc */
regval = getreg32(base + LM3S_GPIO_ODR_OFFSET);
regval = getreg32(base + LM_GPIO_ODR_OFFSET);
regval &= ~odrclr;
regval |= odrset;
putreg32(regval, base + LM3S_GPIO_ODR_OFFSET);
putreg32(regval, base + LM_GPIO_ODR_OFFSET);
#endif
/* Set/clear the GPIO PUR bit. "The GPIOPUR register is the pull-up control
@@ -515,10 +515,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
* corresponding bit in the GPIO Pull-Down Select (GPIOPDR) register ..."
*/
regval = getreg32(base + LM3S_GPIO_PUR_OFFSET);
regval = getreg32(base + LM_GPIO_PUR_OFFSET);
regval &= ~purclr;
regval |= purset;
putreg32(regval, base + LM3S_GPIO_PUR_OFFSET);
putreg32(regval, base + LM_GPIO_PUR_OFFSET);
/* Set/clear the GPIO PDR bit. "The GPIOPDR register is the pull-down control
* register. When a bit is set to 1, it enables a weak pull-down resistor on the
@@ -526,10 +526,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
* the corresponding bit in the GPIO Pull-Up Select (GPIOPUR) register ..."
*/
regval = getreg32(base + LM3S_GPIO_PDR_OFFSET);
regval = getreg32(base + LM_GPIO_PDR_OFFSET);
regval &= ~pdrclr;
regval |= pdrset;
putreg32(regval, base + LM3S_GPIO_PDR_OFFSET);
putreg32(regval, base + LM_GPIO_PDR_OFFSET);
/* Set/clear the GPIO DEN bit. "The GPIODEN register is the digital enable
* register. By default, with the exception of the GPIO signals used for JTAG/SWD
@@ -541,10 +541,10 @@ static inline void lm_gpiopadtype(uint32_t base, uint32_t pin, uint32_t cfgset)
*/
#if 0 /* always overwritten by lm_gpiofunc */
regval = getreg32(base + LM3S_GPIO_DEN_OFFSET);
regval = getreg32(base + LM_GPIO_DEN_OFFSET);
regval &= ~denclr;
regval |= denset;
putreg32(regval, base + LM3S_GPIO_DEN_OFFSET);
putreg32(regval, base + LM_GPIO_DEN_OFFSET);
#endif
}
@@ -589,18 +589,18 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
* on that pin. All bits are cleared by a reset."
*/
regval = getreg32(base + LM3S_GPIO_IM_OFFSET);
regval = getreg32(base + LM_GPIO_IM_OFFSET);
regval &= ~pin;
putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
putreg32(regval, base + LM_GPIO_IM_OFFSET);
/* "The GPIOICR register is the interrupt clear register. Writing a 1 to a bit
* in this register clears the corresponding interrupt edge detection logic
* register. Writing a 0 has no effect."
*/
regval = getreg32(base + LM3S_GPIO_ICR_OFFSET);
regval = getreg32(base + LM_GPIO_ICR_OFFSET);
regval |= pin;
putreg32(regval, base + LM3S_GPIO_ICR_OFFSET);
putreg32(regval, base + LM_GPIO_ICR_OFFSET);
/* Assume rising edge */
@@ -656,10 +656,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
* by a reset.
*/
regval = getreg32(base + LM3S_GPIO_IS_OFFSET);
regval = getreg32(base + LM_GPIO_IS_OFFSET);
regval &= isclr;
regval |= isset;
putreg32(regval, base + LM3S_GPIO_IS_OFFSET);
putreg32(regval, base + LM_GPIO_IS_OFFSET);
/* "The GPIO IBE register is the interrupt both-edges register. When the
* corresponding bit in the GPIO Interrupt Sense (GPIO IS) register ... is
@@ -670,10 +670,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
* are cleared by a reset.
*/
regval = getreg32(base + LM3S_GPIO_IBE_OFFSET);
regval = getreg32(base + LM_GPIO_IBE_OFFSET);
regval &= ibeclr;
regval |= ibeset;
putreg32(regval, base + LM3S_GPIO_IBE_OFFSET);
putreg32(regval, base + LM_GPIO_IBE_OFFSET);
/* "The GPIOIEV register is the interrupt event register. Bits set to
* High in GPIO IEV configure the corresponding pin to detect rising edges
@@ -683,10 +683,10 @@ static inline void lm_interrupt(uint32_t base, uint32_t pin, uint32_t cfgset)
* value in GPIOIS. All bits are cleared by a reset.
*/
regval = getreg32(base + LM3S_GPIO_IEV_OFFSET);
regval = getreg32(base + LM_GPIO_IEV_OFFSET);
regval &= iveclr;
regval |= iveset;
putreg32(regval, base + LM3S_GPIO_IEV_OFFSET);
putreg32(regval, base + LM_GPIO_IEV_OFFSET);
}
/****************************************************************************
@@ -734,9 +734,9 @@ int lm_configgpio(uint32_t cfgset)
* in the RCGC2 register."
*/
regval = getreg32(LM3S_SYSCON_RCGC2);
regval = getreg32(LM_SYSCON_RCGC2);
regval |= SYSCON_RCGC2_GPIO(port);
putreg32(regval, LM3S_SYSCON_RCGC2);
putreg32(regval, LM_SYSCON_RCGC2);
/* First, set the port to digital input. This is the safest state in which
* to perform reconfiguration.
@@ -810,7 +810,7 @@ void lm_gpiowrite(uint32_t pinset, bool value)
* "... All bits are cleared by a reset."
*/
putreg32((uint32_t)value << pinno, base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
putreg32((uint32_t)value << pinno, base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2)));
}
/****************************************************************************
@@ -849,6 +849,6 @@ bool lm_gpioread(uint32_t pinset, bool value)
* are cleared by a reset."
*/
return (getreg32(base + LM3S_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
return (getreg32(base + LM_GPIO_DATA_OFFSET + (1 << (pinno + 2))) != 0);
}
arch/arm/src/lm/lm_gpioirq.c
+45 -46
View File
@@ -73,38 +73,38 @@ static FAR xcpt_t g_gpioirqvector[NR_GPIO_IRQS];
static const uint32_t g_gpiobase[] =
{
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
LM3S_GPIOA_BASE,
LM_GPIOA_BASE,
#endif
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
LM3S_GPIOB_BASE,
LM_GPIOB_BASE,
#endif
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
LM3S_GPIOC_BASE,
LM_GPIOC_BASE,
#endif
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
LM3S_GPIOD_BASE,
LM_GPIOD_BASE,
#endif
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
LM3S_GPIOE_BASE,
LM_GPIOE_BASE,
#endif
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
LM3S_GPIOF_BASE,
LM_GPIOF_BASE,
#endif
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
LM3S_GPIOG_BASE,
LM_GPIOG_BASE,
#endif
/* NOTE: Not all LM3S architectures support GPIOs above GPIOG. If the chip
* does not support these higher ports, then they must be disabled in the
* configuration. Otherwise, the following will likely cause compilation
/* NOTE: Not all Stellaris architectures support GPIOs above GPIOG. If the
* chip does not support these higher ports, then they must be disabled in
* the configuration. Otherwise, the following will likely cause compilation
* errors!
*/
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
LM3S_GPIOH_BASE,
LM_GPIOH_BASE,
#endif
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
LM3S_GPIOJ_BASE,
LM_GPIOJ_BASE,
#endif
};
@@ -161,7 +161,7 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context)
* either no interrupt has been generated, or the interrupt is masked."
*/
mis = getreg32(regbase + LM3S_GPIO_MIS_OFFSET) & 0xff;
mis = getreg32(regbase + LM_GPIO_MIS_OFFSET) & 0xff;
/* Clear all GPIO interrupts that we are going to process. "The GPIO ICR
* register is the interrupt clear register. Writing a 1 to a bit in this
@@ -169,7 +169,7 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context)
* Writing a 0 has no effect."
*/
putreg32(mis, regbase + LM3S_GPIO_ICR_OFFSET);
putreg32(mis, regbase + LM_GPIO_ICR_OFFSET);
/* Now process each IRQ pending in the MIS */
@@ -187,63 +187,63 @@ static int lm_gpiohandler(uint32_t regbase, int irqbase, void *context)
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
static int lm_gpioahandler(int irq, FAR void *context)
{
return lm_gpiohandler(LM3S_GPIOA_BASE, LM3S_IRQ_GPIOA_0, context);
return lm_gpiohandler(LM_GPIOA_BASE, LM_IRQ_GPIOA_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
static int lm_gpiobhandler(int irq, FAR void *context)
{
return lm_gpiohandler(LM3S_GPIOB_BASE, LM3S_IRQ_GPIOB_0, context);
return lm_gpiohandler(LM_GPIOB_BASE, LM_IRQ_GPIOB_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
static int lm_gpiochandler(int irq, FAR void *context)
{
return lm_gpiohandler(LM3S_GPIOC_BASE, LM3S_IRQ_GPIOC_0, context);
return lm_gpiohandler(LM_GPIOC_BASE, LM_IRQ_GPIOC_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
static int lm_gpiodhandler(int irq, FAR void *context)
{
return lm_gpiohandler(LM3S_GPIOD_BASE, LM3S_IRQ_GPIOD_0, context);
return lm_gpiohandler(LM_GPIOD_BASE, LM_IRQ_GPIOD_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
static int lm_gpioehandler(int irq, FAR void *context)
{
return lm_gpiohandler(LM3S_GPIOE_BASE, LM3S_IRQ_GPIOE_0, context);
return lm_gpiohandler(LM_GPIOE_BASE, LM_IRQ_GPIOE_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
static int lm_gpiofhandler(int irq, FAR void *context)
{
return lm_gpiohandler(LM3S_GPIOF_BASE, LM3S_IRQ_GPIOF_0, context);
return lm_gpiohandler(LM_GPIOF_BASE, LM_IRQ_GPIOF_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
static int lm_gpioghandler(int irq, FAR void *context)
{
return lm_gpiohandler(LM3S_GPIOG_BASE, LM3S_IRQ_GPIOG_0, context);
return lm_gpiohandler(LM_GPIOG_BASE, LM_IRQ_GPIOG_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
static int lm_gpiohhandler(int irq, FAR void *context)
{
return lm_gpiohandler(LM3S_GPIOH_BASE, LM3S_IRQ_GPIOH_0, context);
return lm_gpiohandler(LM_GPIOH_BASE, LM_IRQ_GPIOH_0, context);
}
#endif
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
static int lm_gpiojhandler(int irq, FAR void *context)
{
return lm_gpiohandler(LM3S_GPIOJ_BASE, LM3S_IRQ_GPIOJ_0, context);
return lm_gpiohandler(LM_GPIOJ_BASE, LM_IRQ_GPIOJ_0, context);
}
#endif
@@ -275,40 +275,40 @@ int gpio_irqinitialize(void)
*/
#ifndef CONFIG_LM_DISABLE_GPIOA_IRQS
irq_attach(LM3S_IRQ_GPIOA, lm_gpioahandler);
up_enable_irq(LM3S_IRQ_GPIOA);
irq_attach(LM_IRQ_GPIOA, lm_gpioahandler);
up_enable_irq(LM_IRQ_GPIOA);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOB_IRQS
irq_attach(LM3S_IRQ_GPIOB, lm_gpiobhandler);
up_enable_irq(LM3S_IRQ_GPIOB);
irq_attach(LM_IRQ_GPIOB, lm_gpiobhandler);
up_enable_irq(LM_IRQ_GPIOB);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOC_IRQS
irq_attach(LM3S_IRQ_GPIOC, lm_gpiochandler);
up_enable_irq(LM3S_IRQ_GPIOC);
irq_attach(LM_IRQ_GPIOC, lm_gpiochandler);
up_enable_irq(LM_IRQ_GPIOC);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOD_IRQS
irq_attach(LM3S_IRQ_GPIOD, lm_gpiodhandler);
up_enable_irq(LM3S_IRQ_GPIOD);
irq_attach(LM_IRQ_GPIOD, lm_gpiodhandler);
up_enable_irq(LM_IRQ_GPIOD);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOE_IRQS
irq_attach(LM3S_IRQ_GPIOE, lm_gpioehandler);
up_enable_irq(LM3S_IRQ_GPIOE);
irq_attach(LM_IRQ_GPIOE, lm_gpioehandler);
up_enable_irq(LM_IRQ_GPIOE);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOF_IRQS
irq_attach(LM3S_IRQ_GPIOF, lm_gpiofhandler);
up_enable_irq(LM3S_IRQ_GPIOF);
irq_attach(LM_IRQ_GPIOF, lm_gpiofhandler);
up_enable_irq(LM_IRQ_GPIOF);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOG_IRQS
irq_attach(LM3S_IRQ_GPIOG, lm_gpioghandler);
up_enable_irq(LM3S_IRQ_GPIOG);
irq_attach(LM_IRQ_GPIOG, lm_gpioghandler);
up_enable_irq(LM_IRQ_GPIOG);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOH_IRQS
irq_attach(LM3S_IRQ_GPIOH, lm_gpiohhandler);
up_enable_irq(LM3S_IRQ_GPIOH);
irq_attach(LM_IRQ_GPIOH, lm_gpiohhandler);
up_enable_irq(LM_IRQ_GPIOH);
#endif
#ifndef CONFIG_LM_DISABLE_GPIOJ_IRQS
irq_attach(LM3S_IRQ_GPIOJ, lm_gpiojhandler);
up_enable_irq(LM3S_IRQ_GPIOJ);
irq_attach(LM_IRQ_GPIOJ, lm_gpiojhandler);
up_enable_irq(LM_IRQ_GPIOJ);
#endif
return OK;
@@ -386,9 +386,9 @@ void gpio_irqenable(int irq)
*/
flags = irqsave();
regval = getreg32(base + LM3S_GPIO_IM_OFFSET);
regval = getreg32(base + LM_GPIO_IM_OFFSET);
regval |= pin;
putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
putreg32(regval, base + LM_GPIO_IM_OFFSET);
irqrestore(flags);
}
}
@@ -425,10 +425,9 @@ void gpio_irqdisable(int irq)
*/
flags = irqsave();
regval = getreg32(base + LM3S_GPIO_IM_OFFSET);
regval = getreg32(base + LM_GPIO_IM_OFFSET);
regval &= ~pin;
putreg32(regval, base + LM3S_GPIO_IM_OFFSET);
putreg32(regval, base + LM_GPIO_IM_OFFSET);
irqrestore(flags);
}
}
arch/arm/src/lm/lm_irq.c
+26 -26
View File
@@ -63,7 +63,7 @@
* bringup
*/
#undef LM3S_IRQ_DEBUG
#undef LM_IRQ_DEBUG
/* Get a 32-bit version of the default priority */
@@ -95,7 +95,7 @@ volatile uint32_t *current_regs;
*
****************************************************************************/
#if defined(LM3S_IRQ_DEBUG) && defined (CONFIG_DEBUG)
#if defined(LM_IRQ_DEBUG) && defined (CONFIG_DEBUG)
static void lm_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
@@ -201,21 +201,21 @@ static int lm_reserved(int irq, FAR void *context)
static int lm_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
{
DEBUGASSERT(irq >= LM3S_IRQ_NMI && irq < NR_IRQS);
DEBUGASSERT(irq >= LM_IRQ_NMI && irq < NR_IRQS);
/* Check for external interrupt */
if (irq >= LM3S_IRQ_INTERRUPTS)
if (irq >= LM_IRQ_INTERRUPTS)
{
if (irq < LM3S_IRQ_INTERRUPTS + 32)
if (irq < LM_IRQ_INTERRUPTS + 32)
{
*regaddr = NVIC_IRQ0_31_ENABLE;
*bit = 1 << (irq - LM3S_IRQ_INTERRUPTS);
*bit = 1 << (irq - LM_IRQ_INTERRUPTS);
}
else if (irq < NR_IRQS)
{
*regaddr = NVIC_IRQ32_63_ENABLE;
*bit = 1 << (irq - LM3S_IRQ_INTERRUPTS - 32);
*bit = 1 << (irq - LM_IRQ_INTERRUPTS - 32);
}
else
{
@@ -228,19 +228,19 @@ static int lm_irqinfo(int irq, uint32_t *regaddr, uint32_t *bit)
else
{
*regaddr = NVIC_SYSHCON;
if (irq == LM3S_IRQ_MEMFAULT)
if (irq == LM_IRQ_MEMFAULT)
{
*bit = NVIC_SYSHCON_MEMFAULTENA;
}
else if (irq == LM3S_IRQ_BUSFAULT)
else if (irq == LM_IRQ_BUSFAULT)
{
*bit = NVIC_SYSHCON_BUSFAULTENA;
}
else if (irq == LM3S_IRQ_USAGEFAULT)
else if (irq == LM_IRQ_USAGEFAULT)
{
*bit = NVIC_SYSHCON_USGFAULTENA;
}
else if (irq == LM3S_IRQ_SYSTICK)
else if (irq == LM_IRQ_SYSTICK)
{
*regaddr = NVIC_SYSTICK_CTRL;
*bit = NVIC_SYSTICK_CTRL_ENABLE;
@@ -309,13 +309,13 @@ void up_irqinitialize(void)
* under certain conditions.
*/
irq_attach(LM3S_IRQ_SVCALL, up_svcall);
irq_attach(LM3S_IRQ_HARDFAULT, up_hardfault);
irq_attach(LM_IRQ_SVCALL, up_svcall);
irq_attach(LM_IRQ_HARDFAULT, up_hardfault);
/* Set the priority of the SVCall interrupt */
#ifdef CONFIG_ARCH_IRQPRIO
/* up_prioritize_irq(LM3S_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
/* up_prioritize_irq(LM_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
#endif
/* If the MPU is enabled, then attach and enable the Memory Management
@@ -323,22 +323,22 @@ void up_irqinitialize(void)
*/
#ifdef CONFIG_ARMV7M_MPU
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
up_enable_irq(LM3S_IRQ_MEMFAULT);
irq_attach(LM_IRQ_MEMFAULT, up_memfault);
up_enable_irq(LM_IRQ_MEMFAULT);
#endif
/* Attach all other processor exceptions (except reset and sys tick) */
#ifdef CONFIG_DEBUG
irq_attach(LM3S_IRQ_NMI, lm_nmi);
irq_attach(LM_IRQ_NMI, lm_nmi);
#ifndef CONFIG_ARMV7M_MPU
irq_attach(LM3S_IRQ_MEMFAULT, up_memfault);
irq_attach(LM_IRQ_MEMFAULT, up_memfault);
#endif
irq_attach(LM3S_IRQ_BUSFAULT, lm_busfault);
irq_attach(LM3S_IRQ_USAGEFAULT, lm_usagefault);
irq_attach(LM3S_IRQ_PENDSV, lm_pendsv);
irq_attach(LM3S_IRQ_DBGMONITOR, lm_dbgmonitor);
irq_attach(LM3S_IRQ_RESERVED, lm_reserved);
irq_attach(LM_IRQ_BUSFAULT, lm_busfault);
irq_attach(LM_IRQ_USAGEFAULT, lm_usagefault);
irq_attach(LM_IRQ_PENDSV, lm_pendsv);
irq_attach(LM_IRQ_DBGMONITOR, lm_dbgmonitor);
irq_attach(LM_IRQ_RESERVED, lm_reserved);
#endif
lm_dumpnvic("initial", NR_IRQS);
@@ -433,16 +433,16 @@ int up_prioritize_irq(int irq, int priority)
uint32_t regval;
int shift;
DEBUGASSERT(irq >= LM3S_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
DEBUGASSERT(irq >= LM_IRQ_MEMFAULT && irq < NR_IRQS && (unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
if (irq < LM3S_IRQ_INTERRUPTS)
if (irq < LM_IRQ_INTERRUPTS)
{
irq -= 4;
regaddr = NVIC_SYSH_PRIORITY(irq);
}
else
{
irq -= LM3S_IRQ_INTERRUPTS;
irq -= LM_IRQ_INTERRUPTS;
regaddr = NVIC_IRQ_PRIORITY(irq);
}
arch/arm/src/lm/lm_lowputc.c
+46 -46
View File
@@ -57,12 +57,12 @@
/* Configuration **********************************************************/
#if LM3S_NUARTS < 2
#if LM_NUARTS < 2
# undef CONFIG_LM_UART1
# undef CONFIG_UART1_SERIAL_CONSOLE
#endif
#if LM3S_NUARTS < 3
#if LM_NUARTS < 3
# undef CONFIG_LM_UART2
# undef CONFIG_UART2_SERIAL_CONSOLE
#endif
@@ -92,52 +92,52 @@
/* Select UART parameters for the selected console */
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
# define LM3S_CONSOLE_BASE LM3S_UART0_BASE
# define LM3S_CONSOLE_BAUD CONFIG_UART0_BAUD
# define LM3S_CONSOLE_BITS CONFIG_UART0_BITS
# define LM3S_CONSOLE_PARITY CONFIG_UART0_PARITY
# define LM3S_CONSOLE_2STOP CONFIG_UART0_2STOP
# define LM_CONSOLE_BASE LM_UART0_BASE
# define LM_CONSOLE_BAUD CONFIG_UART0_BAUD
# define LM_CONSOLE_BITS CONFIG_UART0_BITS
# define LM_CONSOLE_PARITY CONFIG_UART0_PARITY
# define LM_CONSOLE_2STOP CONFIG_UART0_2STOP
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
# define LM3S_CONSOLE_BASE LM3S_UART1_BASE
# define LM3S_CONSOLE_BAUD CONFIG_UART1_BAUD
# define LM3S_CONSOLE_BITS CONFIG_UART1_BITS
# define LM3S_CONSOLE_PARITY CONFIG_UART1_PARITY
# define LM3S_CONSOLE_2STOP CONFIG_UART1_2STOP
# define LM_CONSOLE_BASE LM_UART1_BASE
# define LM_CONSOLE_BAUD CONFIG_UART1_BAUD
# define LM_CONSOLE_BITS CONFIG_UART1_BITS
# define LM_CONSOLE_PARITY CONFIG_UART1_PARITY
# define LM_CONSOLE_2STOP CONFIG_UART1_2STOP
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
# define LM3S_CONSOLE_BASE LM3S_UART2_BASE
# define LM3S_CONSOLE_BAUD CONFIG_UART2_BAUD
# define LM3S_CONSOLE_BITS CONFIG_UART2_BITS
# define LM3S_CONSOLE_PARITY CONFIG_UART2_PARITY
# define LM3S_CONSOLE_2STOP CONFIG_UART2_2STOP
# define LM_CONSOLE_BASE LM_UART2_BASE
# define LM_CONSOLE_BAUD CONFIG_UART2_BAUD
# define LM_CONSOLE_BITS CONFIG_UART2_BITS
# define LM_CONSOLE_PARITY CONFIG_UART2_PARITY
# define LM_CONSOLE_2STOP CONFIG_UART2_2STOP
#else
# error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
#endif
/* Get LCRH settings */
#if LM3S_CONSOLE_BITS == 5
#if LM_CONSOLE_BITS == 5
# define UART_LCRH_NBITS UART_LCRH_WLEN_5BITS
#elif LM3S_CONSOLE_BITS == 6
#elif LM_CONSOLE_BITS == 6
# define UART_LCRH_NBITS UART_LCRH_WLEN_6BITS
#elif LM3S_CONSOLE_BITS == 7
#elif LM_CONSOLE_BITS == 7
# define UART_LCRH_NBITS UART_LCRH_WLEN_7BITS
#elif LM3S_CONSOLE_BITS == 8
#elif LM_CONSOLE_BITS == 8
# define UART_LCRH_NBITS UART_LCRH_WLEN_8BITS
#else
# error "Number of bits not supported"
#endif
#if LM3S_CONSOLE_PARITY == 0
#if LM_CONSOLE_PARITY == 0
# define UART_LCRH_PARITY (0)
#elif LM3S_CONSOLE_PARITY == 1
#elif LM_CONSOLE_PARITY == 1
# define UART_LCRH_PARITY UART_LCRH_PEN
#elif LM3S_CONSOLE_PARITY == 2
#elif LM_CONSOLE_PARITY == 2
# define UART_LCRH_PARITY (UART_LCRH_PEN|UART_LCRH_EPS)
#else
# error "Invalid parity selection"
#endif
#if LM3S_CONSOLE_2STOP != 0
#if LM_CONSOLE_2STOP != 0
# define UART_LCRH_NSTOP UART_LCRH_STP2
#else
# define UART_LCRH_NSTOP (0)
@@ -177,17 +177,17 @@
* divisor must be followed by a write to the UARTLCRH register for the changes to take effect. ..."
*/
#define LM3S_BRDDEN (16 * LM3S_CONSOLE_BAUD)
#define LM3S_BRDI (SYSCLK_FREQUENCY / LM3S_BRDDEN)
#define LM3S_REMAINDER (SYSCLK_FREQUENCY - LM3S_BRDDEN * LM3S_BRDI)
#define LM3S_DIVFRAC ((LM3S_REMAINDER * 64 + (LM3S_BRDDEN/2)) / LM3S_BRDDEN)
#define LM_BRDDEN (16 * LM_CONSOLE_BAUD)
#define LM_BRDI (SYSCLK_FREQUENCY / LM_BRDDEN)
#define LM_REMAINDER (SYSCLK_FREQUENCY - LM_BRDDEN * LM_BRDI)
#define LM_DIVFRAC ((LM_REMAINDER * 64 + (LM_BRDDEN/2)) / LM_BRDDEN)
/* For example: LM3S_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
/* For example: LM_CONSOLE_BAUD = 115,200, SYSCLK_FREQUENCY = 50,000,000:
*
* LM3S_BRDDEN = (16 * 115,200) = 1,843,200
* LM3S_BRDI = 50,000,000 / 1,843,200 = 27
* LM3S_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600
* LM3S_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8
* LM_BRDDEN = (16 * 115,200) = 1,843,200
* LM_BRDI = 50,000,000 / 1,843,200 = 27
* LM_REMAINDER = 50,000,000 - 1,843,200 * 27 = 233,600
* LM_DIVFRAC = (233,600 * 64 + 921,600) / 1,843,200 = 8
*
* Which should yied BAUD = 50,000,000 / (16 * (27 + 8/64)) = 115207.37
*/
@@ -229,11 +229,11 @@ void up_lowputc(char ch)
#ifdef HAVE_CONSOLE
/* Wait until the TX FIFO is not full */
while ((getreg32(LM3S_CONSOLE_BASE+LM3S_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
while ((getreg32(LM_CONSOLE_BASE+LM_UART_FR_OFFSET) & UART_FR_TXFF) != 0);
/* Then send the character */
putreg32((uint32_t)ch, LM3S_CONSOLE_BASE+LM3S_UART_DR_OFFSET);
putreg32((uint32_t)ch, LM_CONSOLE_BASE+LM_UART_DR_OFFSET);
#endif
}
@@ -260,18 +260,18 @@ void up_lowsetup(void)
*/
#ifdef CONFIG_LM_UART0
regval = getreg32(LM3S_SYSCON_RCGC1);
regval = getreg32(LM_SYSCON_RCGC1);
regval |= SYSCON_RCGC1_UART0;
putreg32(regval, LM3S_SYSCON_RCGC1);
putreg32(regval, LM_SYSCON_RCGC1);
lm_configgpio(GPIO_UART0_RX);
lm_configgpio(GPIO_UART0_TX);
#endif
#ifdef CONFIG_LM_UART1
regval = getreg32(LM3S_SYSCON_RCGC1);
regval = getreg32(LM_SYSCON_RCGC1);
regval |= SYSCON_RCGC1_UART1;
putreg32(regval, LM3S_SYSCON_RCGC1);
putreg32(regval, LM_SYSCON_RCGC1);
lm_configgpio(GPIO_UART1_RX);
lm_configgpio(GPIO_UART1_TX);
@@ -282,26 +282,26 @@ void up_lowsetup(void)
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
/* Disable the UART by clearing the UARTEN bit in the UART CTL register */
ctl = getreg32(LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
ctl = getreg32(LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
ctl &= ~UART_CTL_UARTEN;
putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
/* Write the integer portion of the BRD to the UART IBRD register */
putreg32(LM3S_BRDI, LM3S_CONSOLE_BASE+LM3S_UART_IBRD_OFFSET);
putreg32(LM_BRDI, LM_CONSOLE_BASE+LM_UART_IBRD_OFFSET);
/* Write the fractional portion of the BRD to the UART FBRD register */
putreg32(LM3S_DIVFRAC, LM3S_CONSOLE_BASE+LM3S_UART_FBRD_OFFSET);
putreg32(LM_DIVFRAC, LM_CONSOLE_BASE+LM_UART_FBRD_OFFSET);
/* Write the desired serial parameters to the UART LCRH register */
putreg32(UART_LCRH_VALUE, LM3S_CONSOLE_BASE+LM3S_UART_LCRH_OFFSET);
putreg32(UART_LCRH_VALUE, LM_CONSOLE_BASE+LM_UART_LCRH_OFFSET);
/* Enable the UART by setting the UARTEN bit in the UART CTL register */
ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
putreg32(ctl, LM3S_CONSOLE_BASE+LM3S_UART_CTL_OFFSET);
putreg32(ctl, LM_CONSOLE_BASE+LM_UART_CTL_OFFSET);
#endif
}
arch/arm/src/lm/lm_serial.c
+39 -39
View File
@@ -66,12 +66,12 @@
/* Some sanity checks *******************************************************/
#if LM3S_NUARTS < 2
#if LM_NUARTS < 2
# undef CONFIG_LM_UART1
# undef CONFIG_UART1_SERIAL_CONSOLE
#endif
#if LM3S_NUARTS < 3
#if LM_NUARTS < 3
# undef CONFIG_LM_UART2
# undef CONFIG_UART2_SERIAL_CONSOLE
#endif
@@ -274,14 +274,14 @@ static char g_uart2rxbuffer[CONFIG_UART2_RXBUFSIZE];
static char g_uart2txbuffer[CONFIG_UART2_TXBUFSIZE];
#endif
/* This describes the state of the LM3S uart0 port. */
/* This describes the state of the Stellaris uart0 port. */
#ifdef CONFIG_LM_UART0
static struct up_dev_s g_uart0priv =
{
.uartbase = LM3S_UART0_BASE,
.uartbase = LM_UART0_BASE,
.baud = CONFIG_UART0_BAUD,
.irq = LM3S_IRQ_UART0,
.irq = LM_IRQ_UART0,
.parity = CONFIG_UART0_PARITY,
.bits = CONFIG_UART0_BITS,
.stopbits2 = CONFIG_UART0_2STOP,
@@ -304,14 +304,14 @@ static uart_dev_t g_uart0port =
};
#endif
/* This describes the state of the LM3S uart1 port. */
/* This describes the state of the Stellaris uart1 port. */
#ifdef CONFIG_LM_UART1
static struct up_dev_s g_uart1priv =
{
.uartbase = LM3S_UART1_BASE,
.uartbase = LM_UART1_BASE,
.baud = CONFIG_UART1_BAUD,
.irq = LM3S_IRQ_UART1,
.irq = LM_IRQ_UART1,
.parity = CONFIG_UART1_PARITY,
.bits = CONFIG_UART1_BITS,
.stopbits2 = CONFIG_UART1_2STOP,
@@ -334,14 +334,14 @@ static uart_dev_t g_uart1port =
};
#endif
/* This describes the state of the LM3S uart1 port. */
/* This describes the state of the Stellaris uart1 port. */
#ifdef CONFIG_LM_UART2
static struct up_dev_s g_uart2priv =
{
.uartbase = LM3S_UART2_BASE,
.uartbase = LM_UART2_BASE,
.baud = CONFIG_UART2_BAUD,
.irq = LM3S_IRQ_UART2,
.irq = LM_IRQ_UART2,
.parity = CONFIG_UART2_PARITY,
.bits = CONFIG_UART2_BITS,
.stopbits2 = CONFIG_UART2_2STOP,
@@ -402,7 +402,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
/* Disable all interrupts */
priv->im = 0;
up_serialout(priv, LM3S_UART_IM_OFFSET, 0);
up_serialout(priv, LM_UART_IM_OFFSET, 0);
}
/****************************************************************************
@@ -412,7 +412,7 @@ static inline void up_disableuartint(struct up_dev_s *priv, uint32_t *im)
static inline void up_restoreuartint(struct up_dev_s *priv, uint32_t im)
{
priv->im = im;
up_serialout(priv, LM3S_UART_IM_OFFSET, im);
up_serialout(priv, LM_UART_IM_OFFSET, im);
}
/****************************************************************************
@@ -430,7 +430,7 @@ static inline void up_waittxnotfull(struct up_dev_s *priv)
{
/* Check Tx FIFO is full */
if ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
if ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFF) == 0)
{
/* The Tx FIFO is not full... return */
@@ -471,9 +471,9 @@ static int up_setup(struct uart_dev_s *dev)
/* Disable the UART by clearing the UARTEN bit in the UART CTL register */
ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
ctl = up_serialin(priv, LM_UART_CTL_OFFSET);
ctl &= ~UART_CTL_UARTEN;
up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
up_serialout(priv, LM_UART_CTL_OFFSET, ctl);
/* Calculate BAUD rate from the SYS clock:
*
@@ -517,8 +517,8 @@ static int up_setup(struct uart_dev_s *dev)
remainder = SYSCLK_FREQUENCY - den * brdi;
divfrac = ((remainder << 6) + (den >> 1)) / den;
up_serialout(priv, LM3S_UART_IBRD_OFFSET, brdi);
up_serialout(priv, LM3S_UART_FBRD_OFFSET, divfrac);
up_serialout(priv, LM_UART_IBRD_OFFSET, brdi);
up_serialout(priv, LM_UART_FBRD_OFFSET, divfrac);
/* Set up the LCRH register */
@@ -558,14 +558,14 @@ static int up_setup(struct uart_dev_s *dev)
lcrh |= UART_LCRH_STP2;
}
up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
up_serialout(priv, LM_UART_LCRH_OFFSET, lcrh);
#endif
/* Set the UART to interrupt whenever the TX FIFO is almost empty or when
* any character is received.
*/
up_serialout(priv, LM3S_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
up_serialout(priv, LM_UART_IFLS_OFFSET, UART_IFLS_TXIFLSEL_18th|UART_IFLS_RXIFLSEL_18th);
/* Flush the Rx and Tx FIFOs -- How do you do that?*/
@@ -575,27 +575,27 @@ static int up_setup(struct uart_dev_s *dev)
* yet because the interrupt is still disabled at the interrupt controller.
*/
up_serialout(priv, LM3S_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
up_serialout(priv, LM_UART_IM_OFFSET, UART_IM_RXIM|UART_IM_RTIM);
/* Enable the FIFOs */
#ifdef CONFIG_SUPPRESS_UART_CONFIG
lcrh = up_serialin(priv, LM3S_UART_LCRH_OFFSET);
lcrh = up_serialin(priv, LM_UART_LCRH_OFFSET);
#endif
lcrh |= UART_LCRH_FEN;
up_serialout(priv, LM3S_UART_LCRH_OFFSET, lcrh);
up_serialout(priv, LM_UART_LCRH_OFFSET, lcrh);
/* Enable Rx, Tx, and the UART */
#ifdef CONFIG_SUPPRESS_UART_CONFIG
ctl = up_serialin(priv, LM3S_UART_CTL_OFFSET);
ctl = up_serialin(priv, LM_UART_CTL_OFFSET);
#endif
ctl |= (UART_CTL_UARTEN|UART_CTL_TXE|UART_CTL_RXE);
up_serialout(priv, LM3S_UART_CTL_OFFSET, ctl);
up_serialout(priv, LM_UART_CTL_OFFSET, ctl);
/* Set up the cache IM value */
priv->im = up_serialin(priv, LM3S_UART_IM_OFFSET);
priv->im = up_serialin(priv, LM_UART_IM_OFFSET);
return OK;
}
@@ -716,8 +716,8 @@ static int up_interrupt(int irq, void *context)
/* Get the masked UART status and clear the pending interrupts. */
mis = up_serialin(priv, LM3S_UART_MIS_OFFSET);
up_serialout(priv, LM3S_UART_ICR_OFFSET, mis);
mis = up_serialin(priv, LM_UART_MIS_OFFSET);
up_serialout(priv, LM_UART_ICR_OFFSET, mis);
/* Handle incoming, receive bytes (with or without timeout) */
@@ -797,7 +797,7 @@ static int up_receive(struct uart_dev_s *dev, uint32_t *status)
/* Get the Rx byte + 4 bits of error information. Return those in status */
rxd = up_serialin(priv, LM3S_UART_DR_OFFSET);
rxd = up_serialin(priv, LM_UART_DR_OFFSET);
*status = rxd;
/* The lower 8bits of the Rx data is the actual recevied byte */
@@ -830,7 +830,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
{
priv->im &= ~(UART_IM_RXIM|UART_IM_RTIM);
}
up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
}
/****************************************************************************
@@ -844,7 +844,7 @@ static void up_rxint(struct uart_dev_s *dev, bool enable)
static bool up_rxavailable(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_RXFE) == 0);
}
/****************************************************************************
@@ -858,7 +858,7 @@ static bool up_rxavailable(struct uart_dev_s *dev)
static void up_send(struct uart_dev_s *dev, int ch)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)ch);
}
/****************************************************************************
@@ -881,11 +881,11 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
#ifndef CONFIG_SUPPRESS_SERIAL_INTS
priv->im |= UART_IM_TXIM;
up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
/* The serial driver wants an interrupt here, but will not get get
* one unless we "prime the pump." I believe that this is because
* behave like a level interrupt and the LM3S interrupts behave
* behave like a level interrupt and the Stellaris interrupts behave
* (at least by default) like edge interrupts.
*
* In any event, faking a TX interrupt here solves the problem;
@@ -901,7 +901,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
/* Disable the TX interrupt */
priv->im &= ~UART_IM_TXIM;
up_serialout(priv, LM3S_UART_IM_OFFSET, priv->im);
up_serialout(priv, LM_UART_IM_OFFSET, priv->im);
}
irqrestore(flags);
}
@@ -917,7 +917,7 @@ static void up_txint(struct uart_dev_s *dev, bool enable)
static bool up_txready(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFF) == 0);
}
/****************************************************************************
@@ -931,7 +931,7 @@ static bool up_txready(struct uart_dev_s *dev)
static bool up_txempty(struct uart_dev_s *dev)
{
struct up_dev_s *priv = (struct up_dev_s*)dev->priv;
return ((up_serialin(priv, LM3S_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
return ((up_serialin(priv, LM_UART_FR_OFFSET) & UART_FR_TXFE) != 0);
}
/****************************************************************************
@@ -1016,7 +1016,7 @@ int up_putc(int ch)
up_disableuartint(priv, &im);
up_waittxnotfull(priv);
up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)ch);
up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)ch);
/* Check for LF */
@@ -1025,7 +1025,7 @@ int up_putc(int ch)
/* Add CR */
up_waittxnotfull(priv);
up_serialout(priv, LM3S_UART_DR_OFFSET, (uint32_t)'\r');
up_serialout(priv, LM_UART_DR_OFFSET, (uint32_t)'\r');
}
up_waittxnotfull(priv);
arch/arm/src/lm/lm_ssi.c
+56 -56
View File
@@ -83,12 +83,12 @@
* such case, the following must be expanded).
*/
#if LM3S_NSSI == 0
#if LM_NSSI == 0
# undef CONFIG_SSI0_DISABLE
# define CONFIG_SSI0_DISABLE 1
# undef CONFIG_SSI1_DISABLE
# define CONFIG_SSI1_DISABLE 1
#elif LM3S_NSSI == 1
#elif LM_NSSI == 1
# undef CONFIG_SSI1_DISABLE
# define CONFIG_SSI1_DISABLE 1
#endif
@@ -102,15 +102,15 @@
# define NSSI_ENABLED 2 /* Two SSI interfaces: SSI0 & SSI1 */
# else
# define NSSI_ENABLED 1 /* One SSI interface: SSI0 */
# define SSI_BASE LM3S_SSI0_BASE
# define SSI_IRQ LM3S_IRQ_SSI0
# define SSI_BASE LM_SSI0_BASE
# define SSI_IRQ LM_IRQ_SSI0
# endif
#else
# ifndef CONFIG_SSI1_DISABLE
# define SSI1_NDX 0 /* Index to SSI1 in g_ssidev[] */
# define NSSI_ENABLED 1 /* One SSI interface: SSI1 */
# define SSI_BASE LM3S_SSI1_BASE
# define SSI_IRQ LM3S_IRQ_SSI1
# define SSI_BASE LM_SSI1_BASE
# define SSI_IRQ LM_IRQ_SSI1
# else
# define NSSI_ENABLED 0 /* No SSI interfaces */
# endif
@@ -124,19 +124,19 @@
/* The number of (16-bit) words that will fit in the Tx FIFO */
#define LM3S_TXFIFO_WORDS 8
#define LM_TXFIFO_WORDS 8
/* Configuration settings */
#ifndef CONFIG_SSI_TXLIMIT
# define CONFIG_SSI_TXLIMIT (LM3S_TXFIFO_WORDS/2)
# define CONFIG_SSI_TXLIMIT (LM_TXFIFO_WORDS/2)
#endif
#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM3S_TXFIFO_WORDS
#if CONFIG_SSI_TXLIMIT < 1 || CONFIG_SSI_TXLIMIT > LM_TXFIFO_WORDS
# error "Invalid range for CONFIG_SSI_TXLIMIT"
#endif
#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM3S_TXFIFO_WORDS/2)
#if CONFIG_SSI_TXLIMIT && CONFIG_SSI_TXLIMIT < (LM_TXFIFO_WORDS/2)
# error "CONFIG_SSI_TXLIMIT must be at least half the TX FIFO size"
#endif
@@ -304,10 +304,10 @@ static struct lm_ssidev_s g_ssidev[] =
{
.ops = &g_spiops,
#if NSSI_ENABLED > 1
.base = LM3S_SSI0_BASE,
.base = LM_SSI0_BASE,
#endif
#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
.irq = LM3S_IRQ_SSI0,
.irq = LM_IRQ_SSI0,
#endif
},
#endif
@@ -315,10 +315,10 @@ static struct lm_ssidev_s g_ssidev[] =
{
.ops = &g_spiops,
#if NSSI_ENABLED > 1
.base = LM3S_SSI1_BASE,
.base = LM_SSI1_BASE,
#endif
#if !defined(CONFIG_SSI_POLLWAIT) && NSSI_ENABLED > 1
.irq = LM3S_IRQ_SSI1,
.irq = LM_IRQ_SSI1,
#endif
},
#endif
@@ -404,9 +404,9 @@ static uint32_t ssi_disable(struct lm_ssidev_s *priv)
uint32_t retval;
uint32_t regval;
retval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
retval = ssi_getreg(priv, LM_SSI_CR1_OFFSET);
regval = (retval & ~SSI_CR1_SSE);
ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval);
ssivdbg("CR1: %08x\n", regval);
return retval;
}
@@ -430,10 +430,10 @@ static uint32_t ssi_disable(struct lm_ssidev_s *priv)
static void ssi_enable(struct lm_ssidev_s *priv, uint32_t enable)
{
uint32_t regval = ssi_getreg(priv, LM3S_SSI_CR1_OFFSET);
uint32_t regval = ssi_getreg(priv, LM_SSI_CR1_OFFSET);
regval &= ~SSI_CR1_SSE;
regval |= (enable & SSI_CR1_SSE);
ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, regval);
ssi_putreg(priv, LM_SSI_CR1_OFFSET, regval);
ssivdbg("CR1: %08x\n", regval);
}
@@ -484,14 +484,14 @@ static void ssi_semtake(sem_t *sem)
static void ssi_txnull(struct lm_ssidev_s *priv)
{
ssivdbg("TX: ->0xffff\n");
ssi_putreg(priv, LM3S_SSI_DR_OFFSET, 0xffff);
ssi_putreg(priv, LM_SSI_DR_OFFSET, 0xffff);
}
static void ssi_txuint16(struct lm_ssidev_s *priv)
{
uint16_t *ptr = (uint16_t*)priv->txbuffer;
ssivdbg("TX: %p->%04x\n", ptr, *ptr);
ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++));
priv->txbuffer = (void*)ptr;
}
@@ -499,7 +499,7 @@ static void ssi_txuint8(struct lm_ssidev_s *priv)
{
uint8_t *ptr = (uint8_t*)priv->txbuffer;
ssivdbg("TX: %p->%02x\n", ptr, *ptr);
ssi_putreg(priv, LM3S_SSI_DR_OFFSET, (uint32_t)(*ptr++));
ssi_putreg(priv, LM_SSI_DR_OFFSET, (uint32_t)(*ptr++));
priv->txbuffer = (void*)ptr;
}
@@ -523,17 +523,17 @@ static void ssi_txuint8(struct lm_ssidev_s *priv)
static void ssi_rxnull(struct lm_ssidev_s *priv)
{
#if defined(SSI_DEBUG) && defined(CONFIG_DEBUG_VERBOSE)
uint32_t regval = ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
uint32_t regval = ssi_getreg(priv, LM_SSI_DR_OFFSET);
ssivdbg("RX: discard %04x\n", regval);
#else
(void)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
(void)ssi_getreg(priv, LM_SSI_DR_OFFSET);
#endif
}
static void ssi_rxuint16(struct lm_ssidev_s *priv)
{
uint16_t *ptr = (uint16_t*)priv->rxbuffer;
*ptr = (uint16_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
*ptr = (uint16_t)ssi_getreg(priv, LM_SSI_DR_OFFSET);
ssivdbg("RX: %p<-%04x\n", ptr, *ptr);
priv->rxbuffer = (void*)(++ptr);
}
@@ -541,7 +541,7 @@ static void ssi_rxuint16(struct lm_ssidev_s *priv)
static void ssi_rxuint8(struct lm_ssidev_s *priv)
{
uint8_t *ptr = (uint8_t*)priv->rxbuffer;
*ptr = (uint8_t)ssi_getreg(priv, LM3S_SSI_DR_OFFSET);
*ptr = (uint8_t)ssi_getreg(priv, LM_SSI_DR_OFFSET);
ssivdbg("RX: %p<-%02x\n", ptr, *ptr);
priv->rxbuffer = (void*)(++ptr);
}
@@ -562,7 +562,7 @@ static void ssi_rxuint8(struct lm_ssidev_s *priv)
static inline bool ssi_txfifofull(struct lm_ssidev_s *priv)
{
return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_TNF) == 0;
}
/****************************************************************************
@@ -581,7 +581,7 @@ static inline bool ssi_txfifofull(struct lm_ssidev_s *priv)
static inline bool ssi_rxfifoempty(struct lm_ssidev_s *priv)
{
return (ssi_getreg(priv, LM3S_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
return (ssi_getreg(priv, LM_SSI_SR_OFFSET) & SSI_SR_RNE) == 0;
}
/****************************************************************************
@@ -657,7 +657,7 @@ static int ssi_performtx(struct lm_ssidev_s *priv)
/* Check again... Now have all of the Tx words been sent? */
#ifndef CONFIG_SSI_POLLWAIT
regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
regval = ssi_getreg(priv, LM_SSI_IM_OFFSET);
if (priv->ntxwords > 0)
{
/* No.. Enable the Tx FIFO interrupt. This interrupt occurs
@@ -678,7 +678,7 @@ static int ssi_performtx(struct lm_ssidev_s *priv)
regval &= ~(SSI_IM_TX|SSI_RIS_ROR);
}
ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
ssi_putreg(priv, LM_SSI_IM_OFFSET, regval);
#endif /* CONFIG_SSI_POLLWAIT */
}
return ntxd;
@@ -728,7 +728,7 @@ static inline void ssi_performrx(struct lm_ssidev_s *priv)
*/
#ifndef CONFIG_SSI_POLLWAIT
regval = ssi_getreg(priv, LM3S_SSI_IM_OFFSET);
regval = ssi_getreg(priv, LM_SSI_IM_OFFSET);
if (priv->ntxwords == 0 && priv->nrxwords < priv->nwords)
{
/* There are no more outgoing words to send, but there are
@@ -751,7 +751,7 @@ static inline void ssi_performrx(struct lm_ssidev_s *priv)
regval &= ~(SSI_IM_RX|SSI_IM_RT);
}
ssi_putreg(priv, LM3S_SSI_IM_OFFSET, regval);
ssi_putreg(priv, LM_SSI_IM_OFFSET, regval);
#endif /* CONFIG_SSI_POLLWAIT */
}
@@ -829,7 +829,7 @@ static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer,
flags = irqsave();
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
priv->ntxwords, priv->nrxwords, priv->nwords,
ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
ssi_getreg(priv, LM_SSI_SR_OFFSET));
ntxd = ssi_performtx(priv);
@@ -842,8 +842,8 @@ static int ssi_transfer(struct lm_ssidev_s *priv, const void *txbuffer,
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
priv->ntxwords, priv->nrxwords, priv->nwords,
ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
ssi_getreg(priv, LM_SSI_SR_OFFSET),
ssi_getreg(priv, LM_SSI_IM_OFFSET));
/* Wait for the transfer to complete. Since there is no handshake
* with SPI, the following should complete even if there are problems
@@ -908,11 +908,11 @@ static inline struct lm_ssidev_s *ssi_mapirq(int irq)
switch (irq)
{
#ifndef CONFIG_SSI0_DISABLE
case LM3S_IRQ_SSI0:
case LM_IRQ_SSI0:
return &g_ssidev[SSI0_NDX];
#endif
#ifndef CONFIG_SSI1_DISABLE
case LM3S_IRQ_SSI1:
case LM_IRQ_SSI1:
return &g_ssidev[SSI1_NDX];
#endif
default:
@@ -952,8 +952,8 @@ static int ssi_interrupt(int irq, void *context)
/* Clear pending interrupts */
regval = ssi_getreg(priv, LM3S_SSI_RIS_OFFSET);
ssi_putreg(priv, LM3S_SSI_ICR_OFFSET, regval);
regval = ssi_getreg(priv, LM_SSI_RIS_OFFSET);
ssi_putreg(priv, LM_SSI_ICR_OFFSET, regval);
/* Check for Rx FIFO overruns */
@@ -966,7 +966,7 @@ static int ssi_interrupt(int irq, void *context)
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x\n",
priv->ntxwords, priv->nrxwords, priv->nwords,
ssi_getreg(priv, LM3S_SSI_SR_OFFSET));
ssi_getreg(priv, LM_SSI_SR_OFFSET));
/* Handle outgoing Tx FIFO transfers */
@@ -978,8 +978,8 @@ static int ssi_interrupt(int irq, void *context)
ssivdbg("ntxwords: %d nrxwords: %d nwords: %d SR: %08x IM: %08x\n",
priv->ntxwords, priv->nrxwords, priv->nwords,
ssi_getreg(priv, LM3S_SSI_SR_OFFSET),
ssi_getreg(priv, LM3S_SSI_IM_OFFSET));
ssi_getreg(priv, LM_SSI_SR_OFFSET),
ssi_getreg(priv, LM_SSI_IM_OFFSET));
/* Check if the transfer is complete */
@@ -987,7 +987,7 @@ static int ssi_interrupt(int irq, void *context)
{
/* Yes.. Disable all SSI interrupt sources */
ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
ssi_putreg(priv, LM_SSI_IM_OFFSET, 0);
/* Wake up the waiting thread */
@@ -1135,14 +1135,14 @@ static uint32_t ssi_setfrequencyinternal(struct lm_ssidev_s *priv, uint32_t freq
/* Set CPDVSR */
DEBUGASSERT(cpsdvsr < 255);
ssi_putreg(priv, LM3S_SSI_CPSR_OFFSET, cpsdvsr);
ssi_putreg(priv, LM_SSI_CPSR_OFFSET, cpsdvsr);
/* Set SCR */
regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
regval &= ~SSI_CR0_SCR_MASK;
regval |= (scr << SSI_CR0_SCR_SHIFT);
ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
ssivdbg("CR0: %08x CPSR: %08x\n", regval, cpsdvsr);
/* Calcluate the actual frequency */
@@ -1235,10 +1235,10 @@ static void ssi_setmodeinternal(struct lm_ssidev_s *priv, enum spi_mode_e mode)
/* Then set the selected mode: Freescale SPI format, mode0-3 */
regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
regval &= ~(SSI_CR0_FRF_MASK|SSI_CR0_SPH|SSI_CR0_SPO);
regval |= modebits;
ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
ssivdbg("CR0: %08x\n", regval);
/* Save the mode so that subsequent re-configuratins will be faster */
@@ -1287,10 +1287,10 @@ static void ssi_setbitsinternal(struct lm_ssidev_s *priv, int nbits)
DEBUGASSERT(priv);
if (nbits != priv->nbits && nbits >=4 && nbits <= 16)
{
regval = ssi_getreg(priv, LM3S_SSI_CR0_OFFSET);
regval = ssi_getreg(priv, LM_SSI_CR0_OFFSET);
regval &= ~SSI_CR0_DSS_MASK;
regval |= ((nbits - 1) << SSI_CR0_DSS_SHIFT);
ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, regval);
ssi_putreg(priv, LM_SSI_CR0_OFFSET, regval);
ssivdbg("CR0: %08x\n", regval);
priv->nbits = nbits;
@@ -1464,9 +1464,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
/* Enable the SSI0 peripheral */
regval = getreg32(LM3S_SYSCON_RCGC1);
regval = getreg32(LM_SYSCON_RCGC1);
regval |= SYSCON_RCGC1_SSI0;
putreg32(regval, LM3S_SYSCON_RCGC1);
putreg32(regval, LM_SYSCON_RCGC1);
ssivdbg("RCGC1: %08x\n", regval);
/* Configure SSI0 GPIOs (NOTE that SS is not initialized here, the
@@ -1488,9 +1488,9 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
/* Enable the SSI1 peripheral */
regval = getreg32(LM3S_SYSCON_RCGC1);
regval = getreg32(LM_SYSCON_RCGC1);
regval |= SYSCON_RCGC1_SSI1;
putreg32(regval, LM3S_SYSCON_RCGC1);
putreg32(regval, LM_SYSCON_RCGC1);
ssivdbg("RCGC1: %08x\n", regval);
/* Configure SSI1 GPIOs */
@@ -1518,11 +1518,11 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
/* Set all CR1 fields to reset state. This will be master mode. */
ssi_putreg(priv, LM3S_SSI_CR1_OFFSET, 0);
ssi_putreg(priv, LM_SSI_CR1_OFFSET, 0);
/* Set all CR0 fields to the reset state. This will also select Freescale SPI mode. */
ssi_putreg(priv, LM3S_SSI_CR0_OFFSET, 0);
ssi_putreg(priv, LM_SSI_CR0_OFFSET, 0);
/* Set the initial mode to mode 0. The application may override
* this initial setting using the setmode() method.
@@ -1547,7 +1547,7 @@ FAR struct spi_dev_s *up_spiinitialize(int port)
* while there is an SSI transfer in progress.
*/
ssi_putreg(priv, LM3S_SSI_IM_OFFSET, 0);
ssi_putreg(priv, LM_SSI_IM_OFFSET, 0);
/* Attach the interrupt */
arch/arm/src/lm/lm_syscontrol.c
+15 -15
View File
@@ -159,7 +159,7 @@ static inline void lm_plllock(void)
{
/* Check if the PLL is locked on */
if ((getreg32(LM3S_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
if ((getreg32(LM_SYSCON_RIS) & SYSCON_RIS_PLLLRIS) != 0)
{
/* Yes.. return now */
@@ -191,17 +191,17 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
/* Get the current values of the RCC and RCC2 registers */
rcc = getreg32(LM3S_SYSCON_RCC);
rcc2 = getreg32(LM3S_SYSCON_RCC2);
rcc = getreg32(LM_SYSCON_RCC);
rcc2 = getreg32(LM_SYSCON_RCC2);
/* Temporarily bypass the PLL and system clock dividers */
rcc |= SYSCON_RCC_BYPASS;
rcc &= ~(SYSCON_RCC_USESYSDIV);
putreg32(rcc, LM3S_SYSCON_RCC);
putreg32(rcc, LM_SYSCON_RCC);
rcc2 |= SYSCON_RCC2_BYPASS2;
putreg32(rcc2, LM3S_SYSCON_RCC2);
putreg32(rcc2, LM_SYSCON_RCC2);
/* We are probably using the main oscillator. The main oscillator is disabled on
* reset and so probably must be enabled here. The internal oscillator is enabled
@@ -214,7 +214,7 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
/* Enable any selected osciallators (but don't disable any yet) */
rcc &= (~RCC_OSCMASK | (newrcc & RCC_OSCMASK));
putreg32(rcc, LM3S_SYSCON_RCC);
putreg32(rcc, LM_SYSCON_RCC);
/* Wait for the newly selected oscillator(s) to settle. This is tricky because
* the time that we wait can be significant and is determined by the previous
@@ -234,7 +234,7 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
/* Clear the PLL lock interrupt */
putreg32(SYSCON_MISC_PLLLMIS, LM3S_SYSCON_MISC);
putreg32(SYSCON_MISC_PLLLMIS, LM_SYSCON_MISC);
/* Write the new RCC/RCC2 values. Order depends upon whether RCC2 or RCC
* is currently enabled.
@@ -242,13 +242,13 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
if (rcc2 & SYSCON_RCC2_USERCC2)
{
putreg32(rcc2, LM3S_SYSCON_RCC2);
putreg32(rcc, LM3S_SYSCON_RCC);
putreg32(rcc2, LM_SYSCON_RCC2);
putreg32(rcc, LM_SYSCON_RCC);
}
else
{
putreg32(rcc, LM3S_SYSCON_RCC);
putreg32(rcc2, LM3S_SYSCON_RCC2);
putreg32(rcc, LM_SYSCON_RCC);
putreg32(rcc2, LM_SYSCON_RCC2);
}
/* Wait for the new crystal value and oscillator source to take effect */
@@ -279,8 +279,8 @@ void lm_clockconfig(uint32_t newrcc, uint32_t newrcc2)
/* Now we can set the final RCC/RCC2 values */
putreg32(rcc, LM3S_SYSCON_RCC);
putreg32(rcc2, LM3S_SYSCON_RCC2);
putreg32(rcc, LM_SYSCON_RCC);
putreg32(rcc2, LM_SYSCON_RCC2);
/* Wait for the system divider to be effective */
@@ -303,13 +303,13 @@ void up_clockconfig(void)
* around a PLL bug
*/
putreg32(SYSCON_LPDOPCTL_2750MV, LM3S_SYSCON_LDOPCTL);
putreg32(SYSCON_LPDOPCTL_2750MV, LM_SYSCON_LDOPCTL);
#endif
/* Set the clocking to run with the default settings provided in the board.h
* header file
*/
lm_clockconfig(LM3S_RCC_VALUE, LM3S_RCC2_VALUE);
lm_clockconfig(LM_RCC_VALUE, LM_RCC2_VALUE);
}
arch/arm/src/lm/lm_timerisr.c
+2 -2
View File
@@ -130,7 +130,7 @@ void up_timerinit(void)
/* Attach the timer interrupt vector */
(void)irq_attach(LM3S_IRQ_SYSTICK, (xcpt_t)up_timerisr);
(void)irq_attach(LM_IRQ_SYSTICK, (xcpt_t)up_timerisr);
/* Enable SysTick interrupts */
@@ -138,5 +138,5 @@ void up_timerinit(void)
/* And enable the timer interrupt */
up_enable_irq(LM3S_IRQ_SYSTICK);
up_enable_irq(LM_IRQ_SYSTICK);
}
arch/arm/src/lm/lm_vectors.S
+201 -201
View File
@@ -421,214 +421,214 @@ lm_vectors:
.type handlers, function
.thumb_func
handlers:
HANDLER lm_reserved, LM3S_IRQ_RESERVED /* Unexpected/reserved vector */
HANDLER lm_nmi, LM3S_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
HANDLER lm_hardfault, LM3S_IRQ_HARDFAULT /* Vector 3: Hard fault */
HANDLER lm_mpu, LM3S_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
HANDLER lm_busfault, LM3S_IRQ_BUSFAULT /* Vector 5: Bus fault */
HANDLER lm_usagefault, LM3S_IRQ_USAGEFAULT /* Vector 6: Usage fault */
HANDLER lm_svcall, LM3S_IRQ_SVCALL /* Vector 11: SVC call */
HANDLER lm_dbgmonitor, LM3S_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
HANDLER lm_pendsv, LM3S_IRQ_PENDSV /* Vector 14: Penable system service request */
HANDLER lm_systick, LM3S_IRQ_SYSTICK /* Vector 15: System tick */
HANDLER lm_reserved, LM_IRQ_RESERVED /* Unexpected/reserved vector */
HANDLER lm_nmi, LM_IRQ_NMI /* Vector 2: Non-Maskable Interrupt (NMI) */
HANDLER lm_hardfault, LM_IRQ_HARDFAULT /* Vector 3: Hard fault */
HANDLER lm_mpu, LM_IRQ_MEMFAULT /* Vector 4: Memory management (MPU) */
HANDLER lm_busfault, LM_IRQ_BUSFAULT /* Vector 5: Bus fault */
HANDLER lm_usagefault, LM_IRQ_USAGEFAULT /* Vector 6: Usage fault */
HANDLER lm_svcall, LM_IRQ_SVCALL /* Vector 11: SVC call */
HANDLER lm_dbgmonitor, LM_IRQ_DBGMONITOR /* Vector 12: Debug Monitor */
HANDLER lm_pendsv, LM_IRQ_PENDSV /* Vector 14: Penable system service request */
HANDLER lm_systick, LM_IRQ_SYSTICK /* Vector 15: System tick */
#if defined(CONFIG_ARCH_CHIP_LM3S6918)
HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */
HANDLER lm_ssi1, LM3S_IRQ_SSI1 /* Vector 50: SSI 1 */
HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */
HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm_gpioh, LM_IRQ_GPIOH /* Vector 48: GPIO Port H */
HANDLER lm_ssi1, LM_IRQ_SSI1 /* Vector 50: SSI 1 */
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
#elif defined(CONFIG_ARCH_CHIP_LM3S6432)
HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
#elif defined(CONFIG_ARCH_CHIP_LM3S6965)
HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */
HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */
HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */
HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */
HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm_uart2, LM_IRQ_UART1 /* Vector 49: UART 1 */
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
#elif defined(CONFIG_ARCH_CHIP_LM3S8962)
HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */
HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */
HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm_uart2, LM3S_IRQ_UART1 /* Vector 49: UART 1 */
HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */
HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
HANDLER lm_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */
HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm_hib, LM3S_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm_uart2, LM_IRQ_UART1 /* Vector 49: UART 1 */
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */
HANDLER lm_can0, LM_IRQ_CAN0 /* Vector 55: CAN 0 */
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm_hib, LM_IRQ_HIBERNATE /* Vector 59: Hibernation Module */
#elif defined(CONFIG_ARCH_CHIP_LM3S9B96)
HANDLER lm_gpioa, LM3S_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm_gpiob, LM3S_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm_gpioc, LM3S_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm_gpiod, LM3S_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm_gpioe, LM3S_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm_uart0, LM3S_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm_uart1, LM3S_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm_ssi0, LM3S_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm_i2c0, LM3S_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm_pwmfault, LM3S_IRQ_PWMFAULT /* Vector 25: PWM Fault */
HANDLER lm_pwm0, LM3S_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
HANDLER lm_pwm1, LM3S_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
HANDLER lm_pwm2, LM3S_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
HANDLER lm_qei0, LM3S_IRQ_QEI0 /* Vector 29: QEI 0 */
HANDLER lm_adc0, LM3S_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm_adc1, LM3S_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm_adc2, LM3S_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm_adc3, LM3S_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm_wdog, LM3S_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm_tmr0a, LM3S_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm_tmr0b, LM3S_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm_tmr1a, LM3S_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm_tmr1b, LM3S_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm_tmr2a, LM3S_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm_tmr2b, LM3S_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm_cmp0, LM3S_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm_cmp1, LM3S_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm_cmp2, LM3S_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */
HANDLER lm_syscon, LM3S_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm_flashcon, LM3S_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm_gpiof, LM3S_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm_gpiog, LM3S_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm_gpioh, LM3S_IRQ_GPIOH /* Vector 48: GPIO Port H */
HANDLER lm_uart2, LM3S_IRQ_UART2 /* Vector 49: UART 2 */
HANDLER lm_ssi1, LM3S_IRQ_SSI1 /* Vector 50: GPIO Port H */
HANDLER lm_tmr3a, LM3S_IRQ_TIMER3A /* Vector 51: Timer 3 A */
HANDLER lm_tmr3b, LM3S_IRQ_TIMER3B /* Vector 52: Timer 3 B */
HANDLER lm_i2c1, LM3S_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm_qei1, LM3S_IRQ_QEI1 /* Vector 54: QEI 1 */
HANDLER lm_can0, LM3S_IRQ_CAN0 /* Vector 55: CAN 0 */
HANDLER lm_can1, LM3S_IRQ_CAN1 /* Vector 56: CAN 1 */
HANDLER lm_eth, LM3S_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm_usb, LM3S_IRQ_USB /* Vector 60: USB */
HANDLER lm_pwm3, LM3S_IRQ_PWM3 /* Vector 61: PWM 3 */
HANDLER lm_udmasoft, LM3S_IRQ_UDMASOFT /* Vector 62: uDMA Software */
HANDLER lm_udmaerror, LM3S_IRQ_UDMAERROR /* Vector 63: uDMA Error */
HANDLER lm_adc1_0, LM3S_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */
HANDLER lm_adc1_1, LM3S_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */
HANDLER lm_adc1_2, LM3S_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */
HANDLER lm_adc1_3, LM3S_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */
HANDLER lm_i2s0, LM3S_IRQ_I2S0 /* Vector 68: I2S 0 */
HANDLER lm_epi, LM3S_IRQ_EPI /* Vector 69: EPI */
HANDLER lm_gpioj, LM3S_IRQ_GPIOJ /* Vector 70: GPIO Port J */
HANDLER lm_gpioa, LM_IRQ_GPIOA /* Vector 16: GPIO Port A */
HANDLER lm_gpiob, LM_IRQ_GPIOB /* Vector 17: GPIO Port B */
HANDLER lm_gpioc, LM_IRQ_GPIOC /* Vector 18: GPIO Port C */
HANDLER lm_gpiod, LM_IRQ_GPIOD /* Vector 19: GPIO Port D */
HANDLER lm_gpioe, LM_IRQ_GPIOE /* Vector 20: GPIO Port E */
HANDLER lm_uart0, LM_IRQ_UART0 /* Vector 21: UART 0 */
HANDLER lm_uart1, LM_IRQ_UART1 /* Vector 22: UART 1 */
HANDLER lm_ssi0, LM_IRQ_SSI0 /* Vector 23: SSI 0 */
HANDLER lm_i2c0, LM_IRQ_I2C0 /* Vector 24: I2C 0 */
HANDLER lm_pwmfault, LM_IRQ_PWMFAULT /* Vector 25: PWM Fault */
HANDLER lm_pwm0, LM_IRQ_PWM0 /* Vector 26: PWM Generator 0 */
HANDLER lm_pwm1, LM_IRQ_PWM1 /* Vector 27: PWM Generator 1 */
HANDLER lm_pwm2, LM_IRQ_PWM2 /* Vector 28: PWM Generator 2 */
HANDLER lm_qei0, LM_IRQ_QEI0 /* Vector 29: QEI 0 */
HANDLER lm_adc0, LM_IRQ_ADC0 /* Vector 30: ADC Sequence 0 */
HANDLER lm_adc1, LM_IRQ_ADC1 /* Vector 31: ADC Sequence 1 */
HANDLER lm_adc2, LM_IRQ_ADC2 /* Vector 32: ADC Sequence 2 */
HANDLER lm_adc3, LM_IRQ_ADC3 /* Vector 33: ADC Sequence 3 */
HANDLER lm_wdog, LM_IRQ_WDOG /* Vector 34: Watchdog Timer */
HANDLER lm_tmr0a, LM_IRQ_TIMER0A /* Vector 35: Timer 0 A */
HANDLER lm_tmr0b, LM_IRQ_TIMER0B /* Vector 36: Timer 0 B */
HANDLER lm_tmr1a, LM_IRQ_TIMER1A /* Vector 37: Timer 1 A */
HANDLER lm_tmr1b, LM_IRQ_TIMER1B /* Vector 38: Timer 1 B */
HANDLER lm_tmr2a, LM_IRQ_TIMER2A /* Vector 39: Timer 2 A */
HANDLER lm_tmr2b, LM_IRQ_TIMER2B /* Vector 40: Timer 3 B */
HANDLER lm_cmp0, LM_IRQ_COMPARE0 /* Vector 41: Analog Comparator 0 */
HANDLER lm_cmp1, LM_IRQ_COMPARE1 /* Vector 42: Analog Comparator 1 */
HANDLER lm_cmp2, LM_IRQ_COMPARE2 /* Vector 43: Analog Comparator 2 */
HANDLER lm_syscon, LM_IRQ_SYSCON /* Vector 44: System Control */
HANDLER lm_flashcon, LM_IRQ_FLASHCON /* Vector 45: FLASH Control */
HANDLER lm_gpiof, LM_IRQ_GPIOF /* Vector 46: GPIO Port F */
HANDLER lm_gpiog, LM_IRQ_GPIOG /* Vector 47: GPIO Port G */
HANDLER lm_gpioh, LM_IRQ_GPIOH /* Vector 48: GPIO Port H */
HANDLER lm_uart2, LM_IRQ_UART2 /* Vector 49: UART 2 */
HANDLER lm_ssi1, LM_IRQ_SSI1 /* Vector 50: GPIO Port H */
HANDLER lm_tmr3a, LM_IRQ_TIMER3A /* Vector 51: Timer 3 A */
HANDLER lm_tmr3b, LM_IRQ_TIMER3B /* Vector 52: Timer 3 B */
HANDLER lm_i2c1, LM_IRQ_I2C1 /* Vector 53: I2C 1 */
HANDLER lm_qei1, LM_IRQ_QEI1 /* Vector 54: QEI 1 */
HANDLER lm_can0, LM_IRQ_CAN0 /* Vector 55: CAN 0 */
HANDLER lm_can1, LM_IRQ_CAN1 /* Vector 56: CAN 1 */
HANDLER lm_eth, LM_IRQ_ETHCON /* Vector 58: Ethernet Controller */
HANDLER lm_usb, LM_IRQ_USB /* Vector 60: USB */
HANDLER lm_pwm3, LM_IRQ_PWM3 /* Vector 61: PWM 3 */
HANDLER lm_udmasoft, LM_IRQ_UDMASOFT /* Vector 62: uDMA Software */
HANDLER lm_udmaerror, LM_IRQ_UDMAERROR /* Vector 63: uDMA Error */
HANDLER lm_adc1_0, LM_IRQ_ADC1_0 /* Vector 64: ADC1 Sequence 0 */
HANDLER lm_adc1_1, LM_IRQ_ADC1_1 /* Vector 65: ADC1 Sequence 1 */
HANDLER lm_adc1_2, LM_IRQ_ADC1_2 /* Vector 66: ADC1 Sequence 2 */
HANDLER lm_adc1_3, LM_IRQ_ADC1_3 /* Vector 67: ADC1 Sequence 3 */
HANDLER lm_i2s0, LM_IRQ_I2S0 /* Vector 68: I2S 0 */
HANDLER lm_epi, LM_IRQ_EPI /* Vector 69: EPI */
HANDLER lm_gpioj, LM_IRQ_GPIOJ /* Vector 70: GPIO Port J */
#else
# error "Vectors not specified for this LM3S chip"
# error "Vectors not specified for this Stellaris chip"
#endif
/* Common IRQ handling logic. On entry here, the return stack is on either
configs/avr32dev1/README.txt
+4 -2
View File
@@ -431,14 +431,16 @@ AVR32DEV1 Configuration Options
Configurations
^^^^^^^^^^^^^^
Each Stellaris LM3S6965 Evaluation Kit configuration is maintained in a
sudirectory and can be selected as follow:
Each Atmel AVR32DEV configuration is maintained in a sudirectory and
can be selected as follow:
cd tools
./configure.sh avr32dev1/<subdir>
cd -
. ./setenv.sh
(Or configure.bat in a native Windows environment).
Where <subdir> is one of the following:
nsh:
configs/eagle100/README.txt
+2 -2
View File
@@ -344,7 +344,7 @@ Eagle100-specific Configuration Options
CONFIG_LM_DISABLE_GPIOH_IRQS=y
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
LM3S6818 specific device driver settings
LM3S6918 specific device driver settings
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
console and ttys0 (default is the UART0).
@@ -368,7 +368,7 @@ Eagle100-specific Configuration Options
Rx FIFO overrun errors. Default: half of the Tx FIFO size (4).
CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
to build the LM3S Ethernet driver
to build the Stellaris Ethernet driver
CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
CONFIG_LM_BOARDMAC - If the board-specific logic can provide
a MAC address (via lm_ethernetmac()), then this should be selected.
configs/eagle100/include/board.h
+6 -6
View File
@@ -63,7 +63,7 @@
* of (400 / 2) / 4 = 50MHz
*/
#define LM3S_SYSDIV 4
#define LM_SYSDIV 4
#define SYSCLK_FREQUENCY 50000000 /* 50MHz */
/* Other RCC settings:
@@ -74,7 +74,7 @@
* - No auto-clock gating reset
*/
#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
/* RCC2 settings -- RCC2 not used. Other RCC2 settings
*
@@ -83,7 +83,7 @@
* - Not using RCC2
*/
#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
/* LED definitions ******************************************************************/
@@ -115,9 +115,9 @@
* Name: lm_boardinitialize
*
* Description:
* All LM3S architectures must provide the following entry point. This entry point
* is called early in the intitialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
* All Stellaris architectures must provide the following entry point. This entry
* point is called early in the intitialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
configs/eagle100/src/eagle100_internal.h
+2 -2
View File
@@ -56,12 +56,12 @@
* expanded).
*/
#if LM3S_NSSI == 0
#if LM_NSSI == 0
# undef CONFIG_SSI0_DISABLE
# define CONFIG_SSI0_DISABLE 1
# undef CONFIG_SSI1_DISABLE
# define CONFIG_SSI1_DISABLE 1
#elif LM3S_NSSI == 1
#elif LM_NSSI == 1
# undef CONFIG_SSI1_DISABLE
# define CONFIG_SSI1_DISABLE 1
#endif
configs/eagle100/src/up_boot.c
+4 -3
View File
@@ -63,9 +63,10 @@
* Name: lm_boardinitialize
*
* Description:
* All LM3S architectures must provide the following entry point. This entry point
* is called early in the intitialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
* All Stellaris architectures must provide the following entry point. This entry
* point is called early in the intitialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
void lm_boardinitialize(void)
configs/eagle100/src/up_ethernet.c
+2 -2
View File
@@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
/* Get the current value of the user registers */
user0 = getreg32(LM3S_FLASH_USERREG0);
user1 = getreg32(LM3S_FLASH_USERREG1);
user0 = getreg32(LM_FLASH_USERREG0);
user1 = getreg32(LM_FLASH_USERREG1);
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
configs/ekk-lm3s9b96/README.txt
+4 -4
View File
@@ -324,7 +324,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
CONFIG_DRAM_START=0x20000000
CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
CONFIG_ARCH_IRQPRIO - The LM3S9B96 supports interrupt prioritization
CONFIG_ARCH_IRQPRIO=y
@@ -348,7 +348,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
the delay actually is 100 seconds.
There are configurations for disabling support for interrupts GPIO ports.
GPIOJ must be disabled because it does not exist on the LM3S6918.
GPIOJ must be disabled because it does not exist on the LM3S9B96.
Additional interrupt support can be disabled if desired to reduce memory
footprint.
@@ -362,7 +362,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
CONFIG_LM_DISABLE_GPIOH_IRQS=n
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
LM3S6818 specific device driver settings
LM3S9B96 specific device driver settings
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
console and ttys0 (default is the UART0).
@@ -386,7 +386,7 @@ Stellaris EKK-LM3S9B96 Evaluation Kit Configuration Options
Rx FIFO overrun errors. Default: half of the Tx FIFO size (4).
CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
to build the LM3S Ethernet driver
to build the Stellaris Ethernet driver
CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
CONFIG_LM_BOARDMAC - If the board-specific logic can provide
a MAC address (via lm_ethernetmac()), then this should be selected.
configs/ekk-lm3s9b96/include/board.h
+6 -6
View File
@@ -64,7 +64,7 @@
* of (400 / 2) / 4 = 50MHz
*/
#define LM3S_SYSDIV 4
#define LM_SYSDIV 4
#define SYSCLK_FREQUENCY 50000000 /* 50MHz */
/* Other RCC settings:
@@ -75,7 +75,7 @@
* - No auto-clock gating reset
*/
#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
/* RCC2 settings -- RCC2 not used. Other RCC2 settings
*
@@ -84,7 +84,7 @@
* - Not using RCC2
*/
#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
/* LED definitions ******************************************************************/
@@ -116,9 +116,9 @@
* Name: lm_boardinitialize
*
* Description:
* All LM3S architectures must provide the following entry point. This entry point
* is called early in the intitialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
* All Stellaris architectures must provide the following entry point. This entry
* point is called early in the intitialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
configs/ekk-lm3s9b96/src/ekklm3s9b96_internal.h
+2 -2
View File
@@ -57,12 +57,12 @@
* expanded).
*/
#if LM3S_NSSI == 0
#if LM_NSSI == 0
# undef CONFIG_SSI0_DISABLE
# define CONFIG_SSI0_DISABLE 1
# undef CONFIG_SSI1_DISABLE
# define CONFIG_SSI1_DISABLE 1
#elif LM3S_NSSI == 1
#elif LM_NSSI == 1
# undef CONFIG_SSI1_DISABLE
# define CONFIG_SSI1_DISABLE 1
#endif
configs/ekk-lm3s9b96/src/up_boot.c
+4 -3
View File
@@ -65,9 +65,10 @@
* Name: lm_boardinitialize
*
* Description:
* All LM3S architectures must provide the following entry point. This entry point
* is called early in the intitialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
* All Stellaris architectures must provide the following entry point. This entry
* point is called early in the intitialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
void lm_boardinitialize(void)
configs/ekk-lm3s9b96/src/up_ethernet.c
+2 -2
View File
@@ -81,8 +81,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
/* Get the current value of the user registers */
user0 = getreg32(LM3S_FLASH_USERREG0);
user1 = getreg32(LM3S_FLASH_USERREG1);
user0 = getreg32(LM_FLASH_USERREG0);
user1 = getreg32(LM_FLASH_USERREG1);
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
configs/lm3s6432-s2e/README.txt
+2 -2
View File
@@ -318,7 +318,7 @@ Stellaris MDL-S2E Reference Design Configuration Options
CONFIG_DRAM_START=0x20000000
CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
CONFIG_ARCH_IRQPRIO - The LM3S6432 supports interrupt prioritization
CONFIG_ARCH_IRQPRIO=y
@@ -389,7 +389,7 @@ Stellaris MDL-S2E Reference Design Configuration Options
Rx FIFO overrun errors. Default: half of the Tx FIFO size (4).
CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
to build the LM3S Ethernet driver
to build the Stellaris Ethernet driver
CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
CONFIG_LM_BOARDMAC - This should be set in order to use the
MAC address configured in the flash USER registers.
configs/lm3s6432-s2e/include/board.h
+6 -6
View File
@@ -63,7 +63,7 @@
* of (400 / 2) / 4 = 50MHz
*/
#define LM3S_SYSDIV 4
#define LM_SYSDIV 4
#define SYSCLK_FREQUENCY 50000000 /* 50MHz */
/* Other RCC settings:
@@ -74,7 +74,7 @@
* - No auto-clock gating reset
*/
#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
/* RCC2 settings -- RCC2 not used. Other RCC2 settings
*
@@ -83,7 +83,7 @@
* - Not using RCC2
*/
#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
/* LED definitions ******************************************************************/
@@ -117,9 +117,9 @@
* Name: lm_boardinitialize
*
* Description:
* All LM3S architectures must provide the following entry point. This entry point
* is called early in the intitialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
* All Stellaris architectures must provide the following entry point. This entry
* point is called early in the intitialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
configs/lm3s6432-s2e/src/lm3s6432s2e_internal.h
+1 -1
View File
@@ -55,7 +55,7 @@
* expanded).
*/
#if LM3S_NSSI == 0
#if LM_NSSI == 0
# undef CONFIG_SSI0_DISABLE
# define CONFIG_SSI0_DISABLE 1
#endif
configs/lm3s6432-s2e/src/up_boot.c
+4 -3
View File
@@ -70,9 +70,10 @@
* Name: lm_boardinitialize
*
* Description:
* All LM3S architectures must provide the following entry point. This entry point
* is called early in the intitialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
* All Stellaris architectures must provide the following entry point. This entry
* point is called early in the intitialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
void lm_boardinitialize(void)
configs/lm3s6432-s2e/src/up_ethernet.c
+2 -2
View File
@@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
/* Get the current value of the user registers */
user0 = getreg32(LM3S_FLASH_USERREG0);
user1 = getreg32(LM3S_FLASH_USERREG1);
user0 = getreg32(LM_FLASH_USERREG0);
user1 = getreg32(LM_FLASH_USERREG1);
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);
configs/lm3s6965-ek/README.txt
+4 -4
View File
@@ -387,7 +387,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
CONFIG_DRAM_START=0x20000000
CONFIG_ARCH_IRQPRIO - The LM3S6918 supports interrupt prioritization
CONFIG_ARCH_IRQPRIO - The LM3S6965 supports interrupt prioritization
CONFIG_ARCH_IRQPRIO=y
@@ -411,7 +411,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
the delay actually is 100 seconds.
There are configurations for disabling support for interrupts GPIO ports.
GPIOJ must be disabled because it does not exist on the LM3S6918.
GPIOJ must be disabled because it does not exist on the LM3S6965.
Additional interrupt support can be disabled if desired to reduce memory
footprint.
@@ -425,7 +425,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
CONFIG_LM_DISABLE_GPIOH_IRQS=n
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
LM3S6818 specific device driver settings
LM3S6965 specific device driver settings
CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
console and ttys0 (default is the UART0).
@@ -449,7 +449,7 @@ Stellaris LM3S6965 Evaluation Kit Configuration Options
Rx FIFO overrun errors. Default: half of the Tx FIFO size (4).
CONFIG_LM_ETHERNET - This must be set (along with CONFIG_NET)
to build the LM3S Ethernet driver
to build the Stellaris Ethernet driver
CONFIG_LM_ETHLEDS - Enable to use Ethernet LEDs on the board.
CONFIG_LM_BOARDMAC - If the board-specific logic can provide
a MAC address (via lm_ethernetmac()), then this should be selected.
configs/lm3s6965-ek/include/board.h
+6 -6
View File
@@ -63,7 +63,7 @@
* of (400 / 2) / 4 = 50MHz
*/
#define LM3S_SYSDIV 4
#define LM_SYSDIV 4
#define SYSCLK_FREQUENCY 50000000 /* 50MHz */
/* Other RCC settings:
@@ -74,7 +74,7 @@
* - No auto-clock gating reset
*/
#define LM3S_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM3S_SYSDIV))
#define LM_RCC_VALUE (SYSCON_RCC_OSCSRC | SYSCON_RCC_XTAL | SYSCON_RCC_USESYSDIV | SYSCON_RCC_SYSDIV(LM_SYSDIV))
/* RCC2 settings -- RCC2 not used. Other RCC2 settings
*
@@ -83,7 +83,7 @@
* - Not using RCC2
*/
#define LM3S_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM3S_SYSDIV))
#define LM_RCC2_VALUE (SYSCON_RCC2_OSCSRC | SYSCON_RCC2_SYSDIV(LM_SYSDIV))
/* LED definitions ******************************************************************/
@@ -115,9 +115,9 @@
* Name: lm_boardinitialize
*
* Description:
* All LM3S architectures must provide the following entry point. This entry point
* is called early in the intitialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
* All Stellaris architectures must provide the following entry point. This entry
* point is called early in the intitialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
configs/lm3s6965-ek/nsh/defconfig
+4 -4
View File
@@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
#
# LM3S Configuration Options
# Stellaris Configuration Options
#
# CONFIG_ARCH_CHIP_LM3S6918 is not set
# CONFIG_ARCH_CHIP_LM3S9B96 is not set
@@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y
CONFIG_LM_DFU=y
#
# Select LM3S Peripheral Support
# Select Stellaris Peripheral Support
#
CONFIG_LM_UART0=y
# CONFIG_LM_UART1 is not set
@@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
#
# LM3S Ethernet Configuration
# Stellaris Ethernet Configuration
#
# CONFIG_LM_ETHLEDS is not set
# CONFIG_LM_BOARDMAC is not set
@@ -141,7 +141,7 @@ CONFIG_LM_DISABLE_GPIOJ_IRQS=y
# CONFIG_M3S_DUMPPACKET is not set
#
# LM3S SSI Configuration
# Stellaris SSI Configuration
#
CONFIG_SSI_POLLWAIT=y
CONFIG_SSI_TXLIMIT=4
configs/lm3s6965-ek/nx/defconfig
+3 -3
View File
@@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
#
# LM3S Configuration Options
# Stellaris Configuration Options
#
# CONFIG_ARCH_CHIP_LM3S6918 is not set
# CONFIG_ARCH_CHIP_LM3S9B96 is not set
@@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y
CONFIG_LM_DFU=y
#
# Select LM3S Peripheral Support
# Select Stellaris Peripheral Support
#
CONFIG_LM_UART0=y
# CONFIG_LM_UART1 is not set
@@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
#
# LM3S SSI Configuration
# Stellaris SSI Configuration
#
CONFIG_SSI_POLLWAIT=y
CONFIG_SSI_TXLIMIT=4
configs/lm3s6965-ek/ostest/defconfig
+3 -3
View File
@@ -93,7 +93,7 @@ CONFIG_ARMV7M_TOOLCHAIN_BUILDROOT=y
CONFIG_ARMV7M_OABI_TOOLCHAIN=y
#
# LM3S Configuration Options
# Stellaris Configuration Options
#
# CONFIG_ARCH_CHIP_LM3S6918 is not set
# CONFIG_ARCH_CHIP_LM3S9B96 is not set
@@ -104,7 +104,7 @@ CONFIG_ARCH_CHIP_LM3S6965=y
CONFIG_LM_DFU=y
#
# Select LM3S Peripheral Support
# Select Stellaris Peripheral Support
#
CONFIG_LM_UART0=y
# CONFIG_LM_UART1 is not set
@@ -127,7 +127,7 @@ CONFIG_LM_DISABLE_GPIOH_IRQS=y
CONFIG_LM_DISABLE_GPIOJ_IRQS=y
#
# LM3S SSI Configuration
# Stellaris SSI Configuration
#
CONFIG_SSI_POLLWAIT=y
CONFIG_SSI_TXLIMIT=4
configs/lm3s6965-ek/src/lm3s6965ek_internal.h
+2 -2
View File
@@ -56,12 +56,12 @@
* expanded).
*/
#if LM3S_NSSI == 0
#if LM_NSSI == 0
# undef CONFIG_SSI0_DISABLE
# define CONFIG_SSI0_DISABLE 1
# undef CONFIG_SSI1_DISABLE
# define CONFIG_SSI1_DISABLE 1
#elif LM3S_NSSI == 1
#elif LM_NSSI == 1
# undef CONFIG_SSI1_DISABLE
# define CONFIG_SSI1_DISABLE 1
#endif
configs/lm3s6965-ek/src/up_boot.c
+4 -3
View File
@@ -64,9 +64,10 @@
* Name: lm_boardinitialize
*
* Description:
* All LM3S architectures must provide the following entry point. This entry point
* is called early in the intitialization -- after all memory has been configured
* and mapped but before any devices have been initialized.
* All Stellaris architectures must provide the following entry point. This entry
* point is called early in the intitialization -- after all memory has been
* configured and mapped but before any devices have been initialized.
*
************************************************************************************/
void lm_boardinitialize(void)
configs/lm3s6965-ek/src/up_ethernet.c
+2 -2
View File
@@ -80,8 +80,8 @@ void lm_ethernetmac(struct ether_addr *ethaddr)
/* Get the current value of the user registers */
user0 = getreg32(LM3S_FLASH_USERREG0);
user1 = getreg32(LM3S_FLASH_USERREG1);
user0 = getreg32(LM_FLASH_USERREG0);
user1 = getreg32(LM_FLASH_USERREG1);
nlldbg("user: %06x:%06x\n", user1 & 0x00ffffff, user0 & 0x00ffffff);
DEBUGASSERT(user0 != 0xffffffff && user1 != 0xffffffff);

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