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i.MXRT USDHC: This change completes SDIO support for IMXRT, and also adds support for WiFi using the AP6212A module based on Simon Piriou's rather excellent work. The patch should also address DavidS's concern about width setting for USDHC1 & 2.

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Testing of the WiFi is minimal so far but functionality is proven. I'm specifically not happy that the driver doesn't recover elegantly from a DMA data checksum failure, but that is an issue that can be dealt with in due course ... I'm trying to get the rest of the interfaces fleshed out and the hardware proven so it can go for pre-production build. I _think_ there's only Bluetooth and USB-device left to implement now.
This commit is contained in:
Dave Marples
2019-07-28 16:20:33 -06:00
committed by Gregory Nutt
parent 43e832327c
commit 970295d0fe
5 changed files with 418 additions and 186 deletions
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32
arch/arm/src/imxrt/Kconfig
View File

@@ -700,11 +700,33 @@ config IMXRT_USDHC_DMA
For most usages, SD accesses will cause data overruns if used without
DMA.
config IMXRT_USDHC_WIDTH_D1_ONLY
bool "Use D1 only"
default n
---help---
Select 1-bit transfer mode. Default: 4-bit transfer mode.
choice
prompt "Bus width for USDHC1"
default IMXRT_USDHC1_WIDTH_D1_ONLY
depends on IMXRT_USDHC1
config IMXRT_USDHC1_WIDTH_D1_ONLY
bool "One bit"
config IMXRT_USDHC1_WIDTH_D1_D4
bool "Four bit"
endchoice
choice
depends on IMXRT_USDHC2
prompt "Bus width for USDHC2"
default IMXRT_USDHC2_WIDTH_D1_D4
config IMXRT_USDHC2_WIDTH_D1_ONLY
bool "One bit"
config IMXRT_USDHC2_WIDTH_D1_D4
bool "Four bit"
config IMXRT_USDHC2_WIDTH_D1_D8
bool "Eight bit"
endchoice
endmenu # USDHC Configuration
menu "eDMA Configuration"

136
arch/arm/src/imxrt/imxrt_usdhc.c
View File

@@ -1188,7 +1188,7 @@ static int imxrt_interrupt(int irq, void *context, FAR void *arg)
}
#endif
/* Handle transfer complete events */
/* ... transfer complete events */
if ((pending & USDHC_INT_TC) != 0)
{
@@ -1197,7 +1197,7 @@ static int imxrt_interrupt(int irq, void *context, FAR void *arg)
imxrt_endtransfer(priv, SDIOWAIT_TRANSFERDONE);
}
/* Handle data block send/receive CRC failure */
/* ... data block send/receive CRC failure */
else if ((pending & USDHC_INT_DCE) != 0)
{
@@ -1208,7 +1208,7 @@ static int imxrt_interrupt(int irq, void *context, FAR void *arg)
imxrt_endtransfer(priv, SDIOWAIT_TRANSFERDONE | SDIOWAIT_ERROR);
}
/* Handle data timeout error */
/* ... data timeout error */
else if ((pending & USDHC_INT_DTOE) != 0)
{
@@ -1219,6 +1219,23 @@ static int imxrt_interrupt(int irq, void *context, FAR void *arg)
}
}
/* Handle Card interrupt events *****************************************/
pending = enabled & priv->cintints;
if ((pending & USDHC_INT_CINT) != 0)
{
if (priv->do_sdio_card)
{
(priv->do_sdio_card)(priv->do_sdio_arg);
}
/* We don't want any more ints now, so switch it off */
priv->cintints = 0;
regval &= ~USDHC_INT_CINT;
putreg32(regval, priv->addr + IMXRT_USDHC_IRQSIGEN_OFFSET);
}
/* Handle wait events *****************************************************/
pending = enabled & priv->waitints;
@@ -1228,7 +1245,7 @@ static int imxrt_interrupt(int irq, void *context, FAR void *arg)
if ((pending & USDHC_RESPDONE_INTS) != 0)
{
/* Yes.. Is their a thread waiting for response done? */
/* Yes.. Is there a thread waiting for response done? */
if ((priv->waitevents &
(SDIOWAIT_CMDDONE | SDIOWAIT_RESPONSEDONE)) != 0)
@@ -1375,14 +1392,39 @@ static void imxrt_reset(FAR struct sdio_dev_s *dev)
static sdio_capset_t imxrt_capabilities(FAR struct sdio_dev_s *dev)
{
sdio_capset_t caps = 0;
struct imxrt_dev_s *priv = (struct imxrt_dev_s *)dev;
#ifdef CONFIG_IMXRT_USDHC_WIDTH_D1_ONLY
caps |= SDIO_CAPS_1BIT_ONLY;
switch (priv->addr)
{
case IMXRT_USDHC1_BASE:
#ifdef CONFIG_IMXRT_USDHC1_WIDTH_D1_ONLY
caps |= SDIO_CAPS_1BIT_ONLY;
#endif
#ifdef CONFIG_IMXRT_USDHC1_WIDTH_D1_D4
caps |= SDIO_CAPS_4BIT;
#endif
break;
case IMXRT_USDHC2_BASE:
#ifdef CONFIG_IMXRT_USDHC2_WIDTH_D1_ONLY
caps |= SDIO_CAPS_1BIT_ONLY;
#endif
#ifdef CONFIG_IMXRT_USDHC2_WIDTH_D1_D4
caps |= SDIO_CAPS_4BIT;
#endif
#ifdef CONFIG_IMXRT_USDHC2_WIDTH_D1_D8
caps |= SDIO_CAPS_8BIT;
#endif
break;
default:
break;
}
#ifdef CONFIG_IMXRT_USDHC_DMA
caps |= SDIO_CAPS_DMASUPPORTED;
caps |= SDIO_CAPS_DMASUPPORTED;
#endif
caps |= SDIO_CAPS_DMABEFOREWRITE;
caps |= SDIO_CAPS_DMABEFOREWRITE;
return caps;
}
@@ -1800,7 +1842,7 @@ static int imxrt_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
regval = cmdidx << USDHC_XFERTYP_CMDINX_SHIFT;
mcrregval = USDHC_MC_DEFAULTVAL;
if (cmdidx == SDIO_ACMDIDX53)
if (cmdidx == SD_ACMDIDX53)
{
/* Dynamically set parameters for ACMD53 because it can accomodate
* different transmission characteristics (single and multi-block,
@@ -1824,7 +1866,7 @@ static int imxrt_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
{
/* In block mode */
cmd |= MMCSD_MULTIBLOCK;
cmd |= SDIO_MULTIBLOCK;
}
}
@@ -1845,7 +1887,8 @@ static int imxrt_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
{
/* Yes.. streaming read data transfer */
regval |= USDHC_XFERTYP_DPSEL; mcrregval |= USDHC_MC_DTDSEL;
regval |= USDHC_XFERTYP_DPSEL;
mcrregval |= USDHC_MC_DTDSEL;
}
break;
@@ -1877,21 +1920,24 @@ static int imxrt_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
/* Is it a multi-block transfer? */
if ((cmd & MMCSD_MULTIBLOCK) != 0)
if ((cmd & (MMCSD_MULTIBLOCK | SDIO_MULTIBLOCK)) != 0)
{
mcrregval |= USDHC_MC_MSBSEL;
/* Yes.. should the transfer be stopped with ACMD12? */
if ((cmd & MMCSD_STOPXFR) != 0)
if (((cmd & MMCSD_MULTIBLOCK) != 0) &&
((cmd & MMCSD_STOPXFR) != 0))
{
/* Yes.. Indefinite block transfer */
/* Yes.. Indefinite block transfer (not SDIO) */
mcrregval |= USDHC_MC_MSBSEL | USDHC_MC_AC12EN;
mcrregval |= USDHC_MC_AC12EN;
}
else
{
/* No.. Fixed block transfer */
mcrregval |= USDHC_MC_MSBSEL | USDHC_MC_BCEN;
mcrregval |= USDHC_MC_BCEN;
}
}
@@ -1952,7 +1998,12 @@ static int imxrt_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
mcrregval |= USDHC_MC_DMAEN;
#endif
/* Other bits? What about CMDTYP? */
/* Check for abort. TODO: Check Suspend/Resume bits too in XFR_TYP::CMDTYP */
if (cmd & MMCSD_STOPXFR)
{
regval |= USDHC_XFERTYP_CMDTYP_ABORT;
}
mcinfo("cmd: %08x arg: %08x regval: %08x mcrval: %08x\n", cmd, arg,
regval, mcrregval);
@@ -1990,7 +2041,9 @@ static int imxrt_sendcmd(FAR struct sdio_dev_s *dev, uint32_t cmd,
putreg32(USDHC_RESPDONE_INTS, priv->addr + IMXRT_USDHC_IRQSTAT_OFFSET);
putreg32(mcrregval, priv->addr + IMXRT_USDHC_MIX_OFFSET);
putreg32(regval, priv->addr + IMXRT_USDHC_XFERTYP_OFFSET); return OK;
putreg32(regval, priv->addr + IMXRT_USDHC_XFERTYP_OFFSET);
return OK;
}
/****************************************************************************
@@ -2204,17 +2257,17 @@ static int imxrt_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
clock_t start;
clock_t elapsed;
uint32_t errors;
uint32_t enerrors;
FAR struct imxrt_dev_s *priv = (FAR struct imxrt_dev_s *)dev;
int ret = OK;
switch (cmd & MMCSD_RESPONSE_MASK)
{
case MMCSD_NO_RESPONSE:
{
timeout = USDHC_CMDTIMEOUT;
errors = 0;
return OK;
}
timeout = USDHC_CMDTIMEOUT;
errors = 0;
break;
case MMCSD_R1_RESPONSE:
case MMCSD_R1B_RESPONSE:
@@ -2256,16 +2309,19 @@ static int imxrt_waitresponse(FAR struct sdio_dev_s *dev, uint32_t cmd)
{
mcerr("ERROR: Timeout cmd: %08x IRQSTAT: %08x\n", cmd,
getreg32(priv->addr + IMXRT_USDHC_IRQSTAT_OFFSET));
return -ETIMEDOUT;
}
ret = -ETIMEDOUT;
break;
}
}
/* Check for hardware detected errors */
if ((getreg32(priv->addr + IMXRT_USDHC_IRQSTAT_OFFSET) & errors) != 0)
enerrors = getreg32(priv->addr + IMXRT_USDHC_IRQSTAT_OFFSET) & errors;
if (enerrors != 0)
{
mcerr("ERROR: cmd: %08x errors: %08x IRQSTAT: %08x\n", cmd, errors,
getreg32(priv->addr + IMXRT_USDHC_IRQSTAT_OFFSET)); ret = -EIO;
mcerr("ERROR: cmd: %08x errors: %08x, fired %08x IRQSTAT: %08x\n", cmd, \
errors, enerrors, getreg32(priv->addr + IMXRT_USDHC_IRQSTAT_OFFSET));
ret = -EIO;
}
/* Clear the response wait status bits */
@@ -2994,19 +3050,14 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
*/
#ifndef CONFIG_SDIO_MUXBUS
/* Data width 1, 4 */
(void)imxrt_config_gpio(PIN_USDHC1_D0);
/* Data width 4 */
#ifndef CONFIG_IMXRT_USDHC_WIDTH_D1_ONLY
#if defined(CONFIG_IMXRT_USDHC1_WIDTH_D1_D4)
(void)imxrt_config_gpio(PIN_USDHC1_D1);
(void)imxrt_config_gpio(PIN_USDHC1_D2);
(void)imxrt_config_gpio(PIN_USDHC1_D3);
#endif
/* Clocking and CMD pins (all data widths) */
(void)imxrt_config_gpio(PIN_USDHC1_D0);
(void)imxrt_config_gpio(PIN_USDHC1_DCLK);
(void)imxrt_config_gpio(PIN_USDHC1_CMD);
#endif
@@ -3017,14 +3068,25 @@ FAR struct sdio_dev_s *imxrt_usdhc_initialize(int slotno)
imxrt_clockall_usdhc1();
break;
#if defined(CONFIG_IMXRT_USDHC2)
case IMXRT_USDHC2_BASE:
(void)imxrt_config_gpio(PIN_USDHC2_D0);
(void)imxrt_config_gpio(PIN_USDHC2_DCLK);
(void)imxrt_config_gpio(PIN_USDHC2_CMD);
#if defined(CONFIG_IMXRT_USDHC2_WIDTH_D1_D4) || defined(CONFIG_IMXRT_USDHC2_WIDTH_D1_D8)
(void)imxrt_config_gpio(PIN_USDHC2_D1);
(void)imxrt_config_gpio(PIN_USDHC2_D2);
(void)imxrt_config_gpio(PIN_USDHC2_D3);
(void)imxrt_config_gpio(PIN_USDHC2_DCLK);
(void)imxrt_config_gpio(PIN_USDHC2_CMD);
#endif
#if defined(CONFIG_IMXRT_USDHC2_WIDTH_D1_D8)
(void)imxrt_config_gpio(PIN_USDHC2_D4);
(void)imxrt_config_gpio(PIN_USDHC2_D5);
(void)imxrt_config_gpio(PIN_USDHC2_D6);
(void)imxrt_config_gpio(PIN_USDHC2_D7);
#endif
imxrt_clockall_usdhc2();
break;
#endif

91
drivers/wireless/ieee80211/bcmf_core.c
View File

@@ -43,6 +43,7 @@
#include <debug.h>
#include <errno.h>
#include <fcntl.h>
#include <string.h>
#include <nuttx/arch.h>
#include <nuttx/kmalloc.h>
@@ -86,10 +87,18 @@
#define BCMF_UPLOAD_TRANSFER_SIZE (64 * 256)
/* Define this to validate uploaded materials */
/* #define DBG_VALIDATE_UPLOAD */
/****************************************************************************
* Private Types
****************************************************************************/
#ifdef DBG_VALIDATE_UPLOAD
static uint8_t compare_buffer[BCMF_UPLOAD_TRANSFER_SIZE];
#endif
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
@@ -122,7 +131,7 @@ int bcmf_core_set_backplane_window(FAR struct bcmf_sdio_dev_s *sbus,
{
/* Update current backplane base address */
ret = bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_SBADDRLOW+i-1,
ret = bcmf_write_reg(sbus, 1, SBSDIO_FUNC1_SBADDRLOW + i - 1,
addr_part);
if (ret != OK)
@@ -143,6 +152,12 @@ int bcmf_upload_binary(FAR struct bcmf_sdio_dev_s *sbus, uint32_t address,
{
unsigned int size;
#ifdef DBG_VALIDATE_UPLOAD
uint32_t validate_address = address;
uint8_t *validate_buffer = buf;
unsigned int validate_len = len;
#endif
while (len > 0)
{
/* Set the backplane window to include the start address */
@@ -150,6 +165,7 @@ int bcmf_upload_binary(FAR struct bcmf_sdio_dev_s *sbus, uint32_t address,
int ret = bcmf_core_set_backplane_window(sbus, address);
if (ret != OK)
{
wlerr("Backplane setting failed at %08x\n", address);
return ret;
}
@@ -168,15 +184,63 @@ int bcmf_upload_binary(FAR struct bcmf_sdio_dev_s *sbus, uint32_t address,
address & SBSDIO_SB_OFT_ADDR_MASK, buf, size);
if (ret != OK)
{
wlerr("transfer failed %d %x %d\n", ret, address, size);
return ret;
wlerr("transfer failed %d %x %d\n", ret, address, size);
return ret;
}
len -= size;
address += size;
buf += size;
len -= size;
address += size;
buf += size;
}
#ifdef DBG_VALIDATE_UPLOAD
wlwarn("Validating....\n");
while (validate_len > 0)
{
/* Set the backplane window to include the start address */
int ret = bcmf_core_set_backplane_window(sbus, validate_address);
if (ret != OK)
{
wlerr("Backplane setting failed at %08x\n", validate_address);
return ret;
}
if (validate_len > BCMF_UPLOAD_TRANSFER_SIZE)
{
size = BCMF_UPLOAD_TRANSFER_SIZE;
}
else
{
size = validate_len;
}
/* Transfer firmware data */
ret = bcmf_transfer_bytes(sbus, false, 1,
validate_address & SBSDIO_SB_OFT_ADDR_MASK,
compare_buffer, size);
if (ret != OK)
{
wlerr("validate transfer failed %d %x %d\n", ret, validate_address,
size);
return ret;
}
if (memcmp(validate_buffer, compare_buffer, size))
{
wlerr("Match failed at address base %08x\n", validate_address);
return -EILSEQ;
}
validate_len -= size;
validate_address += size;
validate_buffer += size;
}
wlwarn("Validation passed\n");
#endif
return OK;
}
@@ -193,10 +257,10 @@ int bcmf_upload_file(FAR struct bcmf_sdio_dev_s *sbus, uint32_t address,
/* Open the file in the detached state */
ret = file_open(&finfo, path, O_RDONLY | O_BINARY);
if (ret <0)
if (ret < 0)
{
wlerr("ERROR: Failed to open the FILE MTD file %s: %d\n", path, ret);
return ret;
wlerr("ERROR: Failed to open the FILE MTD file %s: %d\n", path, ret);
return ret;
}
/* Allocate an I/O buffer */
@@ -204,9 +268,9 @@ int bcmf_upload_file(FAR struct bcmf_sdio_dev_s *sbus, uint32_t address,
buf = (FAR uint8_t *)kmm_malloc(BCMF_UPLOAD_TRANSFER_SIZE);
if (buf == NULL)
{
wlerr("ERROR: Failed allocate an I/O buffer\n");
ret = -ENOMEM;
goto errout_with_file;
wlerr("ERROR: Failed allocate an I/O buffer\n");
ret = -ENOMEM;
goto errout_with_file;
}
/* Loop until the firmware has been loaded */
@@ -296,7 +360,7 @@ int bcmf_upload_nvram(FAR struct bcmf_sdio_dev_s *sbus)
/* Generate length token */
token = nvram_sz / 4;
token = (~token << 16) | (token & 0x0000FFFF);
token = (~token << 16) | (token & 0x0000ffff);
/* Write the length token to the last word */
@@ -346,7 +410,6 @@ int bcmf_read_sbreg(FAR struct bcmf_sdio_dev_s *sbus, uint32_t address,
int bcmf_write_sbreg(FAR struct bcmf_sdio_dev_s *sbus, uint32_t address,
FAR uint8_t *reg, unsigned int len)
{
int ret = bcmf_core_set_backplane_window(sbus, address);
if (ret != OK)
{

330
drivers/wireless/ieee80211/mmc_sdio.c
View File

@@ -1,13 +1,61 @@
/****************************************************************************
* drivers/wireless/ieee80211/mmc_sdio.h
*
* Copyright (C) 2017 Gregory Nutt. All rights reserved.
* Author: Simon Piriou <spiriou31@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/wireless/ieee80211/mmc_sdio.h>
#include <debug.h>
#include <errno.h>
#include <nuttx/compiler.h>
#include <nuttx/arch.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define SDIO_CMD53_TIMEOUT_MS 100
#define SDIO_IDLE_DELAY_MS 50
struct __attribute__((packed)) sdio_cmd52
/****************************************************************************
* Private Types
****************************************************************************/
begin_packed_struct struct sdio_cmd52
{
uint32_t write_data : 8;
uint32_t reserved_8 : 1;
@@ -16,9 +64,9 @@ struct __attribute__((packed)) sdio_cmd52
uint32_t raw_flag : 1;
uint32_t function_number : 3;
uint32_t rw_flag : 1;
};
} end_packed_struct;
struct __attribute__((packed)) sdio_cmd53
begin_packed_struct struct sdio_cmd53
{
uint32_t byte_block_count : 9;
uint32_t register_address : 17;
@@ -26,9 +74,9 @@ struct __attribute__((packed)) sdio_cmd53
uint32_t block_mode : 1;
uint32_t function_number : 3;
uint32_t rw_flag : 1;
};
} end_packed_struct;
struct __attribute__((packed)) sdio_resp_R5
begin_packed_struct struct sdio_resp_R5
{
uint32_t data : 8;
struct
@@ -42,7 +90,7 @@ struct __attribute__((packed)) sdio_resp_R5
uint32_t com_crc_error : 1;
} flags;
uint32_t reserved_16 : 16;
};
} end_packed_struct;
union sdio_cmd5x
{
@@ -51,6 +99,10 @@ union sdio_cmd5x
struct sdio_cmd53 cmd53;
};
/****************************************************************************
* Public Functions
****************************************************************************/
int sdio_sendcmdpoll(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t arg)
{
int ret;
@@ -77,58 +129,59 @@ int sdio_io_rw_direct(FAR struct sdio_dev_s *dev, bool write,
uint8_t function, uint32_t address,
uint8_t inb, uint8_t *outb)
{
union sdio_cmd5x arg;
struct sdio_resp_R5 resp;
int ret;
union sdio_cmd5x arg;
struct sdio_resp_R5 resp;
int ret;
/* Setup CMD52 argument */
/* Setup CMD52 argument */
arg.value = 0;
arg.value = 0;
if (write)
{
arg.cmd52.write_data = inb;
}
else
{
arg.cmd52.write_data = 0;
}
arg.cmd52.register_address = address & 0x1ffff;
arg.cmd52.raw_flag = (write && outb);
arg.cmd52.function_number = function & 7;
arg.cmd52.rw_flag = write;
if (write)
{
arg.cmd52.write_data = inb;
}
else
{
arg.cmd52.write_data = 0;
}
/* Send CMD52 command */
arg.cmd52.register_address = address & 0x1ffff;
arg.cmd52.raw_flag = (write && outb);
arg.cmd52.function_number = function & 7;
arg.cmd52.rw_flag = write;
sdio_sendcmdpoll(dev, SDIO_ACMD52, arg.value);
ret = SDIO_RECVR5(dev, SDIO_ACMD52, (uint32_t *)&resp);
/* Send CMD52 command */
if (ret != OK)
{
wlerr("ERROR: SDIO_RECVR5 failed %d\n", ret);
return ret;
}
sdio_sendcmdpoll(dev, SD_ACMD52, arg.value);
ret = SDIO_RECVR5(dev, SD_ACMD52, (uint32_t *)&resp);
/* Check for errors */
if (ret != OK)
{
wlerr("ERROR: SDIO_RECVR5 failed %d\n", ret);
return ret;
}
if (resp.flags.error)
{
return -EIO;
}
/* Check for errors */
if (resp.flags.function_number || resp.flags.out_of_range)
{
return -EINVAL;
}
if (resp.flags.error)
{
return -EIO;
}
/* Write output byte */
if (resp.flags.function_number || resp.flags.out_of_range)
{
return -EINVAL;
}
if (outb)
{
*outb = resp.data & 0xff;
}
/* Write output byte */
return OK;
if (outb)
{
*outb = resp.data & 0xff;
}
return OK;
}
int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write,
@@ -136,88 +189,94 @@ int sdio_io_rw_extended(FAR struct sdio_dev_s *dev, bool write,
bool inc_addr, uint8_t *buf,
unsigned int blocklen, unsigned int nblocks)
{
union sdio_cmd5x arg;
struct sdio_resp_R5 resp;
int ret;
sdio_eventset_t wkupevent;
union sdio_cmd5x arg;
struct sdio_resp_R5 resp;
int ret;
sdio_eventset_t wkupevent;
/* Setup CMD53 argument */
/* Setup CMD53 argument */
arg.value = 0;
arg.cmd53.register_address = address & 0x1ffff;
arg.cmd53.op_code = inc_addr;
arg.cmd53.function_number = function & 7;
arg.cmd53.rw_flag = write;
arg.value = 0;
arg.cmd53.register_address = address & 0x1ffff;
arg.cmd53.op_code = inc_addr;
arg.cmd53.function_number = function & 7;
arg.cmd53.rw_flag = write;
if (nblocks == 0 && blocklen < 512)
{
/* Use byte mode */
if (nblocks == 0 && blocklen < 512)
{
/* Use byte mode */
// wlinfo("byte mode\n");
arg.cmd53.block_mode = 0;
arg.cmd53.byte_block_count = blocklen;
nblocks = 1;
}
else
{
/* Use block mode */
arg.cmd53.block_mode = 0;
arg.cmd53.byte_block_count = blocklen;
nblocks = 1;
}
else
{
/* Use block mode */
arg.cmd53.block_mode = 1;
arg.cmd53.byte_block_count = nblocks;
}
arg.cmd53.block_mode = 1;
arg.cmd53.byte_block_count = nblocks;
}
/* Send CMD53 command */
/* Send CMD53 command */
SDIO_BLOCKSETUP(dev, blocklen, nblocks);
SDIO_WAITENABLE(dev,
SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR);
SDIO_BLOCKSETUP(dev, blocklen, nblocks);
SDIO_WAITENABLE(dev,
SDIOWAIT_TRANSFERDONE | SDIOWAIT_TIMEOUT | SDIOWAIT_ERROR);
if (write)
{
// wlinfo("prep write %d %d\n", blocklen, nblocks);
sdio_sendcmdpoll(dev, SDIO_ACMD53, (uint32_t)arg.value);
ret = SDIO_RECVR5(dev, SDIO_ACMD53, (uint32_t *)&resp);
if (write)
{
wlinfo("prep write %d %d\n", blocklen, nblocks);
SDIO_DMASENDSETUP(dev, buf, blocklen * nblocks);
SDIO_SENDCMD(dev, SD_ACMD53, (uint32_t)arg.value);
SDIO_DMASENDSETUP(dev, buf, blocklen * nblocks);
wkupevent = SDIO_EVENTWAIT(dev, SDIO_CMD53_TIMEOUT_MS);
}
else
{
// wlinfo("prep read %d\n", blocklen * nblocks);
SDIO_DMARECVSETUP(dev, buf, blocklen * nblocks);
SDIO_SENDCMD(dev, SDIO_ACMD53, (uint32_t)arg.value);
wkupevent = SDIO_EVENTWAIT(dev, SDIO_CMD53_TIMEOUT_MS);
ret = SDIO_RECVR5(dev, SD_ACMD53, (uint32_t *)&resp);
}
else
{
wlinfo("prep read %d\n", blocklen * nblocks);
SDIO_DMARECVSETUP(dev, buf, blocklen * nblocks);
SDIO_SENDCMD(dev, SD_ACMD53, (uint32_t)arg.value);
wkupevent = SDIO_EVENTWAIT(dev, SDIO_CMD53_TIMEOUT_MS);
ret = SDIO_RECVR5(dev, SDIO_ACMD53, (uint32_t *)&resp);
}
wkupevent = SDIO_EVENTWAIT(dev, SDIO_CMD53_TIMEOUT_MS);
ret = SDIO_RECVR5(dev, SD_ACMD53, (uint32_t *)&resp);
}
if (ret != OK)
{
wlerr("ERROR: SDIO_RECVR5 failed %d\n", ret);
return ret;
}
wlinfo("Transaction ends\n");
sdio_sendcmdpoll(dev, SD_ACMD52ABRT, 0);
/* Check for errors */
/* There may not be a response to this, so don't look for one */
if (wkupevent & SDIOWAIT_TIMEOUT)
{
wlerr("timeout\n");
return -ETIMEDOUT;
}
SDIO_RECVR1(dev, SD_ACMD52ABRT, (uint32_t *)&resp);
if (resp.flags.error || (wkupevent & SDIOWAIT_ERROR))
{
wlerr("error 1\n");
return -EIO;
}
if (ret != OK)
{
wlerr("ERROR: SDIO_RECVR5 failed %d\n", ret);
return ret;
}
if (resp.flags.function_number || resp.flags.out_of_range)
{
wlerr("error 2\n");
return -EINVAL;
}
/* Check for errors */
return OK;
if (wkupevent & SDIOWAIT_TIMEOUT)
{
wlerr("timeout\n");
return -ETIMEDOUT;
}
if (resp.flags.error || (wkupevent & SDIOWAIT_ERROR))
{
wlerr("error 1\n");
return -EIO;
}
if (resp.flags.function_number || resp.flags.out_of_range)
{
wlerr("error 2\n");
return -EINVAL;
}
return OK;
}
int sdio_set_wide_bus(struct sdio_dev_s *dev)
@@ -255,12 +314,21 @@ int sdio_probe(FAR struct sdio_dev_s *dev)
/* Set device state from reset to idle */
sdio_sendcmdpoll(dev, MMCSD_CMD0, 0);
ret = sdio_sendcmdpoll(dev, MMCSD_CMD0, 0);
if (ret != OK)
{
return ret;
}
up_mdelay(SDIO_IDLE_DELAY_MS);
/* Device is SDIO card compatible so we can send CMD5 instead of ACMD41 */
sdio_sendcmdpoll(dev, SDIO_CMD5, 0);
ret = sdio_sendcmdpoll(dev, SDIO_CMD5, 0);
if (ret != OK)
{
return ret;
}
/* Receive R4 response */
@@ -272,21 +340,31 @@ int sdio_probe(FAR struct sdio_dev_s *dev)
/* Device is in Card Identification Mode, request device RCA */
sdio_sendcmdpoll(dev, SD_CMD3, 0);
ret = SDIO_RECVR6(dev, SD_CMD3, &data);
if (ret != OK)
ret = sdio_sendcmdpoll(dev, SD_CMD3, 0);
if (ret != OK)
{
wlerr("ERROR: RCA request failed: %d\n", ret);
return ret;
return ret;
}
wlinfo("rca is %x\n", data >> 16);
ret = SDIO_RECVR6(dev, SD_CMD3, &data);
if (ret != OK)
{
wlerr("ERROR: RCA request failed: %d\n", ret);
return ret;
}
wlinfo("rca is %x\n", data >> 16);
/* Send CMD7 with the argument == RCA in order to select the card
* and put it in Transfer State */
* and put it in Transfer State.
*/
sdio_sendcmdpoll(dev, MMCSD_CMD7S, data & 0xffff0000);
ret = sdio_sendcmdpoll(dev, MMCSD_CMD7S, data & 0xffff0000);
if (ret != OK)
{
wlerr("ERROR: CMD7 request failed: %d\n", ret);
return ret;
}
ret = SDIO_RECVR1(dev, MMCSD_CMD7S, &data);
if (ret != OK)
@@ -344,7 +422,8 @@ int sdio_enable_function(FAR struct sdio_dev_s *dev, uint8_t function)
return ret;
}
ret = sdio_io_rw_direct(dev, true, 0, SDIO_CCCR_IOEN, value | (1 << function), NULL);
ret = sdio_io_rw_direct(dev, true, 0,
SDIO_CCCR_IOEN, value | (1 << function), NULL);
if (ret != OK)
{
@@ -389,5 +468,6 @@ int sdio_enable_interrupt(FAR struct sdio_dev_s *dev, uint8_t function)
return ret;
}
return sdio_io_rw_direct(dev, true, 0, SDIO_CCCR_INTEN, value | (1 << function), NULL);
return sdio_io_rw_direct(dev, true, 0,
SDIO_CCCR_INTEN, value | (1 << function), NULL);
}

15
include/nuttx/sdio.h
View File

@@ -209,9 +209,9 @@
# define SD_ACMDIDX49 49 /* CHANGE_SECURE_AREA: */
# define SD_ACMDIDX51 51 /* SEND_SCR: Reads the SD Configuration Register (SCR)
* Addressed data transfer command, R1 response */
# define SDIO_ACMDIDX52 52 /* IO_RW_DIRECT: (SDIO only)
# define SD_ACMDIDX52 52 /* IO_RW_DIRECT: (SDIO only)
* -R5 response, 23:16=status 15:8=data */
# define SDIO_ACMDIDX53 53 /* IO_RW_EXTENDED: (SDIO only)
# define SD_ACMDIDX53 53 /* IO_RW_EXTENDED: (SDIO only)
* -R5 response, 23:16=status */
/* Response Encodings:
@@ -222,9 +222,10 @@
* C - Bits 0-5: Command index
* R - Bits 6-9: Response type
* X - Bits 10-12: Data transfer type
* M - Bit 13: Multiple block transfer
* M - Bit 13: MMC Multiblock transfer
* S - Bit 14: Stop data transfer
* O - Bit 15: Open drain
* D - But 16: SDIO Multiblock transfer
*/
#define MMCSD_RESPONSE_SHIFT (6)
@@ -259,6 +260,7 @@
/* Other options */
#define MMCSD_OPENDRAIN (1 << 15)
#define SDIO_MULTIBLOCK (1 << 16)
/* Fully decorated MMC, SD, SDIO commands */
@@ -325,8 +327,9 @@
#define SD_ACMD48 (SD_ACMDIDX48 |MMCSD_R1_RESPONSE |MMCSD_NODATAXFR)
#define SD_ACMD49 (SD_ACMDIDX49 |MMCSD_R1_RESPONSE |MMCSD_NODATAXFR)
#define SD_ACMD51 (SD_ACMDIDX51 |MMCSD_R1_RESPONSE |MMCSD_RDDATAXFR)
#define SDIO_ACMD52 (SDIO_ACMDIDX52|MMCSD_R5_RESPONSE |MMCSD_NODATAXFR)
#define SDIO_ACMD53 (SDIO_ACMDIDX53|MMCSD_R5_RESPONSE |MMCSD_NODATAXFR)
#define SD_ACMD52 (SD_ACMDIDX52 |MMCSD_R5_RESPONSE |MMCSD_NODATAXFR)
#define SD_ACMD52ABRT (SD_ACMDIDX52 |MMCSD_R1_RESPONSE |MMCSD_NODATAXFR|MMCSD_STOPXFR)
#define SD_ACMD53 (SD_ACMDIDX53 |MMCSD_R5_RESPONSE |MMCSD_NODATAXFR)
/* SDIO Card Common Control Registers definitions
* see https://www.sdcard.org/developers/overview/sdio/
@@ -421,6 +424,8 @@
#define SDIO_CAPS_1BIT_ONLY 0x01 /* Bit 0=1: Supports only 1-bit operation */
#define SDIO_CAPS_DMASUPPORTED 0x02 /* Bit 1=1: Supports DMA data transfers */
#define SDIO_CAPS_DMABEFOREWRITE 0x04 /* Bit 2=1: Executes DMA before write command */
#define SDIO_CAPS_4BIT 0x08 /* Bit 3=1: Supports 4 bit operation */
#define SDIO_CAPS_8BIT 0x10 /* Bit 4=1: Supports 8 bit operation */
/****************************************************************************
* Name: SDIO_STATUS