arch/arm/src/s32k1xx: This is a rough port of the i.MXRT Ethernet driver to the S32K1xx. The i.MXRT uses the same IP. Completely untested at this point.

2026-05-18 00:34:10 +08:00 · 2019-08-21 17:33:54 -06:00
parent 7ad9dfb610
commit 962ccb0f68
8 changed files with 3444 additions and 5 deletions
@@ -63,7 +63,7 @@
 #define IMXRT_ENET_PALR_OFFSET     0x00e4 /* Physical Address Lower Register */
 #define IMXRT_ENET_PAUR_OFFSET     0x00e8 /* Physical Address Upper Register */
 #define IMXRT_ENET_OPD_OFFSET      0x00ec /* Opcode/Pause Duration Register */
-#define IMXRT_ENET_TXIC_OFFSET     0x00F0 /* Transmit Interrupt Coalescing Register */
+#define IMXRT_ENET_TXIC_OFFSET     0x00f0 /* Transmit Interrupt Coalescing Register */
 #define IMXRT_ENET_RXIC_OFFSET     0x0100 /* Receive Interrupt Coalescing Register */
 #define IMXRT_ENET_IAUR_OFFSET     0x0118 /* Descriptor Individual Upper Address Register */
 #define IMXRT_ENET_IALR_OFFSET     0x011c /* Descriptor Individual Lower Address Register */
@@ -200,6 +200,7 @@
 #endif
                                               /* Bits 9-31: Reserved */
 #define ECR_RESV_VAL                 (7 << 28) /* Reserve val to write */
+
 /* MII Management Frame Register */

 #define ENET_MMFR_DATA_SHIFT         (0)       /* Bits 0-15: Management frame data */
@@ -286,10 +287,11 @@
 #define ENET_OPD_OPCODE_SHIFT        (16)      /* Bits 16-31: Opcode field in PAUSE frames */
 #define ENET_OPD_OPCODE_MASK         (0xffff << ENET_OPD_OPCODE_SHIFT)

-/* Descriptor Individual Uupper/Lower Address Register (64-bit address in two 32-bit registers) */
+/* Descriptor Individual Upper/Lower Address Register (64-bit address in two 32-bit registers) */
 /* Descriptor Group Upper/Lower Address Register (64-bit address in two 32-bit registers) */

 /* Transmit Interrupt Coalescing Register */
+
 #define ENET_TXIC_ICTT_SHIFT         (0)       /* Bits 0-15: Interrupt coalescing timer threshold */
 #define ENET_TXIC_ICTT_SHIFT_MASK    (0xffff << ENET_TXIC_ICTT_SHIFT)
                                               /* Bits 16-19: Reserved */
@@ -299,6 +301,7 @@
 #define ENET_TXIC_ICTT_ICEN          (1 << 31) /* Bit 31: Eable/disabel Interrupt Coalescing */

 /* Receive Interrupt Coalescing Register */
+
 #define ENET_RXIC_ICTT_SHIFT         (0)       /* Bits 0-15: Interrupt coalescing timer threshold */
 #define ENET_RXIC_ICTT_SHIFT_MASK    (0xffff << ENET_TXIC_ICTT_SHIFT)
                                               /* Bits 16-19: Reserved */
@@ -82,6 +82,10 @@ ifeq ($(CONFIG_S32K1XX_LPSPI),y)
 CHIP_CSRCS += s32k1xx_lpspi.c
 endif

+ifeq ($(CONFIG_S32K1XX_ENET),y)
+CHIP_CSRCS += s32k1xx_enet.c
+endif
+
 # Source files specific to the ARM CPU family and to the S32K1xx chip family

 ifeq ($(CONFIG_ARCH_CHIP_S32K11X),y)
@@ -42,6 +42,7 @@
 ************************************************************************************************************/

 #include <nuttx/config.h>
+#include "hardware/s32k1xx_memorymap.h"

 /************************************************************************************************************
 * Pre-processor Definitions
@@ -0,0 +1,123 @@
+/************************************************************************************
+ * arch/arm/src/s32k1xx/s32k1xx_enet.h
+ *
+ *   Copyright (C) 2018 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_ENET_H
+#define __ARCH_ARM_SRC_S32K1XX_S32K1XX_ENET_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "hardware/s32k1xx_enet.h"
+
+#ifdef CONFIG_S32K1XX_ENET
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Definitions for use with s32k1xx_phy_boardinitialize */
+
+#define EMAC_INTF 0
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Function: up_netinitialize
+ *
+ * Description:
+ *   Initialize the first network interface.  If there are more than one
+ *   interface in the chip, then board-specific logic will have to provide
+ *   this function to determine which, if any, Ethernet controllers should
+ *   be initialized.  Also prototyped in up_internal.h.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ * Assumptions:
+ *   Called very early in the initialization sequence.
+ *
+ ************************************************************************************/
+
+void up_netinitialize(void);
+
+/************************************************************************************
+ * Function: s32k1xx_phy_boardinitialize
+ *
+ * Description:
+ *   Some boards require specialized initialization of the PHY before it can be
+ *   used.  This may include such things as configuring GPIOs, resetting the PHY,
+ *   etc.  If CONFIG_S32K1XX_ENET_PHYINIT is defined in the configuration then the
+ *   board specific logic must provide s32k1xx_phyinitialize();  The i.MX RT Ethernet
+ *   driver will call this function one time before it first uses the PHY.
+ *
+ * Input Parameters:
+ *   intf - Always zero for now.
+ *
+ * Returned Value:
+ *   OK on success; Negated errno on failure.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_S32K1XX_ENET_PHYINIT
+int s32k1xx_phy_boardinitialize(int intf);
+#endif
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_S32K1XX_ENET */
+#endif /* __ARCH_ARM_SRC_S32K1XX_S32K1XX_ENET_H */
@@ -33,8 +33,8 @@
 *
 ****************************************************************************/

-#ifndef __ARCH_ARM_SRC_IMXRT_IMX_LPI2C_H
-#define __ARCH_ARM_SRC_IMXRT_IMX_LPI2C_H
+#ifndef __ARCH_ARM_SRC_S32K1XX_S32K1XX_LPI2C_H
+#define __ARCH_ARM_SRC_S32K1XX_S32K1XX_LPI2C_H

 /****************************************************************************
 * Included Files
@@ -86,4 +86,4 @@ FAR struct i2c_master_s *s32k1xx_i2cbus_initialize(int port);

 int s32k1xx_i2cbus_uninitialize(FAR struct i2c_master_s *dev);

-#endif /* __ARCH_ARM_SRC_IMXRT_IMX_LPI2C_H */
+#endif /* __ARCH_ARM_SRC_S32K1XX_S32K1XX_LPI2C_H */
@@ -1,3 +1,4 @@
+/platform
 /Make.dep
 /.depend
 /*.asm