mirror of
https://github.com/apache/nuttx.git
synced 2026-05-21 13:13:08 +08:00
boards: added a basic support for chipKIT Wi-FIRE board;
added Sourcery CodeBench Lite for MIPS ELF Toolchain option; corrected inaccuracies in Photon board and EMW3162 board README.txt files.
This commit is contained in:
Alexander Lunev
committed by
Xiang Xiao
Xiang Xiao
parent
0e2cbe9a79
commit
95abf562f4
@@ -2284,6 +2284,8 @@ Below is a guide to the available README files in the NuttX source tree:
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| | | `- ubw32/
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| | | `- README.txt
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| | `-pic32mz/
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| | |- chipkit-wifire/
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| | | `- README.txt
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| | |- flipnclick-pic32mz/
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| | | `- README.txt
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| | `- pic32mz-starterkit/
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@@ -67,6 +67,11 @@ config MIPS32_TOOLCHAIN_PINGUINOL
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depends on HOST_LINUX || HOST_MACOS
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select ARCH_TOOLCHAIN_GNU
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config MIPS32_TOOLCHAIN_SOURCERY_CODEBENCH_LITE
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bool "Sourcery CodeBench Lite for MIPS ELF toolchain under Linux"
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depends on HOST_LINUX
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select ARCH_TOOLCHAIN_GNU
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endchoice
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config MIPS32_TOOLCHAIN_MICROCHIP_XC32_LICENSED
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@@ -39,6 +39,12 @@ ifeq ($(filter y, \
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CONFIG_MIPS32_TOOLCHAIN ?= PINGUINOL
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endif
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ifeq ($(filter y, \
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$(CONFIG_MIPS32_TOOLCHAIN_SOURCERY_CODEBENCH_LITE) \
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),y)
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CONFIG_MIPS32_TOOLCHAIN ?= SOURCERY_CODEBENCH_LITE
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endif
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ifeq ($(filter y, \
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$(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32) \
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),y)
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@@ -149,6 +155,17 @@ ifeq ($(CONFIG_MIPS32_TOOLCHAIN),PINGUINOL)
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LDSCRIPT = pinguino-debug.ld
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endif
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# Sourcery CodeBench Lite toolchain under Linux
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ifeq ($(CONFIG_MIPS32_TOOLCHAIN),SOURCERY_CODEBENCH_LITE)
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CROSSDEV ?= mips-sde-elf-
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MAXOPTIMIZATION ?= -O2
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ARCHCPUFLAGS = -mlong32 -membedded-data -msoft-float -march=$(MIPS_MARCH) $(MIPS_MICROMIPS) -EL
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ARCHPICFLAGS = -fpic -membedded-pic
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LDFLAGS += -nostartfiles -nodefaultlibs
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LDSCRIPT = sourcery-debug.ld
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endif
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# Microchip XC32 toolchain under Linux
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ifeq ($(CONFIG_MIPS32_TOOLCHAIN),MICROCHIPL_XC32)
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@@ -306,6 +306,17 @@ config ARCH_BOARD_FIRE_STM32
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and 3 of the boards are supported but only version 2 has been
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tested.
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config ARCH_BOARD_CHIPKIT_WIFIRE
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bool "chipKIT Wi-FIRE"
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depends on ARCH_CHIP_PIC32MZ2048EFG
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select ARCH_HAVE_LEDS
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select ARCH_HAVE_BUTTONS
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select ARCH_HAVE_IRQBUTTONS
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---help---
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This options selects the chipKIT Wi-FIRE board. This
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board is a chipKIT Arduino-compatible board. This board
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features the Microchip PIC32MZ2048EFG100 MCU running at 200 MHz.
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config ARCH_BOARD_FLIPNCLICK_PIC32MZ
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bool "Mikroe Flip&Click PIC32MZ"
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depends on ARCH_CHIP_PIC32MZ2048EFH
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@@ -2340,6 +2351,7 @@ config ARCH_BOARD
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default "ez80f910200kitg" if ARCH_BOARD_EZ80F910200KITG
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default "ez80f910200zco" if ARCH_BOARD_EZ80F910200ZCO
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default "fire-stm32v2" if ARCH_BOARD_FIRE_STM32
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default "chipkit-wifire" if ARCH_BOARD_CHIPKIT_WIFIRE
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default "flipnclick-pic32mz" if ARCH_BOARD_FLIPNCLICK_PIC32MZ
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default "flipnclick-sam3x" if ARCH_BOARD_FLIPNCLICK_SAM3X
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default "freedom-k28f" if ARCH_BOARD_FREEDOM_K28F
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@@ -3152,6 +3164,9 @@ endif
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if ARCH_BOARD_UBW32
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source "boards/mips/pic32mx/ubw32/Kconfig"
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endif
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if ARCH_BOARD_CHIPKIT_WIFIRE
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source "boards/mips/pic32mz/chipkit-wifire/Kconfig"
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endif
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if ARCH_BOARD_FLIPNCLICK_PIC32MZ
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source "boards/mips/pic32mz/flipnclick-pic32mz/Kconfig"
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endif
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@@ -292,6 +292,11 @@ boards/mips/pic32mz/flipnclick-pic32mz
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standard Arduino connectors. This board features the Microchip
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PIC32MZ2048EFH100 MCU running at 200 MHz (252 MHz capable).
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boards/mips/pic32mz/chipkit-wifire
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Board support for the chipKIT Wi-FIRE board. This board is a chipKIT
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Arduino-compatible board. This board features
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the Microchip PIC32MZ2048EFG100 MCU running at 200 MHz.
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boards/arm/sam34/flipnclick-sam3x
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Board support for the Mikroe Flip&Click STM32X board. This board is an
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Arduino-Due work-alike with four Mikroe Click bus interfaces. Like the
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@@ -3,8 +3,8 @@ README
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EMW3162 board (https://www.waveshare.com/EMW3162.htm) features the
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STM32F205RG MCU and Broadcom BCM43362KUBG Wi-Fi chip.
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The STM32F205RG is a 120 MHz Cortex-M3 operation with 1Mbit Flash
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memory and 128kbytes.
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The STM32F205RG is a 120 MHz Cortex-M3 operation with 1MB Flash
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memory and 128KB RAM.
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Contents
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========
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@@ -3,8 +3,8 @@ README
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This README discusses issues unique to NuttX configurations for the
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Particle.io Photon board featuring the STM32F205RG MCU.
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The STM32F205RG is a 120 MHz Cortex-M3 operation with 1Mbit Flash
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memory and 128kbytes. The board includes a Broadcom BCM43362 WiFi.
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The STM32F205RG is a 120 MHz Cortex-M3 operation with 1MB Flash
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memory and 128KB RAM. The board includes a Broadcom BCM43362 WiFi.
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Contents
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========
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@@ -18,8 +18,8 @@ Selecting the Photon board on NuttX
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===================================
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NOTICE: We will not discuss about toolchains and environment configuration
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here, please take a look at STM32F4Discory board README or other STM32 board
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because it should work for Photon board as well.
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here, please take a look at STM32F4Discovery board README or other
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STM32 board because it should work for Photon board as well.
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Let us to consider that you cloned the nuttx and apps repositories, then
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follow these steps:
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@@ -0,0 +1,7 @@
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#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_BOARD_CHIPKIT_WIFIRE
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endif # ARCH_BOARD_CHIPKIT_WIFIRE
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@@ -0,0 +1,75 @@
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README
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======
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chipKIT Wi-FIRE board
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(https://chipkit.net/wiki/index.php?title=ChipKIT_Wi-Fire) features
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the Microchip PIC32MZ2048EFG100 MCU, Microchip MRF24WG0MA Wi-Fi module,
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USB 2.0 Full-Speed / Hi-Speed OTG controller, Micro SD card connector etc.
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The PIC32MZ2048EFG100 is a 200 MHz 32-bit MIPS M5150 operation with 2MB Flash
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memory and 512KB RAM.
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Contents
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========
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- Toolchain
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- Building NuttX for the chipKIT Wi-FIRE board
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- Programming Flash
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- Serial console
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Toolchain
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=========
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The following Toolchain options have been tested and confirmed to work:
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CONFIG_MIPS32_TOOLCHAIN_PINGUINOL - Pinquino Toolchain
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for Linux
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CONFIG_MIPS32_TOOLCHAIN_SOURCERY_CODEBENCH_LITE - Sourcery CodeBench Lite
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Toolchain for Linux
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Pinquino Toolchain can be downloaded here:
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https://github.com/PinguinoIDE/pinguino-compilers
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Sourcery CodeBench Lite Toolchain for Linux can be downloaded and
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installed as follows:
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$ wget https://sourcery.mentor.com/GNUToolchain/package12725/public/mips-sde-elf/mips-2014.05-24-mips-sde-elf-i686-pc-linux-gnu.tar.bz2
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$ sudo tar xvjf mips-2014.05-24-mips-sde-elf-i686-pc-linux-gnu.tar.bz2 \
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-C /usr/local
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Building NuttX for the chipKIT Wi-FIRE board
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============================================
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$ cd nuttx
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$ make apps_distclean
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$ make distclean
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$ ./tools/configure.sh -l chipkit-wifire:nsh
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$ make
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Programming Flash
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=================
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CAUTION:
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Currently the pre-installed bootloader of the chipKIT Wi-FIRE board
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is not supported in this NuttX configuration. Doing the following
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steps will erase the factory installed bootloader in the Flash
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memory! If you are going to recover the bootloader later on your
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chipKIT Wi-FIRE board, the original chipKIT bootloader can be found here:
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https://reference.digilentinc.com/_media/chipkit_wifire/chipkit-wifire-v01000303.zip
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Flash memory can be programmed by pic32prog utility
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(https://github.com/sergev/pic32prog.git) and PICkit 2 programmer
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(via 6-pin ICSP (JP1) of chipKIT Wi-FIRE board) as follows:
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$ sudo pic32prog nuttx.hex
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Serial console
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==============
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Connect USB cable from your PC to connector J1 (labeled "UART") of
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the chipKIT Wi-FIRE board.
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Then use some serial console client (minicom, picocom, teraterm, etc)
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configured to 115200 8n1 without software or hardware flow control.
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Reset the board and you should see NuttX starting in the serial.
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@@ -0,0 +1,49 @@
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#
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# This file is autogenerated: PLEASE DO NOT EDIT IT.
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#
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# You can use "make menuconfig" to make any modifications to the installed .config file.
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# You can then do "make savedefconfig" to generate a new defconfig file that includes your
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# modifications.
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#
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# CONFIG_ARCH_RAMFUNCS is not set
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CONFIG_ARCH="mips"
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CONFIG_ARCH_BOARD="chipkit-wifire"
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CONFIG_ARCH_BOARD_CHIPKIT_WIFIRE=y
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CONFIG_ARCH_CHIP="pic32mz"
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CONFIG_ARCH_CHIP_PIC32MZ2048EFG=y
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CONFIG_ARCH_CHIP_PIC32MZ=y
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CONFIG_ARCH_CHIP_PIC32MZEF=y
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CONFIG_ARCH_MIPS=y
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CONFIG_ARCH_STACKDUMP=y
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CONFIG_BOARD_LOOPSPERMSEC=7245
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CONFIG_BUILTIN=y
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CONFIG_FAT_LCNAMES=y
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CONFIG_FAT_LFN=y
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CONFIG_FS_FAT=y
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CONFIG_FS_PROCFS=y
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CONFIG_HOST_WINDOWS=y
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CONFIG_IDLETHREAD_STACKSIZE=2048
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CONFIG_INTELHEX_BINARY=y
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CONFIG_MIPS_MICROMIPS=y
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CONFIG_MMCSD=y
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CONFIG_MTD=y
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CONFIG_NSH_ARCHINIT=y
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CONFIG_NSH_BUILTIN_APPS=y
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CONFIG_NSH_DISABLE_IFUPDOWN=y
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CONFIG_NSH_FILEIOSIZE=512
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CONFIG_NSH_LINELEN=64
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CONFIG_NSH_READLINE=y
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CONFIG_PIC32MZ_ICESEL_CH2=y
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CONFIG_PIC32MZ_UART4=y
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CONFIG_PREALLOC_TIMERS=4
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CONFIG_RAM_SIZE=131072
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CONFIG_RAM_START=0xa0000000
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CONFIG_RR_INTERVAL=200
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CONFIG_SCHED_WAITPID=y
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CONFIG_SDCLONE_DISABLE=y
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CONFIG_START_DAY=7
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CONFIG_START_MONTH=3
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CONFIG_START_YEAR=2012
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CONFIG_SYSTEM_NSH=y
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CONFIG_UART4_SERIAL_CONSOLE=y
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CONFIG_USER_ENTRYPOINT="nsh_main"
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@@ -0,0 +1,321 @@
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/****************************************************************************
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* boards/mips/pic32mz/chipkit-wifire/include/board.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_MIPS_PIC32MZ_CHIPKIT_WIFIRE_INCLUDE_BOARD_H
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#define __BOARDS_MIPS_PIC32MZ_CHIPKIT_WIFIRE_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdbool.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* Crystal frequencies
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*
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* - A 24 MHz oscillator circuit (IC7) is connected to the on-board
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* microcontroller. This oscillator circuit functions as the controller’s
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* primary oscillator.
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* - The starter kit also has provisions for an external secondary 32 kHz
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* oscillator (X2); however, this is not populated.
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*/
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#define BOARD_POSC_FREQ 24000000 /* Primary OSC XTAL frequency (IC7, 24MHz) */
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#define BOARD_SOSC_FREQ 32000 /* Secondary OSC XTAL frequency (X2, 32KHz) */
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/* Oscillator modes.
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*
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* - BOARD_POSC_ECMODE: An external oscillator is connected to OSC1/OSC2
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* - BOARD_POSC_HSMODE: An external crystal or resonator is connected to
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* OSC1/OSC2
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*/
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#define BOARD_FNOSC_SPLL 1 /* Use system PLL */
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#define BOARD_POSC_ECMODE 1 /* External clock (EC) mode */
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#define BOARD_POSC_SWITCH 1 /* Enable clock switching */
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#undef BOARD_POSC_FSCM /* Disable clock monitoring */
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/* PLL configuration and resulting CPU clock.
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* CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
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*/
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#define BOARD_PLL_INPUT BOARD_POSC_FREQ
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#define BOARD_PLL_IDIV 3 /* PLL input divider */
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#define BOARD_PLL_MULT 50 /* PLL multiplier */
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#define BOARD_PLL_ODIV 2 /* PLL output divider */
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#define BOARD_CPU_CLOCK 200000000 /* CPU clock: 200MHz = (24MHz / 3) * 50 / 2) */
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/* Peripheral clocks */
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/* PBCLK1
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* Peripherals: OSC2 pin
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*
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* NOTES:
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* - PBCLK1 is used by system modules and cannot be turned off
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* - PBCLK1 divided by 2 is available on the OSC2 pin in certain clock
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* modes.
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*/
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#define BOARD_PB1DIV 5 /* Divider = 5 */
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#define BOARD_PBCLK1 40000000 /* PBCLK1 frequency = 200MHz/5 = 40MHz */
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/* PBCLK2
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* Peripherals: PMP, I2C, UART, SPI
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*/
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#define BOARD_PBCLK2_ENABLE 1 /* Enable PBCLK2 */
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#define BOARD_PB2DIV 2 /* Divider = 2 */
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#define BOARD_PBCLK2 100000000 /* PBCLK2 frequency = 200MHz/2 = 100MHz */
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/* PBCLK3
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* Peripherals: ADC, Comparator, Timers, Output Compare, Input Compare
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*
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* NOTES:
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* - Timer 1 uses SOSC
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*/
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#define BOARD_PBCLK3_ENABLE 1 /* Enable PBCLK3 */
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#define BOARD_PB3DIV 4 /* Divider = 4 */
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#define BOARD_PBCLK3 50000000 /* PBCLK3 frequency = 200MHz/4 = 50MHz */
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/* PBCLK4
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* Peripherals: Ports
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*/
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#define BOARD_PBCLK4_ENABLE 1 /* Enable PBCLK4 */
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#define BOARD_PB4DIV 2 /* Divider = 2 */
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#define BOARD_PBCLK4 100000000 /* PBCLK4 frequency = 200MHz/2 = 100MHz */
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/* PBCLK5
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* Peripherals: Flash, Crypto, RND, USB, Ethernet, SQI
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*
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* NOTES:
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* - PBCLK5 is used to fetch data from/to the Flash Controller, while the
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* FRC clock is used for programming
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*/
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#define BOARD_PBCLK5_ENABLE 1 /* Enable PBCLK5 */
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#define BOARD_PB5DIV 2 /* Divider = 2 */
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#define BOARD_PBCLK5 100000000 /* PBCLK5 frequency = 200MHz/2 = 100MHz */
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/* PBCLK6
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* Peripherals:
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*/
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#undef BOARD_PBCLK6_ENABLE
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/* PBCLK7
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* Peripherals: CPU, Deadman timer
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*/
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#undef BOARD_PBCLK7_ENABLE
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/* PBCLK8
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* Peripherals: EBI
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*/
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#undef BOARD_PBCLK8_ENABLE
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/* Watchdog pre-scaler (re-visit) */
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#define BOARD_WD_PRESCALER 1048576 /* Watchdog pre-scaler */
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/* Ethernet MII clocking.
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*
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* The clock divider used to create the MII Management Clock (MDC). The MIIM
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* module uses the PBCLK5 as an input clock. According to the IEEE 802.3
|
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* Specification this should be no faster than 2.5 MHz. However, some PHYs
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* support clock rates up to 12.5 MHz.
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*/
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#define BOARD_EMAC_MIIM_DIV 40 /* Ideal: 100MHz/40 = 2.5MHz */
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/* LED definitions **********************************************************/
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||||
/* There are four LEDs on the top side of the board:
|
||||
* controlled by software:
|
||||
*
|
||||
* LED LD1 - RG6
|
||||
* LED LD2 - RD4
|
||||
* LED LD3 - RB11
|
||||
* LED LD4 - RG15
|
||||
*
|
||||
* A high output value illuminates the LEDs.
|
||||
*/
|
||||
|
||||
/* LED index values for use with board_userled(): */
|
||||
|
||||
# define BOARD_LED_LD1 0
|
||||
# define BOARD_LED_LD2 1
|
||||
# define BOARD_LED_LD3 2
|
||||
# define BOARD_LED_LD4 3
|
||||
# define BOARD_NLEDS 4
|
||||
|
||||
/* LED bits for use with board_userled_all() */
|
||||
|
||||
# define BOARD_LED_LD1_BIT (1 << BOARD_LED_LD1)
|
||||
# define BOARD_LED_LD2_BIT (1 << BOARD_LED_LD2)
|
||||
# define BOARD_LED_LD3_BIT (1 << BOARD_LED_LD3)
|
||||
# define BOARD_LED_LD4_BIT (1 << BOARD_LED_LD4)
|
||||
|
||||
/* These LEDs are available to the application and are all available to the
|
||||
* application unless CONFIG_ARCH_LEDS is defined. In that case, the usage
|
||||
* by the board port is defined in include/board.h and
|
||||
* src/pic32mz_autoleds.c. The LEDs are used to encode OS-related events
|
||||
* as follows:
|
||||
*
|
||||
* SYMBOL MEANING LED STATE
|
||||
* A B C D
|
||||
* ---------------- ----------------------- --- --- --- ---
|
||||
*/
|
||||
|
||||
#define LED_STARTED 0 /* NuttX has been started ON OFF OFF OFF */
|
||||
#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF ON OFF OFF */
|
||||
#define LED_IRQSENABLED 2 /* Interrupts enabled OFF OFF ON OFF */
|
||||
#define LED_STACKCREATED 3 /* Idle stack created OFF OFF OFF ON */
|
||||
#define LED_INIRQ 4 /* In an interrupt ON ON ON ON */
|
||||
#define LED_SIGNAL 4 /* In a signal handler ON ON ON ON */
|
||||
#define LED_ASSERTION 4 /* An assertion failed ON ON ON ON */
|
||||
#define LED_PANIC 4 /* The system has crashed ON ON ON ON */
|
||||
#undef LED_IDLE /* MCU is is sleep mode ---- Not used - */
|
||||
|
||||
/* Switch definitions *******************************************************/
|
||||
|
||||
/* The chipKIT Wi-Fire has 2 user push buttons labeled BTN1 and BTN2 on the
|
||||
* white side of the board:
|
||||
*
|
||||
* PIN Button Notes
|
||||
* ----- ---- -------------------------
|
||||
* RA5 BTN1 Sensed low when closed
|
||||
* RA4 BTN2 Sensed low when closed
|
||||
*
|
||||
* The switches have external pull-down resistors. The switches are
|
||||
* pulled down and pulled up to +3.3V when pressed.
|
||||
*/
|
||||
|
||||
#define BUTTON_BTN1 0
|
||||
#define BUTTON_BTN2 1
|
||||
#define NUM_BUTTONS 2
|
||||
|
||||
#define BUTTON_BTN1_BIT (1 << BUTTON_BTN1)
|
||||
#define BUTTON_BTN2_BIT (1 << BUTTON_BTN2)
|
||||
|
||||
/* UARTS ********************************************************************/
|
||||
|
||||
#define BOARD_U4RX_PPS U4RXR_RPF2
|
||||
#define BOARD_U4TX_PPS U4TX_RPF8R
|
||||
|
||||
/* SPI **********************************************************************/
|
||||
|
||||
/* SPI1 is available on pins D5,D7,D35,D36 of the Arduino Shield connectors
|
||||
* where you would expect then. The SPI connector is configured as follows:
|
||||
*
|
||||
* Pin J7&10 Board Signal PIC32MZ
|
||||
* --- -- ------------ -------
|
||||
* D5 11 SPI1_SCK RD1
|
||||
* D36 6 SPI1_MISO RF1
|
||||
* D35 4 SPI1_MOSI RC1
|
||||
* D7 15 SPI1_SS RE9
|
||||
*
|
||||
* SPI2 is available on pins D10-D13 of the Arduino Shield connectors where
|
||||
* you would expect then. The SPI connector is configured as follows:
|
||||
*
|
||||
* Pin J7&10 Board Signal PIC32MZ
|
||||
* --- -- ------------ -------
|
||||
* D13 11 SPI2_SCK RG6
|
||||
* D12 9 SPI2_MISO RF0
|
||||
* D11 7 SPI2_MOSI RD11
|
||||
* D10 5 SPI2_SS RG9
|
||||
*
|
||||
* SPI3 is available on microSD connector as follows:
|
||||
*
|
||||
* Pin Board Signal PIC32MZ
|
||||
* ---- ------------ -------
|
||||
* SCK SPI3_SCK RB14
|
||||
* SDO SPI3_MISO RB10
|
||||
* SDI SPI3_MOSI RC4
|
||||
* CS SPI3_SS RC3
|
||||
*
|
||||
* SPI4 is connected to MRF24WG0MA WiFi module as follows:
|
||||
*
|
||||
* Pin Board Signal PIC32MZ
|
||||
* ---- ------------ -------
|
||||
* SCK SPI4_SCK RD10
|
||||
* SDO SPI4_MISO RF5
|
||||
* SDI SPI4_MOSI RG0
|
||||
* CS SPI4_SS RD9
|
||||
*
|
||||
* Chip select pin definitions are provided in
|
||||
* boards/mips/chipkit-wifire/src/chipkit-wifire.h.
|
||||
*
|
||||
* CLK (output) pins have no alternative pin configurations.
|
||||
*/
|
||||
|
||||
#define BOARD_SDI1_PPS SDI1R_RPF1
|
||||
#define BOARD_SDO1_PPS SDO1_RPC1R
|
||||
|
||||
#define BOARD_SDI2_PPS SDI2R_RPF0
|
||||
#define BOARD_SDO2_PPS SDO2_RPD11R
|
||||
|
||||
#define BOARD_SDI3_PPS SDI3R_RPB10
|
||||
#define BOARD_SDO3_PPS SDO3_RPC4R
|
||||
|
||||
#define BOARD_SDI4_PPS SDI4R_RPF5
|
||||
#define BOARD_SDO4_PPS SDO4_RPG0R
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __BOARDS_MIPS_PIC32MZ_CHIPKIT_WIFIRE_INCLUDE_BOARD_H */
|
||||
@@ -0,0 +1,92 @@
|
||||
############################################################################
|
||||
# boards/mips/pic32mz/chipkit-wifire/scripts/Make.defs
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include $(TOPDIR)/.config
|
||||
include $(TOPDIR)/tools/Config.mk
|
||||
include $(TOPDIR)/tools/pic32/Config.mk
|
||||
include $(TOPDIR)/arch/mips/src/mips32/Toolchain.defs
|
||||
|
||||
ifeq ($(CONFIG_MIPS32_TOOLCHAIN_GNU_ELF),y)
|
||||
LDSCRIPT = mips-debug.ld
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_MIPS32_TOOLCHAIN_PINGUINOW),y)
|
||||
LDSCRIPT = pinguino-debug.ld
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32),y)
|
||||
LDSCRIPT = xc32-debug.ld
|
||||
MIPS_MPROCESSOR = 32MZ2048EFG100
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW_XC32),y)
|
||||
LDSCRIPT = xc32-debug.ld
|
||||
MIPS_MPROCESSOR = 32MZ2048EFG100
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW),y)
|
||||
LDSCRIPT = c32-debug.ld
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPW_LITE),y)
|
||||
LDSCRIPT = c32-debug.ld
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_CYGWIN_WINTOOL),y)
|
||||
ARCHSCRIPT = -T "${shell cygpath -w $(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)}"
|
||||
else
|
||||
ARCHSCRIPT = -T$(BOARD_DIR)$(DELIM)scripts$(DELIM)$(LDSCRIPT)
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
|
||||
ARCHOPTIMIZATION = -g
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_DEBUG_NOOPT),y)
|
||||
ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
|
||||
endif
|
||||
|
||||
ARCHCFLAGS = -fno-builtin
|
||||
ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new
|
||||
ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
|
||||
ARCHWARNINGSXX = -Wall -Wshadow -Wundef
|
||||
|
||||
ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32),y)
|
||||
ifeq ($(CONFIG_DEBUG_FEATURES),y)
|
||||
ARCHCFLAGS += -D__DEBUG -D__MPLAB_DEBUGGER_PK3=1 -fframe-base-loclist
|
||||
endif
|
||||
endif
|
||||
|
||||
CFLAGS := $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS) -pipe
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
ifeq ($(CONFIG_MIPS32_TOOLCHAIN_MICROCHIPL_XC32),y)
|
||||
LDFLAGS = -nostdlib --defsym=__MPLAB_BUILD=1 --defsym=__MPLAB_DEBUG=1 --defsym=__DEBUG=1 --defsym=__MPLAB_DEBUGGER_PK3=1 --defsym=_min_heap_size=0 --gc-sections
|
||||
else
|
||||
LDFLAGS = # -no-isn32 --relax
|
||||
endif
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-gotoff.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
@@ -0,0 +1,325 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/scripts/c32-debug.ld
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* Memory Regions ***********************************************************/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 2048Kb of
|
||||
* program FLASH at physical address 0x1d000000 but is always accessed
|
||||
* at KSEG0 address 0x9d00:0000
|
||||
*/
|
||||
|
||||
kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K
|
||||
|
||||
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot
|
||||
* FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and
|
||||
* 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either
|
||||
* may be mapped to the lower boot alias region (0x1fc00000,
|
||||
* boolalias1) or the upper boot alias region (0x1fc20000, bootalias2).
|
||||
* This linker script assumes that Boot Flash 1 is mapped to the lower
|
||||
* alias region and Boot Flash 2 to the upper region.
|
||||
*
|
||||
* NOTE: This linker script simply writes into the lower boot alias,
|
||||
* whichever boot FLASH that may correspond to. The other boot FLASH
|
||||
* is simply ignored.
|
||||
*
|
||||
* The initial reset vector is in KSEG1, but all other accesses are in
|
||||
* KSEG0.
|
||||
*
|
||||
* REGION PHYSICAL KSEG SIZE
|
||||
* DESCRIPTION START ADDR (BYTES)
|
||||
* ------------- ---------- ------ ----------------------
|
||||
* Exceptions:*
|
||||
* Reset 0x1fc00000 KSEG1 512 512
|
||||
* TLB Refill 0x1fc00200 KSEG1 256 768
|
||||
* Cache Error 0x1fc00300 KSEG1 128 896
|
||||
* Others 0x1fc00380 KSEG1 128 1024 (1Kb)
|
||||
* Interrupt 0x1fc00400 KSEG1 128 1152
|
||||
* JTAG 0x1fc00480 KSEG1 16 1168
|
||||
* Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb)
|
||||
* Debug code 0x1fc02000 KSEG1 4096-16 12272
|
||||
* ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
|
||||
* DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb)
|
||||
*
|
||||
* Exceptions assume:
|
||||
*
|
||||
* STATUS: BEV=0/1 and EXL=0
|
||||
* CAUSE: IV=1
|
||||
* JTAG: ProbEn=0
|
||||
* And multi-vector support disabled
|
||||
*/
|
||||
|
||||
kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
|
||||
kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
|
||||
kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
|
||||
kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
|
||||
kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
|
||||
kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
|
||||
kseg0_bootmem (rx) : ORIGIN = 0x9fc004ac, LENGTH = 8192-1196
|
||||
kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
|
||||
kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128
|
||||
kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128
|
||||
|
||||
/* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb
|
||||
* of data memory at physical address 0x00000000. Since the PIC32MZ
|
||||
* has no data cache, this memory is always accessed through KSEG1.
|
||||
*
|
||||
* When used with MPLABX, we need to set aside 512 bytes of memory
|
||||
* for use by MPLABX and 128 for DSP register storage.
|
||||
*/
|
||||
|
||||
kseg1_datamem (rw!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640
|
||||
}
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips")
|
||||
OUTPUT_ARCH(pic32mz)
|
||||
ENTRY(__start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Boot FLASH sections */
|
||||
|
||||
.reset :
|
||||
{
|
||||
KEEP (*(.reset))
|
||||
} > kseg1_reset
|
||||
|
||||
/* Exception handlers. The following is assumed:
|
||||
*
|
||||
* STATUS: BEV=1 and EXL=0
|
||||
* CAUSE: IV=1
|
||||
* JTAG: ProbEn=0
|
||||
* And multi-vector support disabled
|
||||
*
|
||||
* In that configuration, the vector locations become:
|
||||
*
|
||||
* Reset, Soft Reset bfc0:0000
|
||||
* TLB Refill bfc0:0200
|
||||
* Cache Error bfc0:0300
|
||||
* All others bfc0:0380
|
||||
* Interrupt bfc0:0400
|
||||
* EJTAG Debug bfc0:0480
|
||||
*/
|
||||
|
||||
/* KSEG1 exception handler "trampolines" */
|
||||
|
||||
.gen_excpt :
|
||||
{
|
||||
KEEP (*(.gen_excpt))
|
||||
} > kseg1_genexcpt
|
||||
|
||||
.ebase_excpt :
|
||||
{
|
||||
KEEP (*(.ebase_excpt))
|
||||
} > kseg1_ebexcpt
|
||||
|
||||
.bev_excpt :
|
||||
{
|
||||
KEEP (*(.bev_excpt))
|
||||
} > kseg1_bevexcpt
|
||||
|
||||
.int_excpt :
|
||||
{
|
||||
KEEP (*(.int_excpt))
|
||||
} > kseg1_intexcpt
|
||||
|
||||
.dbg_excpt = ORIGIN(kseg1_dbgexcpt);
|
||||
|
||||
.start :
|
||||
{
|
||||
/* KSEG0 Reset startup logic */
|
||||
|
||||
*(.start)
|
||||
|
||||
/* KSEG0 exception handlers */
|
||||
|
||||
*(.nmi_handler)
|
||||
*(.bev_handler)
|
||||
*(.int_handler)
|
||||
} > kseg0_bootmem
|
||||
|
||||
.dbg_code = ORIGIN(kseg1_dbgcode);
|
||||
|
||||
.adevcfg :
|
||||
{
|
||||
KEEP (*(.adevcfg))
|
||||
} > kseg1_adevcfg
|
||||
|
||||
.devcfg :
|
||||
{
|
||||
KEEP (*(.devcfg))
|
||||
} > kseg1_devcfg
|
||||
|
||||
/* Program FLASH sections */
|
||||
|
||||
.text :
|
||||
{
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.text .text.*)
|
||||
*(.stub)
|
||||
KEEP (*(.text.*personality*))
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.gnu.warning)
|
||||
*(.mips16.fn.*)
|
||||
*(.mips16.call.*)
|
||||
|
||||
/* Read-only data is included in the text section */
|
||||
|
||||
*(.rodata .rodata.*)
|
||||
*(.rodata1)
|
||||
*(.gnu.linkonce.r.*)
|
||||
|
||||
/* Small initialized constant global and static data */
|
||||
|
||||
*(.sdata2 .sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
|
||||
/* Uninitialized constant global and static data */
|
||||
|
||||
*(.sbss2 .sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > kseg0_progmem
|
||||
|
||||
/* Initialization data begins here in progmem */
|
||||
|
||||
_data_loaddr = LOADADDR(.data);
|
||||
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
|
||||
|
||||
/* RAM functions are positioned at the beginning of RAM so that
|
||||
* they can be guaranteed to satisfy the 2Kb alignment requirement.
|
||||
*/
|
||||
|
||||
/* This causes failures if there are no RAM functions
|
||||
.ramfunc ALIGN(2K) :
|
||||
{
|
||||
_sramfunc = ABSOLUTE(.);
|
||||
*(.ramfunc .ramfunc.*)
|
||||
_eramfunc = ABSOLUTE(.);
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
_ramfunc_loadaddr = LOADADDR(.ramfunc);
|
||||
_ramfunc_sizeof = SIZEOF(.ramfunc);
|
||||
_bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ;
|
||||
_bmxdudba_address = LENGTH(kseg1_datamem) ;
|
||||
_bmxdupba_address = LENGTH(kseg1_datamem) ;
|
||||
*/
|
||||
|
||||
.data :
|
||||
{
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP (*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
|
||||
_gp = ALIGN(16) + 0x7FF0 ;
|
||||
|
||||
.got :
|
||||
{
|
||||
*(.got.plt) *(.got)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.sdata :
|
||||
{
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.lit8 :
|
||||
{
|
||||
*(.lit8)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.lit4 :
|
||||
{
|
||||
*(.lit4)
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
} >kseg1_datamem AT>kseg0_progmem
|
||||
|
||||
.sbss :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} >kseg1_datamem
|
||||
|
||||
.bss :
|
||||
{
|
||||
*(.dynbss)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(16);
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > kseg1_datamem
|
||||
|
||||
/* Stabs debugging sections */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/* DWARF debug sections */
|
||||
/* DWARF 1 */
|
||||
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
|
||||
/* GNU DWARF 1 extensions */
|
||||
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
|
||||
/* DWARF 2 */
|
||||
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
}
|
||||
@@ -0,0 +1,325 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/scripts/mips-debug.ld
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* Memory Regions ***********************************************************/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 2048Kb of
|
||||
* program FLASH at physical address 0x1d000000 but is always accessed
|
||||
* at KSEG0 address 0x9d00:0000
|
||||
*/
|
||||
|
||||
kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K
|
||||
|
||||
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot
|
||||
* FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and
|
||||
* 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either
|
||||
* may be mapped to the lower boot alias region (0x1fc00000,
|
||||
* boolalias1) or the upper boot alias region (0x1fc20000, bootalias2).
|
||||
* This linker script assumes that Boot Flash 1 is mapped to the lower
|
||||
* alias region and Boot Flash 2 to the upper region.
|
||||
*
|
||||
* NOTE: This linker script simply writes into the lower boot alias,
|
||||
* whichever boot FLASH that may correspond to. The other boot FLASH
|
||||
* is simply ignored.
|
||||
*
|
||||
* The initial reset vector is in KSEG1, but all other accesses are in
|
||||
* KSEG0.
|
||||
*
|
||||
* REGION PHYSICAL KSEG SIZE
|
||||
* DESCRIPTION START ADDR (BYTES)
|
||||
* ------------- ---------- ------ ----------------------
|
||||
* Exceptions:*
|
||||
* Reset 0x1fc00000 KSEG1 512 512
|
||||
* TLB Refill 0x1fc00200 KSEG1 256 768
|
||||
* Cache Error 0x1fc00300 KSEG1 128 896
|
||||
* Others 0x1fc00380 KSEG1 128 1024 (1Kb)
|
||||
* Interrupt 0x1fc00400 KSEG1 128 1152
|
||||
* JTAG 0x1fc00480 KSEG1 16 1168
|
||||
* Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb)
|
||||
* Debug code 0x1fc02000 KSEG1 4096-16 12272
|
||||
* ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
|
||||
* DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb)
|
||||
*
|
||||
* Exceptions assume:
|
||||
*
|
||||
* STATUS: BEV=0/1 and EXL=0
|
||||
* CAUSE: IV=1
|
||||
* JTAG: ProbEn=0
|
||||
* And multi-vector support disabled
|
||||
*/
|
||||
|
||||
kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
|
||||
kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
|
||||
kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
|
||||
kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
|
||||
kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
|
||||
kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
|
||||
kseg0_bootmem (rx) : ORIGIN = 0x9fc004ac, LENGTH = 8192-1196
|
||||
kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
|
||||
kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128
|
||||
kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128
|
||||
|
||||
/* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb
|
||||
* of data memory at physical address 0x00000000. Since the PIC32MZ
|
||||
* has no data cache, this memory is always accessed through KSEG1.
|
||||
*
|
||||
* When used with MPLABX, we need to set aside 512 bytes of memory
|
||||
* for use by MPLABX and 128 for DSP register storage.
|
||||
*/
|
||||
|
||||
kseg1_datamem (rw!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640
|
||||
}
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips")
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(__start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Boot FLASH sections */
|
||||
|
||||
.reset :
|
||||
{
|
||||
KEEP (*(.reset))
|
||||
} > kseg1_reset
|
||||
|
||||
/* Exception handlers. The following is assumed:
|
||||
*
|
||||
* STATUS: BEV=1 and EXL=0
|
||||
* CAUSE: IV=1
|
||||
* JTAG: ProbEn=0
|
||||
* And multi-vector support disabled
|
||||
*
|
||||
* In that configuration, the vector locations become:
|
||||
*
|
||||
* Reset, Soft Reset bfc0:0000
|
||||
* TLB Refill bfc0:0200
|
||||
* Cache Error bfc0:0300
|
||||
* All others bfc0:0380
|
||||
* Interrupt bfc0:0400
|
||||
* EJTAG Debug bfc0:0480
|
||||
*/
|
||||
|
||||
/* KSEG1 exception handler "trampolines" */
|
||||
|
||||
.gen_excpt :
|
||||
{
|
||||
KEEP (*(.gen_excpt))
|
||||
} > kseg1_genexcpt
|
||||
|
||||
.ebase_excpt :
|
||||
{
|
||||
KEEP (*(.ebase_excpt))
|
||||
} > kseg1_ebexcpt
|
||||
|
||||
.bev_excpt :
|
||||
{
|
||||
KEEP (*(.bev_excpt))
|
||||
} > kseg1_bevexcpt
|
||||
|
||||
.int_excpt :
|
||||
{
|
||||
KEEP (*(.int_excpt))
|
||||
} > kseg1_intexcpt
|
||||
|
||||
.dbg_excpt = ORIGIN(kseg1_dbgexcpt);
|
||||
|
||||
.start :
|
||||
{
|
||||
/* KSEG0 Reset startup logic */
|
||||
|
||||
*(.start)
|
||||
|
||||
/* KSEG0 exception handlers */
|
||||
|
||||
*(.nmi_handler)
|
||||
*(.bev_handler)
|
||||
*(.int_handler)
|
||||
} > kseg0_bootmem
|
||||
|
||||
.dbg_code = ORIGIN(kseg1_dbgcode);
|
||||
|
||||
.adevcfg :
|
||||
{
|
||||
KEEP (*(.adevcfg))
|
||||
} > kseg1_adevcfg
|
||||
|
||||
.devcfg :
|
||||
{
|
||||
KEEP (*(.devcfg))
|
||||
} > kseg1_devcfg
|
||||
|
||||
/* Program FLASH sections */
|
||||
|
||||
.text :
|
||||
{
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.text .text.*)
|
||||
*(.stub)
|
||||
KEEP (*(.text.*personality*))
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.gnu.warning)
|
||||
*(.mips16.fn.*)
|
||||
*(.mips16.call.*)
|
||||
|
||||
/* Read-only data is included in the text section */
|
||||
|
||||
*(.rodata .rodata.*)
|
||||
*(.rodata1)
|
||||
*(.gnu.linkonce.r.*)
|
||||
|
||||
/* Small initialized constant global and static data */
|
||||
|
||||
*(.sdata2 .sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
|
||||
/* Uninitialized constant global and static data */
|
||||
|
||||
*(.sbss2 .sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > kseg0_progmem
|
||||
|
||||
/* Initialization data begins here in progmem */
|
||||
|
||||
_data_loaddr = LOADADDR(.data);
|
||||
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
|
||||
|
||||
/* RAM functions are positioned at the beginning of RAM so that
|
||||
* they can be guaranteed to satisfy the 2Kb alignment requirement.
|
||||
*/
|
||||
|
||||
/* This causes failures if there are no RAM functions
|
||||
.ramfunc ALIGN(2K) :
|
||||
{
|
||||
_sramfunc = ABSOLUTE(.);
|
||||
*(.ramfunc .ramfunc.*)
|
||||
_eramfunc = ABSOLUTE(.);
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
_ramfunc_loadaddr = LOADADDR(.ramfunc);
|
||||
_ramfunc_sizeof = SIZEOF(.ramfunc);
|
||||
_bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ;
|
||||
_bmxdudba_address = LENGTH(kseg1_datamem) ;
|
||||
_bmxdupba_address = LENGTH(kseg1_datamem) ;
|
||||
*/
|
||||
|
||||
.data :
|
||||
{
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP (*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
|
||||
_gp = ALIGN(16) + 0x7FF0 ;
|
||||
|
||||
.got :
|
||||
{
|
||||
*(.got.plt) *(.got)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.sdata :
|
||||
{
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.lit8 :
|
||||
{
|
||||
*(.lit8)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.lit4 :
|
||||
{
|
||||
*(.lit4)
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
} >kseg1_datamem AT>kseg0_progmem
|
||||
|
||||
.sbss :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} >kseg1_datamem
|
||||
|
||||
.bss :
|
||||
{
|
||||
*(.dynbss)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(16);
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > kseg1_datamem
|
||||
|
||||
/* Stabs debugging sections */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/* DWARF debug sections */
|
||||
/* DWARF 1 */
|
||||
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
|
||||
/* GNU DWARF 1 extensions */
|
||||
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
|
||||
/* DWARF 2 */
|
||||
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
}
|
||||
@@ -0,0 +1,325 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/scripts/pinguino-debug.ld
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* Memory Regions ***********************************************************/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 2048Kb of
|
||||
* program FLASH at physical address 0x1d000000 but is always accessed
|
||||
* at KSEG0 address 0x9d00:0000
|
||||
*/
|
||||
|
||||
kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K
|
||||
|
||||
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot
|
||||
* FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and
|
||||
* 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either
|
||||
* may be mapped to the lower boot alias region (0x1fc00000,
|
||||
* boolalias1) or the upper boot alias region (0x1fc20000, bootalias2).
|
||||
* This linker script assumes that Boot Flash 1 is mapped to the lower
|
||||
* alias region and Boot Flash 2 to the upper region.
|
||||
*
|
||||
* NOTE: This linker script simply writes into the lower boot alias,
|
||||
* whichever boot FLASH that may correspond to. The other boot FLASH
|
||||
* is simply ignored.
|
||||
*
|
||||
* The initial reset vector is in KSEG1, but all other accesses are in
|
||||
* KSEG0.
|
||||
*
|
||||
* REGION PHYSICAL KSEG SIZE
|
||||
* DESCRIPTION START ADDR (BYTES)
|
||||
* ------------- ---------- ------ ----------------------
|
||||
* Exceptions:*
|
||||
* Reset 0x1fc00000 KSEG1 512 512
|
||||
* TLB Refill 0x1fc00200 KSEG1 256 768
|
||||
* Cache Error 0x1fc00300 KSEG1 128 896
|
||||
* Others 0x1fc00380 KSEG1 128 1024 (1Kb)
|
||||
* Interrupt 0x1fc00400 KSEG1 128 1152
|
||||
* JTAG 0x1fc00480 KSEG1 16 1168
|
||||
* Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb)
|
||||
* Debug code 0x1fc02000 KSEG1 4096-16 12272
|
||||
* ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
|
||||
* DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb)
|
||||
*
|
||||
* Exceptions assume:
|
||||
*
|
||||
* STATUS: BEV=0/1 and EXL=0
|
||||
* CAUSE: IV=1
|
||||
* JTAG: ProbEn=0
|
||||
* And multi-vector support disabled
|
||||
*/
|
||||
|
||||
kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
|
||||
kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
|
||||
kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
|
||||
kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
|
||||
kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
|
||||
kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
|
||||
kseg0_bootmem (rx) : ORIGIN = 0x9fc004ac, LENGTH = 8192-1196
|
||||
kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
|
||||
kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128
|
||||
kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128
|
||||
|
||||
/* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb
|
||||
* of data memory at physical address 0x00000000. Since the PIC32MZ
|
||||
* has no data cache, this memory is always accessed through KSEG1.
|
||||
*
|
||||
* When used with MPLABX, we need to set aside 512 bytes of memory
|
||||
* for use by MPLABX and 128 for DSP register storage.
|
||||
*/
|
||||
|
||||
kseg1_datamem (rw!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640
|
||||
}
|
||||
|
||||
OUTPUT_FORMAT("elf32-littlemips")
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(__start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Boot FLASH sections */
|
||||
|
||||
.reset :
|
||||
{
|
||||
KEEP (*(.reset))
|
||||
} > kseg1_reset
|
||||
|
||||
/* Exception handlers. The following is assumed:
|
||||
*
|
||||
* STATUS: BEV=1 and EXL=0
|
||||
* CAUSE: IV=1
|
||||
* JTAG: ProbEn=0
|
||||
* And multi-vector support disabled
|
||||
*
|
||||
* In that configuration, the vector locations become:
|
||||
*
|
||||
* Reset, Soft Reset bfc0:0000
|
||||
* TLB Refill bfc0:0200
|
||||
* Cache Error bfc0:0300
|
||||
* All others bfc0:0380
|
||||
* Interrupt bfc0:0400
|
||||
* EJTAG Debug bfc0:0480
|
||||
*/
|
||||
|
||||
/* KSEG1 exception handler "trampolines" */
|
||||
|
||||
.gen_excpt :
|
||||
{
|
||||
KEEP (*(.gen_excpt))
|
||||
} > kseg1_genexcpt
|
||||
|
||||
.ebase_excpt :
|
||||
{
|
||||
KEEP (*(.ebase_excpt))
|
||||
} > kseg1_ebexcpt
|
||||
|
||||
.bev_excpt :
|
||||
{
|
||||
KEEP (*(.bev_excpt))
|
||||
} > kseg1_bevexcpt
|
||||
|
||||
.int_excpt :
|
||||
{
|
||||
KEEP (*(.int_excpt))
|
||||
} > kseg1_intexcpt
|
||||
|
||||
.dbg_excpt = ORIGIN(kseg1_dbgexcpt);
|
||||
|
||||
.start :
|
||||
{
|
||||
/* KSEG0 Reset startup logic */
|
||||
|
||||
*(.start)
|
||||
|
||||
/* KSEG0 exception handlers */
|
||||
|
||||
*(.nmi_handler)
|
||||
*(.bev_handler)
|
||||
*(.int_handler)
|
||||
} > kseg0_bootmem
|
||||
|
||||
.dbg_code = ORIGIN(kseg1_dbgcode);
|
||||
|
||||
.adevcfg :
|
||||
{
|
||||
KEEP (*(.adevcfg))
|
||||
} > kseg1_adevcfg
|
||||
|
||||
.devcfg :
|
||||
{
|
||||
KEEP (*(.devcfg))
|
||||
} > kseg1_devcfg
|
||||
|
||||
/* Program FLASH sections */
|
||||
|
||||
.text :
|
||||
{
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.text .text.*)
|
||||
*(.stub)
|
||||
KEEP (*(.text.*personality*))
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.gnu.warning)
|
||||
*(.mips16.fn.*)
|
||||
*(.mips16.call.*)
|
||||
|
||||
/* Read-only data is included in the text section */
|
||||
|
||||
*(.rodata .rodata.*)
|
||||
*(.rodata1)
|
||||
*(.gnu.linkonce.r.*)
|
||||
|
||||
/* Small initialized constant global and static data */
|
||||
|
||||
*(.sdata2 .sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
|
||||
/* Uninitialized constant global and static data */
|
||||
|
||||
*(.sbss2 .sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > kseg0_progmem
|
||||
|
||||
/* Initialization data begins here in progmem */
|
||||
|
||||
_data_loaddr = LOADADDR(.data);
|
||||
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
|
||||
|
||||
/* RAM functions are positioned at the beginning of RAM so that
|
||||
* they can be guaranteed to satisfy the 2Kb alignment requirement.
|
||||
*/
|
||||
|
||||
/* This causes failures if there are no RAM functions
|
||||
.ramfunc ALIGN(2K) :
|
||||
{
|
||||
_sramfunc = ABSOLUTE(.);
|
||||
*(.ramfunc .ramfunc.*)
|
||||
_eramfunc = ABSOLUTE(.);
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
_ramfunc_loadaddr = LOADADDR(.ramfunc);
|
||||
_ramfunc_sizeof = SIZEOF(.ramfunc);
|
||||
_bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ;
|
||||
_bmxdudba_address = LENGTH(kseg1_datamem) ;
|
||||
_bmxdupba_address = LENGTH(kseg1_datamem) ;
|
||||
*/
|
||||
|
||||
.data :
|
||||
{
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP (*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
|
||||
_gp = ALIGN(16) + 0x7FF0 ;
|
||||
|
||||
.got :
|
||||
{
|
||||
*(.got.plt) *(.got)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.sdata :
|
||||
{
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.lit8 :
|
||||
{
|
||||
*(.lit8)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.lit4 :
|
||||
{
|
||||
*(.lit4)
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
} >kseg1_datamem AT>kseg0_progmem
|
||||
|
||||
.sbss :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} >kseg1_datamem
|
||||
|
||||
.bss :
|
||||
{
|
||||
*(.dynbss)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(16);
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > kseg1_datamem
|
||||
|
||||
/* Stabs debugging sections */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/* DWARF debug sections */
|
||||
/* DWARF 1 */
|
||||
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
|
||||
/* GNU DWARF 1 extensions */
|
||||
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
|
||||
/* DWARF 2 */
|
||||
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
}
|
||||
@@ -0,0 +1,325 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/scripts/sourcery-debug.ld
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* Memory Regions ***********************************************************/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 2048Kb of
|
||||
* program FLASH at physical address 0x1d000000 but is always accessed
|
||||
* at KSEG0 address 0x9d00:0000
|
||||
*/
|
||||
|
||||
kseg0_progmem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K
|
||||
|
||||
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot
|
||||
* FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and
|
||||
* 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either
|
||||
* may be mapped to the lower boot alias region (0x1fc00000,
|
||||
* boolalias1) or the upper boot alias region (0x1fc20000, bootalias2).
|
||||
* This linker script assumes that Boot Flash 1 is mapped to the lower
|
||||
* alias region and Boot Flash 2 to the upper region.
|
||||
*
|
||||
* NOTE: This linker script simply writes into the lower boot alias,
|
||||
* whichever boot FLASH that may correspond to. The other boot FLASH
|
||||
* is simply ignored.
|
||||
*
|
||||
* The initial reset vector is in KSEG1, but all other accesses are in
|
||||
* KSEG0.
|
||||
*
|
||||
* REGION PHYSICAL KSEG SIZE
|
||||
* DESCRIPTION START ADDR (BYTES)
|
||||
* ------------- ---------- ------ ----------------------
|
||||
* Exceptions:*
|
||||
* Reset 0x1fc00000 KSEG1 512 512
|
||||
* TLB Refill 0x1fc00200 KSEG1 256 768
|
||||
* Cache Error 0x1fc00300 KSEG1 128 896
|
||||
* Others 0x1fc00380 KSEG1 128 1024 (1Kb)
|
||||
* Interrupt 0x1fc00400 KSEG1 128 1152
|
||||
* JTAG 0x1fc00480 KSEG1 16 1168
|
||||
* Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb)
|
||||
* Debug code 0x1fc02000 KSEG1 4096-16 12272
|
||||
* ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
|
||||
* DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb)
|
||||
*
|
||||
* Exceptions assume:
|
||||
*
|
||||
* STATUS: BEV=0/1 and EXL=0
|
||||
* CAUSE: IV=1
|
||||
* JTAG: ProbEn=0
|
||||
* And multi-vector support disabled
|
||||
*/
|
||||
|
||||
kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
|
||||
kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
|
||||
kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
|
||||
kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
|
||||
kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
|
||||
kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
|
||||
kseg0_bootmem (rx) : ORIGIN = 0x9fc004ac, LENGTH = 8192-1196
|
||||
kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
|
||||
kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128
|
||||
kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128
|
||||
|
||||
/* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb
|
||||
* of data memory at physical address 0x00000000. Since the PIC32MZ
|
||||
* has no data cache, this memory is always accessed through KSEG1.
|
||||
*
|
||||
* When used with MPLABX, we need to set aside 512 bytes of memory
|
||||
* for use by MPLABX and 128 for DSP register storage.
|
||||
*/
|
||||
|
||||
kseg1_datamem (rw!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640
|
||||
}
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips")
|
||||
OUTPUT_ARCH(mips)
|
||||
ENTRY(__start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Boot FLASH sections */
|
||||
|
||||
.reset :
|
||||
{
|
||||
KEEP (*(.reset))
|
||||
} > kseg1_reset
|
||||
|
||||
/* Exception handlers. The following is assumed:
|
||||
*
|
||||
* STATUS: BEV=1 and EXL=0
|
||||
* CAUSE: IV=1
|
||||
* JTAG: ProbEn=0
|
||||
* And multi-vector support disabled
|
||||
*
|
||||
* In that configuration, the vector locations become:
|
||||
*
|
||||
* Reset, Soft Reset bfc0:0000
|
||||
* TLB Refill bfc0:0200
|
||||
* Cache Error bfc0:0300
|
||||
* All others bfc0:0380
|
||||
* Interrupt bfc0:0400
|
||||
* EJTAG Debug bfc0:0480
|
||||
*/
|
||||
|
||||
/* KSEG1 exception handler "trampolines" */
|
||||
|
||||
.gen_excpt :
|
||||
{
|
||||
KEEP (*(.gen_excpt))
|
||||
} > kseg1_genexcpt
|
||||
|
||||
.ebase_excpt :
|
||||
{
|
||||
KEEP (*(.ebase_excpt))
|
||||
} > kseg1_ebexcpt
|
||||
|
||||
.bev_excpt :
|
||||
{
|
||||
KEEP (*(.bev_excpt))
|
||||
} > kseg1_bevexcpt
|
||||
|
||||
.int_excpt :
|
||||
{
|
||||
KEEP (*(.int_excpt))
|
||||
} > kseg1_intexcpt
|
||||
|
||||
.dbg_excpt = ORIGIN(kseg1_dbgexcpt);
|
||||
|
||||
.start :
|
||||
{
|
||||
/* KSEG0 Reset startup logic */
|
||||
|
||||
*(.start)
|
||||
|
||||
/* KSEG0 exception handlers */
|
||||
|
||||
*(.nmi_handler)
|
||||
*(.bev_handler)
|
||||
*(.int_handler)
|
||||
} > kseg0_bootmem
|
||||
|
||||
.dbg_code = ORIGIN(kseg1_dbgcode);
|
||||
|
||||
.adevcfg :
|
||||
{
|
||||
KEEP (*(.adevcfg))
|
||||
} > kseg1_adevcfg
|
||||
|
||||
.devcfg :
|
||||
{
|
||||
KEEP (*(.devcfg))
|
||||
} > kseg1_devcfg
|
||||
|
||||
/* Program FLASH sections */
|
||||
|
||||
.text :
|
||||
{
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.text .text.*)
|
||||
*(.stub)
|
||||
KEEP (*(.text.*personality*))
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.gnu.warning)
|
||||
*(.mips16.fn.*)
|
||||
*(.mips16.call.*)
|
||||
|
||||
/* Read-only data is included in the text section */
|
||||
|
||||
*(.rodata .rodata.*)
|
||||
*(.rodata1)
|
||||
*(.gnu.linkonce.r.*)
|
||||
|
||||
/* Small initialized constant global and static data */
|
||||
|
||||
*(.sdata2 .sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
|
||||
/* Uninitialized constant global and static data */
|
||||
|
||||
*(.sbss2 .sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > kseg0_progmem
|
||||
|
||||
/* Initialization data begins here in progmem */
|
||||
|
||||
_data_loaddr = LOADADDR(.data);
|
||||
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
|
||||
|
||||
/* RAM functions are positioned at the beginning of RAM so that
|
||||
* they can be guaranteed to satisfy the 2Kb alignment requirement.
|
||||
*/
|
||||
|
||||
/* This causes failures if there are no RAM functions
|
||||
.ramfunc ALIGN(2K) :
|
||||
{
|
||||
_sramfunc = ABSOLUTE(.);
|
||||
*(.ramfunc .ramfunc.*)
|
||||
_eramfunc = ABSOLUTE(.);
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
_ramfunc_loadaddr = LOADADDR(.ramfunc);
|
||||
_ramfunc_sizeof = SIZEOF(.ramfunc);
|
||||
_bmxdkpba_address = _sramfunc - ORIGIN(kseg1_datamem) ;
|
||||
_bmxdudba_address = LENGTH(kseg1_datamem) ;
|
||||
_bmxdupba_address = LENGTH(kseg1_datamem) ;
|
||||
*/
|
||||
|
||||
.data :
|
||||
{
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP (*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
|
||||
_gp = ALIGN(16) + 0x7FF0 ;
|
||||
|
||||
.got :
|
||||
{
|
||||
*(.got.plt) *(.got)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.sdata :
|
||||
{
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.lit8 :
|
||||
{
|
||||
*(.lit8)
|
||||
} > kseg1_datamem AT > kseg0_progmem
|
||||
|
||||
.lit4 :
|
||||
{
|
||||
*(.lit4)
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
} >kseg1_datamem AT>kseg0_progmem
|
||||
|
||||
.sbss :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} >kseg1_datamem
|
||||
|
||||
.bss :
|
||||
{
|
||||
*(.dynbss)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(16);
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > kseg1_datamem
|
||||
|
||||
/* Stabs debugging sections */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/* DWARF debug sections */
|
||||
/* DWARF 1 */
|
||||
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
|
||||
/* GNU DWARF 1 extensions */
|
||||
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
|
||||
/* DWARF 2 */
|
||||
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
}
|
||||
@@ -0,0 +1,325 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/scripts/mips-debug.ld
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* Memory Regions ***********************************************************/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 2048Kb of
|
||||
* program FLASH at physical address 0x1d000000 but is always accessed
|
||||
* at KSEG0 address 0x9d00:0000
|
||||
*/
|
||||
|
||||
kseg0_program_mem (rx) : ORIGIN = 0x9d000000, LENGTH = 2048K
|
||||
|
||||
/* The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have 160Kb of boot
|
||||
* FLASH: 80Kb at physical address 0x1fc4000 (Boot Flash 1, boot1) and
|
||||
* 80Kb at physical address 0x1fc60000 (Boot Flash 2, boot2). Either
|
||||
* may be mapped to the lower boot alias region (0x1fc00000,
|
||||
* boolalias1) or the upper boot alias region (0x1fc20000, bootalias2).
|
||||
* This linker script assumes that Boot Flash 1 is mapped to the lower
|
||||
* alias region and Boot Flash 2 to the upper region.
|
||||
*
|
||||
* NOTE: This linker script simply writes into the lower boot alias,
|
||||
* whichever boot FLASH that may correspond to. The other boot FLASH
|
||||
* is simply ignored.
|
||||
*
|
||||
* The initial reset vector is in KSEG1, but all other accesses are in
|
||||
* KSEG0.
|
||||
*
|
||||
* REGION PHYSICAL KSEG SIZE
|
||||
* DESCRIPTION START ADDR (BYTES)
|
||||
* ------------- ---------- ------ ----------------------
|
||||
* Exceptions:*
|
||||
* Reset 0x1fc00000 KSEG1 512 512
|
||||
* TLB Refill 0x1fc00200 KSEG1 256 768
|
||||
* Cache Error 0x1fc00300 KSEG1 128 896
|
||||
* Others 0x1fc00380 KSEG1 128 1024 (1Kb)
|
||||
* Interrupt 0x1fc00400 KSEG1 128 1152
|
||||
* JTAG 0x1fc00480 KSEG1 16 1168
|
||||
* Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb)
|
||||
* Debug code 0x1fc02000 KSEG1 4096-16 12272
|
||||
* ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
|
||||
* DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb)
|
||||
*
|
||||
* Exceptions assume:
|
||||
*
|
||||
* STATUS: BEV=0/1 and EXL=0
|
||||
* CAUSE: IV=1
|
||||
* JTAG: ProbEn=0
|
||||
* And multi-vector support disabled
|
||||
*/
|
||||
|
||||
kseg1_reset (rx) : ORIGIN = 0xbfc00000, LENGTH = 384
|
||||
kseg1_genexcpt (rx) : ORIGIN = 0xbfc00180, LENGTH = 128
|
||||
kseg1_ebexcpt (rx) : ORIGIN = 0xbfc00200, LENGTH = 128
|
||||
kseg1_bevexcpt (rx) : ORIGIN = 0xbfc00380, LENGTH = 128
|
||||
kseg1_intexcpt (rx) : ORIGIN = 0xbfc00400, LENGTH = 128
|
||||
kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
|
||||
kseg0_bootmem (rx) : ORIGIN = 0x9fc004ac, LENGTH = 8192-1196
|
||||
kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
|
||||
kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128
|
||||
kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128
|
||||
|
||||
/* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb
|
||||
* of data memory at physical address 0x00000000. Since the PIC32MZ
|
||||
* has no data cache, this memory is always accessed through KSEG1.
|
||||
*
|
||||
* When used with MPLABX, we need to set aside 512 bytes of memory
|
||||
* for use by MPLABX and 128 for DSP register storage.
|
||||
*/
|
||||
|
||||
kseg1_data_mem (rw!x) : ORIGIN = 0xa0000200, LENGTH = 512K - 640
|
||||
}
|
||||
|
||||
OUTPUT_FORMAT("elf32-tradlittlemips")
|
||||
OUTPUT_ARCH(pic32mx)
|
||||
ENTRY(__start)
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* Boot FLASH sections */
|
||||
|
||||
.reset :
|
||||
{
|
||||
KEEP (*(.reset))
|
||||
} > kseg1_reset
|
||||
|
||||
/* Exception handlers. The following is assumed:
|
||||
*
|
||||
* STATUS: BEV=1 and EXL=0
|
||||
* CAUSE: IV=1
|
||||
* JTAG: ProbEn=0
|
||||
* And multi-vector support disabled
|
||||
*
|
||||
* In that configuration, the vector locations become:
|
||||
*
|
||||
* Reset, Soft Reset bfc0:0000
|
||||
* TLB Refill bfc0:0200
|
||||
* Cache Error bfc0:0300
|
||||
* All others bfc0:0380
|
||||
* Interrupt bfc0:0400
|
||||
* EJTAG Debug bfc0:0480
|
||||
*/
|
||||
|
||||
/* KSEG1 exception handler "trampolines" */
|
||||
|
||||
.gen_excpt :
|
||||
{
|
||||
KEEP (*(.gen_excpt))
|
||||
} > kseg1_genexcpt
|
||||
|
||||
.ebase_excpt :
|
||||
{
|
||||
KEEP (*(.ebase_excpt))
|
||||
} > kseg1_ebexcpt
|
||||
|
||||
.bev_excpt :
|
||||
{
|
||||
KEEP (*(.bev_excpt))
|
||||
} > kseg1_bevexcpt
|
||||
|
||||
.int_excpt :
|
||||
{
|
||||
KEEP (*(.int_excpt))
|
||||
} > kseg1_intexcpt
|
||||
|
||||
.dbg_excpt = ORIGIN(kseg1_dbgexcpt);
|
||||
|
||||
.start :
|
||||
{
|
||||
/* KSEG0 Reset startup logic */
|
||||
|
||||
*(.start)
|
||||
|
||||
/* KSEG0 exception handlers */
|
||||
|
||||
*(.nmi_handler)
|
||||
*(.bev_handler)
|
||||
*(.int_handler)
|
||||
} > kseg0_bootmem
|
||||
|
||||
.dbg_code = ORIGIN(kseg1_dbgcode);
|
||||
|
||||
.adevcfg :
|
||||
{
|
||||
KEEP (*(.adevcfg))
|
||||
} > kseg1_adevcfg
|
||||
|
||||
.devcfg :
|
||||
{
|
||||
KEEP (*(.devcfg))
|
||||
} > kseg1_devcfg
|
||||
|
||||
/* Program FLASH sections */
|
||||
|
||||
.text :
|
||||
{
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.text .text.*)
|
||||
*(.stub)
|
||||
KEEP (*(.text.*personality*))
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.gnu.warning)
|
||||
*(.mips16.fn.*)
|
||||
*(.mips16.call.*)
|
||||
|
||||
/* Read-only data is included in the text section */
|
||||
|
||||
*(.rodata .rodata.*)
|
||||
*(.rodata1)
|
||||
*(.gnu.linkonce.r.*)
|
||||
|
||||
/* Small initialized constant global and static data */
|
||||
|
||||
*(.sdata2 .sdata2.*)
|
||||
*(.gnu.linkonce.s2.*)
|
||||
|
||||
/* Uninitialized constant global and static data */
|
||||
|
||||
*(.sbss2 .sbss2.*)
|
||||
*(.gnu.linkonce.sb2.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > kseg0_program_mem
|
||||
|
||||
/* Initialization data begins here in progmem */
|
||||
|
||||
_data_loaddr = LOADADDR(.data);
|
||||
|
||||
.eh_frame_hdr : { *(.eh_frame_hdr) *(.eh_frame_entry .eh_frame_entry.*) }
|
||||
.eh_frame : ONLY_IF_RO { KEEP (*(.eh_frame)) }
|
||||
|
||||
/* RAM functions are positioned at the beginning of RAM so that
|
||||
* they can be guaranteed to satisfy the 2Kb alignment requirement.
|
||||
*/
|
||||
|
||||
/* This causes failures if there are no RAM functions
|
||||
.ramfunc ALIGN(2K) :
|
||||
{
|
||||
_sramfunc = ABSOLUTE(.);
|
||||
*(.ramfunc .ramfunc.*)
|
||||
_eramfunc = ABSOLUTE(.);
|
||||
} > kseg1_data_mem AT > kseg0_program_mem
|
||||
|
||||
_ramfunc_loadaddr = LOADADDR(.ramfunc);
|
||||
_ramfunc_sizeof = SIZEOF(.ramfunc);
|
||||
_bmxdkpba_address = _sramfunc - ORIGIN(kseg1_data_mem) ;
|
||||
_bmxdudba_address = LENGTH(kseg1_data_mem) ;
|
||||
_bmxdupba_address = LENGTH(kseg1_data_mem) ;
|
||||
*/
|
||||
|
||||
.data :
|
||||
{
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
KEEP (*(.gnu.linkonce.d.*personality*))
|
||||
*(.data1)
|
||||
} > kseg1_data_mem AT > kseg0_program_mem
|
||||
|
||||
.eh_frame : ONLY_IF_RW { KEEP (*(.eh_frame)) }
|
||||
_gp = ALIGN(16) + 0x7FF0 ;
|
||||
|
||||
.got :
|
||||
{
|
||||
*(.got.plt) *(.got)
|
||||
} > kseg1_data_mem AT > kseg0_program_mem
|
||||
|
||||
.sdata :
|
||||
{
|
||||
*(.sdata .sdata.* .gnu.linkonce.s.*)
|
||||
} > kseg1_data_mem AT > kseg0_program_mem
|
||||
|
||||
.lit8 :
|
||||
{
|
||||
*(.lit8)
|
||||
} > kseg1_data_mem AT > kseg0_program_mem
|
||||
|
||||
.lit4 :
|
||||
{
|
||||
*(.lit4)
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
} >kseg1_data_mem AT>kseg0_program_mem
|
||||
|
||||
.sbss :
|
||||
{
|
||||
. = ALIGN(16);
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.dynsbss)
|
||||
*(.sbss .sbss.* .gnu.linkonce.sb.*)
|
||||
*(.scommon)
|
||||
} >kseg1_data_mem
|
||||
|
||||
.bss :
|
||||
{
|
||||
*(.dynbss)
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(16);
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > kseg1_data_mem
|
||||
|
||||
/* Stabs debugging sections */
|
||||
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
|
||||
/* DWARF debug sections */
|
||||
/* DWARF 1 */
|
||||
|
||||
.debug 0 : { *(.debug) }
|
||||
.line 0 : { *(.line) }
|
||||
|
||||
/* GNU DWARF 1 extensions */
|
||||
|
||||
.debug_srcinfo 0 : { *(.debug_srcinfo) }
|
||||
.debug_sfnames 0 : { *(.debug_sfnames) }
|
||||
|
||||
/* DWARF 1.1 and DWARF 2 */
|
||||
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
|
||||
/* DWARF 2 */
|
||||
|
||||
.debug_info 0 : { *(.debug_info .gnu.linkonce.wi.*) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_frame 0 : { *(.debug_frame) }
|
||||
.debug_str 0 : { *(.debug_str) }
|
||||
.debug_loc 0 : { *(.debug_loc) }
|
||||
.debug_macinfo 0 : { *(.debug_macinfo) }
|
||||
|
||||
/* SGI/MIPS DWARF 2 extensions */
|
||||
|
||||
.debug_weaknames 0 : { *(.debug_weaknames) }
|
||||
.debug_funcnames 0 : { *(.debug_funcnames) }
|
||||
.debug_typenames 0 : { *(.debug_typenames) }
|
||||
.debug_varnames 0 : { *(.debug_varnames) }
|
||||
|
||||
/DISCARD/ : { *(.note.GNU-stack) }
|
||||
}
|
||||
@@ -0,0 +1,37 @@
|
||||
############################################################################
|
||||
# boards/mips/pic32mz/chipkit-wifire/src/Makefile
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
include $(TOPDIR)/Make.defs
|
||||
|
||||
CSRCS = pic32mz_boot.c pic32mz_bringup.c pic32mz_userleds.c pic32mz_spi.c
|
||||
|
||||
ifeq ($(CONFIG_LIB_BOARDCTL),y)
|
||||
CSRCS += pic32mz_appinit.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_LEDS),y)
|
||||
CSRCS += pic32mz_autoleds.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_BUTTONS),y)
|
||||
CSRCS += pic32mz_buttons.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/boards/Board.mk
|
||||
@@ -0,0 +1,183 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/src/chipkit-wifire.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __BOARDS_MIPS_PIC32MZ_CHIPKIT_WIFIRE_SRC_CHIPKIT_WIFIRE_H
|
||||
#define __BOARDS_MIPS_PIC32MZ_CHIPKIT_WIFIRE_SRC_CHIPKIT_WIFIRE_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
/* LEDs *********************************************************************/
|
||||
|
||||
/* There are four LEDs on the top side of the board:
|
||||
*
|
||||
* LED LD1 - RG6
|
||||
* LED LD2 - RD4
|
||||
* LED LD3 - RB11
|
||||
* LED LD4 - RG15
|
||||
*
|
||||
* A high output value illuminates the LEDs.
|
||||
*/
|
||||
|
||||
#define GPIO_LED_LD1 (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTG | GPIO_PIN6)
|
||||
#define GPIO_LED_LD2 (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTD | GPIO_PIN4)
|
||||
#define GPIO_LED_LD3 (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTB | GPIO_PIN11)
|
||||
#define GPIO_LED_LD4 (GPIO_OUTPUT | GPIO_VALUE_ZERO | GPIO_PORTG | GPIO_PIN15)
|
||||
|
||||
/* The chipKIT Wi-Fire has 2 user push buttons labeled BTN1 and BTN2 on the
|
||||
* white side of the board:
|
||||
*
|
||||
* PIN Button Notes
|
||||
* ----- ---- -------------------------
|
||||
* RA5 BTN1 Sensed low when closed
|
||||
* RA4 BTN2 Sensed low when closed
|
||||
*
|
||||
* The switches have external pull-down resistors. The switches are
|
||||
* pulled down and pulled up to +3.3V when pressed.
|
||||
*/
|
||||
|
||||
#define GPIO_BTN1 (GPIO_INPUT | GPIO_INTERRUPT | GPIO_PORTA | GPIO_PIN5)
|
||||
#define GPIO_BTN2 (GPIO_INPUT | GPIO_INTERRUPT | GPIO_PORTA | GPIO_PIN4)
|
||||
|
||||
/* SPI Chip Selects
|
||||
*
|
||||
* SPI1 is available on pins D5,D7,D35,D36 of the Arduino Shield connectors
|
||||
* where you would expect then. The SPI connector is configured as follows:
|
||||
*
|
||||
* Pin J7&10 Board Signal PIC32MZ
|
||||
* --- -- ------------ -------
|
||||
* D5 11 SPI1_SCK RD1
|
||||
* D36 6 SPI1_MISO RF1
|
||||
* D35 4 SPI1_MOSI RC1
|
||||
* D7 15 SPI1_SS RE9
|
||||
*/
|
||||
|
||||
#define GPIO_ARD_SPI1_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTE | GPIO_PIN9)
|
||||
|
||||
/* SPI2 is available on pins D10-D13 of the Arduino Shield connectors where
|
||||
* you would expect then. The SPI connector is configured as follows:
|
||||
*
|
||||
* Pin J7&10 Board Signal PIC32MZ
|
||||
* --- -- ------------ -------
|
||||
* D13 11 SPI2_SCK RG6
|
||||
* D12 9 SPI2_MISO RF0
|
||||
* D11 7 SPI2_MOSI RD11
|
||||
* D10 5 SPI2_SS RG9
|
||||
*/
|
||||
|
||||
#define GPIO_ARD_SPI2_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTG | GPIO_PIN9)
|
||||
|
||||
/* SPI3 is available on microSD connector as follows:
|
||||
*
|
||||
* Pin Board Signal PIC32MZ
|
||||
* ---- ------------ -------
|
||||
* SCK SPI3_SCK RB14
|
||||
* SDO SPI3_MISO RB10
|
||||
* SDI SPI3_MOSI RC4
|
||||
* CS SPI3_SS RC3
|
||||
*/
|
||||
|
||||
#define GPIO_SD_SPI3_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTC | GPIO_PIN3)
|
||||
|
||||
/* SPI4 is connected to MRF24WG0MA WiFi module as follows:
|
||||
*
|
||||
* Pin Board Signal PIC32MZ
|
||||
* ---- ------------ -------
|
||||
* SCK SPI4_SCK RD10
|
||||
* SDO SPI4_MISO RF5
|
||||
* SDI SPI4_MOSI RG0
|
||||
* CS SPI4_SS RD9
|
||||
*/
|
||||
|
||||
#define GPIO_WIFI_SPI4_CS (GPIO_OUTPUT | GPIO_VALUE_ONE | GPIO_PORTD | GPIO_PIN9)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_spidev_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select GPIO pins for the PCB Logic board.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI
|
||||
void weak_function pic32mz_spidev_initialize(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_led_initialize
|
||||
*
|
||||
* Description:
|
||||
* Configure on-board LEDs if LED support has been selected.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
void pic32mz_led_initialize(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_bringup
|
||||
*
|
||||
* Description:
|
||||
* Bring up board features
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int pic32mz_bringup(void);
|
||||
|
||||
#undef EXTERN
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __BOARDS_MIPS_PIC32MZ_CHIPKIT_WIFIRE_SRC_CHIPKIT_WIFIRE_H */
|
||||
@@ -0,0 +1,75 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/src/pic32mz_appinit.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include "chipkit-wifire.h"
|
||||
|
||||
#ifdef CONFIG_LIB_BOARDCTL
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_app_initialize
|
||||
*
|
||||
* Description:
|
||||
* Perform application specific initialization. This function is never
|
||||
* called directly from application code, but only indirectly via the
|
||||
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
|
||||
*
|
||||
* Input Parameters:
|
||||
* arg - The boardctl() argument is passed to the board_app_initialize()
|
||||
* implementation without modification. The argument has no
|
||||
* meaning to NuttX; the meaning of the argument is a contract
|
||||
* between the board-specific initialization logic and the
|
||||
* matching application logic. The value could be such things as a
|
||||
* mode enumeration value, a set of DIP switch switch settings, a
|
||||
* pointer to configuration data read from a file or serial FLASH,
|
||||
* or whatever you would like to do with it. Every implementation
|
||||
* should accept zero/NULL as a default configuration.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; a negated errno value is returned on
|
||||
* any failure to indicate the nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
/* If CONFIG_BOARD_LATE_INITIALIZE is selected then board initialization
|
||||
* was already performed in board_late_initialize.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_BOARD_LATE_INITIALIZE
|
||||
return pic32mz_bringup();
|
||||
#else
|
||||
return OK;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* CONFIG_LIB_BOARDCTL */
|
||||
@@ -0,0 +1,198 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/src/pic32mz_autoleds.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "mips_arch.h"
|
||||
#include "mips_internal.h"
|
||||
|
||||
#include "pic32mz_gpio.h"
|
||||
#include "chipkit-wifire.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* There are four LEDs on the top side of the board:
|
||||
*
|
||||
* LED LD1 - RG6
|
||||
* LED LD2 - RD4
|
||||
* LED LD3 - RB11
|
||||
* LED LD4 - RG15
|
||||
*
|
||||
* A high output value illuminates the LEDs.
|
||||
*
|
||||
* These LEDs are available to the application and are all available to the
|
||||
* application unless CONFIG_ARCH_LEDS is defined. In that case, the usage
|
||||
* by the board port is defined in include/board.h and
|
||||
* src/pic32mz_autoleds.c. The LEDs are used to encode OS-related events
|
||||
* as follows:
|
||||
* SYMBOL MEANING LED STATE
|
||||
* A B C D
|
||||
* ---------------- ----------------------- --- --- --- ---
|
||||
* LED_STARTED NuttX has been started ON OFF OFF OFF
|
||||
* LED_HEAPALLOCATE Heap has been allocated OFF ON OFF OFF
|
||||
* LED_IRQSENABLED Interrupts enabled OFF OFF ON OFF
|
||||
* LED_STACKCREATED Idle stack created OFF OFF OFF ON
|
||||
* LED_INIRQ In an interrupt ON ON ON ON
|
||||
* LED_SIGNAL In a signal handler ON ON ON ON
|
||||
* LED_ASSERTION An assertion failed ON ON ON ON
|
||||
* LED_PANIC The system has crashed ON ON ON ON
|
||||
* LED_IDLE MCU is is sleep mode ---- Not used ----
|
||||
*/
|
||||
|
||||
/* LED indices */
|
||||
|
||||
#define INDEX_LED_LD1 0
|
||||
#define INDEX_LED_LD2 1
|
||||
#define INDEX_LED_LD3 2
|
||||
#define INDEX_LED_LD4 3
|
||||
#define NLEDS 4
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
static void board_autoled_setone(int ledndx)
|
||||
{
|
||||
bool ledon[NLEDS] =
|
||||
{
|
||||
false,
|
||||
false,
|
||||
false,
|
||||
false
|
||||
};
|
||||
|
||||
ledon[ledndx] = true;
|
||||
pic32mz_gpiowrite(GPIO_LED_LD1, ledon[INDEX_LED_LD1]);
|
||||
pic32mz_gpiowrite(GPIO_LED_LD2, ledon[INDEX_LED_LD2]);
|
||||
pic32mz_gpiowrite(GPIO_LED_LD3, ledon[INDEX_LED_LD3]);
|
||||
pic32mz_gpiowrite(GPIO_LED_LD4, ledon[INDEX_LED_LD4]);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_led_initialize
|
||||
****************************************************************************/
|
||||
|
||||
void pic32mz_led_initialize(void)
|
||||
{
|
||||
/* Configure LED GPIOs for output */
|
||||
|
||||
pic32mz_configgpio(GPIO_LED_LD1);
|
||||
pic32mz_configgpio(GPIO_LED_LD2);
|
||||
pic32mz_configgpio(GPIO_LED_LD3);
|
||||
pic32mz_configgpio(GPIO_LED_LD4);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_on
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_on(int led)
|
||||
{
|
||||
/* SYMBOL MEANING LED STATE
|
||||
* A B C D
|
||||
* ------------------- ----------------------- --- --- --- ---
|
||||
* LED_STARTED 0 NuttX has been started ON OFF OFF OFF
|
||||
* LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF OFF
|
||||
* LED_IRQSENABLED 2 Interrupts enabled OFF OFF ON OFF
|
||||
* LED_STACKCREATED 3 Idle stack created OFF OFF OFF ON
|
||||
* LED_INIRQ 4 In an interrupt ON ON ON ON
|
||||
* LED_SIGNAL 4 In a signal handler ON ON ON ON
|
||||
* LED_ASSERTION 4 An assertion failed ON ON ON ON
|
||||
* LED_PANIC 4 The system has crashed ON ON ON ON
|
||||
*/
|
||||
|
||||
switch (led)
|
||||
{
|
||||
default:
|
||||
case 0:
|
||||
board_autoled_setone(INDEX_LED_LD1);
|
||||
break;
|
||||
|
||||
case 1:
|
||||
board_autoled_setone(INDEX_LED_LD2);
|
||||
break;
|
||||
|
||||
case 2:
|
||||
board_autoled_setone(INDEX_LED_LD3);
|
||||
break;
|
||||
|
||||
case 3:
|
||||
board_autoled_setone(INDEX_LED_LD4);
|
||||
break;
|
||||
|
||||
case 4:
|
||||
board_autoled_setone(INDEX_LED_LD1);
|
||||
board_autoled_setone(INDEX_LED_LD2);
|
||||
board_autoled_setone(INDEX_LED_LD3);
|
||||
board_autoled_setone(INDEX_LED_LD4);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_off
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_off(int led)
|
||||
{
|
||||
/* SYMBOL MEANING LED STATE
|
||||
* A B C D
|
||||
* ------------------- ----------------------- --- --- --- ---
|
||||
* LED_STARTED 0 NuttX has been started ON OFF OFF OFF
|
||||
* LED_HEAPALLOCATE 1 Heap has been allocated OFF ON OFF OFF
|
||||
* LED_IRQSENABLED 2 Interrupts enabled OFF OFF ON OFF
|
||||
* LED_STACKCREATED 3 Idle stack created OFF OFF OFF ON
|
||||
* LED_INIRQ 4 In an interrupt ON ON ON ON
|
||||
* LED_SIGNAL 4 In a signal handler ON ON ON ON
|
||||
* LED_ASSERTION 4 An assertion failed ON ON ON ON
|
||||
* LED_PANIC 4 The system has crashed ON ON ON ON
|
||||
*/
|
||||
|
||||
switch (led)
|
||||
{
|
||||
default:
|
||||
pic32mz_gpiowrite(GPIO_LED_LD1, false);
|
||||
pic32mz_gpiowrite(GPIO_LED_LD2, false);
|
||||
pic32mz_gpiowrite(GPIO_LED_LD3, false);
|
||||
pic32mz_gpiowrite(GPIO_LED_LD4, false);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARCH_LEDS */
|
||||
@@ -0,0 +1,91 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/src/pic32mz_boot.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include "chipkit-wifire.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_boardinitialize
|
||||
*
|
||||
* Description:
|
||||
* All PIC32MZ architectures must provide the following entry point.
|
||||
* This entry point is called early in the initialization -- after all
|
||||
* memory has been configured and mapped but before any devices have been
|
||||
* initialized.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void pic32mz_boardinitialize(void)
|
||||
{
|
||||
/* Configure SPI chip selects if 1) at least one SPI is enabled, and 2)
|
||||
* the weak function pic32mz_spidev_initialize() has been brought into the
|
||||
* link.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI
|
||||
if (pic32mz_spidev_initialize)
|
||||
{
|
||||
pic32mz_spidev_initialize();
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure on-board LEDs if LED support has been selected. */
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
pic32mz_led_initialize();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_late_initialize
|
||||
*
|
||||
* Description:
|
||||
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
|
||||
* initialization call will be performed in the boot-up sequence to a
|
||||
* function called board_late_initialize(). board_late_initialize()
|
||||
* will be called immediately after up_initialize() is called and
|
||||
* just before the initial application is started. This additional
|
||||
* initialization phase may be used, for example, to initialize
|
||||
* board-specific device drivers.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INITIALIZE
|
||||
void board_late_initialize(void)
|
||||
{
|
||||
/* Perform board initialization */
|
||||
|
||||
pic32mz_bringup();
|
||||
}
|
||||
#endif /* CONFIG_BOARD_LATE_INITIALIZE */
|
||||
@@ -0,0 +1,63 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/src/pic32mz_bringup.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <syslog.h>
|
||||
|
||||
#include <nuttx/fs/fs.h>
|
||||
|
||||
#include "chipkit-wifire.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_bringup
|
||||
*
|
||||
* Description:
|
||||
* Bring up board features
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int pic32mz_bringup(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
#ifdef CONFIG_FS_PROCFS
|
||||
/* Mount the procfs file system */
|
||||
|
||||
ret = nx_mount(NULL, "/proc", "procfs", 0, NULL);
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: Failed to mount procfs at /proc: %d\n",
|
||||
ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
UNUSED(ret);
|
||||
return OK;
|
||||
}
|
||||
@@ -0,0 +1,163 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/src/pic32mz_buttons.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "pic32mz_gpio.h"
|
||||
#include "chipkit-wifire.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_BUTTONS
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* Pin configuration for each switch. This array is indexed by the BUTTON_*
|
||||
* definitions in board.h
|
||||
*/
|
||||
|
||||
static const pinset_t g_buttons[NUM_BUTTONS] =
|
||||
{
|
||||
GPIO_BTN1, GPIO_BTN2,
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_button_initialize
|
||||
*
|
||||
* Description:
|
||||
* board_button_initialize() must be called to initialize button resources.
|
||||
* After that, board_buttons() may be called to collect the current state
|
||||
* of all buttons or board_button_irq() may be called to register button
|
||||
* interrupt handlers.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t board_button_initialize(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Configure the GPIO pins as inputs. NOTE that EXTI interrupts are
|
||||
* configured for all pins.
|
||||
*/
|
||||
|
||||
for (i = 0; i < NUM_BUTTONS; i++)
|
||||
{
|
||||
pic32mz_configgpio(g_buttons[i]);
|
||||
}
|
||||
|
||||
return NUM_BUTTONS;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_buttons
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
uint32_t ret = 0;
|
||||
int i;
|
||||
|
||||
/* Check that state of each key */
|
||||
|
||||
for (i = 0; i < NUM_BUTTONS; i++)
|
||||
{
|
||||
/* A LOW value means that the key is pressed. */
|
||||
|
||||
bool released = pic32mz_gpioread(g_buttons[i]);
|
||||
|
||||
/* Accumulate the set of depressed (not released) keys */
|
||||
|
||||
if (!released)
|
||||
{
|
||||
ret |= (1 << i);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Button interrupt support.
|
||||
*
|
||||
* Description:
|
||||
* board_button_initialize() must be called to initialize button resources.
|
||||
* After that, board_buttons() may be called to collect the current state
|
||||
* of all buttons or board_button_irq() may be called to register button
|
||||
* interrupt handlers.
|
||||
*
|
||||
* After board_button_initialize() has been called, board_buttons() may be
|
||||
* called to collect the state of all buttons. board_buttons() returns an
|
||||
* 32-bit bit set with each bit associated with a button. See the
|
||||
* BUTTON_*_BIT definitions in board.h for the meaning of each bit.
|
||||
*
|
||||
* board_button_irq() may be called to register an interrupt handler that
|
||||
* will be called when a button is depressed or released. The ID value is
|
||||
* a button enumeration value that uniquely identifies a button resource.
|
||||
* See the BUTTON_* definitions in board.h for the meaning of enumeration
|
||||
* value.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQBUTTONS
|
||||
int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
|
||||
{
|
||||
#ifdef CONFIG_PIC32MZ_GPIOIRQ_PORTA
|
||||
int ret = OK;
|
||||
|
||||
if ((unsigned)id < NUM_BUTTONS)
|
||||
{
|
||||
/* Perform the attach/detach operation */
|
||||
|
||||
ret = pic32mz_gpioattach(g_buttons[id], irqhandler, arg);
|
||||
|
||||
/* The interrupt is now disabled. Are we attaching or detaching from
|
||||
* button interrupt?
|
||||
*/
|
||||
|
||||
if (ret >= 0)
|
||||
{
|
||||
/* Attaching... enable button interrupts now */
|
||||
|
||||
pic32mz_gpioirqenable(g_buttons[id]);
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
#else
|
||||
return -ENOSYS;
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_ARCH_BUTTONS */
|
||||
@@ -0,0 +1,304 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/src/pic32mz_spi.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/spi/spi.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "mips_arch.h"
|
||||
#include "pic32mz_gpio.h"
|
||||
|
||||
#include "chipkit-wifire.h"
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_spidev_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called to configure SPI chip select GPIO pins for the PIC32MZ board.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void weak_function pic32mz_spidev_initialize(void)
|
||||
{
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_spiNselect, pic32mz_spiNstatus, and pic32mz_spiNcmddata
|
||||
*
|
||||
* Description:
|
||||
* These external functions must be provided by board-specific logic.
|
||||
* They are implementations of the select, status, and cmddata methods of
|
||||
* the SPI interface defined by struct spi_ops_s
|
||||
* (see include/nuttx/spi/spi.h).
|
||||
* All other methods including pic32mz_spibus_initialize()) are provided by
|
||||
* common PIC32MZ logic.
|
||||
* To use this common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in pic32mz_boardinitialize() to configure SPI/SPI chip
|
||||
* select pins.
|
||||
* 2. Provide pic32mz_spiNselect() and pic32mz_spiNstatus() functions
|
||||
* in your board-specific logic. These functions will perform chip
|
||||
* selection and status operations using GPIOs in the way your board is
|
||||
* configured.
|
||||
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
|
||||
* pic32mz_spiNcmddata() functions in your board-specific logic. These
|
||||
* functions will perform cmd/data selection operations using GPIOs in
|
||||
* the way your board is configured.
|
||||
* 3. Add a call to pic32mz_spibus_initialize() in your low level
|
||||
* application initialization logic
|
||||
* 4. The handle returned by pic32mz_spibus_initialize() may then be used
|
||||
* to bind the SPI driver to higher level logic (e.g., calling
|
||||
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
|
||||
* the SPI MMC/SD driver).
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct spi_dev_s;
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI1
|
||||
void pic32mz_spi1select(FAR struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected)
|
||||
{
|
||||
spiinfo("devid: %d CS: %s\n", (int)devid,
|
||||
selected ? "assert" : "de-assert");
|
||||
}
|
||||
|
||||
uint8_t pic32mz_spi1status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
spiinfo("Returning nothing\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
int pic32mz_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_PIC32MZ_SPI1 */
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI2
|
||||
void pic32mz_spi2select(FAR struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected)
|
||||
{
|
||||
spiinfo("devid: %d CS: %s\n", (int)devid,
|
||||
selected ? "assert" : "de-assert");
|
||||
}
|
||||
|
||||
uint8_t pic32mz_spi2status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
spiinfo("Returning nothing\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
int pic32mz_spi2cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_PIC32MZ_SPI2 */
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI3
|
||||
void pic32mz_spi3select(FAR struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected)
|
||||
{
|
||||
spiinfo("devid: %d CS: %s\n", (int)devid,
|
||||
selected ? "assert" : "de-assert");
|
||||
}
|
||||
|
||||
uint8_t pic32mz_spi3status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
spiinfo("Returning nothing\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
int pic32mz_spi3cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_PIC32MZ_SPI3 */
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI4
|
||||
void pic32mz_spi4select(FAR struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected)
|
||||
{
|
||||
spiinfo("devid: %d CS: %s\n", (int)devid,
|
||||
selected ? "assert" : "de-assert");
|
||||
}
|
||||
|
||||
uint8_t pic32mz_spi4status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
spiinfo("Returning nothing\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
int pic32mz_spi4cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_PIC32MZ_SPI4 */
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI5
|
||||
void pic32mz_spi5select(FAR struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected)
|
||||
{
|
||||
spiinfo("devid: %d CS: %s\n", (int)devid,
|
||||
selected ? "assert" : "de-assert");
|
||||
}
|
||||
|
||||
uint8_t pic32mz_spi5status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
spiinfo("Returning nothing\n");
|
||||
#warning "Missing logic"
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
int pic32mz_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_PIC32MZ_SPI5 */
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI6
|
||||
void pic32mz_spi6select(FAR struct spi_dev_s *dev, uint32_t devid,
|
||||
bool selected)
|
||||
{
|
||||
spiinfo("devid: %d CS: %s\n", (int)devid,
|
||||
selected ? "assert" : "de-assert");
|
||||
#warning "Missing logic"
|
||||
}
|
||||
|
||||
uint8_t pic32mz_spi6status(FAR struct spi_dev_s *dev, uint32_t devid)
|
||||
{
|
||||
spiinfo("Returning nothing\n");
|
||||
#warning "Missing logic"
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
int pic32mz_spi6cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif /* CONFIG_PIC32MZ_SPI6 */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pic32mz_spi1/2/...register
|
||||
*
|
||||
* Description:
|
||||
* If the board supports a card detect callback to inform the SPI-based
|
||||
* MMC/SD driver when an SD card is inserted or removed, then
|
||||
* CONFIG_SPI_CALLBACK should be defined and the following function(s)
|
||||
* must be implemented. These functions implements the registercallback
|
||||
* method of the SPI interface (see include/nuttx/spi/spi.h for details)
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* callback - The function to call on the media change
|
||||
* arg - A caller provided value to return with the callback
|
||||
*
|
||||
* Returned Value:
|
||||
* 0 on success; negated errno on failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CALLBACK
|
||||
#ifdef CONFIG_PIC32MZ_SPI1
|
||||
int pic32mz_spi1register(FAR struct spi_dev_s *dev,
|
||||
spi_mediachange_t callback, FAR void *arg)
|
||||
{
|
||||
#warning Missing logic
|
||||
return -ENOSYS;
|
||||
}
|
||||
#endif /* CONFIG_PIC32MZ_SPI1 */
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI2
|
||||
int pic32mz_spi2register(FAR struct spi_dev_s *dev,
|
||||
spi_mediachange_t callback, FAR void *arg)
|
||||
{
|
||||
#warning Missing logic
|
||||
return -ENOSYS;
|
||||
}
|
||||
#endif /* CONFIG_PIC32MZ_SPI2 */
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI3
|
||||
int pic32mz_spi3register(FAR struct spi_dev_s *dev,
|
||||
spi_mediachange_t callback, FAR void *arg)
|
||||
{
|
||||
#warning Missing logic
|
||||
return -ENOSYS;
|
||||
}
|
||||
#endif /* CONFIG_PIC32MZ_SPI3 */
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI4
|
||||
int pic32mz_spi4register(FAR struct spi_dev_s *dev,
|
||||
spi_mediachange_t callback, FAR void *arg)
|
||||
{
|
||||
#warning Missing logic
|
||||
return -ENOSYS;
|
||||
}
|
||||
#endif /* CONFIG_PIC32MZ_SPI4 */
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI5
|
||||
int pic32mz_spi5register(FAR struct spi_dev_s *dev,
|
||||
spi_mediachange_t callback, FAR void *arg)
|
||||
{
|
||||
#warning Missing logic
|
||||
return -ENOSYS;
|
||||
}
|
||||
#endif /* CONFIG_PIC32MZ_SPI5 */
|
||||
|
||||
#ifdef CONFIG_PIC32MZ_SPI6
|
||||
int pic32mz_spi6register(FAR struct spi_dev_s *dev,
|
||||
spi_mediachange_t callback, FAR void *arg)
|
||||
{
|
||||
#warning Missing logic
|
||||
return -ENOSYS;
|
||||
}
|
||||
#endif /* CONFIG_PIC32MZ_SPI6 */
|
||||
#endif /* CONFIG_SPI_CALLBACK */
|
||||
|
||||
#endif /* CONFIG_PIC32MZ_SPI */
|
||||
@@ -0,0 +1,126 @@
|
||||
/****************************************************************************
|
||||
* boards/mips/pic32mz/chipkit-wifire/src/pic32mz_userleds.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* There are four LEDs on the top side of the board:
|
||||
*
|
||||
* LED LD1 - RG6
|
||||
* LED LD2 - RD4
|
||||
* LED LD3 - RB11
|
||||
* LED LD4 - RG15
|
||||
*
|
||||
* A high output value illuminates the LEDs.
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "mips_arch.h"
|
||||
#include "mips_internal.h"
|
||||
|
||||
#include "pic32mz_gpio.h"
|
||||
#include "chipkit-wifire.h"
|
||||
|
||||
#ifndef CONFIG_ARCH_LEDS
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_userled_initialize
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t board_userled_initialize(void)
|
||||
{
|
||||
#ifndef CONFIG_ARCH_LEDS
|
||||
/* Configure LED GPIOs for output */
|
||||
|
||||
pic32mz_configgpio(GPIO_LED_LD1);
|
||||
pic32mz_configgpio(GPIO_LED_LD2);
|
||||
pic32mz_configgpio(GPIO_LED_LD3);
|
||||
pic32mz_configgpio(GPIO_LED_LD4);
|
||||
#endif
|
||||
return BOARD_NLEDS;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_userled
|
||||
****************************************************************************/
|
||||
|
||||
void board_userled(int led, bool ledon)
|
||||
{
|
||||
uint32_t ledcfg;
|
||||
|
||||
switch (led)
|
||||
{
|
||||
case BOARD_LED_LD1:
|
||||
ledcfg = GPIO_LED_LD1;
|
||||
break;
|
||||
|
||||
case BOARD_LED_LD2:
|
||||
ledcfg = GPIO_LED_LD2;
|
||||
break;
|
||||
|
||||
case BOARD_LED_LD3:
|
||||
ledcfg = GPIO_LED_LD3;
|
||||
break;
|
||||
|
||||
case BOARD_LED_LD4:
|
||||
ledcfg = GPIO_LED_LD4;
|
||||
break;
|
||||
|
||||
default:
|
||||
return;
|
||||
}
|
||||
|
||||
pic32mz_gpiowrite(ledcfg, ledon);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_userled_all
|
||||
****************************************************************************/
|
||||
|
||||
void board_userled_all(uint32_t ledset)
|
||||
{
|
||||
bool ledon;
|
||||
|
||||
ledon = ((ledset & BOARD_LED_LD1_BIT) != 0);
|
||||
pic32mz_gpiowrite(GPIO_LED_LD1, ledon);
|
||||
|
||||
ledon = ((ledset & BOARD_LED_LD2_BIT) != 0);
|
||||
pic32mz_gpiowrite(GPIO_LED_LD2, ledon);
|
||||
|
||||
ledon = ((ledset & BOARD_LED_LD3_BIT) != 0);
|
||||
pic32mz_gpiowrite(GPIO_LED_LD3, ledon);
|
||||
|
||||
ledon = ((ledset & BOARD_LED_LD4_BIT) != 0);
|
||||
pic32mz_gpiowrite(GPIO_LED_LD4, ledon);
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_ARCH_LEDS */
|
||||
Reference in New Issue
Block a user