Added a lower-half timer driver for stm32 which is compatible with the upper-half driver located at /drivers/timers/timer.c

arch/arm/src/stm32/Make.defs

@@ -111,6 +111,10 @@ CHIP_CSRCS += stm32_lsi.c stm32_gpio.c stm32_exti_gpio.c stm32_flash.c stm32_irq
 CHIP_CSRCS += stm32_dma.c stm32_lowputc.c stm32_serial.c stm32_spi.c
 CHIP_CSRCS += stm32_sdio.c stm32_tim.c stm32_waste.c stm32_ccm.c
 
+ifeq ($(CONFIG_TIMER),y)
+CHIP_CSRCS += stm32_tim_lowerhalf.c
+endif
+
 ifneq ($(CONFIG_SCHED_TICKLESS),y)
 CHIP_CSRCS += stm32_timerisr.c
 endif

arch/arm/src/stm32/stm32_tim.h

@@ -185,6 +185,26 @@ FAR struct stm32_tim_dev_s *stm32_tim_init(int timer);
 
 int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev);
 
+/****************************************************************************
+ * Name: stm32_timer_initialize
+ *
+ * Description:
+ *   Bind the configuration timer to a timer lower half instance and
+ *   register the timer drivers at 'devpath'
+ *
+ * Input Parameters:
+ *   devpath - The full path to the timer device. This should be of the form /dev/timer0
+ *   timer - the timer number.
+ *
+ * Returned Values:
+ *   Zero (OK) is returned on success; A negated errno value is returned
+ *   to indicate the nature of any failure.
+ *
+ ****************************************************************************/
+#ifdef CONFIG_TIMER
+int stm32_timer_initialize(FAR const char *devpath, int timer);
+#endif
+
 #undef EXTERN
 #if defined(__cplusplus)
 }