mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 08:36:24 +08:00
Initial support for the NXP LPC11 family and the LPC1115 MCU in particular. Contributed by Alan Carvalho de Assis.
This commit is contained in:
Gregory Nutt
+13
-1
@@ -94,6 +94,13 @@ config ARCH_CHIP_TIVA
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---help---
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TI Tiva TM4C architectures (ARM Cortex-M4)
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config ARCH_CHIP_LPC11XX
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bool "NXP LPC11xx"
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select ARCH_CORTEXM0
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select ARCH_HAVE_CMNVECTOR
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---help---
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NXP LPC11xx architectures (ARM Cortex-M0)
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config ARCH_CHIP_LPC17XX
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bool "NXP LPC17xx"
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select ARCH_CORTEXM3
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@@ -281,6 +288,7 @@ config ARCH_CHIP
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default "kinetis" if ARCH_CHIP_KINETIS
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default "kl" if ARCH_CHIP_KL
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default "tiva" if ARCH_CHIP_LM || ARCH_CHIP_TIVA
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default "lpc11xx" if ARCH_CHIP_LPC11XX
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default "lpc17xx" if ARCH_CHIP_LPC17XX
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default "lpc214x" if ARCH_CHIP_LPC214X
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default "lpc2378" if ARCH_CHIP_LPC2378
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@@ -386,7 +394,8 @@ config ARMV7M_MPU
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select ARCH_USE_MPU
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---help---
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Build in support for the ARM Cortex-M3/4 Memory Protection Unit (MPU).
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Check your chip specifications first; not all Cortex-M3/4 chips support the MPU.
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Check your chip specifications first; not all Cortex-M3/4 chips
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support the MPU.
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config ARMV7M_MPU_NREGIONS
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int "Number of MPU regions"
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@@ -460,6 +469,9 @@ endif
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if ARCH_CHIP_LM || ARCH_CHIP_TIVA
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source arch/arm/src/tiva/Kconfig
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endif
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if ARCH_CHIP_LPC11XX
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source arch/arm/src/lpc11xx/Kconfig
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endif
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if ARCH_CHIP_LPC17XX
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source arch/arm/src/lpc17xx/Kconfig
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endif
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@@ -0,0 +1,141 @@
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/************************************************************************************
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* arch/arm/include/lpc11xx/chip.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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||||
* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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||||
* notice, this list of conditions and the following disclaimer.
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||||
* 2. Redistributions in binary form must reproduce the above copyright
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||||
* notice, this list of conditions and the following disclaimer in
|
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H
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#define __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Get customizations for each supported chip */
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#if defined(CONFIG_ARCH_CHIP_LPC1115)
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# define LPC111x 1 /* LPC111x family */
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# define LPC11_FLASH_SIZE (64*1024) /* 64Kb */
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# define LPC11_SRAM_SIZE (8*1024) /* 8Kb */
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# define LPC11_CPUSRAM_SIZE (8*1024)
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# undef LPC11_HAVE_BANK0 /* No AHB SRAM bank 0 */
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# undef LPC11_HAVE_BANK1 /* No AHB SRAM bank 1 */
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# define LPC11_NETHCONTROLLERS 0 /* No Ethernet controller */
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# define LPC11_NUSBHOST 0 /* No USB host controller */
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# define LPC11_NUSBOTG 0 /* No USB OTG controller */
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# define LPC11_NUSBDEV 1 /* One USB device controller */
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# define LPC11_NCAN 1 /* One CAN controller */
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# define LPC11_NI2S 0 /* No I2S modules */
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# define LPC11_NDAC 0 /* No DAC module */
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#else
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# error "Unsupported LPC11xx chip"
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#endif
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/* NVIC priority levels *************************************************************/
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/* Each priority field holds a priority value, 0-31. The lower the value, the greater
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* the priority of the corresponding interrupt. The processor implements only
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* bits[7:3] of each field, bits[2:0] read as zero and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xf8 /* All bits[7:3] set is minimum priority */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x08 /* Five bits of interrupt priority used */
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/* If CONFIG_ARMV7M_USEBASEPRI is selected, then interrupts will be disabled
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* by setting the BASEPRI register to NVIC_SYSH_DISABLE_PRIORITY so that most
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* interrupts will not have execution priority. SVCall must have execution
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* priority in all cases.
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*
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* In the normal cases, interrupts are not nest-able and all interrupts run
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* at an execution priority between NVIC_SYSH_PRIORITY_MIN and
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* NVIC_SYSH_PRIORITY_MAX (with NVIC_SYSH_PRIORITY_MAX reserved for SVCall).
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*
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* If, in addition, CONFIG_ARCH_HIPRI_INTERRUPT is defined, then special
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* high priority interrupts are supported. These are not "nested" in the
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* normal sense of the word. These high priority interrupts can interrupt
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* normal processing but execute outside of OS (although they can "get back
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* into the game" via a PendSV interrupt).
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*
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* In the normal course of things, interrupts must occasionally be disabled
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* using the irqsave() inline function to prevent contention in use of
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* resources that may be shared between interrupt level and non-interrupt
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* level logic. Now the question arises, if CONFIG_ARCH_HIPRI_INTERRUPT,
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* do we disable all interrupts (except SVCall), or do we only disable the
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* "normal" interrupts. Since the high priority interrupts cannot interact
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* with the OS, you may want to permit the high priority interrupts even if
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* interrupts are disabled. The setting CONFIG_ARCH_INT_DISABLEALL can be
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* used to select either behavior:
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*
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* ----------------------------+--------------+----------------------------
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* CONFIG_ARCH_HIPRI_INTERRUPT | NO | YES
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* ----------------------------+--------------+--------------+-------------
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* CONFIG_ARCH_INT_DISABLEALL | N/A | YES | NO
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* ----------------------------+--------------+--------------+-------------
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* | | | SVCall
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* | SVCall | SVCall | HIGH
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* Disable here and below --------> MAXNORMAL ---> HIGH --------> MAXNORMAL
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* | | MAXNORMAL |
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* ----------------------------+--------------+--------------+-------------
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*/
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#if defined(CONFIG_ARCH_HIPRI_INTERRUPT) && defined(CONFIG_ARCH_INT_DISABLEALL)
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# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + 2*NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_HIGH_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_HIGH_PRIORITY
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# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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#else
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# define NVIC_SYSH_MAXNORMAL_PRIORITY (NVIC_SYSH_PRIORITY_MAX + NVIC_SYSH_PRIORITY_STEP)
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# define NVIC_SYSH_HIGH_PRIORITY NVIC_SYSH_PRIORITY_MAX
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# define NVIC_SYSH_DISABLE_PRIORITY NVIC_SYSH_MAXNORMAL_PRIORITY
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# define NVIC_SYSH_SVCALL_PRIORITY NVIC_SYSH_PRIORITY_MAX
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#endif
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/************************************************************************************
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* Public Data
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************************************************************************************/
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#endif /* __ARCH_ARM_INCLUDE_LPC11XX_CHIP_H */
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@@ -0,0 +1,144 @@
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/****************************************************************************
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* arch/arm/include/lpc11xxx/irq.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
|
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*
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
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****************************************************************************/
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/* This file should never be included directed but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H
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#define __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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#include <arch/lpc11xx/chip.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* IRQ numbers. The IRQ number corresponds vector number and hence map
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* directly to bits in the NVIC. This does, however, waste several words of
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* memory in the IRQ to handle mapping tables.
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*/
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/* Common Processor Exceptions (vectors 0-15) */
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#define LPC11_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG) */
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/* Vector 0: Reset stack pointer value */
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/* Vector 1: Reset (not handler as an IRQ) */
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#define LPC11_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
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#define LPC11_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
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/* Vectors 4-10: Reserved */
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#define LPC11_IRQ_SVCALL (11) /* Vector 11: SVC call */
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/* Vector 12-13: Reserved */
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#define LPC11_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
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#define LPC11_IRQ_SYSTICK (15) /* Vector 15: System tick */
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/* External interrupts (vectors >= 16) */
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#define LPC11_IRQ_EXTINT (16) /* Vector number of the first external interrupt */
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#if defined(CONFIG_ARCH_CHIP_LPC1115)
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#define LPC11_IRQ_PIO0_0 (16) /* Vector 16: PIO0_0 */
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#define LPC11_IRQ_PIO0_1 (17) /* Vector 17: PIO0_1 */
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#define LPC11_IRQ_PIO0_2 (18) /* Vector 18: PIO0_2 */
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#define LPC11_IRQ_PIO0_3 (19) /* Vector 19: PIO0_3 */
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#define LPC11_IRQ_PIO0_4 (20) /* Vector 20: PIO0_4 */
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#define LPC11_IRQ_PIO0_5 (21) /* Vector 21: PIO0_5 */
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#define LPC11_IRQ_PIO0_6 (22) /* Vector 22: PIO0_6 */
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#define LPC11_IRQ_PIO0_7 (23) /* Vector 23: PIO0_7 */
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#define LPC11_IRQ_PIO0_8 (24) /* Vector 24: PIO0_8 */
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#define LPC11_IRQ_PIO0_9 (25) /* Vector 25: PIO0_9 */
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#define LPC11_IRQ_PIO0_10 (26) /* Vector 26: PIO0_10 */
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#define LPC11_IRQ_PIO0_11 (27) /* Vector 27: PIO0_11 */
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#define LPC11_IRQ_PIO1_0 (28) /* Vector 28: PIO1_0 */
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#define LPC11_IRQ_CCAN (29) /* Vector 29: C_CAN controller for LPC11Cxx */
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#define LPC11_IRQ_SSP1 (30) /* Vector 30: SPI1/SSP1 */
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#define LPC11_IRQ_I2C (31) /* Vector 31: I2C */
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#define LPC11_IRQ_CT16B0 (32) /* Vector 32: Clock/Timer0 16 bits */
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#define LPC11_IRQ_CT16B1 (33) /* Vector 33: Clock/Timer1 16 bits */
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#define LPC11_IRQ_CT32B0 (34) /* Vector 34: Clock/Timer0 32 bits */
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#define LPC11_IRQ_CT32B1 (35) /* Vector 35: Clock/Timer1 32 bits */
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#define LPC11_IRQ_SSP0 (36) /* Vector 36: SPI0/SSP0 */
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#define LPC11_IRQ_UART (37) /* Vector 37: UART */
|
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/* Vector 38: Reserved */
|
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/* Vector 39: Reserved */
|
||||
#define LPC11_IRQ_ADC (40) /* Vector 40: Analog/Digital Converter */
|
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#define LPC11_IRQ_WDT (41) /* Vector 41: Watchdog timer */
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#define LPC11_IRQ_BOD (42) /* Vector 42: Brownout Detection */
|
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/* Vector 43: Reserved */
|
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#define LPC11_IRQ_PIO3 (44) /* Vector 44: PIO3 */
|
||||
#define LPC11_IRQ_PIO2 (45) /* Vector 45: PIO2 */
|
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#define LPC11_IRQ_PIO1 (46) /* Vector 46: PIO1 */
|
||||
#define LPC11_IRQ_PIO0 (47) /* Vector 47: PIO0 */
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||||
#endif
|
||||
|
||||
#define NR_VECTORS (64) /* 64 vectors */
|
||||
#define NR_IRQS (48) /* 64 interrupts but 48 IRQ numbers */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
typedef void (*vic_vector_t)(uint32_t *regs);
|
||||
|
||||
/****************************************************************************
|
||||
* Inline functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Variables
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_LPC11XX_IRQ_H */
|
||||
@@ -0,0 +1,263 @@
|
||||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see misc/tools/kconfig-language.txt.
|
||||
#
|
||||
|
||||
comment "LPC11xx Configuration Options"
|
||||
|
||||
choice
|
||||
prompt "NXP LPC11XX Chip Selection"
|
||||
default ARCH_CHIP_LPC1115
|
||||
depends on ARCH_CHIP_LPC11XX
|
||||
|
||||
config ARCH_CHIP_LPC1114
|
||||
bool "LPC1114"
|
||||
select ARCH_FAMILY_LPC111X
|
||||
|
||||
config ARCH_CHIP_LPC1115
|
||||
bool "LPC1115"
|
||||
select ARCH_FAMILY_LPC111X
|
||||
|
||||
endchoice
|
||||
|
||||
config ARCH_FAMILY_LPC111X
|
||||
bool
|
||||
|
||||
menu "LPC11xx Peripheral Support"
|
||||
|
||||
choice
|
||||
prompt "System Clock:"
|
||||
default LPC11_INTRCOSC
|
||||
|
||||
config LPC11_INTRCOSC
|
||||
bool "Internal RC"
|
||||
|
||||
config LPC11_MAINOSC
|
||||
bool "External Crystal"
|
||||
|
||||
endchoice
|
||||
|
||||
choice
|
||||
prompt "SysTick clock source"
|
||||
default LPC11_SYSTICK_CORECLK
|
||||
|
||||
config LPC11_SYSTICK_CORECLK
|
||||
bool "Cortex-M0 core clock"
|
||||
|
||||
config LPC11_SYSTICK_CORECLK_DIV16
|
||||
bool "Cortex-M0 core clock divided by 16"
|
||||
|
||||
endchoice
|
||||
|
||||
config LPC11_PLL
|
||||
bool "PLL"
|
||||
default y
|
||||
|
||||
config LPC11_UART0
|
||||
bool "UART0"
|
||||
select ARCH_HAVE_UART0
|
||||
default y
|
||||
|
||||
config LPC11_CAN0
|
||||
bool "CAN0"
|
||||
default n
|
||||
|
||||
config LPC11_SPI
|
||||
bool "SPI"
|
||||
default n
|
||||
|
||||
config LPC11_SSP0
|
||||
bool "SSP0"
|
||||
default n
|
||||
|
||||
config LPC11_SSP1
|
||||
bool "SSP1"
|
||||
default n
|
||||
|
||||
config LPC11_I2C0
|
||||
bool "I2C0"
|
||||
default n
|
||||
|
||||
config LPC11_TMR0
|
||||
bool "Timer 0"
|
||||
default n
|
||||
|
||||
config LPC11_TMR1
|
||||
bool "Timer 1"
|
||||
default n
|
||||
|
||||
config LPC11_WDT
|
||||
bool "WDT"
|
||||
default n
|
||||
|
||||
config LPC11_ADC
|
||||
bool "ADC"
|
||||
default n
|
||||
|
||||
config LPC11_FLASH
|
||||
bool "FLASH"
|
||||
default n
|
||||
|
||||
endmenu
|
||||
|
||||
menu "Serial driver options"
|
||||
depends on LPC11_UART0 || LPC11_UART1 || LPC11_UART2 || LPC11_UART3 || LPC11_UART4
|
||||
|
||||
config SERIAL_TERMIOS
|
||||
bool "Serial driver TERMIOS supported"
|
||||
depends on LPC11_UART0 || LPC11_UART1 || LPC11_UART2 || LPC11_UART3
|
||||
default n
|
||||
---help---
|
||||
Serial driver supports termios.h interfaces (tcsetattr, tcflush, etc.).
|
||||
If this is not defined, then the terminal settings (baud, parity, etc).
|
||||
are not configurable at runtime; serial streams cannot be flushed, etc..
|
||||
|
||||
endmenu
|
||||
|
||||
menu "ADC driver options"
|
||||
depends on LPC11_ADC
|
||||
|
||||
config ADC0_AVERAGE
|
||||
int "ADC0 average"
|
||||
default 200
|
||||
|
||||
config ADC0_MASK
|
||||
int "ADC0 mask"
|
||||
default 1
|
||||
|
||||
config ADC0_SPS
|
||||
int "ADC0 SPS"
|
||||
default 1000
|
||||
|
||||
config ADC_CHANLIST
|
||||
bool "Use ADC channel list"
|
||||
default n
|
||||
---help---
|
||||
The errata that states: "A/D Global Data register should not be used
|
||||
with burst mode or hardware triggering". If this option is selected,
|
||||
then the ADC driver will grab from the individual channel registers
|
||||
rather than from the global data register as this is the stated
|
||||
workaround in the errata.
|
||||
|
||||
The ADC interrupt will trigger on conversion complete on the last
|
||||
channel listed in the array g_adc_chanlist[] (as opposed to
|
||||
triggering interrupt from the global DONE flag).
|
||||
|
||||
If this option is enabled, then the platform specific code must do
|
||||
two things: (1) define ADC_NCHANNELS in the configuration file and
|
||||
(2) provide an array g_adc_chanlist[] with the channel numbers
|
||||
matching the ADC0_MASK within the board-specific library.
|
||||
|
||||
config ADC_BURSTMODE
|
||||
bool "One interrupt at the end of all ADC cconversions"
|
||||
default n
|
||||
---help---
|
||||
Select this if you want to generate only one interrupt once all selected channels has been converted by the ADC
|
||||
|
||||
config ADC_NCHANNELS
|
||||
int "ADC0 number of channels"
|
||||
depends on ADC_CHANLIST
|
||||
default 0
|
||||
---help---
|
||||
If ADC_CHANLIST is enabled, then the platform specific code
|
||||
must do two things: (1) define ADC_NCHANNELS in the configuration
|
||||
file and (2) provide an array g_adc_chanlist[] with the channel
|
||||
numbers matching the ADC0_MASK within the board-specific library.
|
||||
|
||||
endmenu
|
||||
|
||||
menu "CAN driver options"
|
||||
depends on LPC11_CAN1 || LPC11_CAN2
|
||||
|
||||
config CAN_EXTID
|
||||
bool "CAN extended IDs"
|
||||
default n
|
||||
---help---
|
||||
Enables support for the 29-bit extended ID. Default Standard 11-bit IDs.
|
||||
|
||||
config CAN1_BAUD
|
||||
int "CAN1 BAUD"
|
||||
depends on LPC11_CAN1
|
||||
---help---
|
||||
CAN1 BAUD rate. Required if LPC11_CAN1 is defined.
|
||||
|
||||
config CAN2_BAUD
|
||||
int "CAN2 BAUD"
|
||||
depends on LPC11_CAN2
|
||||
---help---
|
||||
CAN2 BAUD rate. Required if LPC11_CAN2 is defined.
|
||||
|
||||
config CAN1_DIVISOR
|
||||
int "CAN1 CCLK divisor"
|
||||
depends on LPC11_CAN1
|
||||
default 4
|
||||
---help---
|
||||
CAN1 is clocked at CCLK divided by this number. (the CCLK frequency is divided
|
||||
by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4.
|
||||
|
||||
config CAN2_DIVISOR
|
||||
int "CAN2 CCLK divisor"
|
||||
depends on LPC11_CAN2
|
||||
default 4
|
||||
---help---
|
||||
CAN2 is clocked at CCLK divided by this number. (the CCLK frequency is divided
|
||||
by this number to get the CAN clock). Options = {1,2,4,6}. Default: 4.
|
||||
|
||||
config CAN_TSEG1
|
||||
int "TSEG1 quanta"
|
||||
default 6
|
||||
---help---
|
||||
The number of CAN time quanta in segment 1. Default: 6
|
||||
|
||||
config CAN_TSEG2
|
||||
int "TSEG2 quanta"
|
||||
default 4
|
||||
---help---
|
||||
The number of CAN time quanta in segment 2. Default: 7
|
||||
|
||||
config CAN_SAM
|
||||
bool "CAN sampling"
|
||||
default n
|
||||
---help---
|
||||
The bus is sampled 3 times (recommended for low to medium speed buses to spikes on the bus-line).
|
||||
|
||||
config CAN_LOOPBACK
|
||||
bool "CAN looopback mode"
|
||||
default n
|
||||
---help---
|
||||
Enable CAN loopback mode
|
||||
|
||||
config CAN_REGDEBUG
|
||||
bool "Register level debug"
|
||||
depends on DEBUG
|
||||
default n
|
||||
---help---
|
||||
Output detailed register-level CAN debug information. Requires also DEBUG and DEBUG_CAN.
|
||||
|
||||
endmenu
|
||||
|
||||
config GPIO_IRQ
|
||||
bool "GPIO interrupt support"
|
||||
default n
|
||||
---help---
|
||||
Enable support for GPIO interrupts
|
||||
|
||||
menu "I2C driver options"
|
||||
depends on LPC11_I2C0 || LPC11_I2C1 || LPC11_I2C2
|
||||
|
||||
config I2C0_FREQ
|
||||
int "I2C0 frequency"
|
||||
depends on LPC11_I2C0
|
||||
default 100000
|
||||
|
||||
config I2C1_FREQ
|
||||
int "I2C1 frequency"
|
||||
depends on LPC11_I2C1
|
||||
default 100000
|
||||
|
||||
config I2C2_FREQ
|
||||
int "I2C2 frequency"
|
||||
depends on LPC11_I2C2
|
||||
default 100000
|
||||
|
||||
endmenu
|
||||
@@ -0,0 +1,103 @@
|
||||
############################################################################
|
||||
# arch/arm/src/lpc11xx/Make.defs
|
||||
#
|
||||
# Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name NuttX nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
HEAD_ASRC =
|
||||
|
||||
CMN_ASRCS = up_exception.S up_saveusercontext.S up_fullcontextrestore.S
|
||||
CMN_ASRCS += up_switchcontext.S vfork.S
|
||||
|
||||
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c
|
||||
CMN_CSRCS += up_createstack.c up_mdelay.c up_udelay.c up_exit.c
|
||||
CMN_CSRCS += up_initialize.c up_initialstate.c up_interruptcontext.c
|
||||
CMN_CSRCS += up_puts.c up_modifyreg8.c up_modifyreg16.c up_modifyreg32.c
|
||||
CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c
|
||||
CMN_CSRCS += up_schedulesigaction.c up_sigdeliver.c up_stackframe.c
|
||||
CMN_CSRCS += up_systemreset.c up_unblocktask.c up_usestack.c up_doirq.c
|
||||
CMN_CSRCS += up_hardfault.c up_svcall.c up_vectors.c up_vfork.c
|
||||
|
||||
ifeq ($(CONFIG_BUILD_PROTECTED),y)
|
||||
CMN_CSRCS += up_task_start.c up_pthread_start.c
|
||||
ifneq ($(CONFIG_DISABLE_SIGNALS),y)
|
||||
CMN_CSRCS += up_signal_dispatch.c
|
||||
CMN_UASRCS += up_signal_handler.S
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STACK_COLORATION),y)
|
||||
CMN_CSRCS += up_checkstack.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ELF),y)
|
||||
CMN_CSRCS += up_elf.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_DEBUG),y)
|
||||
CMN_CSRCS += up_dumpnvic.c
|
||||
endif
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS = lpc11_clockconfig.c lpc11_gpio.c lpc11_i2c.c lpc11_idle.c
|
||||
CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_serial.c lpc11_spi.c
|
||||
CHIP_CSRCS += lpc11_ssp.c lpc11_start.c
|
||||
|
||||
# Configuration-dependent LPC11xx files
|
||||
|
||||
ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
||||
CHIP_CSRCS += lpc11_timerisr.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BUILD_PROTECTED),y)
|
||||
CHIP_CSRCS += lpc11_userspace.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_GPIO_IRQ),y)
|
||||
CHIP_CSRCS += lpc11_gpioint.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_IRQPRIO),y)
|
||||
CHIP_CSRCS += lpc11_irqprio.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_LPC11_SPI0),y)
|
||||
CHIP_CSRCS += lpc11_spi.c
|
||||
else
|
||||
ifeq ($(CONFIG_LPC11_SPI1),y)
|
||||
CHIP_CSRCS += lpc11_spi.c
|
||||
endif
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_PWM),y)
|
||||
CHIP_CSRCS += lpc11_pwm.c
|
||||
endif
|
||||
@@ -0,0 +1,74 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip.h
|
||||
*
|
||||
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_CHIP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "nvic.h"
|
||||
|
||||
/* Include the chip capabilities file */
|
||||
|
||||
#include <arch/lpc11xx/chip.h>
|
||||
|
||||
#define ARMV6M_PERIPHERAL_INTERRUPTS 32
|
||||
|
||||
/* Include the memory map file. Other chip hardware files should then include
|
||||
* this file for the proper setup.
|
||||
*/
|
||||
|
||||
#include "chip/lpc11_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_H */
|
||||
@@ -0,0 +1,219 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc111x_iocon.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Rommel Marcelo
|
||||
* Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_IOCON_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_IOCON_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/lpc11_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#define IOCON_NPINS 12
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
/* Note: The IOCON offset is not linear. See User manual UM10398 Page 74 */
|
||||
/* Note: The IOCON base is not linear. See User manual UM10398 Page 74 */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC11_IOCON_P0_0 (LPC11_IOCON_BASE + 0x00C)
|
||||
#define LPC11_IOCON_P0_1 (LPC11_IOCON_BASE + 0x010)
|
||||
#define LPC11_IOCON_P0_2 (LPC11_IOCON_BASE + 0x01C)
|
||||
#define LPC11_IOCON_P0_3 (LPC11_IOCON_BASE + 0x02C)
|
||||
#define LPC11_IOCON_P0_4 (LPC11_IOCON_BASE + 0x030)
|
||||
#define LPC11_IOCON_P0_5 (LPC11_IOCON_BASE + 0x034)
|
||||
#define LPC11_IOCON_P0_6 (LPC11_IOCON_BASE + 0x04C)
|
||||
#define LPC11_IOCON_P0_7 (LPC11_IOCON_BASE + 0x050)
|
||||
#define LPC11_IOCON_P0_8 (LPC11_IOCON_BASE + 0x060)
|
||||
#define LPC11_IOCON_P0_9 (LPC11_IOCON_BASE + 0x064)
|
||||
#define LPC11_IOCON_P0_10 (LPC11_IOCON_BASE + 0x068)
|
||||
#define LPC11_IOCON_P0_11 (LPC11_IOCON_BASE + 0x074)
|
||||
|
||||
#define LPC11_IOCON_P1_0 (LPC11_IOCON_BASE + 0x078)
|
||||
#define LPC11_IOCON_P1_1 (LPC11_IOCON_BASE + 0x07c)
|
||||
#define LPC11_IOCON_P1_2 (LPC11_IOCON_BASE + 0x080)
|
||||
#define LPC11_IOCON_P1_3 (LPC11_IOCON_BASE + 0x090)
|
||||
#define LPC11_IOCON_P1_4 (LPC11_IOCON_BASE + 0x094)
|
||||
#define LPC11_IOCON_P1_5 (LPC11_IOCON_BASE + 0x0a0)
|
||||
#define LPC11_IOCON_P1_6 (LPC11_IOCON_BASE + 0x0a4)
|
||||
#define LPC11_IOCON_P1_7 (LPC11_IOCON_BASE + 0x0a8)
|
||||
#define LPC11_IOCON_P1_8 (LPC11_IOCON_BASE + 0x014)
|
||||
#define LPC11_IOCON_P1_9 (LPC11_IOCON_BASE + 0x038)
|
||||
#define LPC11_IOCON_P1_10 (LPC11_IOCON_BASE + 0x06c)
|
||||
#define LPC11_IOCON_P1_11 (LPC11_IOCON_BASE + 0x098)
|
||||
|
||||
#define LPC11_IOCON_P2_0 (LPC11_IOCON_BASE + 0x008)
|
||||
#define LPC11_IOCON_P2_1 (LPC11_IOCON_BASE + 0x028)
|
||||
#define LPC11_IOCON_P2_2 (LPC11_IOCON_BASE + 0x05c)
|
||||
#define LPC11_IOCON_P2_3 (LPC11_IOCON_BASE + 0x08c)
|
||||
#define LPC11_IOCON_P2_4 (LPC11_IOCON_BASE + 0x040)
|
||||
#define LPC11_IOCON_P2_5 (LPC11_IOCON_BASE + 0x044)
|
||||
#define LPC11_IOCON_P2_6 (LPC11_IOCON_BASE + 0x000)
|
||||
#define LPC11_IOCON_P2_7 (LPC11_IOCON_BASE + 0x020)
|
||||
#define LPC11_IOCON_P2_8 (LPC11_IOCON_BASE + 0x024)
|
||||
#define LPC11_IOCON_P2_9 (LPC11_IOCON_BASE + 0x054)
|
||||
#define LPC11_IOCON_P2_10 (LPC11_IOCON_BASE + 0x058)
|
||||
#define LPC11_IOCON_P2_11 (LPC11_IOCON_BASE + 0x070)
|
||||
|
||||
#define LPC11_IOCON_P3_0 (LPC11_IOCON_BASE + 0x084)
|
||||
#define LPC11_IOCON_P3_1 (LPC11_IOCON_BASE + 0x088)
|
||||
#define LPC11_IOCON_P3_2 (LPC11_IOCON_BASE + 0x09C)
|
||||
#define LPC11_IOCON_P3_3 (LPC11_IOCON_BASE + 0x0ac)
|
||||
#define LPC11_IOCON_P3_4 (LPC11_IOCON_BASE + 0x03c)
|
||||
#define LPC11_IOCON_P3_5 (LPC11_IOCON_BASE + 0x048)
|
||||
|
||||
#define LPC11_IOCON_SCK_LOC (LPC11_IOCON_BASE + 0x0b0)
|
||||
#define LPC11_IOCON_DSR_LOC (LPC11_IOCON_BASE + 0x0b4)
|
||||
#define LPC11_IOCON_DCD_LOC (LPC11_IOCON_BASE + 0x0b8)
|
||||
#define LPC11_IOCON_RI_LOC (LPC11_IOCON_BASE + 0x0bc)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* IOCON pin function select */
|
||||
|
||||
#define IOCON_FUNC_GPIO (0)
|
||||
#define IOCON_FUNC_ALT1 (1)
|
||||
#define IOCON_FUNC_ALT2 (2)
|
||||
#define IOCON_FUNC_ALT3 (3)
|
||||
#define IOCON_FUNC_ALT4 (4)
|
||||
#define IOCON_FUNC_ALT5 (5)
|
||||
#define IOCON_FUNC_ALT6 (6)
|
||||
#define IOCON_FUNC_ALT7 (7)
|
||||
|
||||
#define IOCON_FUNC_SHIFT (0) /* Bits 0-2: All types */
|
||||
#define IOCON_FUNC_MASK (7 << IOCON_FUNC_SHIFT)
|
||||
#define IOCON_MODE_SHIFT (3) /* Bits 3-4: Type D,A,W */
|
||||
#define IOCON_MODE_MASK (3 << IOCON_MODE_SHIFT )
|
||||
#define IOCON_HYS_SHIFT (5) /* Bit 5: Type D,W */
|
||||
#define IOCON_HYS_MASK (1 << IOCON_HYS_SHIFT)
|
||||
/* Bit 6-9: Reserved */
|
||||
#define IOCON_OD_SHIFT (10) /* Bit 10: Type D,A,W */
|
||||
#define IOCON_OD_MASK (1 << IOCON_OD_SHIFT)
|
||||
/* Bit 11-31: Reserved */
|
||||
|
||||
/* Pin modes */
|
||||
|
||||
#define IOCON_MODE_FLOAT (0) /* 00: pin has neither pull-up nor pull-down */
|
||||
#define IOCON_MODE_PD (1) /* 01: pin has a pull-down resistor enabled */
|
||||
#define IOCON_MODE_PU (2) /* 10: pin has a pull-up resistor enabled */
|
||||
#define IOCON_MODE_RM (3) /* 11: pin has repeater mode enabled */
|
||||
|
||||
/* Pin types */
|
||||
|
||||
#define IOCON_TYPE_D_MASK (0x0000067f) /* All ports except where ADC/DAC, USB, I2C is present */
|
||||
#define IOCON_TYPE_A_MASK (0x000105df) /* USB/ADC/DAC P0:12-13, P0:23-26, P1:30-31 */
|
||||
#define IOCON_TYPE_U_MASK (0x00000007) /* USB P0:29 to 31 */
|
||||
#define IOCON_TYPE_I_MASK (0x00000347) /* I2C/USB P0:27-28, P5:2-3 */
|
||||
#define IOCON_TYPE_W_MASK (0x000007ff) /* I2S P0:7-9 */
|
||||
|
||||
/* Analog/Digital mode */
|
||||
|
||||
#define IOCON_ADMODE_SHIFT (7)
|
||||
#define IOCON_ADMODE_ANALOG (0 << IOCON_ADMODE_SHIFT)
|
||||
#define IOCON_ADMODE_DIGITAL (1 << IOCON_ADMODE_SHIFT)
|
||||
|
||||
/* I2C modes */
|
||||
|
||||
#define IOCON_I2CMODE_SHIFT (8)
|
||||
#define IOCON_I2CMODE_MASK (3 << IOCON_I2CMODE_SHIFT)
|
||||
# define IOCON_I2CMODE_STANDARD (0 << IOCON_I2CMODE_SHIFT)
|
||||
# define IOCON_I2CMODE_STANDIO (1 << IOCON_I2CMODE_SHIFT)
|
||||
# define IOCON_I2CMODE_FASTPLUS (2 << IOCON_I2CMODE_SHIFT)
|
||||
/*(3 << IOCON_I2CMODE_SHIFT) Reserved */
|
||||
/* Bits 10-31: Reserved */
|
||||
|
||||
/* SCK location register */
|
||||
|
||||
#define IOCON_SCK_LOC_SHIFT (0)
|
||||
#define IOCON_SCK_LOC_MASK (3 << IOCON_SCK_LOC_SHIFT)
|
||||
# define IOCON_SCK_LOC_SWCLK (0 << IOCON_SCK_LOC_SHIFT)
|
||||
# define IOCON_SCK_LOC_PIO2_11 (1 << IOCON_SCK_LOC_SHIFT)
|
||||
# define IOCON_SCK_LOC_PIO0_6 (2 << IOCON_SCK_LOC_SHIFT)
|
||||
/*(3 << IOCON_SCK_LOC_SHIFT) Reserved */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/* DSR location register */
|
||||
|
||||
#define IOCON_DSR_LOC_SHIFT (0)
|
||||
#define IOCON_DSR_LOC_MASK (3 << IOCON_DSR_LOC_SHIFT)
|
||||
# define IOCON_DSR_LOC_PIO2_1 (0 << IOCON_DSR_LOC_SHIFT)
|
||||
# define IOCON_DSR_LOC_PIO3_1 (1 << IOCON_DSR_LOC_SHIFT)
|
||||
/*(2 << IOCON_DSR_LOC_SHIFT) Reserved */
|
||||
/*(3 << IOCON_DSR_LOC_SHIFT) Reserved */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/* DCD location register */
|
||||
|
||||
#define IOCON_DCD_LOC_SHIFT (0)
|
||||
#define IOCON_DCD_LOC_MASK (3 << IOCON_DCD_LOC_SHIFT)
|
||||
# define IOCON_DCD_LOC_PIO2_2 (0 << IOCON_DCD_LOC_SHIFT)
|
||||
# define IOCON_DCD_LOC_PIO3_2 (1 << IOCON_DCD_LOC_SHIFT)
|
||||
/*(2 << IOCON_DCD_LOC_SHIFT) Reserved */
|
||||
/*(3 << IOCON_DCD_LOC_SHIFT) Reserved */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/* RI location register */
|
||||
|
||||
#define IOCON_RI_LOC_SHIFT (0)
|
||||
#define IOCON_RI_LOC_MASK (3 << IOCON_RI_LOC_SHIFT)
|
||||
# define IOCON_RI_LOC_PIO2_3 (0 << IOCON_RI_LOC_SHIFT)
|
||||
# define IOCON_RI_LOC_PIO3_3 (1 << IOCON_RI_LOC_SHIFT)
|
||||
/*(2 << IOCON_RI_LOC_SHIFT) Reserved */
|
||||
/*(3 << IOCON_RI_LOC_SHIFT) Reserved */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC118X_IOCON_H */
|
||||
@@ -0,0 +1,107 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc111x_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC111X_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC111X_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Memory Map ***********************************************************************/
|
||||
|
||||
#define LPC11_FLASH_BASE 0x00000000 /* -0x1fffffff: On-chip non-volatile memory */
|
||||
#define LPC11_SRAM_BASE 0x10000000 /* -0x10007fff: On-chip SRAM (devices <=16Kb) */
|
||||
#define LPC11_ROM_BASE 0x1fff0000 /* -0x1fffffff: 16Kb Boot ROM with flash services */
|
||||
#define LPC11_AHBSRAM_BASE 0x20000000 /* -0x3fffffff: On-chip AHB SRAM (devices >32Kb) */
|
||||
#define LPC11_GPIO_BASE 0x50000000 /* -0x2009ffff: GPIO at AHB Peripherals */
|
||||
#define LPC11_APB_BASE 0x40000000 /* -0x4007ffff: APB Peripherals */
|
||||
#define LPC11_AHB_BASE 0x50000000 /* -0x501fffff: AHB Peripherals */
|
||||
#define LPC11_CORTEXM3_BASE 0xe0000000 /* -0xe00fffff: (see armv7-m/nvic.h) */
|
||||
#define LPC11_SCS_BASE 0xe000e000
|
||||
#define LPC11_DEBUGMCU_BASE 0xe0042000
|
||||
|
||||
/* APB Peripherals *****************************************************************/
|
||||
|
||||
#define LPC11_I2C0_BASE 0x40000000 /* -0x40003fff: I2C-bus */
|
||||
#define LPC11_WDT_BASE 0x40004000 /* -0x40007fff: Watchdog timer */
|
||||
#define LPC11_UART0_BASE 0x40008000 /* -0x4000bfff: UART 0 */
|
||||
#define LPC11_TMR0_BASE 0x4000c000 /* -0x4000ffff: Timer 0 */
|
||||
#define LPC11_TMR1_BASE 0x40010000 /* -0x40013fff: Timer 1 */
|
||||
#define LPC11_TMR2_BASE 0x40014000 /* -0x40017fff: Timer 0 */
|
||||
#define LPC11_TMR3_BASE 0x40018000 /* -0x4001bfff: Timer 1 */
|
||||
#define LPC11_ADC_BASE 0x4001c000 /* -0x4001ffff: ADC */
|
||||
/* -0x40037fff: Reserved */
|
||||
#define LPC11_PMU_BASE 0x40038000 /* -0x4003bfff: PMU */
|
||||
/* -0x40017fff: Reserved */
|
||||
#define LPC11_FLASHC_BASE 0x4003c000 /* -0x4003ffff: Flash Controller */
|
||||
#define LPC11_SPI0_BASE 0x40040000 /* -0x40043fff: SPI0 */
|
||||
#define LPC11_IOCON_BASE 0x40044000 /* -0x40047fff: IOCONFIG */
|
||||
#define LPC11_SYSCON_BASE 0x40048000 /* -0x4004bfff: System Control */
|
||||
/* -0x4004ffff: Reserved */
|
||||
#define LPC11_CAN0_BASE 0x40050000 /* -0x40053fff: CAN0 */
|
||||
/* -0x40057ffff: Reserved */
|
||||
#define LPC11_SPI1_BASE 0x40058000 /* -0x4005bffff: SPI1 */
|
||||
/* -0x4007fffff: Reserved */
|
||||
|
||||
/* AHB Peripherals ******************************************************************/
|
||||
|
||||
#define LPC11_GPIO_PIO0 (LPC11_GPIO_BASE + 0) /* -0x5000ffff: GPIO PIO0 */
|
||||
#define LPC11_GPIO_PIO1 (LPC11_GPIO_BASE + 0x10000) /* -0x5001ffff: GPIO PIO1 */
|
||||
#define LPC11_GPIO_PIO2 (LPC11_GPIO_BASE + 0x20000) /* -0x5002ffff: GPIO PIO1 */
|
||||
#define LPC11_GPIO_PIO3 (LPC11_GPIO_BASE + 0x30000) /* -0x5003ffff: GPIO PIO1 */
|
||||
/* -0x501fffff: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC116X_MEMORYMAP_H */
|
||||
@@ -0,0 +1,122 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc111x_pinconfig.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_PINCONFIG_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC111X_PINCONFIG_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
/* GPIO pin definitions *************************************************************/
|
||||
/* NOTE that functions have a alternate pins that can be selected. These alternates
|
||||
* are identified with a numeric suffix like _1, _2, or _3. Your board.h file
|
||||
* should select the correct alternative for your board by including definitions
|
||||
* such as:
|
||||
*
|
||||
* #define GPIO_UART1_RXD GPIO_UART1_RXD_1
|
||||
*
|
||||
* (without the suffix)
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_LPC1115
|
||||
|
||||
#define GPIO_CLKOUT (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1)
|
||||
#define GPIO_CT32B0_MAT2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN1)
|
||||
#define GPIO_SPI0_SSEL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2)
|
||||
#define GPIO_CT16B0_CAP0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN2)
|
||||
#define GPIO_I2C_SCL (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN4)
|
||||
#define GPIO_I2C_SDA (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN5)
|
||||
#define GPIO_SPI0_SCK_1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN6)
|
||||
#define GPIO_UART0_CTS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN7)
|
||||
#define GPIO_SPI0_MISO (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
|
||||
#define GPIO_CT16B0_MAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN8)
|
||||
#define GPIO_SPI0_MOSI (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
|
||||
#define GPIO_CT16B0_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN9)
|
||||
#define GPIO_JTAG_SWCLK (GPIO_ALT0 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
|
||||
#define GPIO_PIO0_10 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
|
||||
#define GPIO_SPI0_SCK (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
|
||||
#define GPIO_CT16B0_MAT2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN10)
|
||||
#define GPIO_PIO0_11 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11)
|
||||
#define GPIO_AD_inp0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11)
|
||||
#define GPIO_CT32B0_MAT3 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT0 | GPIO_PIN11)
|
||||
#define GPIO_PIO1_0 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0)
|
||||
#define GPIO_AD_inp1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0)
|
||||
#define GPIO_CT32B1_CAP0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN0)
|
||||
#define GPIO_PIO1_1 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1)
|
||||
#define GPIO_AD_inp2 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1)
|
||||
#define GPIO_CT32B1_MAT0 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN1)
|
||||
#define GPIO_PIO1_2 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2)
|
||||
#define GPIO_AD_inp3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2)
|
||||
#define GPIO_CT32B1_MAT1 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN2)
|
||||
#define GPIO_JTAG_SWDIO (GPIO_ALT0 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3)
|
||||
#define GPIO_PIO1_3 (GPIO_ALT_GPIO | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3)
|
||||
#define GPIO_AD_inp4 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3)
|
||||
#define GPIO_CT32B1_MAT2 (GPIO_ALT3 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN3)
|
||||
#define GPIO_AD_inp5 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4)
|
||||
#define GPIO_CT32B1_MAT3 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN4)
|
||||
#define GPIO_UART0_RTS (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN5)
|
||||
#define GPIO_CT32B0_CAP0 (GPIO_ALT2 | GPIO_PULLDN | GPIO_PORT1 | GPIO_PIN5)
|
||||
#define GPIO_UART0_RXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6)
|
||||
#define GPIO_CT32B0_MAT0 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN6)
|
||||
#define GPIO_UART0_TXD (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7)
|
||||
#define GPIO_CT32B0_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN7)
|
||||
#define GPIO_CT16B1_CAP0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN8)
|
||||
#define GPIO_CT16B1_MAT0 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN9)
|
||||
#define GPIO_AD_inp6 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN10)
|
||||
#define GPIO_CT16B1_MAT1 (GPIO_ALT2 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN10)
|
||||
#define GPIO_AD_inp7 (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT1 | GPIO_PIN11)
|
||||
#define GPIO_UART0_DTR (GPIO_ALT1 | GPIO_PULLUP | GPIO_PORT2 | GPIO_PIN0)
|
||||
|
||||
#endif /* CONFIG_ARCH_CHIP_LPC1115 */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC116X_PINCONFIG_H */
|
||||
@@ -0,0 +1,171 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc11_adc.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_ADC_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_ADC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/lpc11_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC11_ADC_CR_OFFSET 0x0000 /* A/D Control Register */
|
||||
#define LPC11_ADC_GDR_OFFSET 0x0004 /* A/D Global Data Register */
|
||||
#define LPC11_ADC_INTEN_OFFSET 0x000c /* A/D Interrupt Enable Register */
|
||||
|
||||
#define LPC11_ADC_DR_OFFSET(n) (0x0010+((n) << 2))
|
||||
#define LPC11_ADC_DR0_OFFSET 0x0010 /* A/D Channel 0 Data Register */
|
||||
#define LPC11_ADC_DR1_OFFSET 0x0014 /* A/D Channel 1 Data Register */
|
||||
#define LPC11_ADC_DR2_OFFSET 0x0018 /* A/D Channel 2 Data Register */
|
||||
#define LPC11_ADC_DR3_OFFSET 0x001c /* A/D Channel 3 Data Register */
|
||||
#define LPC11_ADC_DR4_OFFSET 0x0020 /* A/D Channel 4 Data Register */
|
||||
#define LPC11_ADC_DR5_OFFSET 0x0024 /* A/D Channel 5 Data Register */
|
||||
#define LPC11_ADC_DR6_OFFSET 0x0028 /* A/D Channel 6 Data Register */
|
||||
#define LPC11_ADC_DR7_OFFSET 0x002c /* A/D Channel 7 Data Register */
|
||||
|
||||
#define LPC11_ADC_STAT_OFFSET 0x0030 /* A/D Status Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC11_ADC_CR (LPC11_ADC_BASE+LPC11_ADC_CR_OFFSET)
|
||||
#define LPC11_ADC_GDR (LPC11_ADC_BASE+LPC11_ADC_GDR_OFFSET)
|
||||
#define LPC11_ADC_INTEN (LPC11_ADC_BASE+LPC11_ADC_INTEN_OFFSET)
|
||||
|
||||
#define LPC11_ADC_DR(n) (LPC11_ADC_BASE+LPC11_ADC_DR_OFFSET(n))
|
||||
#define LPC11_ADC_DR0 (LPC11_ADC_BASE+LPC11_ADC_DR0_OFFSET)
|
||||
#define LPC11_ADC_DR1 (LPC11_ADC_BASE+LPC11_ADC_DR1_OFFSET)
|
||||
#define LPC11_ADC_DR2 (LPC11_ADC_BASE+LPC11_ADC_DR2_OFFSET)
|
||||
#define LPC11_ADC_DR3 (LPC11_ADC_BASE+LPC11_ADC_DR3_OFFSET)
|
||||
#define LPC11_ADC_DR4 (LPC11_ADC_BASE+LPC11_ADC_DR4_OFFSET)
|
||||
#define LPC11_ADC_DR5 (LPC11_ADC_BASE+LPC11_ADC_DR5_OFFSET)
|
||||
#define LPC11_ADC_DR6 (LPC11_ADC_BASE+LPC11_ADC_DR6_OFFSET)
|
||||
#define LPC11_ADC_DR7 (LPC11_ADC_BASE+LPC11_ADC_DR7_OFFSET)
|
||||
|
||||
#define LPC11_ADC_STAT (LPC11_ADC_BASE+LPC11_ADC_STAT_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* A/D Control Register */
|
||||
|
||||
#define ADC_CR_SEL_SHIFT (0) /* Bits 0-7: Selects pins to be sampled */
|
||||
#define ADC_CR_SEL_MASK (0xff << ADC_CR_SEL_MASK)
|
||||
#define ADC_CR_CLKDIV_SHIFT (8) /* Bits 8-15: APB clock (PCLK_ADC0) divisor */
|
||||
#define ADC_CR_CLKDIV_MASK (0xff << ADC_CR_CLKDIV_SHIFT)
|
||||
#define ADC_CR_BURST (1 << 16) /* Bit 16: A/D Repeated conversions */
|
||||
#define ADC_CR_CLKS_SHIFT (17) /* Bits 17-19: Clocks used on burst mode conv. */
|
||||
#define ADC_CR_CLKS_MASK (3 << ADC_CR_CLKS_SHIFT)
|
||||
/* Bits 20-23: Reserved */
|
||||
#define ADC_CR_START_SHIFT (24) /* Bits 24-26: Control A/D conversion start */
|
||||
#define ADC_CR_START_MASK (7 << ADC_CR_START_SHIFT)
|
||||
# define ADC_CR_START_NOSTART (0 << ADC_CR_START_SHIFT) /* No start */
|
||||
# define ADC_CR_START_NOW (1 << ADC_CR_START_SHIFT) /* Start now */
|
||||
# define ADC_CR_START_P0p2 (2 << ADC_CR_START_SHIFT) /* Start edge on P0.2/SSEL/CT16B0_CAP0 */
|
||||
# define ADC_CR_START_P1p5 (3 << ADC_CR_START_SHIFT) /* Start edge on P1.5/DIR/CT32B0_CAP0 */
|
||||
# define ADC_CR_START_CT32B0MAT0 (4 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer32 MAT0 */
|
||||
# define ADC_CR_START_CT32B0MAT1 (5 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer32 MAT1 */
|
||||
# define ADC_CR_START_CT16B0MAT0 (6 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer16 MAT0 */
|
||||
# define ADC_CR_START_CT16B0MAT1 (7 << ADC_CR_START_SHIFT) /* Start edge on Counter/Timer16 MAT1 */
|
||||
#define ADC_CR_EDGE (1 << 27) /* Bit 27: Start on falling edge */
|
||||
/* Bits 28-31: Reserved */
|
||||
/* A/D Global Data Register AND Channel 0-7 Data Register */
|
||||
/* Bits 0-5: Reserved */
|
||||
#define ADC_DR_RESULT_SHIFT (5) /* Bits 6-15: Result of conversion (DONE==1) */
|
||||
#define ADC_DR_RESULT_MASK (0x3ff << ADC_DR_RESULT_SHIFT)
|
||||
/* Bits 16-23: Reserved */
|
||||
#define ADC_DR_CHAN_SHIFT (24) /* Bits 24-26: Channel converted */
|
||||
#define ADC_DR_CHAN_MASK (3 << ADC_DR_CHN_SHIFT)
|
||||
/* Bits 27-29: Reserved */
|
||||
#define ADC_DR_OVERRUN (1 << 30) /* Bit 30: Conversion(s) lost/overwritten*/
|
||||
#define ADC_DR_DONE (1 << 31) /* Bit 31: A/D conversion complete*/
|
||||
|
||||
/* A/D Interrupt Enable Register */
|
||||
|
||||
#define ADC_INTEN_CHAN(n) (1 << (n))
|
||||
#define ADC_INTEN_CHAN0 (1 << 0) /* Bit 0: Enable ADC chan 0 complete intterrupt */
|
||||
#define ADC_INTEN_CHAN1 (1 << 1) /* Bit 1: Enable ADC chan 1 complete interrupt */
|
||||
#define ADC_INTEN_CHAN2 (1 << 2) /* Bit 2: Enable ADC chan 2 complete interrupt */
|
||||
#define ADC_INTEN_CHAN3 (1 << 3) /* Bit 3: Enable ADC chan 3 complete interrupt */
|
||||
#define ADC_INTEN_CHAN4 (1 << 4) /* Bit 4: Enable ADC chan 4 complete interrupt */
|
||||
#define ADC_INTEN_CHAN5 (1 << 5) /* Bit 5: Enable ADC chan 5 complete interrupt */
|
||||
#define ADC_INTEN_CHAN6 (1 << 6) /* Bit 6: Enable ADC chan 6 complete interrupt */
|
||||
#define ADC_INTEN_CHAN7 (1 << 7) /* Bit 7: Enable ADC chan 7 complete interrupt */
|
||||
#define ADC_INTEN_GLOBAL (1 << 8) /* Bit 8: Only the global DONE generates interrupt */
|
||||
/* Bits 9-31: Reserved */
|
||||
/* A/D Status Register */
|
||||
|
||||
#define ADC_STAT_DONE(n) (1 << (n))
|
||||
#define ADC_STAT_DONE0 (1 << 0) /* Bit 0: A/D chan 0 DONE */
|
||||
#define ADC_STAT_DONE1 (1 << 1) /* Bit 1: A/D chan 1 DONE */
|
||||
#define ADC_STAT_DONE2 (1 << 2) /* Bit 2: A/D chan 2 DONE */
|
||||
#define ADC_STAT_DONE3 (1 << 3) /* Bit 3: A/D chan 3 DONE */
|
||||
#define ADC_STAT_DONE4 (1 << 4) /* Bit 4: A/D chan 4 DONE */
|
||||
#define ADC_STAT_DONE5 (1 << 5) /* Bit 5: A/D chan 5 DONE */
|
||||
#define ADC_STAT_DONE6 (1 << 6) /* Bit 6: A/D chan 6 DONE */
|
||||
#define ADC_STAT_DONE7 (1 << 7) /* Bit 7: A/D chan 7 DONE */
|
||||
#define ADC_STAT_OVERRUN(n) ((1 << (n)) + 8)
|
||||
#define ADC_STAT_OVERRUN0 (1 << 8) /* Bit 8: A/D chan 0 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN1 (1 << 9) /* Bit 9: A/D chan 1 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN2 (1 << 10) /* Bit 10: A/D chan 2 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN3 (1 << 11) /* Bit 11: A/D chan 3 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN4 (1 << 12) /* Bit 12: A/D chan 4 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN5 (1 << 13) /* Bit 13: A/D chan 5 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN6 (1 << 14) /* Bit 14: A/D chan 6 OVERRUN */
|
||||
#define ADC_STAT_OVERRUN7 (1 << 15) /* Bit 15: A/D chan 7 OVERRUN */
|
||||
#define ADC_STAT_INT (1 << 16) /* Bit 15: A/D interrupt */
|
||||
/* Bits 17-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_ADC_H */
|
||||
@@ -0,0 +1,146 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc11_gpio.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_GPIO_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/lpc11_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
/* GPIO block register offsets ******************************************************/
|
||||
|
||||
#define LPC11_GPIO0_OFFSET 0x00000
|
||||
#define LPC11_GPIO1_OFFSET 0x10000
|
||||
#define LPC11_GPIO2_OFFSET 0x20000
|
||||
#define LPC11_GPIO3_OFFSET 0x30000
|
||||
#define LPC11_GPIO_OFFSET(n) (0x10000*(n))
|
||||
|
||||
#define LPC11_GPIO_DATA_OFFSET 0x3FFC
|
||||
#define LPC11_GPIO_DIR_OFFSET 0x8000 /* GPIO Port Direction control */
|
||||
#define LPC11_GPIO_IS_OFFSET 0x8004 /* Interrupt Sense register */
|
||||
#define LPC11_GPIO_IBE_OFFSET 0x8008 /* Interrupt Both Edges register */
|
||||
#define LPC11_GPIO_IEV_OFFSET 0x800c /* Interrupt Event register */
|
||||
#define LPC11_GPIO_IE_OFFSET 0x8010 /* Interrupt Mask register */
|
||||
#define LPC11_GPIO_RIS_OFFSET 0x8014 /* Raw interrupt status register */
|
||||
#define LPC11_GPIO_MIS_OFFSET 0x8018 /* Masked interrupt status register */
|
||||
#define LPC11_GPIO_IC_OFFSET 0x801c /* Interrupt clear register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
/* GPIO block register addresses ****************************************************/
|
||||
|
||||
#define LPC11_GPIOn_BASE(n) (LPC11_GPIO_BASE+LPC11_GPIO_OFFSET(n))
|
||||
#define LPC11_GPIO0_BASE (LPC11_GPIO_BASE+LPC11_GPIO0_OFFSET)
|
||||
#define LPC11_GPIO1_BASE (LPC11_GPIO_BASE+LPC11_GPIO1_OFFSET)
|
||||
#define LPC11_GPIO2_BASE (LPC11_GPIO_BASE+LPC11_GPIO2_OFFSET)
|
||||
#define LPC11_GPIO3_BASE (LPC11_GPIO_BASE+LPC11_GPIO3_OFFSET)
|
||||
|
||||
#define LPC11_GPIO_DIR(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_DIR_OFFSET) /* GPIO Port Direction register */
|
||||
#define LPC11_GPIO_IS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IS_OFFSET) /* GPIO Interrupt Sense register */
|
||||
#define LPC11_GPIO_IBE(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IBE_OFFSET) /* GPIO Interrupt Both Edges sense register */
|
||||
#define LPC11_GPIO_IEV(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IVE_OFFSET) /* GPIO Interrupt Event register */
|
||||
#define LPC11_GPIO_IE(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IE_OFFSET) /* GPIO Interrupt Mask register */
|
||||
#define LPC11_GPIO_RIS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_RIS_OFFSET) /* GPIO Raw Interrupt Status register */
|
||||
#define LPC11_GPIO_MIS(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_MIS_OFFSET) /* GPIO Masked Interrupt Status register */
|
||||
#define LPC11_GPIO_IC(n) (LPC11_GPIO_BASE(n)+LPC11_GPIO_IC_OFFSET) /* GPIO Interrupt Clear register */
|
||||
|
||||
#define LPC11_GPIO0_DATA (LPC11_GPIO0_BASE+LPC11_GPIO_DATA_OFFSET)
|
||||
#define LPC11_GPIO0_DIR (LPC11_GPIO0_BASE+LPC11_GPIO_DIR_OFFSET)
|
||||
#define LPC11_GPIO0_IS (LPC11_GPIO0_BASE+LPC11_GPIO_IS_OFFSET)
|
||||
#define LPC11_GPIO0_IBE (LPC11_GPIO0_BASE+LPC11_GPIO_IBE_OFFSET)
|
||||
#define LPC11_GPIO0_IEV (LPC11_GPIO0_BASE+LPC11_GPIO_IVE_OFFSET)
|
||||
#define LPC11_GPIO0_IE (LPC11_GPIO0_BASE+LPC11_GPIO_IE_OFFSET)
|
||||
#define LPC11_GPIO0_RIS (LPC11_GPIO0_BASE+LPC11_GPIO_RIS_OFFSET)
|
||||
#define LPC11_GPIO0_MIS (LPC11_GPIO0_BASE+LPC11_GPIO_MIS_OFFSET)
|
||||
#define LPC11_GPIO0_IC (LPC11_GPIO0_BASE+LPC11_GPIO_IC_OFFSET)
|
||||
|
||||
#define LPC11_GPIO1_DATA (LPC11_GPIO1_BASE+LPC11_GPIO_DATA_OFFSET)
|
||||
#define LPC11_GPIO1_DIR (LPC11_GPIO1_BASE+LPC11_GPIO_DIR_OFFSET)
|
||||
#define LPC11_GPIO1_IS (LPC11_GPIO1_BASE+LPC11_GPIO_IS_OFFSET)
|
||||
#define LPC11_GPIO1_IBE (LPC11_GPIO1_BASE+LPC11_GPIO_IBE_OFFSET)
|
||||
#define LPC11_GPIO1_IEV (LPC11_GPIO1_BASE+LPC11_GPIO_IVE_OFFSET)
|
||||
#define LPC11_GPIO1_IE (LPC11_GPIO1_BASE+LPC11_GPIO_IE_OFFSET)
|
||||
#define LPC11_GPIO1_RIS (LPC11_GPIO1_BASE+LPC11_GPIO_RIS_OFFSET)
|
||||
#define LPC11_GPIO1_MIS (LPC11_GPIO1_BASE+LPC11_GPIO_MIS_OFFSET)
|
||||
#define LPC11_GPIO1_IC (LPC11_GPIO1_BASE+LPC11_GPIO_IC_OFFSET)
|
||||
|
||||
#define LPC11_GPIO2_DATA (LPC11_GPIO2_BASE+LPC11_GPIO_DATA_OFFSET)
|
||||
#define LPC11_GPIO2_DIR (LPC11_GPIO2_BASE+LPC11_GPIO_DIR_OFFSET)
|
||||
#define LPC11_GPIO2_IS (LPC11_GPIO2_BASE+LPC11_GPIO_IS_OFFSET)
|
||||
#define LPC11_GPIO2_IBE (LPC11_GPIO2_BASE+LPC11_GPIO_IBE_OFFSET)
|
||||
#define LPC11_GPIO2_IEV (LPC11_GPIO2_BASE+LPC11_GPIO_IVE_OFFSET)
|
||||
#define LPC11_GPIO2_IE (LPC11_GPIO2_BASE+LPC11_GPIO_IE_OFFSET)
|
||||
#define LPC11_GPIO2_RIS (LPC11_GPIO2_BASE+LPC11_GPIO_RIS_OFFSET)
|
||||
#define LPC11_GPIO2_MIS (LPC11_GPIO2_BASE+LPC11_GPIO_MIS_OFFSET)
|
||||
#define LPC11_GPIO2_IC (LPC11_GPIO2_BASE+LPC11_GPIO_IC_OFFSET)
|
||||
|
||||
#define LPC11_GPIO3_DATA (LPC11_GPIO3_BASE+LPC11_GPIO_DATA_OFFSET)
|
||||
#define LPC11_GPIO3_DIR (LPC11_GPIO3_BASE+LPC11_GPIO_DIR_OFFSET)
|
||||
#define LPC11_GPIO3_IS (LPC11_GPIO3_BASE+LPC11_GPIO_IS_OFFSET)
|
||||
#define LPC11_GPIO3_IBE (LPC11_GPIO3_BASE+LPC11_GPIO_IBE_OFFSET)
|
||||
#define LPC11_GPIO3_IEV (LPC11_GPIO3_BASE+LPC11_GPIO_IVE_OFFSET)
|
||||
#define LPC11_GPIO3_IE (LPC11_GPIO3_BASE+LPC11_GPIO_IE_OFFSET)
|
||||
#define LPC11_GPIO3_RIS (LPC11_GPIO3_BASE+LPC11_GPIO_RIS_OFFSET)
|
||||
#define LPC11_GPIO3_MIS (LPC11_GPIO3_BASE+LPC11_GPIO_MIS_OFFSET)
|
||||
#define LPC11_GPIO3_IC (LPC11_GPIO3_BASE+LPC11_GPIO_IC_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* GPIO block register bit definitions **********************************************/
|
||||
|
||||
#define GPIO(n) (1 << (n)) /* n=0,1,..11 */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_CHIP_GPIO_H */
|
||||
@@ -0,0 +1,208 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc11_i2c.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_I2C_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_I2C_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/lpc11_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC11_I2C_CONSET_OFFSET 0x0000 /* I2C Control Set Register */
|
||||
#define LPC11_I2C_STAT_OFFSET 0x0004 /* I2C Status Register */
|
||||
#define LPC11_I2C_DAT_OFFSET 0x0008 /* I2C Data Register */
|
||||
#define LPC11_I2C_ADR0_OFFSET 0x000c /* I2C Slave Address Register 0 */
|
||||
#define LPC11_I2C_SCLH_OFFSET 0x0010 /* SCH Duty Cycle Register High Half Word */
|
||||
#define LPC11_I2C_SCLL_OFFSET 0x0014 /* SCL Duty Cycle Register Low Half Word */
|
||||
#define LPC11_I2C_CONCLR_OFFSET 0x0018 /* I2C Control Clear Register */
|
||||
#define LPC11_I2C_MMCTRL_OFFSET 0x001c /* Monitor mode control register */
|
||||
#define LPC11_I2C_ADR1_OFFSET 0x0020 /* I2C Slave Address Register 1 */
|
||||
#define LPC11_I2C_ADR2_OFFSET 0x0024 /* I2C Slave Address Register 2 */
|
||||
#define LPC11_I2C_ADR3_OFFSET 0x0028 /* I2C Slave Address Register 3 */
|
||||
#define LPC11_I2C_BUFR_OFFSET 0x002c /* Data buffer register */
|
||||
#define LPC11_I2C_MASK0_OFFSET 0x0030 /* I2C Slave address mask register 0 */
|
||||
#define LPC11_I2C_MASK1_OFFSET 0x0034 /* I2C Slave address mask register 1 */
|
||||
#define LPC11_I2C_MASK2_OFFSET 0x0038 /* I2C Slave address mask register 2 */
|
||||
#define LPC11_I2C_MASK3_OFFSET 0x003c /* I2C Slave address mask register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC11_I2C0_CONSET (LPC11_I2C0_BASE+LPC11_I2C_CONSET_OFFSET)
|
||||
#define LPC11_I2C0_STAT (LPC11_I2C0_BASE+LPC11_I2C_STAT_OFFSET)
|
||||
#define LPC11_I2C0_DAT (LPC11_I2C0_BASE+LPC11_I2C_DAT_OFFSET)
|
||||
#define LPC11_I2C0_ADR0 (LPC11_I2C0_BASE+LPC11_I2C_ADR0_OFFSET)
|
||||
#define LPC11_I2C0_SCLH (LPC11_I2C0_BASE+LPC11_I2C_SCLH_OFFSET)
|
||||
#define LPC11_I2C0_SCLL (LPC11_I2C0_BASE+LPC11_I2C_SCLL_OFFSET)
|
||||
#define LPC11_I2C0_CONCLR (LPC11_I2C0_BASE+LPC11_I2C_CONCLR_OFFSET)
|
||||
#define LPC11_I2C0_MMCTRL (LPC11_I2C0_BASE+LPC11_I2C_MMCTRL_OFFSET)
|
||||
#define LPC11_I2C0_ADR1 (LPC11_I2C0_BASE+LPC11_I2C_ADR1_OFFSET)
|
||||
#define LPC11_I2C0_ADR2 (LPC11_I2C0_BASE+LPC11_I2C_ADR2_OFFSET)
|
||||
#define LPC11_I2C0_ADR3 (LPC11_I2C0_BASE+LPC11_I2C_ADR3_OFFSET)
|
||||
#define LPC11_I2C0_BUFR (LPC11_I2C0_BASE+LPC11_I2C_BUFR_OFFSET)
|
||||
#define LPC11_I2C0_MASK0 (LPC11_I2C0_BASE+LPC11_I2C_MASK0_OFFSET)
|
||||
#define LPC11_I2C0_MASK1 (LPC11_I2C0_BASE+LPC11_I2C_MASK1_OFFSET)
|
||||
#define LPC11_I2C0_MASK2 (LPC11_I2C0_BASE+LPC11_I2C_MASK2_OFFSET)
|
||||
#define LPC11_I2C0_MASK3 (LPC11_I2C0_BASE+LPC11_I2C_MASK3_OFFSET)
|
||||
|
||||
#define LPC11_I2C1_CONSET (LPC11_I2C1_BASE+LPC11_I2C_CONSET_OFFSET)
|
||||
#define LPC11_I2C1_STAT (LPC11_I2C1_BASE+LPC11_I2C_STAT_OFFSET)
|
||||
#define LPC11_I2C1_DAT (LPC11_I2C1_BASE+LPC11_I2C_DAT_OFFSET)
|
||||
#define LPC11_I2C1_ADR0 (LPC11_I2C1_BASE+LPC11_I2C_ADR0_OFFSET)
|
||||
#define LPC11_I2C1_SCLH (LPC11_I2C1_BASE+LPC11_I2C_SCLH_OFFSET)
|
||||
#define LPC11_I2C1_SCLL (LPC11_I2C1_BASE+LPC11_I2C_SCLL_OFFSET)
|
||||
#define LPC11_I2C1_CONCLR (LPC11_I2C1_BASE+LPC11_I2C_CONCLR_OFFSET)
|
||||
#define LPC11_I2C1_MMCTRL (LPC11_I2C1_BASE+LPC11_I2C_MMCTRL_OFFSET)
|
||||
#define LPC11_I2C1_ADR1 (LPC11_I2C1_BASE+LPC11_I2C_ADR1_OFFSET)
|
||||
#define LPC11_I2C1_ADR2 (LPC11_I2C1_BASE+LPC11_I2C_ADR2_OFFSET)
|
||||
#define LPC11_I2C1_ADR3 (LPC11_I2C1_BASE+LPC11_I2C_ADR3_OFFSET)
|
||||
#define LPC11_I2C1_BUFR (LPC11_I2C1_BASE+LPC11_I2C_BUFR_OFFSET)
|
||||
#define LPC11_I2C1_MASK0 (LPC11_I2C1_BASE+LPC11_I2C_MASK0_OFFSET)
|
||||
#define LPC11_I2C1_MASK1 (LPC11_I2C1_BASE+LPC11_I2C_MASK1_OFFSET)
|
||||
#define LPC11_I2C1_MASK2 (LPC11_I2C1_BASE+LPC11_I2C_MASK2_OFFSET)
|
||||
#define LPC11_I2C1_MASK3 (LPC11_I2C1_BASE+LPC11_I2C_MASK3_OFFSET)
|
||||
|
||||
#define LPC11_I2C2_CONSET (LPC11_I2C2_BASE+LPC11_I2C_CONSET_OFFSET)
|
||||
#define LPC11_I2C2_STAT (LPC11_I2C2_BASE+LPC11_I2C_STAT_OFFSET)
|
||||
#define LPC11_I2C2_DAT (LPC11_I2C2_BASE+LPC11_I2C_DAT_OFFSET)
|
||||
#define LPC11_I2C2_ADR0 (LPC11_I2C2_BASE+LPC11_I2C_ADR0_OFFSET)
|
||||
#define LPC11_I2C2_SCLH (LPC11_I2C2_BASE+LPC11_I2C_SCLH_OFFSET)
|
||||
#define LPC11_I2C2_SCLL (LPC11_I2C2_BASE+LPC11_I2C_SCLL_OFFSET)
|
||||
#define LPC11_I2C2_CONCLR (LPC11_I2C2_BASE+LPC11_I2C_CONCLR_OFFSET)
|
||||
#define LPC11_I2C2_MMCTRL (LPC11_I2C2_BASE+LPC11_I2C_MMCTRL_OFFSET)
|
||||
#define LPC11_I2C2_ADR1 (LPC11_I2C2_BASE+LPC11_I2C_ADR1_OFFSET)
|
||||
#define LPC11_I2C2_ADR2 (LPC11_I2C2_BASE+LPC11_I2C_ADR2_OFFSET)
|
||||
#define LPC11_I2C2_ADR3 (LPC11_I2C2_BASE+LPC11_I2C_ADR3_OFFSET)
|
||||
#define LPC11_I2C2_BUFR (LPC11_I2C2_BASE+LPC11_I2C_BUFR_OFFSET)
|
||||
#define LPC11_I2C2_MASK0 (LPC11_I2C2_BASE+LPC11_I2C_MASK0_OFFSET)
|
||||
#define LPC11_I2C2_MASK1 (LPC11_I2C2_BASE+LPC11_I2C_MASK1_OFFSET)
|
||||
#define LPC11_I2C2_MASK2 (LPC11_I2C2_BASE+LPC11_I2C_MASK2_OFFSET)
|
||||
#define LPC11_I2C2_MASK3 (LPC11_I2C2_BASE+LPC11_I2C_MASK3_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* I2C Control Set Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define I2C_CONSET_AA (1 << 2) /* Bit 2: Assert acknowledge flag */
|
||||
#define I2C_CONSET_SI (1 << 3) /* Bit 3: I2C interrupt flag */
|
||||
#define I2C_CONSET_STO (1 << 4) /* Bit 4: STOP flag */
|
||||
#define I2C_CONSET_STA (1 << 5) /* Bit 5: START flag */
|
||||
#define I2C_CONSET_I2EN (1 << 6) /* Bit 6: I2C interface enable */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* I2C Control Clear Register */
|
||||
/* Bits 0-1: Reserved */
|
||||
#define I2C_CONCLR_AAC (1 << 2) /* Bit 2: Assert acknowledge Clear bit */
|
||||
#define I2C_CONCLR_SIC (1 << 3) /* Bit 3: I2C interrupt Clear bit */
|
||||
/* Bit 4: Reserved */
|
||||
#define I2C_CONCLR_STAC (1 << 5) /* Bit 5: START flag Clear bit */
|
||||
#define I2C_CONCLRT_I2ENC (1 << 6) /* Bit 6: I2C interface Disable bit */
|
||||
/* Bits 7-31: Reserved */
|
||||
/* I2C Status Register
|
||||
*
|
||||
* See tables 399-402 in the "LPC11xx User Manual" (UM10398), Rev. 01, 4 January
|
||||
* 2010, NXP for definitions of status codes.
|
||||
*/
|
||||
|
||||
#define I2C_STAT_MASK (0xff) /* Bits 0-7: I2C interface status
|
||||
* Bits 0-1 always zero */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Data Register */
|
||||
|
||||
#define I2C_DAT_MASK (0xff) /* Bits 0-7: I2C data */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* Monitor mode control register */
|
||||
|
||||
#define I2C_MMCTRL_MMENA (1 << 0) /* Bit 0: Monitor mode enable */
|
||||
#define I2C_MMCTRL_ENASCL (1 << 1) /* Bit 1: SCL output enable */
|
||||
#define I2C_MMCTRL_MATCHALL (1 << 2) /* Bit 2: Select interrupt register match */
|
||||
/* Bits 3-31: Reserved */
|
||||
/* Data buffer register */
|
||||
|
||||
#define I2C_BUFR_MASK (0xff) /* Bits 0-7: 8 MSBs of the I2DAT shift register */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Slave address registers:
|
||||
*
|
||||
* I2C Slave Address Register 0
|
||||
* I2C Slave Address Register 1
|
||||
* I2C Slave Address Register 2
|
||||
* I2C Slave Address Register 3
|
||||
*/
|
||||
|
||||
#define I2C_ADR_GC (1 << 0) /* Bit 0: GC General Call enable bit */
|
||||
#define I2C_ADR_ADDR_SHIFT (1) /* Bits 1-7: I2C slave address */
|
||||
#define I2C_ADR_ADDR_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* I2C Slave address mask registers:
|
||||
*
|
||||
* I2C Slave address mask register 0
|
||||
* I2C Slave address mask register 1
|
||||
* I2C Slave address mask register 2
|
||||
* I2C Slave address mask register 3
|
||||
*/
|
||||
/* Bit 0: Reserved */
|
||||
#define I2C_MASK_SHIFT (1) /* Bits 1-7: I2C mask bits */
|
||||
#define I2C_MASK_MASK (0x7f << I2C_ADR_ADDR_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SCH Duty Cycle Register High Half Word */
|
||||
|
||||
#define I2C_SCLH_MASK (0xffff) /* Bit 0-15: Count for SCL HIGH time period selection */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* SCL Duty Cycle Register Low Half Word */
|
||||
|
||||
#define I2C_SCLL_MASK (0xffff) /* Bit 0-15: Count for SCL LOW time period selection */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_I2C_H */
|
||||
@@ -0,0 +1,73 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc11_memorymap.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_MEMORYMAP_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_MEMORYMAP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* This file is only a thin shell that includes the correct memory map definitions
|
||||
* for the selected LPC11xx family.
|
||||
*/
|
||||
|
||||
#include <arch/lpc11xx/chip.h>
|
||||
|
||||
#if defined(LPC111x)
|
||||
# include "chip/lpc111x_memorymap.h"
|
||||
#else
|
||||
# error "Unrecognized LPC11xx family"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_MEMORYMAP_H */
|
||||
@@ -0,0 +1,73 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc11_pinconfig.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PINCONFIG_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PINCONFIG_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* This file is only a thin shell that includes the correct pin configuration
|
||||
* definitions for the selected LPC11xx family.
|
||||
*/
|
||||
|
||||
#include <arch/lpc11xx/chip.h>
|
||||
|
||||
#if defined(LPC111x)
|
||||
# include "chip/lpc111x_pinconfig.h"
|
||||
#else
|
||||
# error "Unrecognized LPC11xx family"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PINCONFIG_H */
|
||||
@@ -0,0 +1,106 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc11_pmu.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PMU_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PMU_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/lpc11_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC11_PMU_PCON_OFFSET 0x0000 /* Power control register */
|
||||
#define LPC11_PMU_GPREG0 0x0004 /* General purpose register 0 */
|
||||
#define LPC11_PMU_GPREG1 0x0008 /* General purpose register 1 */
|
||||
#define LPC11_PMU_GPREG2 0x000C /* General purpose register 2 */
|
||||
#define LPC11_PMU_GPREG3 0x0010 /* General purpose register 3 */
|
||||
#define LPC11_PMU_GPREG4 0x0014 /* General purpose register 0 */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC11_PMU_PCON (LPC11_PMU_BASE+LPC11_PMU_PCON_OFFSET)
|
||||
#define LPC11_PMU_GPREG0 (LPC11_PMU_BASE+LPC11_PMU_GPREG0)
|
||||
#define LPC11_PMU_GPREG1 (LPC11_PMU_BASE+LPC11_PMU_GPREG1)
|
||||
#define LPC11_PMU_GPREG2 (LPC11_PMU_BASE+LPC11_PMU_GPREG2)
|
||||
#define LPC11_PMU_GPREG3 (LPC11_PMU_BASE+LPC11_PMU_GPREG3)
|
||||
#define LPC11_PMU_GPREG4 (LPC11_PMU_BASE+LPC11_PMU_GPREG4)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* Power control register */
|
||||
/* Bit 0: Reserved. Do not write 1 to this bit */
|
||||
#define PMU_PCON_DPDEN (1 << 1) /* Deep power-down mode enable */
|
||||
/* Bits 2-7: Reserved. Do not write ones to this bit */
|
||||
#define PMU_PCON_SLEEPFLAG (1 << 8) /* Sleep mode flag */
|
||||
/* Bits 9-10: Reserved. Do not write ones to this bit */
|
||||
#define PMU_PCON_DPDFLAG (1 << 11) /* Deep power-down flag. */
|
||||
/* Bits 12-31: Reserved. Do not write ones to this bit */
|
||||
|
||||
|
||||
/* General Purpose REG */
|
||||
|
||||
#define PMU_GPREG03_GPDATA_MASK (0xffffffff) /* Bits 0-31: Data retained during Deep power-down mode */
|
||||
|
||||
|
||||
/* General Purpose REG4 Register */
|
||||
|
||||
/* Bits 0-9: Reserved. Do not write ones to this bit */
|
||||
#define PMU_GPREG4_WAKEUPHYS (1 << 10) /* WAKEUP pin hysteresis enable */
|
||||
#define PMU_GPREG4_GPDATA_SHIFT 11 /* Data retained during Deep power-down mode. */
|
||||
#define PMU_GPREG4_GPDATA_MASK (0x1fffff << PMU_GPREG4_GPDATA_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_PMU_H */
|
||||
@@ -0,0 +1,182 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc11_ssp.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SSP_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SSP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/lpc11_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC11_SSP_CR0_OFFSET 0x0000 /* Control Register 0 */
|
||||
#define LPC11_SSP_CR1_OFFSET 0x0004 /* Control Register 1 */
|
||||
#define LPC11_SSP_DR_OFFSET 0x0008 /* Data Register */
|
||||
#define LPC11_SSP_SR_OFFSET 0x000c /* Status Register */
|
||||
#define LPC11_SSP_CPSR_OFFSET 0x0010 /* Clock Prescale Register */
|
||||
#define LPC11_SSP_IMSC_OFFSET 0x0014 /* Interrupt Mask Set/Clear Register */
|
||||
#define LPC11_SSP_RIS_OFFSET 0x0018 /* Raw Interrupt Status Register */
|
||||
#define LPC11_SSP_MIS_OFFSET 0x001c /* Masked Interrupt Status Register */
|
||||
#define LPC11_SSP_ICR_OFFSET 0x0020 /* Interrupt Clear Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
/* SPI 0 */
|
||||
#define LPC11_SSP0_CR0 (LPC11_SPI0_BASE+LPC11_SSP_CR0_OFFSET)
|
||||
#define LPC11_SSP0_CR1 (LPC11_SPI0_BASE+LPC11_SSP_CR1_OFFSET)
|
||||
#define LPC11_SSP0_DR (LPC11_SPI0_BASE+LPC11_SSP_DR_OFFSET)
|
||||
#define LPC11_SSP0_SR (LPC11_SPI0_BASE+LPC11_SSP_SR_OFFSET)
|
||||
#define LPC11_SSP0_CPSR (LPC11_SPI0_BASE+LPC11_SSP_CPSR_OFFSET)
|
||||
#define LPC11_SSP0_IMSC (LPC11_SPI0_BASE+LPC11_SSP_IMSC_OFFSET)
|
||||
#define LPC11_SSP0_RIS (LPC11_SPI0_BASE+LPC11_SSP_RIS_OFFSET)
|
||||
#define LPC11_SSP0_MIS (LPC11_SPI0_BASE+LPC11_SSP_MIS_OFFSET)
|
||||
#define LPC11_SSP0_ICR (LPC11_SPI0_BASE+LPC11_SSP_ICR_OFFSET)
|
||||
|
||||
/* SPI 1 */
|
||||
#define LPC11_SSP1_CR0 (LPC11_SPI1_BASE+LPC11_SSP_CR0_OFFSET)
|
||||
#define LPC11_SSP1_CR1 (LPC11_SPI1_BASE+LPC11_SSP_CR1_OFFSET)
|
||||
#define LPC11_SSP1_DR (LPC11_SPI1_BASE+LPC11_SSP_DR_OFFSET)
|
||||
#define LPC11_SSP1_SR (LPC11_SPI1_BASE+LPC11_SSP_SR_OFFSET)
|
||||
#define LPC11_SSP1_CPSR (LPC11_SPI1_BASE+LPC11_SSP_CPSR_OFFSET)
|
||||
#define LPC11_SSP1_IMSC (LPC11_SPI1_BASE+LPC11_SSP_IMSC_OFFSET)
|
||||
#define LPC11_SSP1_RIS (LPC11_SPI1_BASE+LPC11_SSP_RIS_OFFSET)
|
||||
#define LPC11_SSP1_MIS (LPC11_SPI1_BASE+LPC11_SSP_MIS_OFFSET)
|
||||
#define LPC11_SSP1_ICR (LPC11_SPI1_BASE+LPC11_SSP_ICR_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* SPI/SSP Control Register 0 */
|
||||
|
||||
#define SSP_CR0_DSS_SHIFT (0) /* Data Size Select */
|
||||
#define SSP_CR0_DSS_MASK (15 << SSP_CR0_SHIFT)
|
||||
# define SSP_CR0_DSS_4BITS (3 << SSP_CR0_DSS_SHIFT) /* 4 bits per transfer */
|
||||
# define SSP_CR0_DSS_5BITS (4 << SSP_CR0_DSS_SHIFT) /* 5 bits per transfer */
|
||||
# define SSP_CR0_DSS_6BITS (5 << SSP_CR0_DSS_SHIFT) /* 6 bits per transfer */
|
||||
# define SSP_CR0_DSS_7BITS (6 << SSP_CR0_DSS_SHIFT) /* 7 bits per transfer */
|
||||
# define SSP_CR0_DSS_8BITS (7 << SSP_CR0_DSS_SHIFT) /* 8 bits per transfer */
|
||||
# define SSP_CR0_DSS_9BITS (8 << SSP_CR0_DSS_SHIFT) /* 9 bits per transfer */
|
||||
# define SSP_CR0_DSS_10BITS (9 << SSP_CR0_DSS_SHIFT) /* 10 bits per transfer */
|
||||
# define SSP_CR0_DSS_11BITS (10 << SSP_CR0_DSS_SHIFT) /* 11 bits per transfer */
|
||||
# define SSP_CR0_DSS_12BITS (11 << SSP_CR0_DSS_SHIFT) /* 12 bits per transfer */
|
||||
# define SSP_CR0_DSS_13BITS (12 << SSP_CR0_DSS_SHIFT) /* 13 bits per transfer */
|
||||
# define SSP_CR0_DSS_14BITS (13 << SSP_CR0_DSS_SHIFT) /* 14 bits per transfer */
|
||||
# define SSP_CR0_DSS_15BITS (14 << SSP_CR0_DSS_SHIFT) /* 15 bits per transfer */
|
||||
# define SSP_CR0_DSS_16BITS (15 << SSP_CR0_DSS_SHIFT) /* 16 bits per transfer */
|
||||
#define SSP_CR0_FRF_SHIFT (4) /* Frame Format */
|
||||
#define SSP_CR0_FRF_MASK (3 << SSP_CR0_FRF_SHIFT)
|
||||
# define SSP_CR0_FRF_SPI (0 << SSP_CR0_FRF_SHIFT) /* SPI Frame Format */
|
||||
# define SSP_CR0_FRF_TI (1 << SSP_CR0_FRF_SHIFT) /* TI Frame Format */
|
||||
# define SSP_CR0_FRF_MWIRE (2 << SSP_CR0_FRF_SHIFT) /* Microwire Frame Format */
|
||||
/* (3 << SSP_CR0_FRF_SHIFT) format is not supported */
|
||||
#define SSP_CR0_CPOL (1 << 6) /* Bit 6: Clock polarity control */
|
||||
#define SSP_CR0_CPHA (1 << 7) /* Bit 7: Clock phase control */
|
||||
#define SSP_CR0_SCR_SHIFT (8) /* Bit 8-15: Serial Clock Rate. PCLK/(CPSDVSR x [SCR + 1] */
|
||||
#define SSP_CR0_SCR_MASK (255 << SSP_CR0_SCR_SHIFT)
|
||||
|
||||
/* SPI/SSP Control Register 1 */
|
||||
|
||||
#define SSP_CR1_LBM (1 << 0) /* Bit 0: Loop Back Mode */
|
||||
#define SSP_CR1_SSE (1 << 1) /* Bit 1: SPI Enable */
|
||||
#define SSP_CR1_MS (1 << 2) /* Bit 2: Master/Slave Mode */
|
||||
#define SSP_CR1_SOD (1 << 3) /* Bit 3: Slave Output Disable */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
/* SPI/SSP Data Register */
|
||||
|
||||
#define SSP_DR_MASK (0xffff) /* Bits 0-15: Data */
|
||||
/* Bits 16-31: Reserved */
|
||||
/* SPI/SSP Status Register */
|
||||
|
||||
#define SSP_SR_TFE (1 << 0) /* Bit 0: Transmit FIFO Empty */
|
||||
#define SSP_SR_TNF (1 << 1) /* Bit 1: Transmit FIFO Not Full */
|
||||
#define SSP_SR_RNE (1 << 2) /* Bit 2: Receive FIFO Not Empty */
|
||||
#define SSP_SR_RFF (1 << 3) /* Bit 3: Receive FIFO Full */
|
||||
#define SSP_SR_BSY (1 << 4) /* Bit 4: Busy */
|
||||
/* Bits 5-31: Reserved */
|
||||
/* SPI/SSP Clock Prescale Register */
|
||||
|
||||
#define SSP_CPSR_DVSR_MASK (0xff) /* Even values between 2 and 254 */
|
||||
|
||||
/* SPI/SSP Interrupt Mask Set/Clear Register */
|
||||
|
||||
#define SSP_IMSC_RORIM (1 << 0) /* Bit 0: Enable Receive Overrun Interrupt */
|
||||
#define SSP_IMSC_RTIM (1 << 1) /* Bit 1: Enable Receive Timeout Interrupt */
|
||||
#define SSP_IMSC_RXIM (1 << 2) /* Bit 2: Enable Rx FIFO half full Interrupt */
|
||||
#define SSP_IMSC_TXIM (1 << 3) /* Bit 3: Enable Tx FIFO halt empty */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
/* SPI/SSP Raw Interrupt Status */
|
||||
|
||||
#define SSP_RIS_RORIS (1 << 0) /* Bit 0: An Overrun event occurred */
|
||||
#define SSP_RIS_RTRIS (1 << 1) /* Bit 1: Rx FIFO has data and MCU didn't read it */
|
||||
#define SSP_RIS_RXRIS (1 << 2) /* Bit 2: The Rx FIFO is at least half full */
|
||||
#define SSP_RIS_TXRIS (1 << 3) /* Bit 3: Tx FIFO is at least halt empty */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
/* SPI/SSP Masked Interrupt Status Register */
|
||||
|
||||
#define SSP_MIS_RORMIS (1 << 0) /* Bit 0: An Overrun occurred and this interrupt is enabled */
|
||||
#define SSP_MIS_RTMIS (1 << 1) /* Bit 1: An Rx FIFO timeout happened and this int is enabled */
|
||||
#define SSP_MIS_RXMIS (1 << 2) /* Bit 2: Rx FIFO is at least half empty and this int is enabled */
|
||||
#define SSP_MIS_TXMIS (1 << 3) /* Bit 3: Tx FIFO is at least halt full and this int is enabled */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* SPI/SSP Interrupt Clear Register */
|
||||
|
||||
#define SSP_ICR_RORIC (1 << 0) /* Bit 0: Clear Rx FIFO Overrun Interrupt */
|
||||
#define SSP_ICR_RTIC (1 << 1) /* Bit 1: Clear Rx FIFO read timeout Interrupt */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SPI_H */
|
||||
@@ -0,0 +1,449 @@
|
||||
/********************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc11_syscon.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
********************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SYSCON_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SYSCON_H
|
||||
|
||||
/********************************************************************************************
|
||||
* Included Files
|
||||
********************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/lpc11_memorymap.h"
|
||||
|
||||
/********************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
********************************************************************************************/
|
||||
|
||||
/* Register offsets *************************************************************************/
|
||||
|
||||
#define LPC11_SYSCON_SYSMEMREMAP_OFFSET 0x0000 /* System memory remap */
|
||||
#define LPC11_SYSCON_PRESETCTRL_OFFSET 0x0004 /* Pefipheral reset control */
|
||||
#define LPC11_SYSCON_SYSPLLCTRL_OFFSET 0x0008 /* System PLL control */
|
||||
#define LPC11_SYSCON_SYSPLLSTAT_OFFSET 0x000C /* System PLL status */
|
||||
/* 0x010 - 0x01c: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_SYSOSCCTRL_OFFSET 0x0020 /* System oscillator control */
|
||||
#define LPC11_SYSCON_WDTOSCCTRL_OFFSET 0x0024 /* Watchdog oscillator control */
|
||||
#define LPC11_SYSCON_IRCCTRL_OFFSET 0x0028 /* IRC control */
|
||||
/* 0x02c: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_SYSRSTSTAT_OFFSET 0x0030 /* System reset status register */
|
||||
/* 0x034 - 0x03c: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_SYSPLLCLKSEL_OFFSET 0x0040 /* System PLL clock source select */
|
||||
#define LPC11_SYSCON_SYSPLLCLKUEN_OFFSET 0x0044 /* System PLL clock source update enable */
|
||||
/* 0x048 - 0x06c: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_MAINCLKSEL_OFFSET 0x0070 /* Main clock source select */
|
||||
#define LPC11_SYSCON_MAINCLKUEN_OFFSET 0x0074 /* Main clock source update enable */
|
||||
#define LPC11_SYSCON_SYSAHBCLKDIV_OFFSET 0x0078 /* System AHB clock divider */
|
||||
/* 0x07c: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_SYSAHBCLKCTRL_OFFSET 0x0080 /* System AHB clock control */
|
||||
/* 0x084 - 0x090: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_SSP0CLKDIV_OFFSET 0x0094 /* SPI0 clock divider */
|
||||
#define LPC11_SYSCON_UARTCLKDIV_OFFSET 0x0098 /* UART clock divider */
|
||||
#define LPC11_SYSCON_SSP1CLKDIV_OFFSET 0x009c /* SPI1 clock divider */
|
||||
/* 0x0a0 - 0x0cc: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_WDTCLKSEL_OFFSET 0x00d0 /* WDT clock source select */
|
||||
#define LPC11_SYSCON_WDTCLKUEN_OFFSET 0x00d4 /* WDT clock source update enable */
|
||||
#define LPC11_SYSCON_WDTCLKDIV_OFFSET 0x00d8 /* WDT clock divider */
|
||||
/* 0x0dc: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_CLKOUTCLKSEL_OFFSET 0x00e0 /* CLKOUT clock source select */
|
||||
#define LPC11_SYSCON_CLKOUTUEN_OFFSET 0x00e4 /* CLKOUT clock source update enable */
|
||||
#define LPC11_SYSCON_CLKOUTCLKDIV_OFFSET 0x00e8 /* CLKOUT clock divider */
|
||||
/* 0x0ec - 0x0fc: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_PIOPORCAP0_OFFSET 0x0100 /* POR captured PIO status 0 */
|
||||
#define LPC11_SYSCON_PIOPORCAP1_OFFSET 0x0104 /* POR captured PIO status 1 */
|
||||
/* 0x108 - 0x14c: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_BODCTRL_OFFSET 0x0150 /* BOD control */
|
||||
#define LPC11_SYSCON_SYSTCKCAL_OFFSET 0x0154 /* System tick counter calibration */
|
||||
/* 0x158 - 0x16c: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_IRQLATENCY_OFFSET 0x0170 /* IRQ delay */
|
||||
#define LPC11_SYSCON_NMISRC_OFFSET 0x0174 /* NMI source selection */
|
||||
/* 0x178 - 0x1fc: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_STARTAPRP0_OFFSET 0x0200 /* Start logic edge control register 0 */
|
||||
#define LPC11_SYSCON_STARTERP0_OFFSET 0x0204 /* Start logic signal enable register 0 */
|
||||
#define LPC11_SYSCON_STARTRSRP0CLR_OFFSET 0x0208 /* Start logic reset register 0 */
|
||||
#define LPC11_SYSCON_STARTSRP0_OFFSET 0x020c /* Start logic status register 0 */
|
||||
/* 0x210 - 0x22c: Reserved */
|
||||
|
||||
#define LPC11_SYSCON_PDSLEEPCFG_OFFSET 0x0230 /* Power-down states in Deep-sleep mode */
|
||||
#define LPC11_SYSCON_PDAWAKECFG_OFFSET 0x0234 /* Power-down states after wake-up from Deep-sleep mode */
|
||||
#define LPC11_SYSCON_PDRUNCFG_OFFSET 0x0238 /* Power-down configuration register */
|
||||
/* 0x023c - 0x3f0: Reserved */
|
||||
#define LPC11_SYSCON_DEVICE_ID_OFFSET 0x03f4 /* Device ID register 0 for parts LPC1100, LPC1100C, LPC1100L */
|
||||
|
||||
|
||||
/* Register addresses ***********************************************************************/
|
||||
|
||||
#define LPC11_SYSCON_SYSMEMREMAP (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSMEMREMAP_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_PRESETCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_PRESETCTRL_OFFSET)
|
||||
#define LPC11_SYSCON_SYSPLLCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCTRL_OFFSET)
|
||||
#define LPC11_SYSCON_SYSPLLSTAT (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLSTAT_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_SYSOSCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSOSCCTRL_OFFSET)
|
||||
#define LPC11_SYSCON_WDTOSCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTOSCCTRL_OFFSET)
|
||||
#define LPC11_SYSCON_IRCCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_IRCCTRL_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_SYSRSTSTAT (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSRSTSTAT_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_SYSPLLCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCLKSEL_OFFSET)
|
||||
#define LPC11_SYSCON_SYSPLLCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSPLLCLKUEN_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_MAINCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_MAINCLKSEL_OFFSET)
|
||||
#define LPC11_SYSCON_MAINCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_MAINCLKUEN_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_SYSAHBCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSAHBCLKDIV_OFFSET)
|
||||
#define LPC11_SYSCON_SYSAHBCLKCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSAHBCLKCTRL_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_SSP0CLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SSP0CLKDIV_OFFSET)
|
||||
#define LPC11_SYSCON_UARTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_UARTCLKDIV_OFFSET)
|
||||
#define LPC11_SYSCON_SSP1CLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_SSP1CLKDIV_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_WDTCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKSEL_OFFSET)
|
||||
#define LPC11_SYSCON_WDTCLKUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKUEN_OFFSET)
|
||||
#define LPC11_SYSCON_WDTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_WDTCLKDIV_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_CLKOUTCLKSEL (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTCLKSEL_OFFSET)
|
||||
#define LPC11_SYSCON_CLKOUTUEN (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTUEN_OFFSET_OFFSET)
|
||||
#define LPC11_SYSCON_CLKOUTCLKDIV (LPC11_SYSCON_BASE + LPC11_SYSCON_CLKOUTCLKDIV_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_PIOPORCAP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_PIOPORCAP0_OFFSET)
|
||||
#define LPC11_SYSCON_PIOPORCAP1 (LPC11_SYSCON_BASE + LPC11_SYSCON_PIOPORCAP1_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_BODCTRL (LPC11_SYSCON_BASE + LPC11_SYSCON_BODCTRL_OFFSET)
|
||||
#define LPC11_SYSCON_SYSTCKCAL (LPC11_SYSCON_BASE + LPC11_SYSCON_SYSTCKCAL_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_IRQLATENCY (LPC11_SYSCON_BASE + LPC11_SYSCON_IRQLATENCY_OFFSET)
|
||||
#define LPC11_SYSCON_NMISRC (LPC11_SYSCON_BASE + LPC11_SYSCON_NMISRC_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_STARTAPRP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTAPRP0_OFFSET)
|
||||
#define LPC11_SYSCON_STARTERP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTERP0_OFFSET)
|
||||
#define LPC11_SYSCON_STARTRSRP0CLR (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTRSRP0CLR_OFFSET)
|
||||
#define LPC11_SYSCON_STARTSRP0 (LPC11_SYSCON_BASE + LPC11_SYSCON_STARTSRP0_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_PDSLEEPCFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDSLEEPCFG_OFFSET)
|
||||
#define LPC11_SYSCON_PDAWAKECFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDAWAKECFG_OFFSET)
|
||||
#define LPC11_SYSCON_PDRUNCFG (LPC11_SYSCON_BASE + LPC11_SYSCON_PDRUNCFG_OFFSET)
|
||||
|
||||
#define LPC11_SYSCON_DEVICE_ID (LPC11_SYSCON_BASE + LPC11_SYSCON_DEVICE_ID_OFFSET)
|
||||
|
||||
/* Register bit definitions *****************************************************************/
|
||||
|
||||
#define SYSCON_SYSMEMREMAP_MAP_SHIFT (0) /* Bits 0-1: System memory remap register */
|
||||
#define SYSCON_SYSMEMREMAP_MAP_MASK (3 << SYSCON_SYSMEMREMAP_MAP_SHIFT)
|
||||
# define SYSCON_SYSMEMREMAP_MAP_BOOTLOADER (0 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are re-mapped to Boot ROM */
|
||||
# define SYSCON_SYSMEMREMAP_MAP_RAM (1 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are re-mapped to Static RAM */
|
||||
# define SYSCON_SYSMEMREMAP_MAP_FLASH (2 << SYSCON_SYSMEMREMAP_MAP_SHIFT) /* Interrupt vectors are keeped in flash */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
#define SYSCON_PRESETCTRL_SSP0_RST_N (1 << 0) /* SPI0 reset control */
|
||||
#define SYSCON_PRESETCTRL_I2C_RST_N (1 << 1) /* I2C reset control */
|
||||
#define SYSCON_PRESETCTRL_SSP1_RST_N (1 << 2) /* SPI1 reset control */
|
||||
#define SYSCON_PRESETCTRL_CAN_RST_N (1 << 3) /* C_CAN reset control */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
#define SYSCON_SYSPLLCTRL_MSEL_SHIFT (0) /* Bits 0-4: Feedback divider value. */
|
||||
#define SYSCON_SYSPLLCTRL_MSEL_MASK (0x1f << SYSCON_SYSPLLCTRL_MSEL_SHIFT)
|
||||
# define SYSCON_SYSPLLCTRL_MSEL_DIV(n) ((n-1) << SYSCON_SYSPLLCTRL_MSEL_SHIFT) /* n=1,2,3,..32 */
|
||||
#define SYSCON_SYSPLLCTRL_PSEL_SHIFT (5) /* Bits 5-6: Post divider ratio P. The division ratio is 2 x P */
|
||||
#define SYSCON_SYSPLLCTRL_PSEL_MASK (3 << SYSCON_SYSPLLCTRL_PSEL_SHIFT)
|
||||
# define SYSCON_SYSPLLCTRL_PSEL_DIV1 (0 << SYSCON_SYSPLLCTRL_PSEL_SHIFT)
|
||||
# define SYSCON_SYSPLLCTRL_PSEL_DIV2 (1 << SYSCON_SYSPLLCTRL_PSEL_SHIFT)
|
||||
# define SYSCON_SYSPLLCTRL_PSEL_DIV4 (2 << SYSCON_SYSPLLCTRL_PSEL_SHIFT)
|
||||
# define SYSCON_SYSPLLCTRL_PSEL_DIV8 (3 << SYSCON_SYSPLLCTRL_PSEL_SHIFT)
|
||||
/* Bits 7-31: Reserved */
|
||||
|
||||
#define SYSCON_SYSPLLSTAT_LOCK (1 << 0) /* PLL lock status. 0 = PLL not locked, 1 = PLL locked */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
#define SYSCON_SYSOSCCTRL_BYPASS (1 << 0) /* Bypass system oscillator */
|
||||
#define SYSCON_SYSOSCCTRL_FREQRANGE (1 << 1) /* Determines freq. range for low-power oscillator */
|
||||
/* Bits 2-31: Reserved */
|
||||
#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0) /* Bits 0-4: Select divider for Fclkana. wdt_osc_clk = Fclkana/(2x(1+DIVSEL)) */
|
||||
#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1f << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)
|
||||
# define SYSCON_WDTOSCCTRL_DIVSEL(n) (((n-2)/2) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT) /* n = 2,4,8,..64 */
|
||||
#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5) /* Bits 5-8: Select watchdog oscillator analog output frequency */
|
||||
#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (15 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_0p6Mhz (1 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 0.6 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_1p05Mhz (2 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.05 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_1p4Mhz (3 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.4 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_1p75Mhz (4 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 1.75 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_2p1Mhz (5 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.1 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_2p4Mhz (6 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.4 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_2p7Mhz (7 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 2.7 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_3Mhz (8 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.0 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_3p25Mhz (9 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.25 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_3p5Mhz (10 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.5 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_3p75Mhz (11 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 3.75 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_4Mhz (12 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_4p2Mhz (13 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.2 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_4p4Mhz (14 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.4 MHz */
|
||||
# define SYSCON_WDTOSCCTRL_FREQSEL_4p6Mhz (15 << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT) /* Select watchdog osc analog freq 4.6 MHz */
|
||||
/* Bits 9-31: Reserved */
|
||||
|
||||
#define SYSCON_IRCCTRL_TRIM_MASK (0xff) /* Bits 0-7: Trim value used to adjust on-chip 12 MHz oscillator */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
#define SYSCON_SYSRSTSTAT_POR (1 << 0) /* POR reset status */
|
||||
#define SYSCON_SYSRSTSTAT_EXTRST (1 << 1) /* Status of the external /RESET pin */
|
||||
#define SYSCON_SYSRSTSTAT_WDT (1 << 2) /* Status of the Watchdog reset */
|
||||
#define SYSCON_SYSRSTSTAT_BOD (1 << 3) /* Status of Brown-out detect reset */
|
||||
#define SYSCON_SYSRSTSTAT_SYSRST (1 << 4) /* Status of the software system reset */
|
||||
/* Bits 5-31: Reserved */
|
||||
|
||||
#define SYSCON_SYSPLLCLKSEL_SHIFT (0) /* Bits 0-1: System PLL clock source */
|
||||
#define SYSCON_SYSPLLCLKSEL_MASK (3 << SYSCON_SYSPLLCLKSEL_SHIFT)
|
||||
# define SYSCON_SYSPLLCLKSEL_IRCOSC (0 << SYSCON_SYSPLLCLKSEL_SHIFT)
|
||||
# define SYSCON_SYSPLLCLKSEL_SYSOSC (1 << SYSCON_SYSPLLCLKSEL_SHIFT)
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
#define SYSCON_SYSPLLCLKUEN_ENA (1 << 0) /* Bit 0: Enable system PLL clock source update */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
#define SYSCON_MAINCLKSEL_SHIFT (0) /* Bits 0-1: Clock source for main clock */
|
||||
#define SYSCON_MAINCLKSEL_MASK (3 << SYSCON_MAINCLKSEL_SHIFT)
|
||||
# define SYSCON_MAINCLKSEL_IRCOSC (0 << SYSCON_MAINCLKSEL_SHIFT) /* IRC oscillator */
|
||||
# define SYSCON_MAINCLKSEL_PLLOSC (1 << SYSCON_MAINCLKSEL_SHIFT) /* Input clock to system PLL */
|
||||
# define SYSCON_MAINCLKSEL_WDTOSC (2 << SYSCON_MAINCLKSEL_SHIFT) /* WDT oscillator */
|
||||
# define SYSCON_MAINCLKSEL_SYSPLLCLKOUT (3 << SYSCON_MAINCLKSEL_SHIFT) /* System PLL clock out */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
#define SYSCON_MAINCLKUEN_ENA (1 << 0) /* Bit 0: Enable main clock source update */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
#define SYSCON_SYSAHBCLKDIV_SHIFT (0) /* Bits 0-7: 0=System clock disabled, 1=Divide by 1 ... 255 = Divide by 255 */
|
||||
#define SYSCON_SYSAHBCLKDIV_MASK (0xff << SYSCON_SYSAHBCLKDIV_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
//# define SYSCON_CCLKCFG_DIV(n) ((n-1) << SYSCON_CCLKCFG_SHIFT) /* n=2,3,..255 */
|
||||
|
||||
#define SYSCON_SYSAHBCLKCTRL_SYS (1 << 0) /* Bit 0: Enables clock for AHB to APB bridge */
|
||||
#define SYSCON_SYSAHBCLKCTRL_ROM (1 << 1) /* Bit 1: Enables clock for ROM */
|
||||
#define SYSCON_SYSAHBCLKCTRL_RAM (1 << 2) /* Bit 2: Enables clock for RAM */
|
||||
#define SYSCON_SYSAHBCLKCTRL_FLASHREG (1 << 3) /* Bit 3: Enables clock for flash register interface */
|
||||
#define SYSCON_SYSAHBCLKCTRL_FLASHARRAY (1 << 4) /* Bit 4: Enables clock for flash array access */
|
||||
#define SYSCON_SYSAHBCLKCTRL_I2C (1 << 5) /* Bit 5: Enables clock for I2C */
|
||||
#define SYSCON_SYSAHBCLKCTRL_GPIO (1 << 6) /* Bit 6: Enables clock for GPIO */
|
||||
#define SYSCON_SYSAHBCLKCTRL_CT16B0 (1 << 7) /* Bit 7: Enables clock for 16-bit counter/timer 0 */
|
||||
#define SYSCON_SYSAHBCLKCTRL_CT16B1 (1 << 8) /* Bit 8: Enables clock for 16-bit counter/timer 1 */
|
||||
#define SYSCON_SYSAHBCLKCTRL_CT32B0 (1 << 9) /* Bit 9: Enables clock for 32-bit counter/timer 0 */
|
||||
#define SYSCON_SYSAHBCLKCTRL_CT32B1 (1 << 10) /* Bit 10: Enables clock for 32-bit counter/timer 1 */
|
||||
#define SYSCON_SYSAHBCLKCTRL_SSP0 (1 << 11) /* Bit 11: Enables clock for SPI0 */
|
||||
#define SYSCON_SYSAHBCLKCTRL_UART (1 << 12) /* Bit 12: Enables clock for UART */
|
||||
#define SYSCON_SYSAHBCLKCTRL_ADC (1 << 13) /* Bit 13: Enables clock for ADC */
|
||||
/* Bit 14: Reserved */
|
||||
#define SYSCON_SYSAHBCLKCTRL_WDT (1 << 15) /* Bit 15: Enables clock for WDT */
|
||||
#define SYSCON_SYSAHBCLKCTRL_IOCON (1 << 16) /* Bit 16: Enables clock for I/O configuration block */
|
||||
#define SYSCON_SYSAHBCLKCTRL_CAN (1 << 17) /* Bit 17: Enables clock for C_CAN */
|
||||
#define SYSCON_SYSAHBCLKCTRL_SSP1 (1 << 18) /* Bit 18: Enables clock for SPI1 */
|
||||
/* Bits 19-31: Reserved */
|
||||
|
||||
#define SYSCON_SSP0CLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable SPI0_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
#define SYSCON_UARTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable UART_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
#define SYSCON_SSP1CLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable SPI1_PCLK, 1=Divide by 1 ... 255 = Divide by 255 */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
#define SYSCON_WDTCLKSEL_SHIFT (0) /* Bits 0-1: WDT clock source */
|
||||
#define SYSCON_WDTCLKSEL_MASK (3 << SYSCON_WDTCLKSEL_SHIFT)
|
||||
# define SYSCON_WDTCLKSEL_IRCOSC (0 << SYSCON_WDTCLKSEL_SHIFT) /* IRC oscillator */
|
||||
# define SYSCON_WDTCLKSEL_MAINCLK (1 << SYSCON_WDTCLKSEL_SHIFT) /* Main clock */
|
||||
# define SYSCON_WDTCLKSEL_WDTOSC (2 << SYSCON_WDTCLKSEL_SHIFT) /* Watchdog oscillator */
|
||||
/* Bits 2-31: reserved */
|
||||
|
||||
#define SYSCON_WDTCLKUEN_ENA (1 << 0) /* Bit 0: Enable WDT clock source update */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
#define SYSCON_WDTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable WDCLK, 1=Divide by 1 ... 255 = Divide by 255 */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
#define SYSCON_CLKOUTCLKSEL_SHIFT (0) /* Bits 0-1: CLKOUT clock source */
|
||||
#define SYSCON_CLKOUTCLKSEL_MASK (3 << SYSCON_CLKOUTCLKSEL_SHIFT)
|
||||
# define SYSCON_CLKOUTCLKSEL_IRCOSC (0 << SYSCON_CLKOUTCLKSEL_SHIFT) /* IRC oscillator */
|
||||
# define SYSCON_CLKOUTCLKSEL_SYSOSC (1 << SYSCON_CLKOUTCLKSEL_SHIFT) /* System oscillator */
|
||||
# define SYSCON_CLKOUTCLKSEL_WDTOSC (2 << SYSCON_CLKOUTCLKSEL_SHIFT) /* Watchdog oscillator */
|
||||
# define SYSCON_CLKOUTCLKSEL_MAINCLK (3 << SYSCON_CLKOUTCLKSEL_SHIFT) /* Main clock */
|
||||
/* Bits 2-31: Reserved */
|
||||
|
||||
#define SYSCON_CLKOUTUEN_ENA (1 << 0) /* Bit 0: Enable CLKOUT clock source update */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
#define SYSCON_CLKOUTCLKDIV_MASK (0xff) /* Bits 0-7: 0=Disable CLKOUT, 1=Divide by 1 ... 255 = Divide by 255 */
|
||||
/* Bits 1-31: Reserved */
|
||||
|
||||
#define SYSCON_PIOPORCAP0_CAPPIO0_SHIFT (0) /* Bits 0-11: Raw reset stats input PIO0_n: PIO0_11 to PIO0_0 */
|
||||
#define SYSCON_PIOPORCAP0_CAPPIO0_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO0_SHIFT)
|
||||
# define SYSCON_PIOPORCAP0_CAPPIO0_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO0_SHIFT) /* n = 0 to 11 */
|
||||
|
||||
#define SYSCON_PIOPORCAP0_CAPPIO1_SHIFT (12) /* Bits 12-23: Raw reset stats input PIO0_n: PIO1_11 to PIO1_0 */
|
||||
#define SYSCON_PIOPORCAP0_CAPPIO1_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO1_SHIFT)
|
||||
# define SYSCON_PIOPORCAP0_CAPPIO1_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO1_SHIFT) /* n = 0 to 11 */
|
||||
|
||||
#define SYSCON_PIOPORCAP0_CAPPIO2_SHIFT (24) /* Bits 24-31: Raw reset stats input PIO0_n: PIO2_11 to PIO2_0 */
|
||||
#define SYSCON_PIOPORCAP0_CAPPIO2_MASK (0xfff << SYSCON_PIOPORCAP0_CAPPIO2_SHIFT)
|
||||
# define SYSCON_PIOPORCAP0_CAPPIO2_BIT(n) ((1 << n) << SYSCON_PIOPORCAP0_CAPPIO2_SHIFT) /* n = 0 to 11 */
|
||||
|
||||
|
||||
#define SYSCON_PIOPORCAP1_CAPPIO2_8 (1 << 0) /* Bit 0: Raw reset status input PIO2_8 */
|
||||
#define SYSCON_PIOPORCAP1_CAPPIO2_9 (1 << 1) /* Bit 1: Raw reset status input PIO2_9 */
|
||||
#define SYSCON_PIOPORCAP1_CAPPIO2_10 (1 << 2) /* Bit 2: Raw reset status input PIO2_10 */
|
||||
#define SYSCON_PIOPORCAP1_CAPPIO2_11 (1 << 3) /* Bit 3: Raw reset status input PIO2_11 */
|
||||
#define SYSCON_PIOPORCAP1_CAPPIO3_0 (1 << 4) /* Bit 4: Raw reset status input PIO3_0 */
|
||||
#define SYSCON_PIOPORCAP1_CAPPIO3_1 (1 << 5) /* Bit 5: Raw reset status input PIO3_1 */
|
||||
#define SYSCON_PIOPORCAP1_CAPPIO3_2 (1 << 6) /* Bit 6: Raw reset status input PIO3_2 */
|
||||
#define SYSCON_PIOPORCAP1_CAPPIO3_3 (1 << 7) /* Bit 7: Raw reset status input PIO3_3 */
|
||||
#define SYSCON_PIOPORCAP1_CAPPIO3_4 (1 << 8) /* Bit 8: Raw reset status input PIO3_4 */
|
||||
#define SYSCON_PIOPORCAP1_CAPPIO3_5 (1 << 9) /* Bit 9: Raw reset status input PIO3_5 */
|
||||
/* Bits 10-31: Reserved */
|
||||
|
||||
#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0) /* Bits 0-1: BOD reset level */
|
||||
#define SYSCON_BODCTRL_BODRSTLEV_MASK (3 << SYSCON_BODCTRL_BODRSTLEV_SHIFT)
|
||||
# define SYSCON_BODCTRL_BODRSTLEV_LEVEL0 (0 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 0: assert 1.46V, de-assert 1.63V */
|
||||
# define SYSCON_BODCTRL_BODRSTLEV_LEVEL1 (1 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 1: assert 2.06V, de-assert 2.15V */
|
||||
# define SYSCON_BODCTRL_BODRSTLEV_LEVEL2 (2 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 2: assert 2.35V, de-assert 2.43V */
|
||||
# define SYSCON_BODCTRL_BODRSTLEV_LEVEL3 (3 << SYSCON_BODCTRL_BODRSTLEV_SHIFT) /* Level 3: assert 2.63V, de-assert 2.71V */
|
||||
#define SYSCON_BODCTRL_BODINTVAL_SHIFT (2) /* Bits 2-3: BOD interrupt level */
|
||||
#define SYSCON_BODCTRL_BODINTVAL_MASK (3 << SYSCON_BODCTRL_BODRSTLEV_BODINTVAL_SHIFT)
|
||||
# define SYSCON_BODCTRL_BODINTVAL_LEVEL0 (0 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 0: Reserved */
|
||||
# define SYSCON_BODCTRL_BODINTVAL_LEVEL1 (1 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 1: int. assert 2.22V,de-a. 2.35V */
|
||||
# define SYSCON_BODCTRL_BODINTVAL_LEVEL2 (2 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 2: int. assert 2.52V,de-a. 2.66V */
|
||||
# define SYSCON_BODCTRL_BODINTVAL_LEVEL3 (3 << SYSCON_BODCTRL_BODINTVAL_SHIFT) /* Level 3: int. assert 2.80V,de-a. 2.90V */
|
||||
#define SYSCON_BODCTRL_BODRSTENA (1 << 4) /* BOD reset enable */
|
||||
/* Bits 5-31: Reserved */
|
||||
|
||||
#define SYSCON_SYSTCKCAL_CAL 0x3ffffff /* Bits 0-25: System tick timer calibration value */
|
||||
/* Bits 26-31: Reserved */
|
||||
|
||||
#define SYSCON_IRQLATENCY_LATENCY_MASK (0xff) /* Bits 0-7: 8-bit latency value */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
#define SYSCON_NMISRC_IRQNO_SHIFT (0) /* Bits 0-4: The IRQ number of interrupt that acts as NMI if bit 31 is 1 */
|
||||
#define SYSCON_NMISRC_IRQNO_MASK (31 << SYSCON_NMISRC_IRQNO_SHIFT)
|
||||
/* Bits 5-30: Reserved */
|
||||
#define SYSCON_NMISRC_NMIEN (1 << 31) /* Write 1 to this bit to enable NMI source selected by bits 4:0 */
|
||||
|
||||
#define SYSCON_STARTAPRP0_APRPIO0_SHIFT (0) /* Bits 0-11: Edge select for start logic input PIO0_[0-11], 0=fall/1=rise */
|
||||
#define SYSCON_STARTAPRP0_APRPIO0_MASK (0xfff << SYSCON_STARTAPRP0_APRPIO0_SHIFT)
|
||||
# define SYSCON_STARTAPRP0_APRPIO0_BIT(n) ((1 << n) << SYSCON_STARTAPRP0_APRPIO0_SHIFT) /* n = 0 to 11 */
|
||||
#define SYSCON_STARTAPRP0_APRPIO1_0 (1 << 12) /* Bit 12: Edge select start logic input PIO1_0, 0=falling/1=rising */
|
||||
/* Bits 13-31: Reserved */
|
||||
|
||||
#define SYSCON_STARTERP0_ERPIO0_SHIFT (0) /* Bits 0-11: Enable start signal for start logic input PIO0[0-11] */
|
||||
#define SYSCON_STARTERP0_ERPIO0_MASK (0xfff << SYSCON_STARTERP0_ERPIO0_SHIFT)
|
||||
# define SYSCON_STARTERP0_ERPIO0_BIT(n) ((1 << n) << SYSCON_STARTERP0_ERPIO0_SHIFT) /* n = 0 to 11 */
|
||||
#define SYSCON_STARTERP0_ERPIO1_0 (1 << 12) /* Bit 12: Enable start signal for start logic input PIO1_0 */
|
||||
/* Bits 13-31: Reserved */
|
||||
|
||||
#define SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT (0) /* Bits 0-11: Start logic reset register 0 */
|
||||
#define SYSCON_STARTRSRP0CLR_RSRPIO0_MASK (0xfff << SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT)
|
||||
# define SYSCON_STARTRSRP0CLR_RSRPIO0_BIT(n) ((1 << n) << SYSCON_STARTRSRP0CLR_RSRPIO0_SHIFT) /* n = 0 to 11 */
|
||||
#define SYSCON_STARTRSRP0CLR_RSRPIO1_0 (1 << 12) /* Bit 12: Start signal reset for start logic input PIO1_0 */
|
||||
/* Bits 13-31: Reserved */
|
||||
|
||||
#define SYSCON_STARTSRP0_SRPIO0_SHIFT (0) /* Bits 0-11: Start logic status register 0 */
|
||||
#define SYSCON_STARTSRP0_SRPIO0_MASK (0xfff << SYSCON_STARTSRP0_SRPIO0_SHIFT)
|
||||
# define SYSCON_STARTSRP0_SRPIO0_BIT(n) ((1 << n) << SYSCON_STARTSRP0_SRPIO0_SHIFT) /* n = 0 to 11 */
|
||||
#define SYSCON_STARTSRP0_SRPIO1_0 (1 << 12) /* Bit 12: Start signal status for start logic input PIO1_0 */
|
||||
/* Bits 13-31: Reserved */
|
||||
|
||||
/* Bits 0-2: Reserved. NOTE: Always write these bits as 111 */
|
||||
#define SYSCON_PDSLEEPCFG_BOD_PD (1 << 3) /* BOD power-down control in Deep-sleep mode */
|
||||
/* Bits 4-5: Reserved. NOTE: Always write these bits as 11 */
|
||||
#define SYSCON_PDSLEEPCFG_WDTOSC_PD (1 << 6) /* Watchdog oscillator power control in Deep-sleep mode */
|
||||
/* Bit 7: Reserved. NOTE: Always write this bit as 1 */
|
||||
/* Bits 8-10: Reserved NOTE: Always write these bits as 000 */
|
||||
/* Bits 11-12: Reserved. NOTE: Always write these bits as 11 */
|
||||
/* Bits 13-31: Reserved */
|
||||
|
||||
#define SYSCON_PDAWAKECFG_IRCOUT_PD (1 << 0) /* Bit 0: IRC oscillator output wake-up configuration */
|
||||
#define SYSCON_PDAWAKECFG_IRC_PD (1 << 1) /* Bit 1: IRC oscillator wake-up configuration */
|
||||
#define SYSCON_PDAWAKECFG_FLASH_PD (1 << 2) /* Bit 2: Flash wake-up configuration */
|
||||
#define SYSCON_PDAWAKECFG_BOD_PD (1 << 3) /* Bit 3: Brownout Detection wake-up configuration */
|
||||
#define SYSCON_PDAWAKECFG_ADC_PD (1 << 4) /* Bit 4: ADC wake-up configuration */
|
||||
#define SYSCON_PDAWAKECFG_SYSOSC_PD (1 << 5) /* Bit 5: System oscillator wake-up configuration */
|
||||
#define SYSCON_PDAWAKECFG_WDTOSC_PD (1 << 6) /* Bit 6: Watchdog oscillator wake-up configuration */
|
||||
#define SYSCON_PDAWAKECFG_SYSPLL_PD (1 << 7) /* Bit 7: System PLL wake-up configuration */
|
||||
/* Bit 8: Reserved. NOTE: Always write this bit as 1 */
|
||||
/* Bit 9: Reserved. NOTE: Always write this bit as 0 */
|
||||
/* Bit 10: Reserved. NOTE: Always write this bit as 1 */
|
||||
/* Bit 11: Reserved. NOTE: Always write this bit as 1 */
|
||||
/* Bit 12: Reserved. NOTE: Always write this bit as 0 */
|
||||
/* Bits 13-15: Reserved. NOTE: Always write these bits as 111 */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
#define SYSCON_PDRUNCFG_IRCOUT_PD (1 << 0) /* Bit 0: IRC oscillator output power-down */
|
||||
#define SYSCON_PDRUNCFG_IRC_PD (1 << 1) /* Bit 1: IRC oscillator power-down */
|
||||
#define SYSCON_PDRUNCFG_FLASH_PD (1 << 2) /* Bit 2: Flash power-down */
|
||||
#define SYSCON_PDRUNCFG_BOD_PD (1 << 3) /* Bit 3: Brownout Detection power-down */
|
||||
#define SYSCON_PDRUNCFG_ADC_PD (1 << 4) /* Bit 4: ADC power-down */
|
||||
#define SYSCON_PDRUNCFG_SYSOSC_PD (1 << 5) /* Bit 5: System oscillator power-down */
|
||||
#define SYSCON_PDRUNCFG_WDTOSC_PD (1 << 6) /* Bit 6: Watchdog oscillator power-down */
|
||||
#define SYSCON_PDRUNCFG_SYSPLL_PD (1 << 7) /* Bit 7: System PLL power-down */
|
||||
/* Bit 8: Reserved. NOTE: Always write this bit as 1 */
|
||||
/* Bit 9: Reserved. NOTE: Always write this bit as 0 */
|
||||
/* Bit 10: Reserved. NOTE: Always write this bit as 1 */
|
||||
/* Bit 11: Reserved. NOTE: Always write this bit as 1 */
|
||||
/* Bit 12: Reserved. NOTE: Always write this bit as 0 */
|
||||
/* Bits 13-15: Reserved. NOTE: Always write these bits as 111 */
|
||||
/* Bits 16-31: Reserved */
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Types
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Data
|
||||
********************************************************************************************/
|
||||
|
||||
/********************************************************************************************
|
||||
* Public Functions
|
||||
********************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_SYSCON_H */
|
||||
@@ -0,0 +1,271 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc11_timer.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_TIMER_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_TIMER_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/lpc11_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC11_TMR_IR_OFFSET 0x0000 /* Interrupt Register */
|
||||
#define LPC11_TMR_TCR_OFFSET 0x0004 /* Timer Control Register */
|
||||
#define LPC11_TMR_TC_OFFSET 0x0008 /* Timer Counter */
|
||||
#define LPC11_TMR_PR_OFFSET 0x000c /* Prescale Register */
|
||||
#define LPC11_TMR_PC_OFFSET 0x0010 /* Prescale Counter */
|
||||
#define LPC11_TMR_MCR_OFFSET 0x0014 /* Match Control Register */
|
||||
#define LPC11_TMR_MR0_OFFSET 0x0018 /* Match Register 0 */
|
||||
#define LPC11_TMR_MR1_OFFSET 0x001c /* Match Register 1 */
|
||||
#define LPC11_TMR_MR2_OFFSET 0x0020 /* Match Register 2 */
|
||||
#define LPC11_TMR_MR3_OFFSET 0x0024 /* Match Register 3 */
|
||||
#define LPC11_TMR_CCR_OFFSET 0x0028 /* Capture Control Register */
|
||||
#define LPC11_TMR_CR0_OFFSET 0x002c /* Capture Register 0 */
|
||||
#define LPC11_TMR_CR1_OFFSET 0x0030 /* Capture Register 1 */
|
||||
#define LPC11_TMR_EMR_OFFSET 0x003c /* External Match Register */
|
||||
#define LPC11_TMR_CTCR_OFFSET 0x0070 /* Count Control Register */
|
||||
#define LPC11_TMR_PWMC_OFFSET 0x0074 /* PWM Control Register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC11_TMR16B0IR (LPC11_TMR16B0_BASE+LPC11_TMR_IR_OFFSET)
|
||||
#define LPC11_TMR16B0TCR (LPC11_TMR16B0_BASE+LPC11_TMR_TCR_OFFSET)
|
||||
#define LPC11_TMR16B0TC (LPC11_TMR16B0_BASE+LPC11_TMR_TC_OFFSET)
|
||||
#define LPC11_TMR16B0PR (LPC11_TMR16B0_BASE+LPC11_TMR_PR_OFFSET)
|
||||
#define LPC11_TMR16B0PC (LPC11_TMR16B0_BASE+LPC11_TMR_PC_OFFSET)
|
||||
#define LPC11_TMR16B0MCR (LPC11_TMR16B0_BASE+LPC11_TMR_MCR_OFFSET)
|
||||
#define LPC11_TMR16B0MR0 (LPC11_TMR16B0_BASE+LPC11_TMR_MR0_OFFSET)
|
||||
#define LPC11_TMR16B0MR1 (LPC11_TMR16B0_BASE+LPC11_TMR_MR1_OFFSET)
|
||||
#define LPC11_TMR16B0MR2 (LPC11_TMR16B0_BASE+LPC11_TMR_MR2_OFFSET)
|
||||
#define LPC11_TMR16B0MR3 (LPC11_TMR16B0_BASE+LPC11_TMR_MR3_OFFSET)
|
||||
#define LPC11_TMR16B0CCR (LPC11_TMR16B0_BASE+LPC11_TMR_CCR_OFFSET)
|
||||
#define LPC11_TMR16B0CR0 (LPC11_TMR16B0_BASE+LPC11_TMR_CR0_OFFSET)
|
||||
#define LPC11_TMR16B0CR1 (LPC11_TMR16B0_BASE+LPC11_TMR_CR1_OFFSET)
|
||||
#define LPC11_TMR16B0EMR (LPC11_TMR16B0_BASE+LPC11_TMR_EMR_OFFSET)
|
||||
#define LPC11_TMR16B0CTCR (LPC11_TMR16B0_BASE+LPC11_TMR_CTCR_OFFSET)
|
||||
#define LPC11_TMR16B0PWMC (LPC11_TMR16B0_BASE+LPC11_TMR_PWMC_OFFSET)
|
||||
|
||||
#define LPC11_TMR16B1IR (LPC11_TMR16B1_BASE+LPC11_TMR_IR_OFFSET)
|
||||
#define LPC11_TMR16B1TCR (LPC11_TMR16B1_BASE+LPC11_TMR_TCR_OFFSET)
|
||||
#define LPC11_TMR16B1TC (LPC11_TMR16B1_BASE+LPC11_TMR_TC_OFFSET)
|
||||
#define LPC11_TMR16B1PR (LPC11_TMR16B1_BASE+LPC11_TMR_PR_OFFSET)
|
||||
#define LPC11_TMR16B1PC (LPC11_TMR16B1_BASE+LPC11_TMR_PC_OFFSET)
|
||||
#define LPC11_TMR16B1MCR (LPC11_TMR16B1_BASE+LPC11_TMR_MCR_OFFSET)
|
||||
#define LPC11_TMR16B1MR0 (LPC11_TMR16B1_BASE+LPC11_TMR_MR0_OFFSET)
|
||||
#define LPC11_TMR16B1MR1 (LPC11_TMR16B1_BASE+LPC11_TMR_MR1_OFFSET)
|
||||
#define LPC11_TMR16B1MR2 (LPC11_TMR16B1_BASE+LPC11_TMR_MR2_OFFSET)
|
||||
#define LPC11_TMR16B1MR3 (LPC11_TMR16B1_BASE+LPC11_TMR_MR3_OFFSET)
|
||||
#define LPC11_TMR16B1CCR (LPC11_TMR16B1_BASE+LPC11_TMR_CCR_OFFSET)
|
||||
#define LPC11_TMR16B1CR0 (LPC11_TMR16B1_BASE+LPC11_TMR_CR0_OFFSET)
|
||||
#define LPC11_TMR16B1CR1 (LPC11_TMR16B1_BASE+LPC11_TMR_CR1_OFFSET)
|
||||
#define LPC11_TMR16B1EMR (LPC11_TMR16B1_BASE+LPC11_TMR_EMR_OFFSET)
|
||||
#define LPC11_TMR16B1CTCR (LPC11_TMR16B1_BASE+LPC11_TMR_CTCR_OFFSET)
|
||||
#define LPC11_TMR16B1PWMC (LPC11_TMR16B1_BASE+LPC11_TMR_PWMC_OFFSET)
|
||||
|
||||
#define LPC11_TMR32B0IR (LPC11_TMR32B0_BASE+LPC11_TMR_IR_OFFSET)
|
||||
#define LPC11_TMR32B0TCR (LPC11_TMR32B0_BASE+LPC11_TMR_TCR_OFFSET)
|
||||
#define LPC11_TMR32B0TC (LPC11_TMR32B0_BASE+LPC11_TMR_TC_OFFSET)
|
||||
#define LPC11_TMR32B0PR (LPC11_TMR32B0_BASE+LPC11_TMR_PR_OFFSET)
|
||||
#define LPC11_TMR32B0PC (LPC11_TMR32B0_BASE+LPC11_TMR_PC_OFFSET)
|
||||
#define LPC11_TMR32B0MCR (LPC11_TMR32B0_BASE+LPC11_TMR_MCR_OFFSET)
|
||||
#define LPC11_TMR32B0MR0 (LPC11_TMR32B0_BASE+LPC11_TMR_MR0_OFFSET)
|
||||
#define LPC11_TMR32B0MR1 (LPC11_TMR32B0_BASE+LPC11_TMR_MR1_OFFSET)
|
||||
#define LPC11_TMR32B0MR2 (LPC11_TMR32B0_BASE+LPC11_TMR_MR2_OFFSET)
|
||||
#define LPC11_TMR32B0MR3 (LPC11_TMR32B0_BASE+LPC11_TMR_MR3_OFFSET)
|
||||
#define LPC11_TMR32B0CCR (LPC11_TMR32B0_BASE+LPC11_TMR_CCR_OFFSET)
|
||||
#define LPC11_TMR32B0CR0 (LPC11_TMR32B0_BASE+LPC11_TMR_CR0_OFFSET)
|
||||
#define LPC11_TMR32B0CR1 (LPC11_TMR32B0_BASE+LPC11_TMR_CR1_OFFSET)
|
||||
#define LPC11_TMR32B0EMR (LPC11_TMR32B0_BASE+LPC11_TMR_EMR_OFFSET)
|
||||
#define LPC11_TMR32B0CTCR (LPC11_TMR32B0_BASE+LPC11_TMR_CTCR_OFFSET)
|
||||
#define LPC11_TMR32B0PWMC (LPC11_TMR32B0_BASE+LPC11_TMR_PWMC_OFFSET)
|
||||
|
||||
#define LPC11_TMR32B1IR (LPC11_TMR32B1_BASE+LPC11_TMR_IR_OFFSET)
|
||||
#define LPC11_TMR32B1TCR (LPC11_TMR32B1_BASE+LPC11_TMR_TCR_OFFSET)
|
||||
#define LPC11_TMR32B1TC (LPC11_TMR32B1_BASE+LPC11_TMR_TC_OFFSET)
|
||||
#define LPC11_TMR32B1PR (LPC11_TMR32B1_BASE+LPC11_TMR_PR_OFFSET)
|
||||
#define LPC11_TMR32B1PC (LPC11_TMR32B1_BASE+LPC11_TMR_PC_OFFSET)
|
||||
#define LPC11_TMR32B1MCR (LPC11_TMR32B1_BASE+LPC11_TMR_MCR_OFFSET)
|
||||
#define LPC11_TMR32B1MR0 (LPC11_TMR32B1_BASE+LPC11_TMR_MR0_OFFSET)
|
||||
#define LPC11_TMR32B1MR1 (LPC11_TMR32B1_BASE+LPC11_TMR_MR1_OFFSET)
|
||||
#define LPC11_TMR32B1MR2 (LPC11_TMR32B1_BASE+LPC11_TMR_MR2_OFFSET)
|
||||
#define LPC11_TMR32B1MR3 (LPC11_TMR32B1_BASE+LPC11_TMR_MR3_OFFSET)
|
||||
#define LPC11_TMR32B1CCR (LPC11_TMR32B1_BASE+LPC11_TMR_CCR_OFFSET)
|
||||
#define LPC11_TMR32B1CR0 (LPC11_TMR32B1_BASE+LPC11_TMR_CR0_OFFSET)
|
||||
#define LPC11_TMR32B1CR1 (LPC11_TMR32B1_BASE+LPC11_TMR_CR1_OFFSET)
|
||||
#define LPC11_TMR32B1EMR (LPC11_TMR32B1_BASE+LPC11_TMR_EMR_OFFSET)
|
||||
#define LPC11_TMR32B1CTCR (LPC11_TMR32B1_BASE+LPC11_TMR_CTCR_OFFSET)
|
||||
#define LPC11_TMR32B1PWMC (LPC11_TMR32B1_BASE+LPC11_TMR_PWMC_OFFSET)
|
||||
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
/* Registers holding 32-bit numeric values (no bit field definitions):
|
||||
*
|
||||
* Timer Counter (TC)
|
||||
* Prescale Register (PR)
|
||||
* Prescale Counter (PC)
|
||||
* Match Register 0 (MR0)
|
||||
* Match Register 1 (MR1)
|
||||
* Match Register 2 (MR2)
|
||||
* Match Register 3 (MR3)
|
||||
* Capture Register 0 (CR0)
|
||||
* Capture Register 1 (CR1)
|
||||
*/
|
||||
|
||||
/* Interrupt Register */
|
||||
|
||||
#define TMR_MR0INT (1 << 0) /* Bit 0: Match channel 0 interrupt */
|
||||
#define TMR_MR1INT (1 << 1) /* Bit 1: Match channel 1 interrupt */
|
||||
#define TMR_MR2INT (1 << 2) /* Bit 2: Match channel 2 interrupt */
|
||||
#define TMR_MR3INT (1 << 3) /* Bit 3: Match channel 3 interrupt */
|
||||
#define TMR_CR0INT (1 << 4) /* Bit 4: Capture channel 0 interrupt */
|
||||
#define TMR_CR1INT (1 << 5) /* Bit 5: Capture channel 1 interrupt */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* Timer Control Register */
|
||||
|
||||
#define TMR_TCR_CEN (1 << 0) /* Bit 0: Counter Enable */
|
||||
#define TMR_TCR_CRST (1 << 1) /* Bit 1: Counter Reset */
|
||||
/* Bits 2-31: Reserved */
|
||||
/* Match Control Register */
|
||||
|
||||
#define TMR_MCR_MR0I (1 << 0) /* Bit 0: Interrupt on MR0 */
|
||||
#define TMR_MCR_MR0R (1 << 1) /* Bit 1: Reset on MR0 */
|
||||
#define TMR_MCR_MR0S (1 << 2) /* Bit 2: Stop on MR0 */
|
||||
#define TMR_MCR_MR1I (1 << 3) /* Bit 3: Interrupt on MR1 */
|
||||
#define TMR_MCR_MR1R (1 << 4) /* Bit 4: Reset on MR1 */
|
||||
#define TMR_MCR_MR1S (1 << 5) /* Bit 5: Stop on MR1 */
|
||||
#define TMR_MCR_MR2I (1 << 6) /* Bit 6: Interrupt on MR2 */
|
||||
#define TMR_MCR_MR2R (1 << 7) /* Bit 7: Reset on MR2 */
|
||||
#define TMR_MCR_MR2S (1 << 8) /* Bit 8: Stop on MR2 */
|
||||
#define TMR_MCR_MR3I (1 << 9) /* Bit 9: Interrupt on MR3 */
|
||||
#define TMR_MCR_MR3R (1 << 10) /* Bit 10: Reset on MR3 */
|
||||
#define TMR_MCR_MR3S (1 << 11) /* Bit 11: Stop on MR3 */
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Capture Control Register */
|
||||
|
||||
#define TMR_CCR_CAP0RE (1 << 0) /* Bit 0: Capture on CAPn.0 rising edge */
|
||||
#define TMR_CCR_CAP0FE (1 << 1) /* Bit 1: Capture on CAPn.0 falling edge */
|
||||
#define TMR_CCR_CAP0I (1 << 2) /* Bit 2: Interrupt on CAPn.0 */
|
||||
#define TMR_CCR_CAP1RE (1 << 3) /* Bit 3: Capture on CAPn.1 rising edge */
|
||||
#define TMR_CCR_CAP1FE (1 << 4) /* Bit 4: Capture on CAPn.1 falling edge */
|
||||
#define TMR_CCR_CAP1I (1 << 5) /* Bit 5: Interrupt on CAPn.1 */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* External Match Register */
|
||||
|
||||
#define TMR_EMR_NOTHING (0) /* Do Nothing */
|
||||
#define TMR_EMR_CLEAR (1) /* Clear external match bit MATn.m */
|
||||
#define TMR_EMR_SET (2) /* Set external match bit MATn.m */
|
||||
#define TMR_EMR_TOGGLE (3) /* Toggle external match bit MATn.m */
|
||||
|
||||
#define TMR_EMR_EM0 (1 << 0) /* Bit 0: External Match 0 */
|
||||
#define TMR_EMR_EM1 (1 << 1) /* Bit 1: External Match 1 */
|
||||
#define TMR_EMR_EM2 (1 << 2) /* Bit 2: External Match 2 */
|
||||
#define TMR_EMR_EM3 (1 << 3) /* Bit 3: External Match 3 */
|
||||
#define TMR_EMR_EMC0_SHIFT (4) /* Bits 4-5: External Match Control 0 */
|
||||
#define TMR_EMR_EMC0_MASK (3 << TMR_EMR_EMC0_SHIFTy)
|
||||
# define TMR_EMR_EMC0_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_SET (TMR_EMR_SET << TMR_EMR_EMC0_SHIFT)
|
||||
# define TMR_EMR_EMC0_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC0_SHIFT)
|
||||
#define TMR_EMR_EMC1_SHIFT (6) /* Bits 6-7: External Match Control 1 */
|
||||
#define TMR_EMR_EMC1_MASK (3 << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_SET (TMR_EMR_SET << TMR_EMR_EMC1_SHIFT)
|
||||
# define TMR_EMR_EMC1_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC1_SHIFT)
|
||||
#define TMR_EMR_EMC2_SHIFT (8) /* Bits 8-9: External Match Control 2 */
|
||||
#define TMR_EMR_EMC2_MASK (3 << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_SET (TMR_EMR_SET << TMR_EMR_EMC2_SHIFT)
|
||||
# define TMR_EMR_EMC2_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC2_SHIFT)
|
||||
#define TMR_EMR_EMC3_SHIFT (10) /* Bits 10-11: External Match Control 3 */
|
||||
#define TMR_EMR_EMC3_MASK (3 << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_NOTHING (TMR_EMR_NOTHING << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_CLEAR (TMR_EMR_CLEAR << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_SET (TMR_EMR_SET << TMR_EMR_EMC3_SHIFT)
|
||||
# define TMR_EMR_EMC3_TOGGLE (TMR_EMR_TOGGLE << TMR_EMR_EMC3_SHIFT)
|
||||
/* Bits 12-31: Reserved */
|
||||
/* Count Control Register */
|
||||
|
||||
#define TMR_CTCR_MODE_SHIFT (0) /* Bits 0-1: Counter/Timer Mode */
|
||||
#define TMR_CTCR_MODE_MASK (3 << TMR_CTCR_MODE_SHIFT)
|
||||
# define TMR_CTCR_MODE_TIMER (0 << TMR_CTCR_MODE_SHIFT) /* Timer Mode, prescale match */
|
||||
# define TMR_CTCR_MODE_CNTRRE (1 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP rising edge */
|
||||
# define TMR_CTCR_MODE_CNTRFE (2 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP falling edge */
|
||||
# define TMR_CTCR_MODE_CNTRBE (3 << TMR_CTCR_MODE_SHIFT) /* Counter Mode, CAP both edges */
|
||||
#define TMR_CTCR_INPSEL_SHIFT (2) /* Bits 2-3: Count Input Select */
|
||||
#define TMR_CTCR_INPSEL_MASK (3 << TMR_CTCR_INPSEL_SHIFT)
|
||||
# define TMR_CTCR_INPSEL_CAPNp0 (0 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.0 for TIMERn */
|
||||
# define TMR_CTCR_INPSEL_CAPNp1 (1 << TMR_CTCR_INPSEL_SHIFT) /* CAPn.1 for TIMERn */
|
||||
#define TMR_CTCR_ENCC (1 << 4) /* Enable Clear Timer/Prescale when capture event happens */
|
||||
#define TMR_CTCR_SELCC_SHIFT (5) /* Bits 5-7: Selects which capture event will clear Timer/Prescale */
|
||||
#define TMR_CTCR_SELCC_MASK (3 << TMR_CTCR_SELCC_SHIFT)
|
||||
# define TMR_CTCR_SELCC_RECAP0 (0 << TMR_CTCR_SELCC_SHIFT) /* Rising edge CAP0 clears timer (if bit 4 is set) */
|
||||
# define TMR_CTCR_SELCC_FECAP0 (1 << TMR_CTCR_SELCC_SHIFT) /* Falling edge CAP0 clears timer (if bit 4 is set) */
|
||||
# define TMR_CTCR_SELCC_RECAP1 (2 << TMR_CTCR_SELCC_SHIFT) /* Rising edge CAP1 clears timer (if bit 4 is set) */
|
||||
# define TMR_CTCR_SELCC_FECAP1 (3 << TMR_CTCR_SELCC_SHIFT) /* Falling edge CAP1 clears timer (if bit 4 is set) */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* PWM Control register */
|
||||
|
||||
#define TMR_PWMC_PWMEN0 (1 << 0) /* PWM channel0 enable */
|
||||
#define TMR_PWMC_PWMEN1 (1 << 1) /* PWM channel1 enable */
|
||||
#define TMR_PWMC_PWMEN2 (1 << 2) /* PWM channel2 enable */
|
||||
#define TMR_PWMC_PWMEN3 (1 << 3) /* PWM channel3 enable */
|
||||
/* Bits 4-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_TIMER_H */
|
||||
@@ -0,0 +1,261 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc11_uart.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_UART_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_UART_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/lpc11_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC11_UART_RBR_OFFSET 0x0000 /* (DLAB =0) Receiver Buffer Register (all) */
|
||||
#define LPC11_UART_THR_OFFSET 0x0000 /* (DLAB =0) Transmit Holding Register (all) */
|
||||
#define LPC11_UART_DLL_OFFSET 0x0000 /* (DLAB =1) Divisor Latch LSB (all) */
|
||||
#define LPC11_UART_DLM_OFFSET 0x0004 /* (DLAB =1) Divisor Latch MSB (all) */
|
||||
#define LPC11_UART_IER_OFFSET 0x0004 /* (DLAB =0) Interrupt Enable Register (all) */
|
||||
#define LPC11_UART_IIR_OFFSET 0x0008 /* Interrupt ID Register (all) */
|
||||
#define LPC11_UART_FCR_OFFSET 0x0008 /* FIFO Control Register (all) */
|
||||
#define LPC11_UART_LCR_OFFSET 0x000c /* Line Control Register (all) */
|
||||
#define LPC11_UART_MCR_OFFSET 0x0010 /* Modem Control Register (UART1 only) */
|
||||
#define LPC11_UART_LSR_OFFSET 0x0014 /* Line Status Register (all) */
|
||||
#define LPC11_UART_MSR_OFFSET 0x0018 /* Modem Status Register (UART1 only) */
|
||||
#define LPC11_UART_SCR_OFFSET 0x001c /* Scratch Pad Register (all) */
|
||||
#define LPC11_UART_ACR_OFFSET 0x0020 /* Auto-baud Control Register (all) */
|
||||
#define LPC11_UART_FDR_OFFSET 0x0028 /* Fractional Divider Register (all) */
|
||||
#define LPC11_UART_TER_OFFSET 0x0030 /* Transmit Enable Register (all) */
|
||||
#define LPC11_UART_RS485CTRL_OFFSET 0x004c /* RS-485/EIA-485 Control (UART1 only) */
|
||||
#define LPC11_UART_ADRMATCH_OFFSET 0x0050 /* RS-485/EIA-485 address match (UART1 only) */
|
||||
#define LPC11_UART_RS485DLY_OFFSET 0x0054 /* RS-485/EIA-485 direction control delay (UART1 only) */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC11_UART0_RBR (LPC11_UART0_BASE+LPC11_UART_RBR_OFFSET)
|
||||
#define LPC11_UART0_THR (LPC11_UART0_BASE+LPC11_UART_THR_OFFSET)
|
||||
#define LPC11_UART0_DLL (LPC11_UART0_BASE+LPC11_UART_DLL_OFFSET)
|
||||
#define LPC11_UART0_DLM (LPC11_UART0_BASE+LPC11_UART_DLM_OFFSET)
|
||||
#define LPC11_UART0_IER (LPC11_UART0_BASE+LPC11_UART_IER_OFFSET)
|
||||
#define LPC11_UART0_IIR (LPC11_UART0_BASE+LPC11_UART_IIR_OFFSET)
|
||||
#define LPC11_UART0_FCR (LPC11_UART0_BASE+LPC11_UART_FCR_OFFSET)
|
||||
#define LPC11_UART0_LCR (LPC11_UART0_BASE+LPC11_UART_LCR_OFFSET)
|
||||
#define LPC11_UART0_MCR (LPC11_UART0_BASE+LPC11_UART_MCR_OFFSET)
|
||||
#define LPC11_UART0_LSR (LPC11_UART0_BASE+LPC11_UART_LSR_OFFSET)
|
||||
#define LPC11_UART0_SCR (LPC11_UART0_BASE+LPC11_UART_SCR_OFFSET)
|
||||
#define LPC11_UART0_ACR (LPC11_UART0_BASE+LPC11_UART_ACR_OFFSET)
|
||||
#define LPC11_UART0_ICR (LPC11_UART0_BASE+LPC11_UART_ICR_OFFSET)
|
||||
#define LPC11_UART0_FDR (LPC11_UART0_BASE+LPC11_UART_FDR_OFFSET)
|
||||
#define LPC11_UART0_TER (LPC11_UART0_BASE+LPC11_UART_TER_OFFSET)
|
||||
#define LPC11_UART0_RS485CTRL (LPC11_UART0_BASE+LPC11_UART_RS485CTRL_OFFSET)
|
||||
#define LPC11_UART0_ADRMATCH (LPC11_UART0_BASE+LPC11_UART_ADRMATCH_OFFSET)
|
||||
#define LPC11_UART0_RS485DLY (LPC11_UART0_BASE+LPC11_UART_RS485DLY_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* RBR (DLAB =0) Receiver Buffer Register (all) */
|
||||
|
||||
#define UART_RBR_MASK (0xff) /* Bits 0-7: Oldest received byte in RX FIFO */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* THR (DLAB =0) Transmit Holding Register (all) */
|
||||
|
||||
#define UART_THR_MASK (0xff) /* Bits 0-7: Adds byte to TX FIFO */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* DLL (DLAB =1) Divisor Latch LSB (all) */
|
||||
|
||||
#define UART_DLL_MASK (0xff) /* Bits 0-7: DLL */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* DLM (DLAB =1) Divisor Latch MSB (all) */
|
||||
|
||||
#define UART_DLM_MASK (0xff) /* Bits 0-7: DLM */
|
||||
/* Bits 8-31: Reserved */
|
||||
|
||||
/* IER (DLAB =0) Interrupt Enable Register (all) */
|
||||
|
||||
#define UART_IER_RBRIE (1 << 0) /* Bit 0: RBR Interrupt Enable */
|
||||
#define UART_IER_THREIE (1 << 1) /* Bit 1: THRE Interrupt Enable */
|
||||
#define UART_IER_RXLIE (1 << 2) /* Bit 2: RX Line Interrupt Enable */
|
||||
/* Bits 3-7: Reserved */
|
||||
#define UART_IER_ABEOINTEN (1 << 8) /* Bit 8: Enables the end of auto-baud interrupt */
|
||||
#define UART_IER_ABTOINTEN (1 << 9) /* Bit 9: Enables the auto-baud time-out interrupt */
|
||||
/* Bits 10-31: Reserved */
|
||||
#define UART_IER_ALLIE (0x038f)
|
||||
|
||||
/* IIR Interrupt ID Register (all) */
|
||||
|
||||
#define UART_IIR_INTSTATUS (1 << 0) /* Bit 0: Interrupt status (active low) */
|
||||
#define UART_IIR_INTID_SHIFT (1) /* Bits 1-3: Interrupt identification */
|
||||
#define UART_IIR_INTID_MASK (7 << UART_IIR_INTID_SHIFT)
|
||||
# define UART_IIR_INTID_MSI (0 << UART_IIR_INTID_SHIFT) /* Modem Interrupt */
|
||||
# define UART_IIR_INTID_THRE (1 << UART_IIR_INTID_SHIFT) /* THRE Interrupt */
|
||||
# define UART_IIR_INTID_RDA (2 << UART_IIR_INTID_SHIFT) /* 2a - Receive Data Available (RDA) */
|
||||
# define UART_IIR_INTID_RLS (3 << UART_IIR_INTID_SHIFT) /* 1 - Receive Line Status (RLS) */
|
||||
# define UART_IIR_INTID_CTI (6 << UART_IIR_INTID_SHIFT) /* 2b - Character Time-out Indicator (CTI) */
|
||||
/* Bits 4-5: Reserved */
|
||||
#define UART_IIR_FIFOEN_SHIFT (6) /* Bits 6-7: Copies of FCR bit 0 */
|
||||
#define UART_IIR_FIFOEN_MASK (3 << UART_IIR_FIFOEN_SHIFT)
|
||||
#define UART_IIR_ABEOINT (1 << 8) /* Bit 8: End of auto-baud interrupt */
|
||||
#define UART_IIR_ABTOINT (1 << 9) /* Bit 9: Auto-baud time-out interrupt */
|
||||
/* Bits 10-31: Reserved */
|
||||
/* FCR FIFO Control Register (all) */
|
||||
|
||||
#define UART_FCR_FIFOEN (1 << 0) /* Bit 0: Enable FIFOs */
|
||||
#define UART_FCR_RXRST (1 << 1) /* Bit 1: RX FIFO Reset */
|
||||
#define UART_FCR_TXRST (1 << 2) /* Bit 2: TX FIFO Reset */
|
||||
/* Bits 3-5: Reserved */
|
||||
#define UART_FCR_RXTRIGGER_SHIFT (6) /* Bits 6-7: RX Trigger Level */
|
||||
#define UART_FCR_RXTRIGGER_MASK (3 << UART_FCR_RXTRIGGER_SHIFT)
|
||||
# define UART_FCR_RXTRIGGER_0 (0 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 0 (1 character) */
|
||||
# define UART_FCR_RXTRIGGER_4 (1 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 1 (4 characters) */
|
||||
# define UART_FCR_RXTRIGGER_8 (2 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 2 (8 characters) */
|
||||
# define UART_FCR_RXTRIGGER_14 (3 << UART_FCR_RXTRIGGER_SHIFT) /* Trigger level 3 (14 characters) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* LCR Line Control Register (all) */
|
||||
|
||||
#define UART_LCR_WLS_SHIFT (0) /* Bit 0-1: Word Length Select */
|
||||
#define UART_LCR_WLS_MASK (3 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_5BIT (0 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_6BIT (1 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_7BIT (2 << UART_LCR_WLS_SHIFT)
|
||||
# define UART_LCR_WLS_8BIT (3 << UART_LCR_WLS_SHIFT)
|
||||
#define UART_LCR_STOP (1 << 2) /* Bit 2: Stop Bit Select */
|
||||
#define UART_LCR_PE (1 << 3) /* Bit 3: Parity Enable */
|
||||
#define UART_LCR_PS_SHIFT (4) /* Bits 4-5: Parity Select */
|
||||
#define UART_LCR_PS_MASK (3 << UART_LCR_PS_SHIFT)
|
||||
# define UART_LCR_PS_ODD (0 << UART_LCR_PS_SHIFT) /* Odd parity */
|
||||
# define UART_LCR_PS_EVEN (1 << UART_LCR_PS_SHIFT) /* Even Parity */
|
||||
# define UART_LCR_PS_STICK1 (2 << UART_LCR_PS_SHIFT) /* Forced "1" stick parity */
|
||||
# define UART_LCR_PS_STICK0 (3 << UART_LCR_PS_SHIFT) /* Forced "0" stick parity */
|
||||
#define UART_LCR_BRK (1 << 6) /* Bit 6: Break Control */
|
||||
#define UART_LCR_DLAB (1 << 7) /* Bit 7: Divisor Latch Access Bit (DLAB) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* MCR Modem Control Register (UART1 only) */
|
||||
|
||||
#define UART_MCR_DTR (1 << 0) /* Bit 0: DTR Control Source for DTR output */
|
||||
#define UART_MCR_RTS (1 << 1) /* Bit 1: Control Source for RTS output */
|
||||
/* Bits 2-3: Reserved */
|
||||
#define UART_MCR_LPBK (1 << 4) /* Bit 4: Loopback Mode Select */
|
||||
/* Bit 5: Reserved */
|
||||
#define UART_MCR_RTSEN (1 << 6) /* Bit 6: Enable auto-rts flow control */
|
||||
#define UART_MCR_CTSEN (1 << 7) /* Bit 7: Enable auto-cts flow control */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* LSR Line Status Register (all) */
|
||||
|
||||
#define UART_LSR_RDR (1 << 0) /* Bit 0: Receiver Data Ready */
|
||||
#define UART_LSR_OE (1 << 1) /* Bit 1: Overrun Error */
|
||||
#define UART_LSR_PE (1 << 2) /* Bit 2: Parity Error */
|
||||
#define UART_LSR_FE (1 << 3) /* Bit 3: Framing Error */
|
||||
#define UART_LSR_BI (1 << 4) /* Bit 4: Break Interrupt */
|
||||
#define UART_LSR_THRE (1 << 5) /* Bit 5: Transmitter Holding Register Empty */
|
||||
#define UART_LSR_TEMT (1 << 6) /* Bit 6: Transmitter Empty */
|
||||
#define UART_LSR_RXFE (1 << 7) /* Bit 7: Error in RX FIFO (RXFE) */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* MSR Modem Status Register (UART1 only) */
|
||||
|
||||
#define UART_MSR_DELTACTS (1 << 0) /* Bit 0: CTS state change */
|
||||
#define UART_MSR_DELTADSR (1 << 1) /* Bit 1: DSR state change */
|
||||
#define UART_MSR_RIEDGE (1 << 2) /* Bit 2: RI ow to high transition */
|
||||
#define UART_MSR_DELTADCD (1 << 3) /* Bit 3: DCD state change */
|
||||
#define UART_MSR_CTS (1 << 4) /* Bit 4: CTS State */
|
||||
#define UART_MSR_DSR (1 << 5) /* Bit 5: DSR State */
|
||||
#define UART_MSR_RI (1 << 6) /* Bit 6: Ring Indicator State */
|
||||
#define UART_MSR_DCD (1 << 7) /* Bit 7: Data Carrier Detect State */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* SCR Scratch Pad Register (all) */
|
||||
|
||||
#define UART_SCR_MASK (0xff) /* Bits 0-7: SCR data */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* ACR Auto-baud Control Register (all) */
|
||||
|
||||
#define UART_ACR_START (1 << 0) /* Bit 0: Auto-baud start/running*/
|
||||
#define UART_ACR_MODE (1 << 1) /* Bit 1: Auto-baud mode select*/
|
||||
#define UART_ACR_AUTORESTART (1 << 2) /* Bit 2: Restart in case of time-out*/
|
||||
/* Bits 3-7: Reserved */
|
||||
#define UART_ACR_ABEOINTCLR (1 << 8) /* Bit 8: End of auto-baud interrupt clear */
|
||||
#define UART_ACR_ABTOINTCLRT (1 << 9) /* Bit 9: Auto-baud time-out interrupt clear */
|
||||
/* Bits 10-31: Reserved */
|
||||
|
||||
/* FDR Fractional Divider Register (all) */
|
||||
|
||||
#define UART_FDR_DIVADDVAL_SHIFT (0) /* Bits 0-3: Baud-rate generation pre-scaler divisor value */
|
||||
#define UART_FDR_DIVADDVAL_MASK (15 << UART_FDR_DIVADDVAL_SHIFT)
|
||||
#define UART_FDR_MULVAL_SHIFT (4) /* Bits 4-7 Baud-rate pre-scaler multiplier value */
|
||||
#define UART_FDR_MULVAL_MASK (15 << UART_FDR_MULVAL_SHIFT)
|
||||
/* Bits 8-31: Reserved */
|
||||
/* TER Transmit Enable Register (all) */
|
||||
/* Bits 0-6: Reserved */
|
||||
#define UART_TER_TXEN (1 << 7) /* Bit 7: TX Enable */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* RS-485/EIA-485 Control */
|
||||
|
||||
#define UART_RS485CTRL_NMMEN (1 << 0) /* Bit 0: RS-485/EIA-485 Normal Multidrop Mode (NMM) enabled */
|
||||
#define UART_RS485CTRL_RXDIS (1 << 1) /* Bit 1: Receiver is disabled */
|
||||
#define UART_RS485CTRL_AADEN (1 << 2) /* Bit 2: Auto Address Detect (AAD) is enabled */
|
||||
#define UART_RS485CTRL_SEL (1 << 3) /* Bit 3: RTS/DTR used for direction control (DCTRL=1) */
|
||||
#define UART_RS485CTRL_DCTRL (1 << 4) /* Bit 4: Enable Auto Direction Control */
|
||||
#define UART_RS485CTRL_OINV (1 << 5) /* Bit 5: Polarity of the direction control signal on RTS/DTR */
|
||||
/* Bits 6-31: Reserved */
|
||||
/* RS-485/EIA-485 address match */
|
||||
|
||||
#define UART_ADRMATCH_MASK (0xff) /* Bits 0-7: Address match value */
|
||||
/* Bits 8-31: Reserved */
|
||||
/* RS-485/EIA-485 direction control delay (UART1 only) */
|
||||
|
||||
#define UART_RS485DLY_MASK (0xff) /* Bits 0-7: Direction control (RTS/DTR) delay */
|
||||
/* Bits 8-31: Reserved */
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_CHIP_LPC11_UART_H */
|
||||
@@ -0,0 +1,102 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/chip/lpc11_wdt.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/lpc11_memorymap.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Register offsets *****************************************************************/
|
||||
|
||||
#define LPC11_WDT_MOD_OFFSET 0x0000 /* Watchdog mode register */
|
||||
#define LPC11_WDT_TC_OFFSET 0x0004 /* Watchdog timer constant register */
|
||||
#define LPC11_WDT_FEED_OFFSET 0x0008 /* Watchdog feed sequence register */
|
||||
#define LPC11_WDT_TV_OFFSET 0x000c /* Watchdog timer value register */
|
||||
|
||||
/* Register addresses ***************************************************************/
|
||||
|
||||
#define LPC11_WDT_MOD (LPC11_WDT_BASE+LPC11_WDT_MOD_OFFSET)
|
||||
#define LPC11_WDT_TC (LPC11_WDT_BASE+LPC11_WDT_TC_OFFSET)
|
||||
#define LPC11_WDT_FEED (LPC11_WDT_BASE+LPC11_WDT_FEED_OFFSET)
|
||||
#define LPC11_WDT_TV (LPC11_WDT_BASE+LPC11_WDT_TV_OFFSET)
|
||||
|
||||
/* Register bit definitions *********************************************************/
|
||||
|
||||
/* Watchdog mode register */
|
||||
|
||||
#define WDT_MOD_WDEN (1 << 0) /* Bit 0: Watchdog enable */
|
||||
#define WDT_MOD_WDRESET (1 << 1) /* Bit 1: Watchdog reset enable */
|
||||
#define WDT_MOD_WDTOF (1 << 2) /* Bit 2: Watchdog time-out */
|
||||
#define WDT_MOD_WDINT (1 << 3) /* Bit 3: Watchdog interrupt */
|
||||
/* Bits 4-31: Reserved */
|
||||
/* Watchdog timer constant register */
|
||||
|
||||
#define WDT_TC (0x00ffffff) /* Bits 0-23: Watchdog time-out interval */
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/* Watchdog feed sequence register */
|
||||
|
||||
#define WDT_FEED_MASK (0xff) /* Bits 0-7: Feed value should be 0xaa
|
||||
* followed by 0x55 */
|
||||
/* Bits 14-31: Reserved */
|
||||
/* Watchdog timer value register */
|
||||
|
||||
#define WDT_TV (0x00ffffff) /* Bits 0-23: Watchdog timer value */
|
||||
/* Bits 24-31: Reserved */
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_WDT_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,178 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc111x_gpio.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC111X_GPIO_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC111X_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Bit-encoded input to lpc11_configgpio() ******************************************/
|
||||
|
||||
/* Encoding: FFFF xxMM OVPP NNNN
|
||||
*
|
||||
* Pin Function: FFF
|
||||
* Pin Mode bits: MM
|
||||
* Open drain: O (output pins)
|
||||
* Initial value: V (output pins)
|
||||
* Port number: PP (0-3)
|
||||
* Pin number: NNNN (0-11)
|
||||
*/
|
||||
|
||||
/* Pin Function bits: FFF
|
||||
* Only meaningful when the GPIO function is GPIO_PIN
|
||||
*/
|
||||
|
||||
#define GPIO_FUNC_SHIFT (12) /* Bits 12-15: GPIO mode */
|
||||
#define GPIO_FUNC_MASK (15 << GPIO_FUNC_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_FUNC_SHIFT) /* 0000 GPIO input pin */
|
||||
# define GPIO_INTFE (1 << GPIO_FUNC_SHIFT) /* 0001 GPIO interrupt falling edge */
|
||||
# define GPIO_INTRE (2 << GPIO_FUNC_SHIFT) /* 0010 GPIO interrupt rising edge */
|
||||
# define GPIO_INTBOTH (3 << GPIO_FUNC_SHIFT) /* 0011 GPIO interrupt both edges */
|
||||
# define GPIO_OUTPUT (4 << GPIO_FUNC_SHIFT) /* 0100 GPIO output pin */
|
||||
# define GPIO_ALT_GPIO (5 << GPIO_FUNC_SHIFT) /* 0101 Alternate function is a GPIO */
|
||||
# define GPIO_ALT0 (5 << GPIO_FUNC_SHIFT) /* 1000 Alternate function 0 */
|
||||
# define GPIO_ALT1 (5 << GPIO_FUNC_SHIFT) /* 1001 Alternate function 1 */
|
||||
# define GPIO_ALT2 (6 << GPIO_FUNC_SHIFT) /* 1010 Alternate function 2 */
|
||||
# define GPIO_ALT3 (7 << GPIO_FUNC_SHIFT) /* 1011 Alternate function 3 */
|
||||
|
||||
#define GPIO_EDGE_SHIFT (13) /* Bits 13-14: Interrupt edge bits */
|
||||
#define GPIO_EDGE_MASK (3 << GPIO_EDGE_SHIFT)
|
||||
|
||||
#define GPIO_INOUT_MASK GPIO_OUTPUT
|
||||
#define GPIO_FE_MASK GPIO_INTFE
|
||||
#define GPIO_RE_MASK GPIO_INTRE
|
||||
|
||||
#define GPIO_ISGPIO(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) < GPIO_ALT0)
|
||||
#define GPIO_ISALT(ps) ((uint16_t(ps) & GPIO_FUNC_MASK) >= GPIO_ALT0)
|
||||
#define GPIO_ISINPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_INPUT)
|
||||
#define GPIO_ISOUTPUT(ps) (((ps) & GPIO_FUNC_MASK) == GPIO_OUTPUT)
|
||||
#define GPIO_ISINORINT(ps) (((ps) & GPIO_INOUT_MASK) == 0)
|
||||
#define GPIO_ISOUTORALT(ps) (((ps) & GPIO_INOUT_MASK) != 0)
|
||||
#define GPIO_ISINTERRUPT(ps) (GPIO_ISOUTPUT(ps) && !GPIO_ISINPUT(ps))
|
||||
#define GPIO_ISFE(ps) (((ps) & GPIO_FE_MASK) != 0)
|
||||
#define GPIO_ISRE(ps) (((ps) & GPIO_RE_MASK) != 0)
|
||||
|
||||
/* Pin Mode: MM */
|
||||
|
||||
#define GPIO_PUMODE_SHIFT (8) /* Bits 8-9: Pin pull-up mode */
|
||||
#define GPIO_PUMODE_MASK (3 << GPIO_PUMODE_SHIFT)
|
||||
# define GPIO_FLOAT (0 << GPIO_PUMODE_SHIFT) /* Neither pull-up nor -down */
|
||||
# define GPIO_PULLDN (1 << GPIO_PUMODE_SHIFT) /* Pull-down resistor enabled */
|
||||
# define GPIO_PULLUP (2 << GPIO_PUMODE_SHIFT) /* Pull-up resistor enabled */
|
||||
# define GPIO_REPEATER (3 << GPIO_PUMODE_SHIFT) /* Repeater mode enabled */
|
||||
|
||||
/* Open drain: O */
|
||||
|
||||
#define GPIO_OPEN_DRAIN (1 << 7) /* Bit 7: Open drain mode */
|
||||
|
||||
/* Initial value: V */
|
||||
|
||||
#define GPIO_VALUE (1 << 6) /* Bit 6: Initial GPIO output value */
|
||||
#define GPIO_VALUE_ONE GPIO_VALUE
|
||||
#define GPIO_VALUE_ZERO (0)
|
||||
|
||||
/* Port number: PP (0-3) */
|
||||
|
||||
#define GPIO_PORT_SHIFT (4) /* Bit 4-5: Port number */
|
||||
#define GPIO_PORT_MASK (3 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT0 (0 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT1 (1 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT2 (2 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORT3 (3 << GPIO_PORT_SHIFT)
|
||||
|
||||
#define GPIO_NPORTS 4
|
||||
|
||||
/* Pin number: NNNN (0-11) */
|
||||
|
||||
#define GPIO_PIN_SHIFT 0 /* Bits 0-3: GPIO number: 0-11 */
|
||||
#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
typedef uint16_t lpc11_pinset_t;
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* These tables have global scope only because they are shared between lpc11_gpio.c,
|
||||
* lpc11_gpioint.c, and lpc11_gpiodbg.c
|
||||
*/
|
||||
|
||||
EXTERN const uint32_t g_lopinsel[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_hipinsel[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_lopinmode[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_hipinmode[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_odmode[GPIO_NPORTS];
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC111X_GPIO_H */
|
||||
@@ -0,0 +1,122 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_clockconfig.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
#include "lpc11_clockconfig.h"
|
||||
#include "chip/lpc11_syscon.h"
|
||||
#include "chip/lpc111x_iocon.h"
|
||||
#include "chip/lpc11_gpio.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc11_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to initialize the LPC11xx. This does whatever setup is needed
|
||||
* to put the SoC in a usable state. This includes the initialization of
|
||||
* clocking using the settings in board.h.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void lpc11_clockconfig(void)
|
||||
{
|
||||
int regval;
|
||||
|
||||
/* Enable the main oscillator (or not) and the frequency range of the main
|
||||
* oscillator.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC11_INTRCOSC
|
||||
regval = SYSCON_SYSPLLCLKSEL_IRCOSC;
|
||||
#else
|
||||
regval = SYSCON_SYSPLLCLKSEL_SYSOSC;
|
||||
#endif
|
||||
putreg32(regval, LPC11_SYSCON_SYSPLLCLKSEL);
|
||||
|
||||
/* MSEL = 3 , PSEL = 1 */
|
||||
|
||||
putreg32((SYSCON_SYSPLLCTRL_MSEL_DIV(4) | SYSCON_SYSPLLCTRL_PSEL_DIV2),
|
||||
LPC11_SYSCON_SYSPLLCTRL);
|
||||
|
||||
/* Power UP the PLL */
|
||||
|
||||
regval = getreg32(LPC11_SYSCON_PDRUNCFG);
|
||||
regval &= ~(SYSCON_PDRUNCFG_SYSPLL_PD);
|
||||
putreg32(regval, LPC11_SYSCON_PDRUNCFG);
|
||||
|
||||
/* Inform the core to use PLL as clock */
|
||||
|
||||
putreg32(SYSCON_MAINCLKSEL_PLLOSC, LPC11_SYSCON_SYSPLLCLKUEN);
|
||||
|
||||
/* Use PLL as main clock */
|
||||
|
||||
putreg32(SYSCON_MAINCLKSEL_SYSPLLCLKOUT, LPC11_SYSCON_MAINCLKSEL);
|
||||
|
||||
/* Inform the core of clock update */
|
||||
|
||||
putreg32(SYSCON_MAINCLKUEN_ENA, LPC11_SYSCON_MAINCLKUEN);
|
||||
}
|
||||
@@ -0,0 +1,84 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_clockconfig.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_CLOCKCONFIG_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_CLOCKCONFIG_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to initialize the LPC11XX. This does whatever setup is needed to put the
|
||||
* MCU in a usable state. This includes the initialization of clocking using the
|
||||
* settings in board.h.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lpc11_clockconfig(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_CLOCKCONFIG_H */
|
||||
@@ -0,0 +1,80 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_gpio.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/* This file is only a thin shell that includes the correct GPIO logic for
|
||||
* the selected LPC17xx family. The correct file cannot be selected by the
|
||||
* make system because it needs the intelligence that only exists in chip.h
|
||||
* that can associate an LPC17xx part number with an LPC17xx family.
|
||||
*/
|
||||
|
||||
#include <arch/lpc11xx/chip.h>
|
||||
|
||||
#if defined(LPC111x)
|
||||
# include "lpc111x_gpio.c"
|
||||
#elif defined(LPC11C)
|
||||
# include "lpc11c_gpio.c"
|
||||
#else
|
||||
# error "Unrecognized LPC11xx family"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
@@ -0,0 +1,194 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_gpio.h
|
||||
*
|
||||
* Copyright (C) 2010, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
# include <stdbool.h>
|
||||
#endif
|
||||
|
||||
#include <arch/lpc11xx/chip.h>
|
||||
|
||||
#include "chip/lpc11_gpio.h"
|
||||
#include "chip/lpc11_pinconfig.h"
|
||||
|
||||
/* Include the GPIO definitions for the selected LPC17xx family. */
|
||||
|
||||
#if defined(LPC111x)
|
||||
# include "lpc111x_gpio.h"
|
||||
#elif defined(LPC11C)
|
||||
# include "lpc11c_gpio.h"
|
||||
#else
|
||||
# error "Unrecognized LPC11xx family"
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* These tables have global scope only because they are shared between lpc11_gpio.c,
|
||||
* lpc11_gpioint.c, and lpc11_gpiodbg.c
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
EXTERN uint64_t g_intedge0;
|
||||
EXTERN uint64_t g_intedge2;
|
||||
#endif
|
||||
|
||||
EXTERN const uint32_t g_fiobase[GPIO_NPORTS];
|
||||
EXTERN const uint32_t g_intbase[GPIO_NPORTS];
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_gpioirqinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize logic to support a second level of interrupt decoding for GPIO pins.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
void lpc11_gpioirqinitialize(void);
|
||||
#else
|
||||
# define lpc11_gpioirqinitialize()
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
int lpc11_configgpio(lpc11_pinset_t cfgset);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lpc11_gpiowrite(lpc11_pinset_t pinset, bool value);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
bool lpc11_gpioread(lpc11_pinset_t pinset);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_gpioirqenable
|
||||
*
|
||||
* Description:
|
||||
* Enable the interrupt for specified GPIO IRQ
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
void lpc11_gpioirqenable(int irq);
|
||||
#else
|
||||
# define lpc11_gpioirqenable(irq)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_gpioirqdisable
|
||||
*
|
||||
* Description:
|
||||
* Disable the interrupt for specified GPIO IRQ
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
void lpc11_gpioirqdisable(int irq);
|
||||
#else
|
||||
# define lpc11_gpioirqdisable(irq)
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Function: lpc11_dumpgpio
|
||||
*
|
||||
* Description:
|
||||
* Dump all GPIO registers associated with the base address of the provided pinset.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_GPIO
|
||||
int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg);
|
||||
#else
|
||||
# define lpc11_dumpgpio(p,m)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_GPIO_H */
|
||||
@@ -0,0 +1,190 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_gpiodbg.c
|
||||
*
|
||||
* Copyright (C) 2010-2011, 2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "chip.h"
|
||||
#include "lpc11_gpio.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_DEBUG
|
||||
# undef CONFIG_DEBUG_GPIO
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_DEBUG_GPIO
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc11_pinsel
|
||||
*
|
||||
* Description:
|
||||
* Get the address of the PINSEL register corresponding to this port and
|
||||
* pin number.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef LPC176x
|
||||
static uint32_t lpc11_pinsel(unsigned int port, unsigned int pin)
|
||||
{
|
||||
if (pin < 16)
|
||||
{
|
||||
return g_lopinsel[port];
|
||||
}
|
||||
else
|
||||
{
|
||||
return g_hipinsel[port];
|
||||
}
|
||||
}
|
||||
#endif /* LPC176x */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc11_pinmode
|
||||
*
|
||||
* Description:
|
||||
* Get the address of the PINMODE register corresponding to this port and
|
||||
* pin number.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef LPC176x
|
||||
static uint32_t lpc11_pinmode(unsigned int port, unsigned int pin)
|
||||
{
|
||||
if (pin < 16)
|
||||
{
|
||||
return g_lopinmode[port];
|
||||
}
|
||||
else
|
||||
{
|
||||
return g_hipinmode[port];
|
||||
}
|
||||
}
|
||||
#endif /* LPC176x */
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: lpc11_dumpgpio
|
||||
*
|
||||
* Description:
|
||||
* Dump all GPIO registers associated with the provided base address
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int lpc11_dumpgpio(lpc11_pinset_t pinset, const char *msg)
|
||||
{
|
||||
irqstate_t flags;
|
||||
uint32_t base;
|
||||
#if defined(LPC176x)
|
||||
uint32_t pinsel;
|
||||
uint32_t pinmode;
|
||||
#elif defined(LPC178x)
|
||||
uint32_t iocon;
|
||||
#endif /* LPC176x */
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
/* Get the base address associated with the GPIO port */
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
#if defined(LPC176x)
|
||||
pinsel = lpc11_pinsel(port, pin);
|
||||
pinmode = lpc11_pinmode(port, pin);
|
||||
#elif defined(LPC178x)
|
||||
iocon = LPC17_IOCON_P(port, pin);
|
||||
#endif /* LPC176x */
|
||||
|
||||
/* The following requires exclusive access to the GPIO registers */
|
||||
|
||||
flags = irqsave();
|
||||
lldbg("GPIO%c pin%d (pinset: %08x) -- %s\n",
|
||||
port + '0', pin, pinset, msg);
|
||||
|
||||
#if defined(LPC176x)
|
||||
lldbg(" PINSEL[%08x]: %08x PINMODE[%08x]: %08x ODMODE[%08x]: %08x\n",
|
||||
pinsel, pinsel ? getreg32(pinsel) : 0,
|
||||
pinmode, pinmode ? getreg32(pinmode) : 0,
|
||||
g_odmode[port], getreg32(g_odmode[port]));
|
||||
#elif defined(LPC178x)
|
||||
lldbg(" IOCON[%08x]: %08x\n", iocon, getreg32(iocon));
|
||||
#endif
|
||||
|
||||
base = g_fiobase[port];
|
||||
lldbg(" FIODIR[%08x]: %08x FIOMASK[%08x]: %08x FIOPIN[%08x]: %08x\n",
|
||||
base+LPC17_FIO_DIR_OFFSET, getreg32(base+LPC17_FIO_DIR_OFFSET),
|
||||
base+LPC17_FIO_MASK_OFFSET, getreg32(base+LPC17_FIO_MASK_OFFSET),
|
||||
base+LPC17_FIO_PIN_OFFSET, getreg32(base+LPC17_FIO_PIN_OFFSET));
|
||||
|
||||
base = g_intbase[port];
|
||||
lldbg(" IOINTSTATUS[%08x]: %08x INTSTATR[%08x]: %08x INSTATF[%08x]: %08x\n",
|
||||
LPC17_GPIOINT_IOINTSTATUS, getreg32(LPC17_GPIOINT_IOINTSTATUS),
|
||||
base+LPC17_GPIOINT_INTSTATR_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATR_OFFSET),
|
||||
base+LPC17_GPIOINT_INTSTATF_OFFSET, getreg32(base+LPC17_GPIOINT_INTSTATF_OFFSET));
|
||||
lldbg(" INTENR[%08x]: %08x INTENF[%08x]: %08x\n",
|
||||
base+LPC17_GPIOINT_INTENR_OFFSET, getreg32(base+LPC17_GPIOINT_INTENR_OFFSET),
|
||||
base+LPC17_GPIOINT_INTENF_OFFSET, getreg32(base+LPC17_GPIOINT_INTENF_OFFSET));
|
||||
irqrestore(flags);
|
||||
return OK;
|
||||
}
|
||||
#endif /* CONFIG_DEBUG_GPIO */
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,62 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_i2c.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_I2C_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_I2C_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip/lpc11_i2c.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_I2C_H */
|
||||
@@ -0,0 +1,118 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/lpc11/lpc11_idle.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Does the board support an IDLE LED to indicate that the board is in the
|
||||
* IDLE state?
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
|
||||
# define BEGIN_IDLE() board_led_on(LED_IDLE)
|
||||
# define END_IDLE() board_led_off(LED_IDLE)
|
||||
#else
|
||||
# define BEGIN_IDLE()
|
||||
# define END_IDLE()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_idle
|
||||
*
|
||||
* Description:
|
||||
* up_idle() is the logic that will be executed when their is no other
|
||||
* ready-to-run task. This is processor idle time and will continue until
|
||||
* some interrupt occurs to cause a context switch from the idle task.
|
||||
*
|
||||
* Processing in this state may be processor-specific. e.g., this is where
|
||||
* power management operations might be performed.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_idle(void)
|
||||
{
|
||||
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
|
||||
/* If the system is idle and there are no timer interrupts, then process
|
||||
* "fake" timer interrupts. Hopefully, something will wake up.
|
||||
*/
|
||||
|
||||
sched_process_timer();
|
||||
#else
|
||||
|
||||
/* If the g_dma_inprogress is zero, then there is no DMA in progress. This
|
||||
* value is needed in the IDLE loop to determine if the IDLE loop should
|
||||
* go into lower power power consumption modes. According to the LPC17xx
|
||||
* User Manual: "The DMA controller can continue to work in Sleep mode, and
|
||||
* has access to the peripheral SRAMs and all peripheral registers. The
|
||||
* flash memory and the Main SRAM are not available in Sleep mode, they are
|
||||
* disabled in order to save power."
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC17_GPDMA
|
||||
if (g_dma_inprogress == 0)
|
||||
#endif
|
||||
{
|
||||
/* Sleep until an interrupt occurs in order to save power */
|
||||
|
||||
BEGIN_IDLE();
|
||||
asm("WFI");
|
||||
END_IDLE();
|
||||
}
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,338 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_irq.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/irq.h>
|
||||
|
||||
#include "nvic.h"
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
//#include "lpc11_irq.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Get a 32-bit version of the default priority */
|
||||
|
||||
#define DEFPRIORITY32 \
|
||||
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | NVIC_SYSH_PRIORITY_DEFAULT << 16 |\
|
||||
NVIC_SYSH_PRIORITY_DEFAULT << 8 | NVIC_SYSH_PRIORITY_DEFAULT)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
volatile uint32_t *current_regs;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc11_dumpnvic
|
||||
*
|
||||
* Description:
|
||||
* Dump some interesting NVIC registers
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_DEBUG_IRQ)
|
||||
static void lpc11_dumpnvic(const char *msg, int irq)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = irqsave();
|
||||
|
||||
lldbg("NVIC (%s, irq=%d):\n", msg, irq);
|
||||
lldbg(" ISER: %08x ICER: %08x\n",
|
||||
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
|
||||
lldbg(" ISPR: %08x ICPR: %08x\n",
|
||||
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
|
||||
lldbg(" IRQ PRIO: %08x %08x %08x %08x\n",
|
||||
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
|
||||
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
|
||||
lldbg(" %08x %08x %08x %08x\n",
|
||||
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
|
||||
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
|
||||
|
||||
lldbg("SYSCON:\n");
|
||||
lldbg(" CPUID: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_CPUID));
|
||||
lldbg(" ICSR: %08x AIRCR: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
|
||||
lldbg(" SCR: %08x CCR: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
|
||||
lldbg(" SHPR2: %08x SHPR3: %08x\n",
|
||||
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
|
||||
|
||||
irqrestore(flags);
|
||||
}
|
||||
|
||||
#else
|
||||
# define lpc11_dumpnvic(msg, irq)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc11_nmi, lpc11_busfault, lpc11_usagefault, lpc11_pendsv,
|
||||
* lpc11_dbgmonitor, lpc11_pendsv, lpc11_reserved
|
||||
*
|
||||
* Description:
|
||||
* Handlers for various execptions. None are handled and all are fatal
|
||||
* error conditions. The only advantage these provided over the default
|
||||
* unexpected interrupt handler is that they provide a diagnostic output.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
static int lpc11_nmi(int irq, FAR void *context)
|
||||
{
|
||||
(void)irqsave();
|
||||
dbg("PANIC!!! NMI received\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpc11_pendsv(int irq, FAR void *context)
|
||||
{
|
||||
(void)irqsave();
|
||||
dbg("PANIC!!! PendSV received\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int lpc11_reserved(int irq, FAR void *context)
|
||||
{
|
||||
(void)irqsave();
|
||||
dbg("PANIC!!! Reserved interrupt\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc11_clrpend
|
||||
*
|
||||
* Description:
|
||||
* Clear a pending interrupt at the NVIC.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void lpc11_clrpend(int irq)
|
||||
{
|
||||
/* This will be called on each interrupt exit whether the interrupt can be
|
||||
* enambled or not. So this assertion is necessarily lame.
|
||||
*/
|
||||
|
||||
DEBUGASSERT((unsigned)irq < NR_IRQS);
|
||||
|
||||
/* Check for an external interrupt */
|
||||
|
||||
if (irq >= LPC11_IRQ_EXTINT && irq < (LPC11_IRQ_EXTINT + 32))
|
||||
{
|
||||
/* Set the appropriate bit in the ISER register to enable the
|
||||
* interrupt
|
||||
*/
|
||||
|
||||
putreg32((1 << (irq - LPC11_IRQ_EXTINT)), ARMV6M_NVIC_ICPR);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irqinitialize
|
||||
****************************************************************************/
|
||||
|
||||
void up_irqinitialize(void)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
int i;
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
putreg32(0xffffffff, ARMV6M_NVIC_ICER);
|
||||
|
||||
/* Set all interrupts (and exceptions) to the default priority */
|
||||
|
||||
putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR2);
|
||||
putreg32(DEFPRIORITY32, ARMV6M_SYSCON_SHPR3);
|
||||
|
||||
/* Now set all of the interrupt lines to the default priority */
|
||||
|
||||
for (i = 0; i < 8; i++)
|
||||
{
|
||||
regaddr = ARMV6M_NVIC_IPR(i);
|
||||
putreg32(DEFPRIORITY32, regaddr);
|
||||
}
|
||||
|
||||
/* currents_regs is non-NULL only while processing an interrupt */
|
||||
|
||||
current_regs = NULL;
|
||||
|
||||
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
|
||||
* exception is used for performing context switches; The Hard Fault
|
||||
* must also be caught because a SVCall may show up as a Hard Fault
|
||||
* under certain conditions.
|
||||
*/
|
||||
|
||||
irq_attach(LPC11_IRQ_SVCALL, up_svcall);
|
||||
irq_attach(LPC11_IRQ_HARDFAULT, up_hardfault);
|
||||
|
||||
/* Attach all other processor exceptions (except reset and sys tick) */
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
irq_attach(LPC11_IRQ_NMI, lpc11_nmi);
|
||||
irq_attach(LPC11_IRQ_PENDSV, lpc11_pendsv);
|
||||
irq_attach(LPC11_IRQ_RESERVED, lpc11_reserved);
|
||||
#endif
|
||||
|
||||
lpc11_dumpnvic("initial", NR_IRQS);
|
||||
|
||||
/* Initialize logic to support a second level of interrupt decoding for
|
||||
* configured pin interrupts.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_GPIO_IRQ
|
||||
lpc11_gpioirqinitialize();
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
|
||||
/* And finally, enable interrupts */
|
||||
|
||||
irqenable();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_disable_irq
|
||||
*
|
||||
* Description:
|
||||
* Disable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_disable_irq(int irq)
|
||||
{
|
||||
DEBUGASSERT((unsigned)irq < NR_IRQS);
|
||||
|
||||
/* Check for an external interrupt */
|
||||
|
||||
if (irq >= LPC11_IRQ_EXTINT && irq < (LPC11_IRQ_EXTINT + 32))
|
||||
{
|
||||
/* Set the appropriate bit in the ICER register to disable the
|
||||
* interrupt
|
||||
*/
|
||||
|
||||
putreg32((1 << (irq - LPC11_IRQ_EXTINT)), ARMV6M_NVIC_ICER);
|
||||
}
|
||||
|
||||
/* Handle processor exceptions. Only SysTick can be disabled */
|
||||
|
||||
else if (irq == LPC11_IRQ_SYSTICK)
|
||||
{
|
||||
modifyreg32(ARMV6M_SYSTICK_CSR, SYSTICK_CSR_ENABLE, 0);
|
||||
}
|
||||
|
||||
lpc11_dumpnvic("disable", irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_enable_irq
|
||||
*
|
||||
* Description:
|
||||
* Enable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_enable_irq(int irq)
|
||||
{
|
||||
/* This will be called on each interrupt exit whether the interrupt can be
|
||||
* enabled or not. So this assertion is necessarily lame.
|
||||
*/
|
||||
|
||||
DEBUGASSERT((unsigned)irq < NR_IRQS);
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= LPC11_IRQ_EXTINT && irq < (LPC11_IRQ_EXTINT + 32))
|
||||
{
|
||||
/* Set the appropriate bit in the ISER register to enable the
|
||||
* interrupt
|
||||
*/
|
||||
|
||||
putreg32((1 << (irq - LPC11_IRQ_EXTINT)), ARMV6M_NVIC_ISER);
|
||||
}
|
||||
|
||||
/* Handle processor exceptions. Only SysTick can be disabled */
|
||||
|
||||
else if (irq == LPC11_IRQ_SYSTICK)
|
||||
{
|
||||
modifyreg32(ARMV6M_SYSTICK_CSR, 0, SYSTICK_CSR_ENABLE);
|
||||
}
|
||||
|
||||
lpc11_dumpnvic("enable", irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_ack_irq
|
||||
*
|
||||
* Description:
|
||||
* Acknowledge the IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_ack_irq(int irq)
|
||||
{
|
||||
lpc11_clrpend(irq);
|
||||
}
|
||||
@@ -0,0 +1,355 @@
|
||||
/**************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_lowputc.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Included Files
|
||||
**************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include <arch/irq.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip/lpc11_syscon.h"
|
||||
#include "chip/lpc11_uart.h"
|
||||
|
||||
#include "lpc11_gpio.h"
|
||||
#include "lpc11_lowputc.h"
|
||||
#include "lpc11_serial.h"
|
||||
|
||||
/**************************************************************************
|
||||
* Private Definitions
|
||||
**************************************************************************/
|
||||
|
||||
/* Select UART parameters for the selected console */
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
# define CONSOLE_BASE LPC11_UART0_BASE
|
||||
# define CONSOLE_BAUD CONFIG_UART0_BAUD
|
||||
# define CONSOLE_BITS CONFIG_UART0_BITS
|
||||
# define CONSOLE_PARITY CONFIG_UART0_PARITY
|
||||
# define CONSOLE_2STOP CONFIG_UART0_2STOP
|
||||
#elif defined(HAVE_CONSOLE)
|
||||
# error "No CONFIG_UART0_SERIAL_CONSOLE Setting"
|
||||
#endif
|
||||
|
||||
/* Get word length setting for the console */
|
||||
|
||||
#if CONSOLE_BITS == 5
|
||||
# define CONSOLE_LCR_WLS UART_LCR_WLS_5BIT
|
||||
#elif CONSOLE_BITS == 6
|
||||
# define CONSOLE_LCR_WLS UART_LCR_WLS_6BIT
|
||||
#elif CONSOLE_BITS == 7
|
||||
# define CONSOLE_LCR_WLS UART_LCR_WLS_7BIT
|
||||
#elif CONSOLE_BITS == 8
|
||||
# define CONSOLE_LCR_WLS UART_LCR_WLS_8BIT
|
||||
#elif defined(HAVE_CONSOLE)
|
||||
# error "Invalid CONFIG_UARTn_BITS setting for console "
|
||||
#endif
|
||||
|
||||
/* Get parity setting for the console */
|
||||
|
||||
#if CONSOLE_PARITY == 0
|
||||
# define CONSOLE_LCR_PAR 0
|
||||
#elif CONSOLE_PARITY == 1
|
||||
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_ODD)
|
||||
#elif CONSOLE_PARITY == 2
|
||||
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_EVEN)
|
||||
#elif CONSOLE_PARITY == 3
|
||||
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK1)
|
||||
#elif CONSOLE_PARITY == 4
|
||||
# define CONSOLE_LCR_PAR (UART_LCR_PE|UART_LCR_PS_STICK0)
|
||||
#elif defined(HAVE_CONSOLE)
|
||||
# error "Invalid CONFIG_UARTn_PARITY setting for CONSOLE"
|
||||
#endif
|
||||
|
||||
/* Get stop-bit setting for the console and UART0-3 */
|
||||
|
||||
#if CONSOLE_2STOP != 0
|
||||
# define CONSOLE_LCR_STOP UART_LCR_STOP
|
||||
#else
|
||||
# define CONSOLE_LCR_STOP 0
|
||||
#endif
|
||||
|
||||
/* LCR and FCR values for the console */
|
||||
|
||||
#define CONSOLE_LCR_VALUE (CONSOLE_LCR_WLS | CONSOLE_LCR_PAR | CONSOLE_LCR_STOP)
|
||||
#define CONSOLE_FCR_VALUE (UART_FCR_RXTRIGGER_8 | UART_FCR_TXRST |\
|
||||
UART_FCR_RXRST | UART_FCR_FIFOEN)
|
||||
|
||||
/* Select a CCLK divider to produce the UART PCLK. The strategy is to select the
|
||||
* smallest divisor that results in an solution within range of the 16-bit
|
||||
* DLM and DLL divisor:
|
||||
*
|
||||
* BAUD = PCLK / (16 * DL), or
|
||||
* DL = PCLK / BAUD / 16
|
||||
*
|
||||
* The PCLK is determined by the UART-specific divisor:
|
||||
*
|
||||
* PCLK = CCLK / divisor
|
||||
*
|
||||
* Ignoring the fractional divider for now. (If you want to extend this driver
|
||||
* to support the fractional divider, see lpc43xx_uart.c. The LPC43xx uses
|
||||
* the same peripheral and that logic could easily leveraged here).
|
||||
*/
|
||||
|
||||
/* Calculate and optimal PCLKSEL0/1 divisor.
|
||||
* First, check divisor == 1. This works if the upper limit is met:
|
||||
*
|
||||
* DL < 0xffff, or
|
||||
* PCLK / BAUD / 16 < 0xffff, or
|
||||
* CCLK / BAUD / 16 < 0xffff, or
|
||||
* CCLK < BAUD * 0xffff * 16
|
||||
* BAUD > CCLK / 0xffff / 16
|
||||
*
|
||||
* And the lower limit is met (we can't allow DL to get very close to one).
|
||||
*
|
||||
* DL >= MinDL
|
||||
* CCLK / BAUD / 16 >= MinDL, or
|
||||
* BAUD <= CCLK / 16 / MinDL
|
||||
*/
|
||||
|
||||
#if CONSOLE_BAUD < (LPC11_CCLK / 16 / UART_MINDL)
|
||||
# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK
|
||||
# define CONSOLE_NUMERATOR (LPC11_CCLK)
|
||||
|
||||
/* Check divisor == 2. This works if:
|
||||
*
|
||||
* 2 * CCLK / BAUD / 16 < 0xffff, or
|
||||
* BAUD > CCLK / 0xffff / 8
|
||||
*
|
||||
* And
|
||||
*
|
||||
* 2 * CCLK / BAUD / 16 >= MinDL, or
|
||||
* BAUD <= CCLK / 8 / MinDL
|
||||
*/
|
||||
|
||||
#elif CONSOLE_BAUD < (LPC11_CCLK / 8 / UART_MINDL)
|
||||
# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK2
|
||||
# define CONSOLE_NUMERATOR (LPC11_CCLK / 2)
|
||||
|
||||
/* Check divisor == 4. This works if:
|
||||
*
|
||||
* 4 * CCLK / BAUD / 16 < 0xffff, or
|
||||
* BAUD > CCLK / 0xffff / 4
|
||||
*
|
||||
* And
|
||||
*
|
||||
* 4 * CCLK / BAUD / 16 >= MinDL, or
|
||||
* BAUD <= CCLK / 4 / MinDL
|
||||
*/
|
||||
|
||||
#elif CONSOLE_BAUD < (LPC11_CCLK / 4 / UART_MINDL)
|
||||
# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK4
|
||||
# define CONSOLE_NUMERATOR (LPC11_CCLK / 4)
|
||||
|
||||
/* Check divisor == 8. This works if:
|
||||
*
|
||||
* 8 * CCLK / BAUD / 16 < 0xffff, or
|
||||
* BAUD > CCLK / 0xffff / 2
|
||||
*
|
||||
* And
|
||||
*
|
||||
* 8 * CCLK / BAUD / 16 >= MinDL, or
|
||||
* BAUD <= CCLK / 2 / MinDL
|
||||
*/
|
||||
|
||||
#else /* if CONSOLE_BAUD < (LPC11_CCLK / 2 / UART_MINDL) */
|
||||
# define CONSOLE_CCLKDIV SYSCON_PCLKSEL_CCLK8
|
||||
# define CONSOLE_NUMERATOR (LPC11_CCLK / 8)
|
||||
#endif
|
||||
|
||||
/* Then this is the value to use for the DLM and DLL registers */
|
||||
|
||||
#define CONSOLE_DL (CONSOLE_NUMERATOR / (CONSOLE_BAUD << 4))
|
||||
|
||||
/**************************************************************************
|
||||
* Private Types
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Private Function Prototypes
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Global Variables
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Private Variables
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Private Functions
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Public Functions
|
||||
**************************************************************************/
|
||||
|
||||
/**************************************************************************
|
||||
* Name: up_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one byte on the serial console
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
void up_lowputc(char ch)
|
||||
{
|
||||
#if defined HAVE_UART && defined HAVE_CONSOLE
|
||||
/* Wait for the transmitter to be available */
|
||||
|
||||
while ((getreg32(CONSOLE_BASE+LPC11_UART_LSR_OFFSET) & UART_LSR_THRE) == 0);
|
||||
|
||||
/* Send the character */
|
||||
|
||||
putreg32((uint32_t)ch, CONSOLE_BASE+LPC11_UART_THR_OFFSET);
|
||||
#endif
|
||||
}
|
||||
|
||||
/**************************************************************************
|
||||
* Name: lpc11_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* This performs basic initialization of the UART used for the serial
|
||||
* console. Its purpose is to get the console output availabe as soon
|
||||
* as possible.
|
||||
*
|
||||
* The UART peripheral is configured using the following registers:
|
||||
* 1. Pins: For the LPC111x/101/201/301 parts, the UART pins must be
|
||||
* configured in the IOCONFIG register block before the UART clocks can
|
||||
* be enabled in the SYSAHBCLKCTRL register. For all other parts, no
|
||||
* special enabling sequence is required.
|
||||
* 2. Power: In the SYSAHBCLKCTRL register, set bit 12.
|
||||
* On reset, UART is disabled.
|
||||
* 3. Peripheral clock: Enable the UART peripheral clock by writing to the
|
||||
* UARTCLKDIV register.
|
||||
*
|
||||
**************************************************************************/
|
||||
|
||||
void lpc11_lowsetup(void)
|
||||
{
|
||||
#ifdef HAVE_UART
|
||||
uint32_t regval;
|
||||
|
||||
/* Enable clock for GPIO and I/O block */
|
||||
|
||||
regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL);
|
||||
regval |= (SYSCON_SYSAHBCLKCTRL_GPIO | SYSCON_SYSAHBCLKCTRL_IOCON);
|
||||
putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL);
|
||||
|
||||
|
||||
/* Step 1: Pins configuration */
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
lpc11_configgpio(GPIO_UART0_TXD);
|
||||
lpc11_configgpio(GPIO_UART0_RXD);
|
||||
#endif
|
||||
|
||||
/* Step 2: Enable power for all console UART and disable power for
|
||||
* other UARTs
|
||||
*/
|
||||
regval = getreg32(LPC11_SYSCON_SYSAHBCLKCTRL);
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
regval |= SYSCON_SYSAHBCLKCTRL_UART;
|
||||
#endif
|
||||
putreg32(regval, LPC11_SYSCON_SYSAHBCLKCTRL);
|
||||
|
||||
/* Step 3: Enable peripheral clocking for the console UART and disable
|
||||
* clocking for all other UARTs
|
||||
*/
|
||||
|
||||
putreg32(1, LPC11_SYSCON_UARTCLKDIV);
|
||||
|
||||
/* Configure Baud rate */
|
||||
|
||||
|
||||
/* Configure the console (only) */
|
||||
|
||||
#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_UART_CONFIG)
|
||||
|
||||
/* Clear fifos */
|
||||
|
||||
putreg32(UART_FCR_RXRST|UART_FCR_TXRST, CONSOLE_BASE+LPC11_UART_FCR_OFFSET);
|
||||
|
||||
/* Set trigger */
|
||||
|
||||
putreg32(UART_FCR_FIFOEN|UART_FCR_RXTRIGGER_8, CONSOLE_BASE+LPC11_UART_FCR_OFFSET);
|
||||
|
||||
/* Set up the LCR and set DLAB=1 */
|
||||
|
||||
putreg32(CONSOLE_LCR_VALUE|UART_LCR_DLAB, CONSOLE_BASE+LPC11_UART_LCR_OFFSET);
|
||||
|
||||
/* Set the BAUD divisor */
|
||||
|
||||
//putreg32(CONSOLE_DL >> 8, CONSOLE_BASE+LPC11_UART_DLM_OFFSET);
|
||||
//putreg32(CONSOLE_DL & 0xff, CONSOLE_BASE+LPC11_UART_DLL_OFFSET);
|
||||
|
||||
regval = getreg32(LPC11_UART0_LCR);
|
||||
regval |= UART_LCR_DLAB;
|
||||
putreg32(regval, LPC11_UART0_LCR);
|
||||
|
||||
putreg32((1 << UART_FDR_MULVAL_SHIFT), LPC11_UART0_FDR);
|
||||
|
||||
putreg32(56, LPC11_UART0_DLL);
|
||||
|
||||
putreg32(1, LPC11_UART0_DLM);
|
||||
|
||||
regval = getreg32(LPC11_UART0_LCR);
|
||||
regval &= ~UART_LCR_DLAB;
|
||||
putreg32(regval, LPC11_UART0_LCR);
|
||||
|
||||
regval = getreg32(LPC11_UART0_LCR);
|
||||
regval |= UART_LCR_WLS_8BIT;
|
||||
putreg32(regval, LPC11_UART0_LCR);
|
||||
|
||||
/* Clear DLAB */
|
||||
|
||||
//putreg32(CONSOLE_LCR_VALUE, CONSOLE_BASE+LPC11_UART_LCR_OFFSET);
|
||||
|
||||
/* Configure the FIFOs */
|
||||
|
||||
putreg32(UART_FCR_RXTRIGGER_8|UART_FCR_TXRST|UART_FCR_RXRST|UART_FCR_FIFOEN,
|
||||
CONSOLE_BASE+LPC11_UART_FCR_OFFSET);
|
||||
#endif
|
||||
#endif /* HAVE_UART */
|
||||
}
|
||||
@@ -0,0 +1,84 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_lowputc.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_LOWPUTC_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_LOWPUTC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* Called at the very beginning of _start. Performs low level initialization
|
||||
* including setup of the console UART. This UART done early so that the serial
|
||||
* console is available for debugging very early in the boot sequence.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lpc11_lowsetup(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_LOWPUTC_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,98 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_serial.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_SERIAL_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_SERIAL_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "chip/lpc11_uart.h"
|
||||
#include "chip/lpc11_syscon.h"
|
||||
|
||||
#include "lpc11_gpio.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/* Configuration *********************************************************************/
|
||||
|
||||
/* Are any UARTs enabled? */
|
||||
|
||||
#undef HAVE_UART
|
||||
#if defined(CONFIG_LPC11_UART0)
|
||||
# define HAVE_UART 1
|
||||
#endif
|
||||
|
||||
/* Is there a serial console? There should be at most one defined. It could be on
|
||||
* any UARTn, n=0,1,2,3
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_UART0_SERIAL_CONSOLE) && defined(CONFIG_LPC11_UART0)
|
||||
# define HAVE_CONSOLE 1
|
||||
#else
|
||||
# undef CONFIG_UART0_SERIAL_CONSOLE
|
||||
# undef HAVE_CONSOLE
|
||||
#endif
|
||||
|
||||
/* We cannot allow the DLM/DLL divisor to become to small or will will lose too
|
||||
* much accuracy. This following is a "fudge factor" that represents the minimum
|
||||
* value of the divisor that we will permit.
|
||||
*/
|
||||
|
||||
#define UART_MINDL 32
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_SERIAL_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,170 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_spi.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_SPI_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_SPI_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/spi/spi.h>
|
||||
|
||||
#include "chip/lpc11_spi.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_LPC11_SPI
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_spiinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SPI port.
|
||||
*
|
||||
* Input Parameter:
|
||||
* Port number (for hardware that has mutiple SPI interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on succcess; a NULL on failure
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
FAR struct spi_dev_s *lpc11_spiinitialize(int port);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_spiselect, lpc11_status, and lpc11_spicmddata
|
||||
*
|
||||
* Description:
|
||||
* These external functions must be provided by board-specific logic. They are
|
||||
* implementations of the select, status, and cmddata methods of the SPI interface
|
||||
* defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods
|
||||
* including lpc11_spiinitialize()) are provided by common LPC11xx logic. To use
|
||||
* this common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in lpc11_boardinitialize() to configure SPI chip select pins.
|
||||
* 2. Provide lpc11_spiselect() and lpc11_spistatus() functions in your board-
|
||||
* specific logic. These functions will perform chip selection and status
|
||||
* operations using GPIOs in the way your board is configured.
|
||||
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
|
||||
* lpc11_spicmddata() functions in your board-specific logic. This function
|
||||
* will perform cmd/data selection operations using GPIOs in the way your
|
||||
* board is configured.
|
||||
* 3. Add a call to lpc11_spiinitialize() in your low level application
|
||||
* initialization logic
|
||||
* 4. The handle returned by lpc11_spiinitialize() may then be used to bind the
|
||||
* SPI driver to higher level logic (e.g., calling mmcsd_spislotinitialize(),
|
||||
* for example, will bind the SPI driver to the SPI MMC/SD driver).
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void lpc11_spiselect(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
uint8_t lpc11_spistatus(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
int lpc11_spicmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: spi_flush
|
||||
*
|
||||
* Description:
|
||||
* Flush and discard any words left in the RX fifo. This can be called
|
||||
* from spiselect after a device is deselected (if you worry about such
|
||||
* things).
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
void spi_flush(FAR struct spi_dev_s *dev);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_spiregister
|
||||
*
|
||||
* Description:
|
||||
* If the board supports a card detect callback to inform the SPI-based
|
||||
* MMC/SD drvier when an SD card is inserted or removed, then
|
||||
* CONFIG_SPI_CALLBACK should be defined and the following function must
|
||||
* must be implemented. These functions implements the registercallback
|
||||
* method of the SPI interface (see include/nuttx/spi/spi.h for details)
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* callback - The funtion to call on the media change
|
||||
* arg - A caller provided value to return with the callback
|
||||
*
|
||||
* Returned Value:
|
||||
* 0 on success; negated errno on failure.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CALLBACK
|
||||
int lpc11_spiregister(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_LPC11_SPI */
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_SPI_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,189 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_ssp.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_SSP_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_SSP_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/spi/spi.h>
|
||||
|
||||
#include "chip/lpc11_ssp.h"
|
||||
|
||||
#if defined(CONFIG_LPC11_SSP0) || defined(CONFIG_LPC11_SSP1)
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
#ifdef __cplusplus
|
||||
extern "C"
|
||||
{
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_sspinitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SSP port.
|
||||
*
|
||||
* Input Parameter:
|
||||
* Port number (for hardware that has multiple SPI interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on success; a NULL on failure
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
FAR struct spi_dev_s *lpc11_sspinitialize(int port);
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_ssp0/ssp1select, lpc11_ssp0/ssp1status, and lpc11_ssp0/ssp1cmddata
|
||||
*
|
||||
* Description:
|
||||
* These external functions must be provided by board-specific logic. They are
|
||||
* implementations of the select, status, and cmddata methods of the SPI interface
|
||||
* defined by struct spi_ops_s (see include/nuttx/spi/spi.h). All other methods
|
||||
* including lpc11_sspinitialize()) are provided by common LPC11xx logic. To use
|
||||
* this common SPI logic on your board:
|
||||
*
|
||||
* 1. Provide logic in lpc11_boardinitialize() to configure SSP chip select pins.
|
||||
* 2. Provide lpc11_ssp0/ssp1select() and lpc11_ssp0/ssp1status() functions
|
||||
* in your board-specific logic. These functions will perform chip selection
|
||||
* and status operations using GPIOs in the way your board is configured.
|
||||
* 2. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, provide
|
||||
* lpc11_ssp0/ssp1cmddata() functions in your board-specific logic. These
|
||||
* functions will perform cmd/data selection operations using GPIOs in the way
|
||||
* your board is configured.
|
||||
* 3. Add a call to lpc11_sspinitialize() in your low level application
|
||||
* initialization logic
|
||||
* 4. The handle returned by lpc11_sspinitialize() may then be used to bind the
|
||||
* SSP driver to higher level logic (e.g., calling mmcsd_spislotinitialize(),
|
||||
* for example, will bind the SSP driver to the SPI MMC/SD driver).
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_LPC11_SSP0
|
||||
void lpc11_ssp0select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
uint8_t lpc11_ssp0status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
int lpc11_ssp0cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPC11_SSP1
|
||||
void lpc11_ssp1select(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool selected);
|
||||
uint8_t lpc11_ssp1status(FAR struct spi_dev_s *dev, enum spi_dev_e devid);
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
int lpc11_ssp1cmddata(FAR struct spi_dev_s *dev, enum spi_dev_e devid, bool cmd);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: ssp_flush
|
||||
*
|
||||
* Description:
|
||||
* Flush and discard any words left in the RX fifo. This can be called
|
||||
* from ssp0/1select after a device is deselected (if you worry about such
|
||||
* things).
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#if defined(CONFIG_LPC11_SSP0) || defined(CONFIG_LPC11_SSP1)
|
||||
void ssp_flush(FAR struct spi_dev_s *dev);
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Name: lpc11_ssp0/1register
|
||||
*
|
||||
* Description:
|
||||
* If the board supports a card detect callback to inform the SPI-based
|
||||
* MMC/SD drvier when an SD card is inserted or removed, then
|
||||
* CONFIG_SPI_CALLBACK should be defined and the following function(s) must
|
||||
* must be implemented. These functiosn implements the registercallback
|
||||
* method of the SPI interface (see include/nuttx/spi/spi.h for details)
|
||||
*
|
||||
* Input Parameters:
|
||||
* dev - Device-specific state data
|
||||
* callback - The funtion to call on the media change
|
||||
* arg - A caller provided value to return with the callback
|
||||
*
|
||||
* Returned Value:
|
||||
* 0 on success; negated errno on failure.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifdef CONFIG_SPI_CALLBACK
|
||||
#ifdef CONFIG_LPC11_SSP0
|
||||
int lpc11_ssp0register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LPC11_SSP1
|
||||
int lpc11_ssp1register(FAR struct spi_dev_s *dev, spi_mediachange_t callback,
|
||||
FAR void *arg);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_LPC11_SSP0 || CONFIG_LPC11_SSP1 */
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_SSP_H */
|
||||
@@ -0,0 +1,175 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_start.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/init.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
#include "lpc11_clockconfig.h"
|
||||
#include "lpc11_lowputc.h"
|
||||
#include "lpc11_userspace.h"
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
# include "nvic.h"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
#define IDLE_STACK ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE-4)
|
||||
#define HEAP_BASE ((uint32_t)&_ebss+CONFIG_IDLETHREAD_STACKSIZE)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
const uint32_t g_idle_topstack = IDLE_STACK;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: showprogress
|
||||
*
|
||||
* Description:
|
||||
* Print a character on the UART to show boot status.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG
|
||||
# define showprogress(c) up_lowputc(c)
|
||||
#else
|
||||
# define showprogress(c)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: _start
|
||||
*
|
||||
* Description:
|
||||
* This is the reset entry point.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void __start(void)
|
||||
{
|
||||
const uint32_t *src;
|
||||
uint32_t *dest;
|
||||
|
||||
/* Configure the uart so that we can get debug output as soon as possible */
|
||||
|
||||
lpc11_clockconfig();
|
||||
lpc11_lowsetup();
|
||||
showprogress('A');
|
||||
|
||||
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
|
||||
* certain that there are no issues with the state of global variables.
|
||||
*/
|
||||
|
||||
for (dest = &_sbss; dest < &_ebss; )
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
|
||||
showprogress('B');
|
||||
|
||||
/* Move the initialized data section from his temporary holding spot in
|
||||
* FLASH into the correct place in SRAM. The correct place in SRAM is
|
||||
* give by _sdata and _edata. The temporary location is in FLASH at the
|
||||
* end of all of the other read-only data (.text, .rodata) at _eronly.
|
||||
*/
|
||||
|
||||
for (src = &_eronly, dest = &_sdata; dest < &_edata; )
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
showprogress('C');
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
up_earlyserialinit();
|
||||
#endif
|
||||
showprogress('D');
|
||||
|
||||
/* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
* Normally this just means initializing the user space .data and .bss
|
||||
* segments.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
lpc11_userspace();
|
||||
showprogress('E');
|
||||
#endif
|
||||
|
||||
/* Initialize onboard resources */
|
||||
|
||||
lpc11_boardinitialize();
|
||||
showprogress('F');
|
||||
|
||||
/* Then start NuttX */
|
||||
|
||||
showprogress('\r');
|
||||
showprogress('\n');
|
||||
|
||||
os_start();
|
||||
|
||||
/* Shouldn't get here */
|
||||
|
||||
for (;;);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,62 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/lpc17_timer.h
|
||||
*
|
||||
* Copyright (C) 2010, 2012-2013 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip/lpc17_timer.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_TIMER_H */
|
||||
@@ -0,0 +1,167 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_timerisr.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <debug.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "nvic.h"
|
||||
#include "clock/clock.h"
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
/* "The CLKSOURCE bit in SysTick Control and Status register selects either
|
||||
* the core clock (when CLKSOURCE = 1) or a divide-by-16 of the core clock
|
||||
* (when CLKSOURCE = 0). ..."
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_LPC11_SYSTICK_CORECLK)
|
||||
# define SYSTICK_CLOCK LPC11_MCLK /* Core clock */
|
||||
#elif defined(CONFIG_LPC11_SYSTICK_CORECLK_DIV16)
|
||||
# define SYSTICK_CLOCK (LPC11_MCLK / 16) /* Core clock divided by 16 */
|
||||
#endif
|
||||
|
||||
/* The desired timer interrupt frequency is provided by the definition
|
||||
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
|
||||
* system clock ticks per second. That value is a user configurable setting
|
||||
* that defaults to 100 (100 ticks per second = 10 MS interval).
|
||||
*
|
||||
* Then, for example, if the external high speed crystal is the SysTick
|
||||
* clock source and BOARD_XTALHI_FREQUENCY is 12MHz and CLK_TCK is 100, then
|
||||
* the reload value would be:
|
||||
*
|
||||
* SYSTICK_RELOAD = (12,000,000 / 100) - 1
|
||||
* = 119,999
|
||||
* = 0x1d4bf
|
||||
*
|
||||
* Which fits within the maximum 24-bit reload value.
|
||||
*/
|
||||
|
||||
#define SYSTICK_RELOAD ((SYSTICK_CLOCK / CLK_TCK) - 1)
|
||||
|
||||
/* The size of the reload field is 24 bits. Verify that the reload value
|
||||
* will fit in the reload register.
|
||||
*/
|
||||
|
||||
#if SYSTICK_RELOAD > 0x00ffffff
|
||||
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Global Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timerisr
|
||||
*
|
||||
* Description:
|
||||
* The timer ISR will perform a variety of services for various portions
|
||||
* of the systems.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_timerisr(int irq, uint32_t *regs)
|
||||
{
|
||||
/* Process timer interrupt */
|
||||
|
||||
sched_process_timer();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* This function is called during start-up to initialize
|
||||
* the timer interrupt.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_timer_initialize(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the SysTick interrupt to the default priority */
|
||||
|
||||
regval = getreg32(ARMV6M_SYSCON_SHPR3);
|
||||
regval &= ~SYSCON_SHPR3_PRI_15_MASK;
|
||||
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << SYSCON_SHPR3_PRI_15_SHIFT);
|
||||
putreg32(regval, ARMV6M_SYSCON_SHPR3);
|
||||
|
||||
/* Configure SysTick to interrupt at the requested rate */
|
||||
|
||||
putreg32(SYSTICK_RELOAD, ARMV6M_SYSTICK_RVR);
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
(void)irq_attach(LPC11_IRQ_SYSTICK, (xcpt_t)up_timerisr);
|
||||
|
||||
/* Enable SysTick interrupts. "The CLKSOURCE bit in SysTick Control and
|
||||
* Status register selects either the core clock (when CLKSOURCE = 1) or
|
||||
* a divide-by-16 of the core clock (when CLKSOURCE = 0). ..."
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_LPC11_SYSTICK_CORECLK
|
||||
putreg32((SYSTICK_CSR_CLKSOURCE | SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE),
|
||||
ARMV6M_SYSTICK_CSR);
|
||||
#else
|
||||
putreg32((SYSTICK_CSR_TICKINT | SYSTICK_CSR_ENABLE), ARMV6M_SYSTICK_CSR);
|
||||
#endif
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(LPC11_IRQ_SYSTICK);
|
||||
}
|
||||
@@ -0,0 +1,118 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_userspace.c
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include <nuttx/userspace.h>
|
||||
|
||||
#include "lpc11_mpuinit.h"
|
||||
#include "lpc11_userspace.h"
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc11_userspace
|
||||
*
|
||||
* Description:
|
||||
* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
* Normally this just means initializing the user space .data and .bss
|
||||
* segments.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void lpc11_userspace(void)
|
||||
{
|
||||
uint8_t *src;
|
||||
uint8_t *dest;
|
||||
uint8_t *end;
|
||||
|
||||
/* Clear all of user-space .bss */
|
||||
|
||||
DEBUGASSERT(USERSPACE->us_bssstart != 0 && USERSPACE->us_bssend != 0 &&
|
||||
USERSPACE->us_bssstart <= USERSPACE->us_bssend);
|
||||
|
||||
dest = (uint8_t*)USERSPACE->us_bssstart;
|
||||
end = (uint8_t*)USERSPACE->us_bssend;
|
||||
|
||||
while (dest != end)
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
|
||||
/* Initialize all of user-space .data */
|
||||
|
||||
DEBUGASSERT(USERSPACE->us_datasource != 0 &&
|
||||
USERSPACE->us_datastart != 0 && USERSPACE->us_dataend != 0 &&
|
||||
USERSPACE->us_datastart <= USERSPACE->us_dataend);
|
||||
|
||||
src = (uint8_t*)USERSPACE->us_datasource;
|
||||
dest = (uint8_t*)USERSPACE->us_datastart;
|
||||
end = (uint8_t*)USERSPACE->us_dataend;
|
||||
|
||||
while (dest != end)
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
/* Configure the MPU to permit user-space access to its FLASH and RAM */
|
||||
|
||||
lpc11_mpuinitialize();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_BUILD_PROTECTED */
|
||||
@@ -0,0 +1,76 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc17xx/lpc17_userspace.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: lpc17_userspace
|
||||
*
|
||||
* Description:
|
||||
* For the case of the separate user-/kernel-space build, perform whatever
|
||||
* platform specific initialization of the user memory is required.
|
||||
* Normally this just means initializing the user space .data and .bss
|
||||
* segments.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_BUILD_PROTECTED
|
||||
void lpc17_userspace(void);
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_USERSPACE_H */
|
||||
@@ -0,0 +1,62 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11xx/lpc11_wdt.h
|
||||
*
|
||||
* Copyright (C) 2015 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H
|
||||
#define __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "chip/lpc11_wdt.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC17XX_LPC17_WDT_H */
|
||||
Reference in New Issue
Block a user