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mps:Supplement the interrupt definition about nvic

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Signed-off-by: anjiahao <anjiahao@xiaomi.com>
Signed-off-by: ligd <liguiding1@xiaomi.com>
This commit is contained in:
anjiahao
2024-05-10 16:57:34 +08:00
committed by Xiang Xiao
parent 9f97d9abb0
commit 9122c3e44d
2 changed files with 2 additions and 2 deletions
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arch/arm/include/mps/chip.h
+2
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@@ -32,6 +32,8 @@
****************************************************************************/
#define NVIC_SYSH_PRIORITY_MIN 0xe0 /* Bits [7:5] set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Steps between priorities */
/****************************************************************************
* Public Types
arch/arm/src/mps/mps_irq.h
-2
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@@ -50,8 +50,6 @@
#define MPS_IRQ_FIRST (16) /* Vector number of the first external interrupt */
#define NVIC_SYSH_PRIORITY_DEFAULT (0x80) /* Midpoint is the default */
#ifndef __ASSEMBLY__
#undef EXTERN