Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-05-23 14:58:13 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

arch/arm/src/am335x/hardware: Add register description files for DCAN and LCD.

Browse Source
This commit is contained in:
Petro Karashchenko
2019-07-06 06:57:05 -06:00
committed by Gregory Nutt
parent ea44bc5691
commit 90bed3383e
4 changed files with 714 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/am335x/hardware/am335x_dcan.h
+423
View File
@@ -0,0 +1,423 @@
/********************************************************************************************
* arch/arm/src/am335x/hardware/am335x_cm.h
*
* Copyright (C) 2019 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
********************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_DCAN_H
#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_DCAN_H
/********************************************************************************************
* Included Files
********************************************************************************************/
#include <nuttx/config.h>
#include <hardware/am335x_memorymap.h>
/********************************************************************************************
* Pre-processor Definitions
********************************************************************************************/
/* Register offsets *****************************************************************/
#define AM335X_DCAN_CTL_OFFSET 0x0000 /* CAN Control Register */
#define AM335X_DCAN_ES_OFFSET 0x0004 /* Error and Status Register */
#define AM335X_DCAN_ERRC_OFFSET 0x0008 /* Error Counter Register */
#define AM335X_DCAN_BTR_OFFSET 0x000c /* Bit Timing Register */
#define AM335X_DCAN_INT_OFFSET 0x0010 /* Interrupt Register */
#define AM335X_DCAN_TEST_OFFSET 0x0014 /* Test Register */
#define AM335X_DCAN_PERR_OFFSET 0x001c /* Parity Error Code Register */
#define AM335X_DCAN_ABOTR_OFFSET 0x0080 /* Auto-Bus-On Time Register */
#define AM335X_DCAN_TXRQ_X_OFFSET 0x0084 /* Transmission Request X Register */
#define AM335X_DCAN_TXRQ12_OFFSET 0x0088 /* Transmission Request Register 12 */
#define AM335X_DCAN_TXRQ34_OFFSET 0x008c /* Transmission Request Register 34 */
#define AM335X_DCAN_TXRQ56_OFFSET 0x0090 /* Transmission Request Register 56 */
#define AM335X_DCAN_TXRQ78_OFFSET 0x0094 /* Transmission Request Register 78 */
#define AM335X_DCAN_NWDAT_X_OFFSET 0x0098 /* New Data X Register */
#define AM335X_DCAN_NWDAT12_OFFSET 0x009c /* New Data Register 12 */
#define AM335X_DCAN_NWDAT34_OFFSET 0x00a0 /* New Data Register 34 */
#define AM335X_DCAN_NWDAT56_OFFSET 0x00a4 /* New Data Register 56 */
#define AM335X_DCAN_NWDAT78_OFFSET 0x00a8 /* New Data Register 78 */
#define AM335X_DCAN_INTPND_X_OFFSET 0x00ac /* Interrupt Pending X Register */
#define AM335X_DCAN_INTPND12_OFFSET 0x00b0 /* Interrupt Pending Register 12 */
#define AM335X_DCAN_INTPND34_OFFSET 0x00b4 /* Interrupt Pending Register 34 */
#define AM335X_DCAN_INTPND56_OFFSET 0x00b8 /* Interrupt Pending Register 56 */
#define AM335X_DCAN_INTPND78_OFFSET 0x00bc /* Interrupt Pending Register 78 */
#define AM335X_DCAN_MSGVAL_X_OFFSET 0x00c0 /* Message Valid X Register */
#define AM335X_DCAN_MSGVAL12_OFFSET 0x00c4 /* Message Valid Register 12 */
#define AM335X_DCAN_MSGVAL34_OFFSET 0x00c8 /* Message Valid Register 34 */
#define AM335X_DCAN_MSGVAL56_OFFSET 0x00cc /* Message Valid Register 56 */
#define AM335X_DCAN_MSGVAL78_OFFSET 0x00d0 /* Message Valid Register 78 */
#define AM335X_DCAN_INTMUX12_OFFSET 0x00d8 /* Interrupt Multiplexer Register 12 */
#define AM335X_DCAN_INTMUX34_OFFSET 0x00dc /* Interrupt Multiplexer Register 34 */
#define AM335X_DCAN_INTMUX56_OFFSET 0x00e0 /* Interrupt Multiplexer Register 56 */
#define AM335X_DCAN_INTMUX78_OFFSET 0x00e4 /* Interrupt Multiplexer Register 78 */
#define AM335X_DCAN_IF1CMD_OFFSET 0x0100 /* IF1 Command Registers */
#define AM335X_DCAN_IF1MSK_OFFSET 0x0104 /* IF1 Mask Register */
#define AM335X_DCAN_IF1ARB_OFFSET 0x0108 /* IF1 Arbitration Register */
#define AM335X_DCAN_IF1MCTL_OFFSET 0x010c /* IF1 Message Control Register */
#define AM335X_DCAN_IF1DATA_OFFSET 0x0110 /* IF1 Data A Register */
#define AM335X_DCAN_IF1DATB_OFFSET 0x0114 /* IF1 Data B Register */
#define AM335X_DCAN_IF2CMD_OFFSET 0x0120 /* IF2 Command Registers */
#define AM335X_DCAN_IF2MSK_OFFSET 0x0124 /* IF2 Mask Register */
#define AM335X_DCAN_IF2ARB_OFFSET 0x0128 /* IF2 Arbitration Register */
#define AM335X_DCAN_IF2MCTL_OFFSET 0x012c /* IF2 Message Control Register */
#define AM335X_DCAN_IF2DATA_OFFSET 0x0130 /* IF2 Data A Register */
#define AM335X_DCAN_IF2DATB_OFFSET 0x0134 /* IF2 Data B Register */
#define AM335X_DCAN_IF3OBS_OFFSET 0x0140 /* IF3 Observation Register */
#define AM335X_DCAN_IF3MSK_OFFSET 0x0144 /* IF3 Mask Register */
#define AM335X_DCAN_IF3ARB_OFFSET 0x0148 /* IF3 Arbitration Register */
#define AM335X_DCAN_IF3MCTL_OFFSET 0x014c /* IF3 Message Control Register */
#define AM335X_DCAN_IF3DATA_OFFSET 0x0150 /* IF3 Data A Register */
#define AM335X_DCAN_IF3DATB_OFFSET 0x0154 /* IF3 Data B Register */
#define AM335X_DCAN_IF3UPD12_OFFSET 0x0160 /* IF3 Update Enable Register 12 */
#define AM335X_DCAN_IF3UPD34_OFFSET 0x0164 /* IF3 Update Enable Register 34 */
#define AM335X_DCAN_IF3UPD56_OFFSET 0x0168 /* IF3 Update Enable Register 56 */
#define AM335X_DCAN_IF3UPD78_OFFSET 0x016c /* IF3 Update Enable Register 78 */
#define AM335X_DCAN_TIOC_OFFSET 0x01e0 /* CAN TX IO Control Register */
#define AM335X_DCAN_RIOC_OFFSET 0x01e4 /* CAN RX IO Control Register */
#define AM335X_DCAN_TXRQ_OFFSET(n) (0x0088 + ((((unsigned int)(n) - 1) >> 5) << 2))
#define AM335X_DCAN_NWDAT_OFFSET(n) (0x009c + ((((unsigned int)(n) - 1) >> 5) << 2))
#define AM335X_DCAN_INTPND_OFFSET(n) (0x00b0 + ((((unsigned int)(n) - 1) >> 5) << 2))
#define AM335X_DCAN_MSGVAL_OFFSET(n) (0x00c4 + ((((unsigned int)(n) - 1) >> 5) << 2))
#define AM335X_DCAN_INTMUX_OFFSET(n) (0x00d8 + ((((unsigned int)(n) - 1) >> 5) << 2))
#define AM335X_DCAN_IFCMD_OFFSET(n) (0x0100 + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IFMSK_OFFSET(n) (0x0104 + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IFARB_OFFSET(n) (0x0108 + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IFMCTL_OFFSET(n) (0x010c + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IFDATA_OFFSET(n) (0x0110 + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IFDATB_OFFSET(n) (0x0114 + ((unsigned int)(n) - 1) * 0x20)
#define AM335X_DCAN_IF3UPD_OFFSET(n) (0x0160 + ((((unsigned int)(n) - 1) >> 5) << 2))
/* Register virtual addresses *******************************************************/
#define AM335X_DCAN0_CTL (AM335X_DCAN0_VADDR + AM335X_DCAN_CTL_OFFSET)
#define AM335X_DCAN0_ES (AM335X_DCAN0_VADDR + AM335X_DCAN_ES_OFFSET)
#define AM335X_DCAN0_ERRC (AM335X_DCAN0_VADDR + AM335X_DCAN_ERRC_OFFSET)
#define AM335X_DCAN0_BTR (AM335X_DCAN0_VADDR + AM335X_DCAN_BTR_OFFSET)
#define AM335X_DCAN0_INT (AM335X_DCAN0_VADDR + AM335X_DCAN_INT_OFFSET)
#define AM335X_DCAN0_TEST (AM335X_DCAN0_VADDR + AM335X_DCAN_TEST_OFFSET)
#define AM335X_DCAN0_PERR (AM335X_DCAN0_VADDR + AM335X_DCAN_PERR_OFFSET)
#define AM335X_DCAN0_ABOTR (AM335X_DCAN0_VADDR + AM335X_DCAN_ABOTR_OFFSET)
#define AM335X_DCAN0_TXRQ_X (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ_X_OFFSET)
#define AM335X_DCAN0_TXRQ12 (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ12_OFFSET)
#define AM335X_DCAN0_TXRQ34 (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ34_OFFSET)
#define AM335X_DCAN0_TXRQ56 (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ56_OFFSET)
#define AM335X_DCAN0_TXRQ78 (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ78_OFFSET)
#define AM335X_DCAN0_NWDAT_X (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT_X_OFFSET)
#define AM335X_DCAN0_NWDAT12 (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT12_OFFSET)
#define AM335X_DCAN0_NWDAT34 (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT34_OFFSET)
#define AM335X_DCAN0_NWDAT56 (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT56_OFFSET)
#define AM335X_DCAN0_NWDAT78 (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT78_OFFSET)
#define AM335X_DCAN0_INTPND_X (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND_X_OFFSET)
#define AM335X_DCAN0_INTPND12 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND12_OFFSET)
#define AM335X_DCAN0_INTPND34 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND34_OFFSET)
#define AM335X_DCAN0_INTPND56 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND56_OFFSET)
#define AM335X_DCAN0_INTPND78 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND78_OFFSET)
#define AM335X_DCAN0_MSGVAL_X (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL_X_OFFSET)
#define AM335X_DCAN0_MSGVAL12 (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL12_OFFSET)
#define AM335X_DCAN0_MSGVAL34 (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL34_OFFSET)
#define AM335X_DCAN0_MSGVAL56 (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL56_OFFSET)
#define AM335X_DCAN0_MSGVAL78 (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL78_OFFSET)
#define AM335X_DCAN0_INTMUX12 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTMUX12_OFFSET)
#define AM335X_DCAN0_INTMUX34 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTMUX34_OFFSET)
#define AM335X_DCAN0_INTMUX56 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTMUX56_OFFSET)
#define AM335X_DCAN0_INTMUX78 (AM335X_DCAN0_VADDR + AM335X_DCAN_INTMUX78_OFFSET)
#define AM335X_DCAN0_IF1CMD (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1CMD_OFFSET)
#define AM335X_DCAN0_IF1MSK (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1MSK_OFFSET)
#define AM335X_DCAN0_IF1ARB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1ARB_OFFSET)
#define AM335X_DCAN0_IF1MCTL (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1MCTL_OFFSET)
#define AM335X_DCAN0_IF1DATA (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1DATA_OFFSET)
#define AM335X_DCAN0_IF1DATB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF1DATB_OFFSET)
#define AM335X_DCAN0_IF2CMD (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2CMD_OFFSET)
#define AM335X_DCAN0_IF2MSK (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2MSK_OFFSET)
#define AM335X_DCAN0_IF2ARB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2ARB_OFFSET)
#define AM335X_DCAN0_IF2MCTL (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2MCTL_OFFSET)
#define AM335X_DCAN0_IF2DATA (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2DATA_OFFSET)
#define AM335X_DCAN0_IF2DATB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF2DATB_OFFSET)
#define AM335X_DCAN0_IF3OBS (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3OBS_OFFSET)
#define AM335X_DCAN0_IF3MSK (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3MSK_OFFSET)
#define AM335X_DCAN0_IF3ARB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3ARB_OFFSET)
#define AM335X_DCAN0_IF3MCTL (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3MCTL_OFFSET)
#define AM335X_DCAN0_IF3DATA (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3DATA_OFFSET)
#define AM335X_DCAN0_IF3DATB (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3DATB_OFFSET)
#define AM335X_DCAN0_IF3UPD12 (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3UPD12_OFFSET)
#define AM335X_DCAN0_IF3UPD34 (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3UPD34_OFFSET)
#define AM335X_DCAN0_IF3UPD56 (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3UPD56_OFFSET)
#define AM335X_DCAN0_IF3UPD78 (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3UPD78_OFFSET)
#define AM335X_DCAN0_TIOC (AM335X_DCAN0_VADDR + AM335X_DCAN_TIOC_OFFSET)
#define AM335X_DCAN0_RIOC (AM335X_DCAN0_VADDR + AM335X_DCAN_RIOC_OFFSET)
#define AM335X_DCAN0_TXRQ(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_TXRQ_OFFSET(n))
#define AM335X_DCAN0_NWDAT(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_NWDAT_OFFSET(n))
#define AM335X_DCAN0_INTPND(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_INTPND_OFFSET(n))
#define AM335X_DCAN0_MSGVAL(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_MSGVAL_OFFSET(n))
#define AM335X_DCAN0_INTMUX(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_INTMUX_OFFSET(n))
#define AM335X_DCAN0_IFCMD(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFCMD_OFFSET(n))
#define AM335X_DCAN0_IFMSK(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFMSK_OFFSET(n))
#define AM335X_DCAN0_IFARB(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFARB_OFFSET(n))
#define AM335X_DCAN0_IFMCTL(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFMCTL_OFFSET(n))
#define AM335X_DCAN0_IFDATA(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFDATA_OFFSET(n))
#define AM335X_DCAN0_IFDATB(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IFDATB_OFFSET(n))
#define AM335X_DCAN0_IF3UPD(n) (AM335X_DCAN0_VADDR + AM335X_DCAN_IF3UPD_OFFSET(n))
#define AM335X_DCAN1_CTL (AM335X_DCAN1_VADDR + AM335X_DCAN_CTL_OFFSET)
#define AM335X_DCAN1_ES (AM335X_DCAN1_VADDR + AM335X_DCAN_ES_OFFSET)
#define AM335X_DCAN1_ERRC (AM335X_DCAN1_VADDR + AM335X_DCAN_ERRC_OFFSET)
#define AM335X_DCAN1_BTR (AM335X_DCAN1_VADDR + AM335X_DCAN_BTR_OFFSET)
#define AM335X_DCAN1_INT (AM335X_DCAN1_VADDR + AM335X_DCAN_INT_OFFSET)
#define AM335X_DCAN1_TEST (AM335X_DCAN1_VADDR + AM335X_DCAN_TEST_OFFSET)
#define AM335X_DCAN1_PERR (AM335X_DCAN1_VADDR + AM335X_DCAN_PERR_OFFSET)
#define AM335X_DCAN1_ABOTR (AM335X_DCAN1_VADDR + AM335X_DCAN_ABOTR_OFFSET)
#define AM335X_DCAN1_TXRQ_X (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ_X_OFFSET)
#define AM335X_DCAN1_TXRQ12 (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ12_OFFSET)
#define AM335X_DCAN1_TXRQ34 (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ34_OFFSET)
#define AM335X_DCAN1_TXRQ56 (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ56_OFFSET)
#define AM335X_DCAN1_TXRQ78 (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ78_OFFSET)
#define AM335X_DCAN1_NWDAT_X (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT_X_OFFSET)
#define AM335X_DCAN1_NWDAT12 (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT12_OFFSET)
#define AM335X_DCAN1_NWDAT34 (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT34_OFFSET)
#define AM335X_DCAN1_NWDAT56 (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT56_OFFSET)
#define AM335X_DCAN1_NWDAT78 (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT78_OFFSET)
#define AM335X_DCAN1_INTPND_X (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND_X_OFFSET)
#define AM335X_DCAN1_INTPND12 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND12_OFFSET)
#define AM335X_DCAN1_INTPND34 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND34_OFFSET)
#define AM335X_DCAN1_INTPND56 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND56_OFFSET)
#define AM335X_DCAN1_INTPND78 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND78_OFFSET)
#define AM335X_DCAN1_MSGVAL_X (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL_X_OFFSET)
#define AM335X_DCAN1_MSGVAL12 (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL12_OFFSET)
#define AM335X_DCAN1_MSGVAL34 (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL34_OFFSET)
#define AM335X_DCAN1_MSGVAL56 (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL56_OFFSET)
#define AM335X_DCAN1_MSGVAL78 (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL78_OFFSET)
#define AM335X_DCAN1_INTMUX12 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTMUX12_OFFSET)
#define AM335X_DCAN1_INTMUX34 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTMUX34_OFFSET)
#define AM335X_DCAN1_INTMUX56 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTMUX56_OFFSET)
#define AM335X_DCAN1_INTMUX78 (AM335X_DCAN1_VADDR + AM335X_DCAN_INTMUX78_OFFSET)
#define AM335X_DCAN1_IF1CMD (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1CMD_OFFSET)
#define AM335X_DCAN1_IF1MSK (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1MSK_OFFSET)
#define AM335X_DCAN1_IF1ARB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1ARB_OFFSET)
#define AM335X_DCAN1_IF1MCTL (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1MCTL_OFFSET)
#define AM335X_DCAN1_IF1DATA (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1DATA_OFFSET)
#define AM335X_DCAN1_IF1DATB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF1DATB_OFFSET)
#define AM335X_DCAN1_IF2CMD (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2CMD_OFFSET)
#define AM335X_DCAN1_IF2MSK (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2MSK_OFFSET)
#define AM335X_DCAN1_IF2ARB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2ARB_OFFSET)
#define AM335X_DCAN1_IF2MCTL (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2MCTL_OFFSET)
#define AM335X_DCAN1_IF2DATA (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2DATA_OFFSET)
#define AM335X_DCAN1_IF2DATB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF2DATB_OFFSET)
#define AM335X_DCAN1_IF3OBS (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3OBS_OFFSET)
#define AM335X_DCAN1_IF3MSK (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3MSK_OFFSET)
#define AM335X_DCAN1_IF3ARB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3ARB_OFFSET)
#define AM335X_DCAN1_IF3MCTL (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3MCTL_OFFSET)
#define AM335X_DCAN1_IF3DATA (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3DATA_OFFSET)
#define AM335X_DCAN1_IF3DATB (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3DATB_OFFSET)
#define AM335X_DCAN1_IF3UPD12 (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3UPD12_OFFSET)
#define AM335X_DCAN1_IF3UPD34 (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3UPD34_OFFSET)
#define AM335X_DCAN1_IF3UPD56 (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3UPD56_OFFSET)
#define AM335X_DCAN1_IF3UPD78 (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3UPD78_OFFSET)
#define AM335X_DCAN1_TIOC (AM335X_DCAN1_VADDR + AM335X_DCAN_TIOC_OFFSET)
#define AM335X_DCAN1_RIOC (AM335X_DCAN1_VADDR + AM335X_DCAN_RIOC_OFFSET)
#define AM335X_DCAN1_TXRQ(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_TXRQ_OFFSET(n))
#define AM335X_DCAN1_NWDAT(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_NWDAT_OFFSET(n))
#define AM335X_DCAN1_INTPND(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_INTPND_OFFSET(n))
#define AM335X_DCAN1_MSGVAL(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_MSGVAL_OFFSET(n))
#define AM335X_DCAN1_INTMUX(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_INTMUX_OFFSET(n))
#define AM335X_DCAN1_IFCMD(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFCMD_OFFSET(n))
#define AM335X_DCAN1_IFMSK(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFMSK_OFFSET(n))
#define AM335X_DCAN1_IFARB(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFARB_OFFSET(n))
#define AM335X_DCAN1_IFMCTL(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFMCTL_OFFSET(n))
#define AM335X_DCAN1_IFDATA(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFDATA_OFFSET(n))
#define AM335X_DCAN1_IFDATB(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IFDATB_OFFSET(n))
#define AM335X_DCAN1_IF3UPD(n) (AM335X_DCAN1_VADDR + AM335X_DCAN_IF3UPD_OFFSET(n))
/* Register bit field definitions ***************************************************/
#define DCAN_CTL_INIT (1 << 0) /* Bit 0: Initialization mode */
#define DCAN_CTL_IE0 (1 << 1) /* Bit 1: Interrupt line 0 enable */
#define DCAN_CTL_SIE (1 << 2) /* Bit 2: Status change interrupt enable */
#define DCAN_CTL_EIE (1 << 3) /* Bit 3: Error interrupt enable */
#define DCAN_CTL_DAR (1 << 5) /* Bit 5: Disable automatic retransmission */
#define DCAN_CTL_CCE (1 << 6) /* Bit 6: Configuration change enable */
#define DCAN_CTL_TEST (1 << 7) /* Bit 7: Test mode enable */
#define DCAN_CTL_IDS (1 << 8) /* Bit 8: Interruption debug support enable */
#define DCAN_CTL_ABO (1 << 9) /* Bit 9: Auto-Bus-On enable */
#define DCAN_CTL_PMD_SHIFT (10) /* Bits 10-13: Parity on/off. */
#define DCAN_CTL_PMD_MASK (15 << DCAN_CTL_PMD_SHIFT)
# define DCAN_CTL_PMD_OFF (5 << DCAN_CTL_PMD_SHIFT) /* Parity function disabled */
# define DCAN_CTL_PMD_ON (10 << DCAN_CTL_PMD_SHIFT) /* Parity function enabled */
#define DCAN_CTL_SWR (1 << 15) /* Bit 15: Software reset enable */
#define DCAN_CTL_INITDBG (1 << 16) /* Bit 16: Internal init state while debug access */
#define DCAN_CTL_IE1 (1 << 17) /* Bit 17: Interrupt line 1 enable */
#define DCAN_CTL_DE1 (1 << 18) /* Bit 18: Enable DMA request line for IF1 */
#define DCAN_CTL_DE2 (1 << 19) /* Bit 19: Enable DMA request line for IF2 */
#define DCAN_CTL_DE3 (1 << 20) /* Bit 20: Enable DMA request line for IF3 */
#define DCAN_CTL_PDR (1 << 24) /* Bit 24: Request for local low power-down mode */
#define DCAN_CTL_WUBA (1 << 25) /* Bit 25: Automatic wake up on bus activity when in local power-down mode */
#define DCAN_ES_LEC_SHIFT (0) /* Bits 0-2: Last error code. */
#define DCAN_ES_LEC_MASK (7 << DCAN_ES_LEC_SHIFT)
# define DCAN_ES_LEC_NO_ERROR (0 << DCAN_ES_LEC_SHIFT) /* No error */
# define DCAN_ES_LEC_STUFF_ERROR (1 << DCAN_ES_LEC_SHIFT) /* Stuff error */
# define DCAN_ES_LEC_FORM_ERROR (2 << DCAN_ES_LEC_SHIFT) /* Form error */
# define DCAN_ES_LEC_ACK_ERROR (3 << DCAN_ES_LEC_SHIFT) /* Ack error */
# define DCAN_ES_LEC_BIT1_ERROR (4 << DCAN_ES_LEC_SHIFT) /* Bit1 error */
# define DCAN_ES_LEC_BIT0_ERROR (5 << DCAN_ES_LEC_SHIFT) /* Bit0 error */
# define DCAN_ES_LEC_CRC_ERROR (6 << DCAN_ES_LEC_SHIFT) /* CRC error */
# define DCAN_ES_LEC_NO_EVENT (7 << DCAN_ES_LEC_SHIFT) /* No CAN bus event since last read */
#define DCAN_ES_TX_OK (1 << 3) /* Bit 3: Transmitted a message successfully */
#define DCAN_ES_RX_OK (1 << 4) /* Bit 4: Received a message successfully */
#define DCAN_ES_EPASSIVE (1 << 5) /* Bit 5: Error passive state */
#define DCAN_ES_EWARN (1 << 6) /* Bit 6: Warning state */
#define DCAN_ES_BUSOFF (1 << 7) /* Bit 7: Bus-Off state */
#define DCAN_ES_PER (1 << 8) /* Bit 8: Parity error detected */
#define DCAN_ES_WKUP_PND (1 << 9) /* Bit 9: Wake up pending */
#define DCAN_ES_PDA (1 << 10) /* Bit 10: Local power-down mode acknowledge */
#define DCAN_ERRC_TEC_SHIFT (0) /* Bits 10-13: Parity on/off. */
#define DCAN_ERRC_TEC_MASK (255 << DCAN_ERRC_TEC_SHIFT)
#define DCAN_ERRC_REC_SHIFT (8) /* Bits 10-13: Parity on/off. */
#define DCAN_ERRC_REC_MASK (255 << DCAN_ERRC_REC_SHIFT)
#define DCAN_ERRC_RP (1 << 15) /* Bit 15: Receive error passive */
#define DCAN_BTR_BRP_SHIFT (0) /* Bits 0-5: Baud rate prescaler */
#define DCAN_BTR_BRP_MASK (63 << DCAN_BTR_BRP_SHIFT)
#define DCAN_BTR_SJW_SHIFT (6) /* Bits 6-7: Synchronization Jump Width */
#define DCAN_BTR_SJW_MASK (3 << DCAN_BTR_SJW_SHIFT)
#define DCAN_BTR_TSEG1_SHIFT (8) /* Bits 8-11: Time segment before the sample point */
#define DCAN_BTR_TSEG1_MASK (15 << DCAN_BTR_TSEG1_SHIFT)
#define DCAN_BTR_TSEG2_SHIFT (12) /* Bits 12-14: Time segment after the sample point */
#define DCAN_BTR_TSEG2_MASK (7 << DCAN_BTR_TSEG2_SHIFT)
#define DCAN_BTR_BRPE_SHIFT (16) /* Bits 16-19: Baud rate prescaler extension */
#define DCAN_BTR_BRPE_MASK (15 << DCAN_BTR_BRPE_SHIFT)
#define DCAN_INT_LINE0_SHIFT (0) /* Bits 0-15: Interrupt Line 0 Identifier */
#define DCAN_INT_LINE0_MASK (65535 << DCAN_INT_LINE0_SHIFT)
#define DCAN_INT_LINE1_SHIFT (16) /* Bits 16-23: Interrupt Line 1 Identifier */
#define DCAN_INT_LINE1_MASK (255 << DCAN_INT_LINE1_SHIFT)
#define DCAN_TEST_SILENT (1 << 3) /* Bit 3: Silent mode */
#define DCAN_TEST_LBACK (1 << 4) /* Bit 4: Loopback mode */
#define DCAN_TEST_TX_SHIFT (5) /* Bits 5-6: Control of CAN_TX pin */
#define DCAN_TEST_TX_MASK (3 << DCAN_TEST_TX_SHIFT)
# define DCAN_TEST_TX_NORMAL (0 << DCAN_TEST_TX_SHIFT) /* Normal operation */
# define DCAN_TEST_TX_SAMLE (1 << DCAN_TEST_TX_SHIFT) /* Sample point can be monitored at CAN_TX pin */
# define DCAN_TEST_TX_DOMINANT (2 << DCAN_TEST_TX_SHIFT) /* CAN_TX pin drives a dominant value */
# define DCAN_TEST_TX_RECESSIVE (3 << DCAN_TEST_TX_SHIFT) /* CAN_TX pin drives a recessive value */
#define DCAN_TEST_RX (1 << 7) /* Bit 7: Receive pin monitoring */
#define DCAN_TEST_EXL (1 << 8) /* Bit 8: External loopback mode */
#define DCAN_TEST_RDA (1 << 9) /* Bit 9: RAM direct access enable */
#define DCAN_PERR_MSG_NUM_SHIFT (0) /* Bits 0-7: Message number */
#define DCAN_PERR_MSG_NUM_MASK (255 << DCAN_PERR_MSG_NUM_SHIFT)
#define DCAN_PERR_WORD_NUM_SHIFT (8) /* Bits 8-10: Word number where parity error has been detected */
#define DCAN_PERR_WORD_NUM_MASK (7 << DCAN_PERR_WORD_NUM_SHIFT)
#define DCAN_TXRQ(n) (1 << (((unsigned int)(n) - 1) & 0x1f)) /* Bit 0-31: Transmission request bits (for all message objects) */
#define DCAN_NWDAT(n) (1 << (((unsigned int)(n) - 1) & 0x1f)) /* Bit 0-31: New Data Bits (for all message objects) */
#define DCAN_INTPND(n) (1 << (((unsigned int)(n) - 1) & 0x1f)) /* Bit 0-31: Interrupt Pending Bits (for all message objects) */
#define DCAN_MSGVAL(n) (1 << (((unsigned int)(n) - 1) & 0x1f)) /* Bit 0-31: Message valid bits (for all message objects) */
#define DCAN_INTMUX_LAST (1 << 0) /* Bit 0: Last implemented message object */
#define DCAN_INTMUX(n) (1 << ((unsigned int)(n) & 0x1f)) /* Bit n: Message object number n */
#define DCAN_IFCMD_MSG_NUM_SHIFT (0) /* Bits 0-7: Number of message object in message RAM which is used for data transfer */
#define DCAN_IFCMD_MSG_NUM_MASK (0xff << DCAN_IFCMD_MSG_NUM_SHIFT)
#define DCAN_IFCMD_DMA_ACTIVE (1 << 14) /* Bit 14: Activation of DMA feature for subsequent internal IF update */
#define DCAN_IFCMD_BUSY (1 << 15) /* Bit 15: Busy flag */
#define DCAN_IFCMD_DATA_B (1 << 16) /* Bit 16: Access Data Bytes 4 to 7 */
#define DCAN_IFCMD_DATA_A (1 << 17) /* Bit 17: Access Data Bytes 0 to 3 */
#define DCAN_IFCMD_TX_RQST_NEWDAT (1 << 18) /* Bit 18: Access transmission request bit */
#define DCAN_IFCMD_CLR_INTPND (1 << 19) /* Bit 19: Clear interrupt pending bit */
#define DCAN_IFCMD_CONTROL (1 << 20) /* Bit 20: Access control bits */
#define DCAN_IFCMD_ARB (1 << 21) /* Bit 21: Access arbitration bits */
#define DCAN_IFCMD_MASK (1 << 22) /* Bit 22: Access mask bits */
#define DCAN_IFCMD_WR_RD (1 << 23) /* Bit 23: Write/Read direction */
#define DCAN_IFMSK_MSK_SHIFT (0) /* Bits 0-28: Message identifier mask */
#define DCAN_IFMSK_MSK_MASK (0x1fffffff << DCAN_IFCMD_MSK_SHIFT)
#define DCAN_IFMSK_MDIR (1 << 30) /* Bit 30: Mask message direction */
#define DCAN_IFMSK_MXTD (1 << 31) /* Bit 31: Mask extended identifier */
#define DCAN_IFARB_ID_SHIFT (0) /* Bits 0-28: Message identifier */
#define DCAN_IFARB_ID_MASK (0x1fffffff << DCAN_IFCMD_MSK_SHIFT)
#define DCAN_IFARB_DIR (1 << 29) /* Bit 29: Message direction */
#define DCAN_IFARB_XTD (1 << 30) /* Bit 30: Extended identifier */
#define DCAN_IFARB_MSG_VAL (1 << 31) /* Bit 31: Message valid */
#define DCAN_IFMCTL_DLC_SHIFT (0) /* Bits 0-3: Data length code */
#define DCAN_IFMCTL_DLC_MASK (15 << DCAN_IFMCTL_DLC_SHIFT)
#define DCAN_IFMCTL_EOB (1 << 7) /* Bit 7: Data frame has 0 to 8 data bits. */
#define DCAN_IFMCTL_TX_RQST (1 << 8) /* Bit 8: Transmit request */
#define DCAN_IFMCTL_RMT_EN (1 << 9) /* Bit 9: Remote enable */
#define DCAN_IFMCTL_RX_IE (1 << 10) /* Bit 10: Receive interrupt enable */
#define DCAN_IFMCTL_TX_IE (1 << 11) /* Bit 11: Transmit interrupt enable */
#define DCAN_IFMCTL_UMASK (1 << 12) /* Bit 12: Use acceptance mask */
#define DCAN_IFMCTL_INTPND (1 << 13) /* Bit 13: Interrupt pending */
#define DCAN_IFMCTL_MSGLST (1 << 14) /* Bit 14: Message lost (only valid for message objects with direction Receive) */
#define DCAN_IFMCTL_NEWDAT (1 << 15) /* Bit 15: New data */
#define DCAN_IF3OBS_MASK (1 << 0) /* Bit 0: Mask data read observation */
#define DCAN_IF3OBS_ARB (1 << 1) /* Bit 1: Arbitration data read observation */
#define DCAN_IF3OBS_CTRL (1 << 2) /* Bit 2: Control read observation */
#define DCAN_IF3OBS_DATAA (1 << 3) /* Bit 3: Data A read observation */
#define DCAN_IF3OBS_DATAB (1 << 4) /* Bit 4: Data B read observation */
#define DCAN_IF3OBS_SM (1 << 8) /* Bit 8: Status of Mask data read access */
#define DCAN_IF3OBS_SA (1 << 9) /* Bit 9: Status of Arbitration data read access */
#define DCAN_IF3OBS_SC (1 << 10) /* Bit 10: Status of control bits read access */
#define DCAN_IF3OBS_SDA (1 << 11) /* Bit 11: Status of Data A read access */
#define DCAN_IF3OBS_SDB (1 << 12) /* Bit 12: Status of Data B read access */
#define DCAN_IF3OBS_UPD (1 << 15) /* Bit 15: Update Data*/
#define DCAN_IF3UPD(n) (1 << (((unsigned int)(n) - 1) & 0x1f)) /* Bit 0-31: IF3 Update Enabled (for all message objects) */
#define DCAN_TIOC_IN (1 << 0) /* Bit 0: CAN_TX data in */
#define DCAN_TIOC_OUT (1 << 1) /* Bit 1: CAN_TX data out write */
#define DCAN_TIOC_DIR (1 << 2) /* Bit 2: CAN_TX data direction */
#define DCAN_TIOC_FUNC (1 << 3) /* Bit 3: CAN_TX function */
#define DCAN_TIOC_OD (1 << 16) /* Bit 16: CAN_TX open drain enable */
#define DCAN_TIOC_PD (1 << 17) /* Bit 17: CAN_TX pull disable */
#define DCAN_TIOC_PU (1 << 18) /* Bit 18: CAN_TX pull up/pull down select */
#define DCAN_RIOC_IN (1 << 0) /* Bit 0: CAN_RX data in */
#define DCAN_RIOC_OUT (1 << 1) /* Bit 1: CAN_RX data out write */
#define DCAN_RIOC_DIR (1 << 2) /* Bit 2: CAN_RX data direction */
#define DCAN_RIOC_FUNC (1 << 3) /* Bit 3: CAN_RX function */
#define DCAN_RIOC_OD (1 << 16) /* Bit 16: CAN_RX open drain enable */
#define DCAN_RIOC_PD (1 << 17) /* Bit 17: CAN_RX pull disable */
#define DCAN_RIOC_PU (1 << 18) /* Bit 18: CAN_RX pull up/pull down select */
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_DCAN_H */
arch/arm/src/am335x/hardware/am335x_lcd.h
+288
View File
@@ -0,0 +1,288 @@
/************************************************************************************
* arch/arm/src/am335x/hardware/am335x_lcd.h
*
* Copyright (C) 2019 Petro Karashchenko. All rights reserved.
* Author: Petro Karashchenko <petro.karashchenko@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
************************************************************************************/
#ifndef __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_LCD_H
#define __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_LCD_H
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h>
#include "hardware/am335x_memorymap.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register offsets *****************************************************************/
#define AM335X_LCD_PID_OFFSET 0x0000
#define AM335X_LCD_CTRL_OFFSET 0x0004
#define AM335X_LCD_LIDD_CTRL_OFFSET 0x000c
#define AM335X_LCD_LIDD_CS0_CONF_OFFSET 0x0010
#define AM335X_LCD_LIDD_CS0_ADDR_OFFSET 0x0014
#define AM335X_LCD_LIDD_CS0_DATA_OFFSET 0x0018
#define AM335X_LCD_LIDD_CS1_CONF_OFFSET 0x001c
#define AM335X_LCD_LIDD_CS1_ADDR_OFFSET 0x0020
#define AM335X_LCD_LIDD_CS1_DATA_OFFSET 0x0024
#define AM335X_LCD_RASTER_CTRL_OFFSET 0x0028
#define AM335X_LCD_RASTER_TIMING_0_OFFSET 0x002c
#define AM335X_LCD_RASTER_TIMING_1_OFFSET 0x0030
#define AM335X_LCD_RASTER_TIMING_2_OFFSET 0x0034
#define AM335X_LCD_RASTER_SUBPANEL_OFFSET 0x0038
#define AM335X_LCD_RASTER_SUBPANEL2_OFFSET 0x003c
#define AM335X_LCD_DMA_CTRL_OFFSET 0x0040
#define AM335X_LCD_DMA_FB0_BASE_OFFSET 0x0044
#define AM335X_LCD_DMA_FB0_CEIL_OFFSET 0x0048
#define AM335X_LCD_DMA_FB1_BASE_OFFSET 0x004c
#define AM335X_LCD_DMA_FB1_CEIL_OFFSET 0x0050
#define AM335X_LCD_SYSCONFIG_OFFSET 0x0054
#define AM335X_LCD_IRQ_STAT_RAW_OFFSET 0x0058
#define AM335X_LCD_IRQ_STAT_OFFSET 0x005c
#define AM335X_LCD_IRQ_EN_SET_OFFSET 0x0060
#define AM335X_LCD_IRQ_EN_CLEAR_OFFSET 0x0064
#define AM335X_LCD_CLKC_ENABLE_OFFSET 0x006c
#define AM335X_LCD_CLKC_RESET_OFFSET 0x0070
#define AM335X_LCD_LIDD_CS_CONF_OFFSET(n) (0x0010 + (unsigned int)(n) * 0x0c)
#define AM335X_LCD_LIDD_CS_ADDR_OFFSET(n) (0x0014 + (unsigned int)(n) * 0x0c)
#define AM335X_LCD_LIDD_CS_DATA_OFFSET(n) (0x0018 + (unsigned int)(n) * 0x0c)
#define AM335X_LCD_DMA_FB_BASE_OFFSET(n) (0x0044 + (unsigned int)(n) * 0x08)
#define AM335X_LCD_DMA_FB_CEIL_OFFSET(n) (0x0048 + (unsigned int)(n) * 0x08)
/* Register virtual addresses *******************************************************/
#define AM335X_LCD_PID (AM335X_LCD_VADDR + AM335X_LCD_PID_OFFSET)
#define AM335X_LCD_CTRL (AM335X_LCD_VADDR + AM335X_LCD_CTRL_OFFSET)
#define AM335X_LCD_LIDD_CTRL (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CTRL_OFFSET)
#define AM335X_LCD_LIDD_CS0_CONF (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS0_CONF_OFFSET)
#define AM335X_LCD_LIDD_CS0_ADDR (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS0_ADDR_OFFSET)
#define AM335X_LCD_LIDD_CS0_DATA (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS0_DATA_OFFSET)
#define AM335X_LCD_LIDD_CS1_CONF (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS1_CONF_OFFSET)
#define AM335X_LCD_LIDD_CS1_ADDR (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS1_ADDR_OFFSET)
#define AM335X_LCD_LIDD_CS1_DATA (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS1_DATA_OFFSET)
#define AM335X_LCD_RASTER_CTRL (AM335X_LCD_VADDR + AM335X_LCD_RASTER_CTRL_OFFSET)
#define AM335X_LCD_RASTER_TIMING_0 (AM335X_LCD_VADDR + AM335X_LCD_RASTER_TIMING_0_OFFSET)
#define AM335X_LCD_RASTER_TIMING_1 (AM335X_LCD_VADDR + AM335X_LCD_RASTER_TIMING_1_OFFSET)
#define AM335X_LCD_RASTER_TIMING_2 (AM335X_LCD_VADDR + AM335X_LCD_RASTER_TIMING_2_OFFSET)
#define AM335X_LCD_RASTER_SUBPANEL (AM335X_LCD_VADDR + AM335X_LCD_RASTER_SUBPANEL_OFFSET)
#define AM335X_LCD_RASTER_SUBPANEL2 (AM335X_LCD_VADDR + AM335X_LCD_RASTER_SUBPANEL2_OFFSET)
#define AM335X_LCD_DMA_CTRL (AM335X_LCD_VADDR + AM335X_LCD_DMA_CTRL_OFFSET)
#define AM335X_LCD_DMA_FB0_BASE (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB0_BASE_OFFSET)
#define AM335X_LCD_DMA_FB0_CEIL (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB0_CEIL_OFFSET)
#define AM335X_LCD_DMA_FB1_BASE (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB1_BASE_OFFSET)
#define AM335X_LCD_DMA_FB1_CEIL (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB1_CEIL_OFFSET)
#define AM335X_LCD_SYSCONFIG (AM335X_LCD_VADDR + AM335X_LCD_SYSCONFIG_OFFSET)
#define AM335X_LCD_IRQ_STAT_RAW (AM335X_LCD_VADDR + AM335X_LCD_IRQ_STAT_RAW_OFFSET)
#define AM335X_LCD_IRQ_STAT (AM335X_LCD_VADDR + AM335X_LCD_IRQ_STAT_OFFSET)
#define AM335X_LCD_IRQ_EN_SET (AM335X_LCD_VADDR + AM335X_LCD_IRQ_EN_SET_OFFSET)
#define AM335X_LCD_IRQ_EN_CLEAR (AM335X_LCD_VADDR + AM335X_LCD_IRQ_EN_CLEAR_OFFSET)
#define AM335X_LCD_CLKC_ENABLE (AM335X_LCD_VADDR + AM335X_LCD_CLKC_ENABLE_OFFSET)
#define AM335X_LCD_CLKC_RESET (AM335X_LCD_VADDR + AM335X_LCD_CLKC_RESET_OFFSET)
#define AM335X_LCD_LIDD_CS_CONF(n) (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS_CONF_OFFSET(n))
#define AM335X_LCD_LIDD_CS_ADDR(n) (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS_ADDR_OFFSET(n))
#define AM335X_LCD_LIDD_CS_DATA(n) (AM335X_LCD_VADDR + AM335X_LCD_LIDD_CS_DATA_OFFSET(n))
#define AM335X_LCD_DMA_FB_BASE(n) (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB_BASE_OFFSET(n))
#define AM335X_LCD_DMA_FB_CEIL(n) (AM335X_LCD_VADDR + AM335X_LCD_DMA_FB_CEIL_OFFSET(n))
/* Register bit field definitions ***************************************************/
#define LCD_CTRL_MODE_SEL (1 << 0) /* Bit 0: LCD Mode select */
#define LCD_CTRL_AUTO_UFLOW_RESTART (1 << 1) /* Bit 1: Underflow restart selection */
#define LCD_CTRL_CLKDIV_SHIFT (8) /* Bits 8-15: Clock divisor */
#define LCD_CTRL_CLKDIV_MASK (255 << LCD_CTRL_CLKDIV_SHIFT)
#define LCD_LIDD_CTRL_MODE_SEL_SHIFT (0) /* Bits 0-2: LIDD Mode Select */
#define LCD_LIDD_CTRL_MODE_SEL_MASK (7 << LCD_LIDD_CTRL_MODE_SEL_SHIFT)
# define LCD_LIDD_CTRL_SYNC_MPU68 (0 << LCD_LIDD_CTRL_MODE_SEL_SHIFT) /* Sync MPU68 */
# define LCD_LIDD_CTRL_ASYNC_MPU68 (1 << LCD_LIDD_CTRL_MODE_SEL_SHIFT) /* Async MPU68 */
# define LCD_LIDD_CTRL_SYNC_MPU80 (2 << LCD_LIDD_CTRL_MODE_SEL_SHIFT) /* Sync MPU80 */
# define LCD_LIDD_CTRL_ASYNC_MPU80 (3 << LCD_LIDD_CTRL_MODE_SEL_SHIFT) /* Async MPU80 */
# define LCD_LIDD_CTRL_HITACHI (4 << LCD_LIDD_CTRL_MODE_SEL_SHIFT) /* Hitachi (Async) */
#define LCD_LIDD_CTRL_ALEPOL (1 << 3) /* Bit 3: Address Latch Enable (ALE) Polarity Control */
#define LCD_LIDD_CTRL_RS_EN_POL (1 << 4) /* Bit 4: Read Strobe/Direction Polarity Control */
#define LCD_LIDD_CTRL_WS_DIR_POL (1 << 5) /* Bit 5: Write Strobe/Direction Polarity Control */
#define LCD_LIDD_CTRL_CS0_E0_POL (1 << 6) /* Bit 6: Chip Select 0/Enable 0 (Secondary) Polarity Control */
#define LCD_LIDD_CTRL_CS1_E1_POL (1 << 7) /* Bit 7: Chip Select 1/Enable 1 (Secondary) Polarity Control */
#define LCD_LIDD_CTRL_DMA_EN (1 << 8) /* Bit 8: LIDD DMA Enable */
#define LCD_LIDD_CTRL_DMA_CS0_CS1 (1 << 9) /* Bit 9: CS0/CS1 Select for LIDD DMA writes */
#define LCD_LIDD_CS_CONF_TA_SHIFT (0) /* Bits 0-1: Turn-around Access */
#define LCD_LIDD_CS_CONF_TA_MASK (3 << LCD_LIDD_CS0_CONF_TA_SHIFT)
#define LCD_LIDD_CS_CONF_R_HOLD_SHIFT (2) /* Bits 2-5: Read Strobe Hold cycles */
#define LCD_LIDD_CS_CONF_R_HOLD_MASK (15 << LCD_LIDD_CS0_CONF_R_HOLD_SHIFT)
#define LCD_LIDD_CS_CONF_R_STROBE_SHIFT (6) /* Bits 6-11: Read Strobe Duration cycles */
#define LCD_LIDD_CS_CONF_R_STROBE_MASK (63 << LCD_LIDD_CS0_CONF_R_STROBE_SHIFT)
#define LCD_LIDD_CS_CONF_R_SU_SHIFT (12) /* Bits 12-16: Read Strobe Set-Up cycles */
#define LCD_LIDD_CS_CONF_R_SU_MASK (31 << LCD_LIDD_CS0_CONF_R_SU_SHIFT)
#define LCD_LIDD_CS_CONF_W_HOLD_SHIFT (17) /* Bits 17-20: Write Strobe Hold cycles */
#define LCD_LIDD_CS_CONF_W_HOLD_MASK (15 << LCD_LIDD_CS0_CONF_W_HOLD_SHIFT)
#define LCD_LIDD_CS_CONF_W_STROBE_SHIFT (21) /* Bits 21-26: Write Strobe Duration cycles */
#define LCD_LIDD_CS_CONF_W_STROBE_MASK (63 << LCD_LIDD_CS0_CONF_W_STROBE_SHIFT)
#define LCD_LIDD_CS_CONF_W_SU_SHIFT (27) /* Bits 27-31: Write Strobe Set-Up cycles */
#define LCD_LIDD_CS_CONF_W_SU_MASK (31 << LCD_LIDD_CS0_CONF_W_SU_SHIFT)
#define LCD_LIDD_CS_ADDR_SHIFT (0) /* Bits 0-15: Address index */
#define LCD_LIDD_CS_ADDR_MASK (0xffff << LCD_LIDD_CS_ADDR_SHIFT)
#define LCD_LIDD_CS_DATA_SHIFT (0) /* Bits 0-15: Data */
#define LCD_LIDD_CS_DATA_MASK (0xffff << LCD_LIDD_CS_DATA_SHIFT)
#define LCD_RASTER_CTRL_LCD_EN (1 << 0) /* Bit 0: LCD Controller Enable */
#define LCD_RASTER_CTRL_LCD_BW (1 << 1) /* Bit 1: Only Applies for Passive Matrix Panels LCD Monochrome */
#define LCD_RASTER_CTRL_LCD_TFT (1 << 7) /* Bit 7: Active/Passive or display operation selection */
#define LCD_RASTER_CTRL_RD_ORDER (1 << 8) /* Bit 8: Raster Data Order Select */
#define LCD_RASTER_CTRL_MONO_8B (1 << 9) /* Bit 9: Mono 8 bit */
#define LCD_RASTER_CTRL_REQDLY_SHIFT (12) /* Bits 12-19: Palette Loading Delay When loading the Palette from DDR */
#define LCD_RASTER_CTRL_REQDLY_MASK (255 << LCD_RASTER_CTRL_REQDLY_SHIFT)
#define LCD_RASTER_CTRL_PALMODE_SHIFT (0) /* Bits 20-21: Palette Loading Mode */
#define LCD_RASTER_CTRL_PALMODE_MASK (3 << LCD_RASTER_CTRL_PALMODE_SHIFT)
# define LCD_RASTER_CTRL_PALLET_DATA (0 << LCD_RASTER_CTRL_PALMODE_SHIFT) /* Palette and data loading */
# define LCD_RASTER_CTRL_PALLET (1 << LCD_RASTER_CTRL_PALMODE_SHIFT) /* Palette loading only */
# define LCD_RASTER_CTRL_DATA (2 << LCD_RASTER_CTRL_PALMODE_SHIFT) /* Data loading only For Raw Data (12/16/24 bpp) framebuffers, no palette lookup is employed */
#define LCD_RASTER_CTRL_NIB_MODE (1 << 22) /* Bit 22: Nibble Mode */
#define LCD_RASTER_CTRL_TFT_MAP (1 << 23) /* Bit 23: TFT Mode Alternate Signal Mapping for Palettized framebuffer */
#define LCD_RASTER_CTRL_STN565 (1 << 24) /* Bit 24: Selects whether the framebuffer format is 16 bpp 565 or 12 bpp. */
#define LCD_RASTER_CTRL_TFT24 (1 << 25) /* Bit 25: 24 bit mode */
#define LCD_RASTER_CTRL_TFT24_UNPACKED (1 << 26) /* Bit 26: 24 bit Mode Packing */
#define LCD_RASTER_TIMING_0_PPLMSB (1 << 3) /* Bit 3: Pixels-per-line MSB[10] */
#define LCD_RASTER_TIMING_0_PPLLSB_SHIFT (4) /* Bits 4-9: Pixels-per-line LSB */
#define LCD_RASTER_TIMING_0_PPLLSB_MASK (63 << LCD_RASTER_TIMING_0_PPLLSB_SHIFT)
#define LCD_RASTER_TIMING_0_HSW_SHIFT (10) /* Bits 10-15: Horizontal Sync Pulse Width Lowbits*/
#define LCD_RASTER_TIMING_0_HSW_MASK (63 << LCD_RASTER_TIMING_0_HSW_SHIFT)
#define LCD_RASTER_TIMING_0_HFP_SHIFT (16) /* Bits 16-23: Horizontal Front Porch Lowbits */
#define LCD_RASTER_TIMING_0_HFP_MASK (255 << LCD_RASTER_TIMING_0_HFP_SHIFT)
#define LCD_RASTER_TIMING_0_HBP_SHIFT (24) /* Bits 24-31: Horizontal Back Porch Lowbits */
#define LCD_RASTER_TIMING_0_HBP_MASK (255 << LCD_RASTER_TIMING_0_HBP_SHIFT)
#define LCD_RASTER_TIMING_1_LPP_SHIFT (0) /* Bits 0-9: Lines Per Panel */
#define LCD_RASTER_TIMING_1_LPP_MASK (255 << LCD_RASTER_TIMING_1_LPP_SHIFT)
#define LCD_RASTER_TIMING_1_VSW_SHIFT (10) /* Bits 10-15: Vertical Sync Width Pulse */
#define LCD_RASTER_TIMING_1_VSW_MASK (255 << LCD_RASTER_TIMING_1_VSW_SHIFT)
#define LCD_RASTER_TIMING_1_VFP_SHIFT (16) /* Bits 16-23: Vertical Front Porch */
#define LCD_RASTER_TIMING_1_VFP_MASK (255 << LCD_RASTER_TIMING_1_VFP_SHIFT)
#define LCD_RASTER_TIMING_1_VBP_SHIFT (24) /* Bits 24-31: Vertical Back Porch */
#define LCD_RASTER_TIMING_1_VBP_MASK (255 << LCD_RASTER_TIMING_1_VBP_SHIFT)
#define LCD_RASTER_TIMING_2_HFP_HBITS_SHIFT (0) /* Bits 0-1: Bits 9:8 of the horizontal front porch field */
#define LCD_RASTER_TIMING_2_HFP_HBITS_MASK (3 << LCD_RASTER_TIMING_2_HFP_HBITS_SHIFT)
#define LCD_RASTER_TIMING_2_HBP_HBITS_SHIFT (4) /* Bits 4-5: Bits 9:8 of the horizontal back porch field */
#define LCD_RASTER_TIMING_2_HBP_HBITS_MASK (3 << LCD_RASTER_TIMING_2_HBP_HBITS_SHIFT)
#define LCD_RASTER_TIMING_2_ACB_SHIFT (8) /* Bits 8-15: AC Bias Pin Frequency */
#define LCD_RASTER_TIMING_2_ACB_MASK (255 << LCD_RASTER_TIMING_2_ACB_SHIFT)
#define LCD_RASTER_TIMING_2_ACBI_SHIFT (16) /* Bits 16-19: AC Bias Pins Transitions per Interrupt */
#define LCD_RASTER_TIMING_2_ACBI_MASK (15 << LCD_RASTER_TIMING_2_ACBI_SHIFT)
#define LCD_RASTER_TIMING_2_IVS (1 << 20) /* Bit 20: Invert Vsync */
#define LCD_RASTER_TIMING_2_IHS (1 << 21) /* Bit 21: Invert Hsync */
#define LCD_RASTER_TIMING_2_IPC (1 << 22) /* Bit 22: Invert Pixel Clock */
#define LCD_RASTER_TIMING_2_IEO (1 << 23) /* Bit 23: Invert Output Enable */
#define LCD_RASTER_TIMING_2_PHSVS_RF (1 << 24) /* Bit 24: Program HSYNC/VSYNC Rise or Fall */
#define LCD_RASTER_TIMING_2_PHSVS_ON (1 << 25) /* Bit 25: Hsync/Vsync Pixel Clock Control On/Off */
#define LCD_RASTER_TIMING_2_LPP_B10 (1 << 26) /* Bit 26: Lines Per Panel Bit 10 */
#define LCD_RASTER_TIMING_2_HSW_HBITS_SHITF (27) /* Bits 27-30: Bits 9 to 6 of the horizontal sync width field */
#define LCD_RASTER_TIMING_2_HSW_HBITS_MASK (15 << LCD_RASTER_TIMING_2_HSW_HBITS_SHITF)
#define LCD_RASTER_SUBPANEL_DPDLSB_SHIFT (0) /* Bits 0-15: Default Pixel Data LSB */
#define LCD_RASTER_SUBPANEL_DPDLSB_MASK (65535 << LCD_RASTER_SUBPANEL_DPDLSB_SHIFT)
#define LCD_RASTER_SUBPANEL_LPPT_SHIFT (16) /* Bits 16-25: Line Per Panel Threshold */
#define LCD_RASTER_SUBPANEL_LPPT_MASK (1023 << LCD_RASTER_SUBPANEL_LPPT_SHIFT)
#define LCD_RASTER_SUBPANEL_HOLS (1 << 29) /* Bit 29: High or Low Signal */
#define LCD_RASTER_SUBPANEL_SPEN (1 << 31) /* Bit 31: Sub Panel Enable */
#define LCD_RASTER_SUBPANEL2_DPDMSB_SHIFT (0) /* Bits 0-7: Default Pixel Data MSB */
#define LCD_RASTER_SUBPANEL2_DPDMSB_MASK (255 << LCD_RASTER_SUBPANEL2_DPDMSB_SHIFT)
#define LCD_RASTER_SUBPANEL2_LPPT_B10 (1 << 8) /* Bit 8: Lines Per Panel Threshold Bit 10 */
#define LCD_DMA_CTRL_FRAME_MODE (1 << 0) /* Bit 0: Frame Mode */
#define LCD_DMA_CTRL_BE (1 << 1) /* Bit 1: Big Endian Enable */
#define LCD_DMA_CTRL_BYTE_SWAP (1 << 3) /* Bit 3: Bytelane Ordering */
#define LCD_DMA_CTRL_BURST_SIZE_SHIFT (4) /* Bits 4-6: Burst Size setting for DMA transfers */
#define LCD_DMA_CTRL_BURST_SIZE_MASK (7 << LCD_DMA_CTRL_BURST_SIZE_SHIFT)
# define LCD_DMA_CTRL_BURST_SIZE_1 (0 << LCD_DMA_CTRL_BURST_SIZE_SHIFT) /* Burst size of 1 */
# define LCD_DMA_CTRL_BURST_SIZE_2 (1 << LCD_DMA_CTRL_BURST_SIZE_SHIFT) /* Burst size of 2 */
# define LCD_DMA_CTRL_BURST_SIZE_4 (2 << LCD_DMA_CTRL_BURST_SIZE_SHIFT) /* Burst size of 4 */
# define LCD_DMA_CTRL_BURST_SIZE_8 (3 << LCD_DMA_CTRL_BURST_SIZE_SHIFT) /* Burst size of 8 */
# define LCD_DMA_CTRL_BURST_SIZE_16 (4 << LCD_DMA_CTRL_BURST_SIZE_SHIFT) /* Burst size of 6 */
#define LCD_DMA_CTRL_TH_FIFO_RDY_SHIFT (8) /* Bits 8-10: DMA FIFO threshold */
#define LCD_DMA_CTRL_TH_FIFO_RDY_MASK (7 << LCD_DMA_CTRL_TH_FIFO_RDY_SHIFT)
# define LCD_DMA_CTRL_TH_FIFO_RDY_8 (0 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 8 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_16 (1 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 16 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_32 (2 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 32 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_64 (3 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 64 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_128 (4 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 128 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_256 (5 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 256 words have been loaded */
# define LCD_DMA_CTRL_TH_FIFO_RDY_512 (6 << LCD_DMA_CTRL_TH_FIFO_RDY_MASK) /* 512 words have been loaded */
#define LCD_DMA_CTRL_MASTER_PRIO_SHIFT (16) /* Bits 16-18: Priority for the L3 OCP Master Bus */
#define LCD_DMA_CTRL_MASTER_PRIO_MASK (7 << LCD_DMA_CTRL_MASTER_PRIO_SHIFT)
#define LCD_DMA_FB_BASE_SHIFT (2) /* Bits 2-31: Frame Buffer Base Address pointer */
#define LCD_DMA_FB_BASE_MASK (0x3fffffff << LCD_DMA_FB_BASE_SHIFT)
#define LCD_DMA_FB_CEIL_SHIFT (2) /* Bits 2-31: Frame Buffer Ceiling Address pointer */
#define LCD_DMA_FB_CEIL_MASK (0x3fffffff << LCD_DMA_FB_BASE_SHIFT)
#define LCD_SYSCONFIG_IDLE_SHIFT (2) /* Bits 2-3: Configuration of the local target state management mode */
#define LCD_SYSCONFIG_IDLE_MASK (3 << LCD_SYSCONFIG_IDLE_SHIFT)
# define LCD_SYSCONFIG_IDLE_FORCE (0 << LCD_SYSCONFIG_IDLEMODE_SHIFT) /* Force-idle mode */
# define LCD_SYSCONFIG_IDLE_NO (1 << LCD_SYSCONFIG_IDLEMODE_SHIFT) /* No-idle mode */
# define LCD_SYSCONFIG_IDLE_SMART (2 << LCD_SYSCONFIG_IDLEMODE_SHIFT) /* Smart-idle mode */
#define LCD_SYSCONFIG_STANDBY_SHIFT (4) /* Bits 4-5: Configuration of the local initiator state management mode */
#define LCD_SYSCONFIG_STANDBY_MASK (3 << LCD_SYSCONFIG_STANDBY_SHIFT)
# define LCD_SYSCONFIG_STANDBY_FORCE (0 << LCD_SYSCONFIG_STANDBY_SHIFT) /* Force-standby mode */
# define LCD_SYSCONFIG_STANDBY_NO (1 << LCD_SYSCONFIG_STANDBY_SHIFT) /* No-standby mode */
# define LCD_SYSCONFIG_STANDBY_SMART (2 << LCD_SYSCONFIG_STANDBY_SHIFT) /* Smart-standby mode */
#define LCD_IRQ_DONE (1 << 0) /* Bit 0: Raster or LIDD Frame Done */
#define LCD_IRQ_RR_DONE (1 << 1) /* Bit 1: Raster Mode Frame Done */
#define LCD_IRQ_SYNC (1 << 2) /* Bit 2: Frame Synchronization Lost */
#define LCD_IRQ_ACB (1 << 3) /* Bit 3: For Passive Matrix Panels Only AC Bias Count */
#define LCD_IRQ_FUF (1 << 5) /* Bit 5: DMA FIFO Underflow */
#define LCD_IRQ_PL (1 << 6) /* Bit 6: DMA Palette Loaded */
#define LCD_IRQ_OEF0 (1 << 8) /* Bit 8: DMA End-of-Frame 0 */
#define LCD_IRQ_EOF1 (1 << 9) /* Bit 9: DMA End-of-Frame 1 */
#define LCD_CLKC_ENABLE_CORE (1 << 0) /* Bit 0: Software Clock Enable for the DMA submodule */
#define LCD_CLKC_ENABLE_LIDD (1 << 1) /* Bit 1: Software Clock Enable for the LIDD submodule */
#define LCD_CLKC_ENABLE_DMA (1 << 2) /* Bit 2: Software Clock Enable for the Core */
#define LCD_CLKC_RESET_CORE (1 << 0) /* Bit 0: Software Reset for the Core */
#define LCD_CLKC_RESET_LIDD (1 << 1) /* Bit 1: Software Reset for the LIDD submodule */
#define LCD_CLKC_RESET_DMA (1 << 2) /* Bit 2: Software Reset for the DMA submodule */
#define LCD_CLKC_RESET_MAIN (1 << 3) /* Bit 3: Software Reset for the entire LCD module */
#endif /* __ARCH_ARM_SRC_AM335X_HARDWARE_AM335X_LCD_H */
arch/arm/src/kinetis/hardware/kinetis_mmcau.h
+2
View File
@@ -49,6 +49,7 @@
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
/* Register Offsets *****************************************************************/
#define KINETIS_CAU_CASR_OFFSET 0x0000 /* Status Register */
@@ -140,3 +141,4 @@
#endif /* KINETIS_NMMCAU && KINETIS_NMMCAU > 0 */
#endif /* __ARCH_ARM_SRC_KINETIS_HARDWARE_KINETIS_MMCAU_H */
include/nuttx/lcd/edid.h
+1 -1
View File
@@ -1,6 +1,6 @@
/********************************************************************************************
* include/nuttx/lcd/edid.h
* EDID (Extended Display Identification Data) Format
* EDID (Extended Display Identification Data) Format
*
* Copyright (C) 2019 Gregory Nutt. All rights reserved.
* Author: Gregory Nutt <gnutt@nuttx.org>