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arch/arm64: porting mu drv and scmi from arm imx9
Signed-off-by: lipengfei28 <lipengfei28@xiaomi.com>
This commit is contained in:
lipengfei28
Xiang Xiao
+377
-270
File diff suppressed because it is too large
Load Diff
@@ -28,11 +28,16 @@ config ARCH_CHIP_IMX95
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select ARCH_HAVE_MULTICPU
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select ARMV8A_HAVE_GICv3
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select ARCH_CORTEX_A55
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select IMX9_HAVE_MU
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endchoice # i.MX9 Chip Selection
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endmenu # "i.MX9 Chip Selection"
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config IMX9_HAVE_MU
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bool
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default n
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config IMX9_BIN_ROMFS
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bool "Register the /bin ROMFS file system at /dev/ram0"
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depends on FS_ROMFS
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@@ -510,6 +515,16 @@ config IMX9_LPSPI
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bool "LPSPI support"
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default n
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config IMX9_MU
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bool "Mailbox support"
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default y
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depends on IMX9_HAVE_MU
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config IMX9_SCMI
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bool "SCMI Interface"
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default y
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depends on IMX9_MU
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menu "LPI2C Peripherals"
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menuconfig IMX9_LPI2C1
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@@ -40,6 +40,15 @@ ifeq ($(CONFIG_IMX9_GPIO_IRQ),y)
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CHIP_CSRCS += imx9_gpioirq.c
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endif
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ifeq ($(CONFIG_IMX9_MU),y)
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CHIP_CSRCS += imx9_mu.c
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endif
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ifeq ($(CONFIG_IMX9_SCMI),y)
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CHIP_CSRCS += imx9_scmi.c
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# NXP SDK SCMI interface for pinctrl and clocking
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endif
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ifeq ($(CONFIG_IMX9_FLEXIO_PWM),y)
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CHIP_CSRCS += imx9_flexio_pwm.c
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endif
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@@ -101,12 +101,13 @@
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#define IMX9_LPUART7_BASE (0x42690000UL)
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#define IMX9_LPUART8_BASE (0x426A0000UL)
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#define IMX9_M33_CACHE_MCM_BASE (0x44401000UL)
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#define IMX9_MU2_MUA_BASE (0x445b0000UL)
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#define IMX9_BLK_CTRL_MEDIAMIX_BASE (0x4AC10000UL)
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#define IMX9_MIPI_CSI_CSR_BASE (0x4AE00000UL)
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#define IMX9_MIPI_DSI_BASE (0x4AE10000UL)
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#define IMX9_S3MUA_BASE (0x47520000UL)
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#define IMX9_MU1__MUB_BASE (0x44230000UL)
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#define IMX9_MU2__MUB_BASE (0x42440000UL)
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#define IMX9_S3MUA_BASE (0x47520000UL)
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#define IMX9_TRDC_BASE (0x49010000UL)
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#define IMX9_NPU_BASE (0x4A900000UL)
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#define IMX9_OCOTP_BASE (0x47518000UL)
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@@ -0,0 +1,265 @@
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/****************************************************************************
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* arch/arm64/src/imx9/hardware/imx9_mu.h
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-FileCopyrightText: 2024 NXP
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_MU_H
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#define __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_MU_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets */
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#define IMX9_MU_VER_OFFSET 0x0000 /* Version ID */
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#define IMX9_MU_PAR_OFFSET 0x0004 /* Parameter */
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#define IMX9_MU_CR_OFFSET 0x0008 /* Control */
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#define IMX9_MU_SR_OFFSET 0x000c /* Status */
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#define IMX9_MU_FCR_OFFSET 0x0100 /* Flag Control */
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#define IMX9_MU_FSR_OFFSET 0x0104 /* Flag Status */
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#define IMX9_MU_GIER_OFFSET 0x0110 /* General-Purpose Interrupt Enable */
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#define IMX9_MU_GCR_OFFSET 0x0114 /* General-Purpose Control */
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#define IMX9_MU_GSR_OFFSET 0x0118 /* General-purpose Status */
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#define IMX9_MU_TCR_OFFSET 0x0120 /* Transmit Control */
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#define IMX9_MU_TSR_OFFSET 0x0124 /* Transmit Status */
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#define IMX9_MU_RCR_OFFSET 0x0128 /* Receive Control */
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#define IMX9_MU_RSR_OFFSET 0x012c /* Receive Status */
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#define IMX9_MU_TR1_OFFSET 0x0200 /* Transmit */
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#define IMX9_MU_TR2_OFFSET 0x0200 /* Transmit */
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#define IMX9_MU_TR3_OFFSET 0x0200 /* Transmit */
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#define IMX9_MU_TR4_OFFSET 0x0200 /* Transmit */
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#define IMX9_MU_RR1_OFFSET 0x0280 /* Receive */
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#define IMX9_MU_RR2_OFFSET 0x0280 /* Receive */
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#define IMX9_MU_RR3_OFFSET 0x0280 /* Receive */
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#define IMX9_MU_RR4_OFFSET 0x0280 /* Receive */
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/* Register macros */
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#define IMX9_MU_VER(n) ((n) + IMX9_MU_VER_OFFSET) /* Version ID */
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#define IMX9_MU_PAR(n) ((n) + IMX9_MU_PAR_OFFSET) /* Parameter */
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#define IMX9_MU_CR(n) ((n) + IMX9_MU_CR_OFFSET) /* Control */
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#define IMX9_MU_SR(n) ((n) + IMX9_MU_SR_OFFSET) /* Status */
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#define IMX9_MU_FCR(n) ((n) + IMX9_MU_FCR_OFFSET) /* Flag Control */
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#define IMX9_MU_FSR(n) ((n) + IMX9_MU_FSR_OFFSET) /* Flag Status */
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#define IMX9_MU_GIER(n) ((n) + IMX9_MU_GIER_OFFSET) /* General-Purpose Interrupt Enable */
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#define IMX9_MU_GCR(n) ((n) + IMX9_MU_GCR_OFFSET) /* General-Purpose Cntrol */
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#define IMX9_MU_GSR(n) ((n) + IMX9_MU_GSR_OFFSET) /* General-purpose Status */
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#define IMX9_MU_TCR(n) ((n) + IMX9_MU_TCR_OFFSET) /* Transmit Control */
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#define IMX9_MU_TSR(n) ((n) + IMX9_MU_TSR_OFFSET) /* Transmit Status */
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#define IMX9_MU_RCR(n) ((n) + IMX9_MU_RCR_OFFSET) /* Receive Control */
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#define IMX9_MU_RSR(n) ((n) + IMX9_MU_RSR_OFFSET) /* Receive Status */
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#define IMX9_MU_TR1(n) ((n) + IMX9_MU_TR1_OFFSET) /* Transmit */
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#define IMX9_MU_TR2(n) ((n) + IMX9_MU_TR2_OFFSET) /* Transmit */
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#define IMX9_MU_TR3(n) ((n) + IMX9_MU_TR3_OFFSET) /* Transmit */
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#define IMX9_MU_TR4(n) ((n) + IMX9_MU_TR4_OFFSET) /* Transmit */
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#define IMX9_MU_RR1(n) ((n) + IMX9_MU_RR1_OFFSET) /* Receive */
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#define IMX9_MU_RR2(n) ((n) + IMX9_MU_RR2_OFFSET) /* Receive */
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#define IMX9_MU_RR3(n) ((n) + IMX9_MU_RR3_OFFSET) /* Receive */
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#define IMX9_MU_RR4(n) ((n) + IMX9_MU_RR4_OFFSET) /* Receive */
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/* Field definitions */
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/* VER register */
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#define IMX9_MU_VER_FEATURE_SHIFT 0 /* Feature Set Number */
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#define IMX9_MU_VER_FEATURE_MASK 0xffff /* Feature Set Number */
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#define IMX9_MU_VER_MINOR_SHIFT 16 /* Minor Version Number */
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#define IMX9_MU_VER_MINOR_MASK 0xff /* Minor Version Number */
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#define IMX9_MU_VER_MAJOR_SHIFT 24 /* Major Version Number */
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#define IMX9_MU_VER_MAJOR_MASK 0xff /* Major Version Number */
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/* PAR register */
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#define IMX9_MU_PAR_TR_NUM_SHIFT 0 /* Transmit Register Number */
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#define IMX9_MU_PAR_TR_NUM_MASK 0xff /* Transmit Register Number */
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#define IMX9_MU_PAR_RR_NUM_SHIFT 8 /* Receive Register Number */
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#define IMX9_MU_PAR_RR_NUM_MASK 0xff /* Receive Register Number */
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#define IMX9_MU_PAR_GIR_NUM_SHIFT 16 /* General-Purpose Interrupt Request Number */
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#define IMX9_MU_PAR_GIR_NUM_MASK 0xff /* General-Purpose Interrupt Request Number */
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#define IMX9_MU_PAR_FLAG_WIDTH_SHIFT 24 /* Flag Width */
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#define IMX9_MU_PAR_FLAG_WIDTH_MASK 0xff /* Flag Width */
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/* CR register */
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#define IMX9_MU_CR_MUR_SHIFT 0 /* MU Reset */
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#define IMX9_MU_CR_MUR_FLAG (1 << IMX9_MU_CR_MUR_SHIFT) /* MU Reset */
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#define IMX9_MU_CR_MURIE_SHIFT 1 /* MUA Reset Interrupt Enable */
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#define IMX9_MU_CR_MURIE_FLAG (1 << IMX9_MU_CR_MURIE_SHIFT) /* MUA Reset Interrupt Enable */
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/* SR register */
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#define IMX9_MU_SR_MURS_SHIFT 0 /* MUA and MUB Reset State */
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#define IMX9_MU_SR_MURS_FLAG (1 << IMX9_MU_SR_MURS_SHIFT) /* MUA and MUB Reset State */
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#define IMX9_MU_SR_MURIP_SHIFT 1 /* MU Reset Interrupt Pending Flag */
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#define IMX9_MU_SR_MURIP_FLAG (1 << IMX9_MU_SR_MURIP_SHIFT) /* MU Reset Interrupt Pending Flag */
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#define IMX9_MU_SR_EP_SHIFT 2 /* MUA Side Event Pending */
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#define IMX9_MU_SR_EP_FLAG (1 << IMX9_MU_SR_EP_SHIFT) /* MUA Side Event Pending */
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#define IMX9_MU_SR_FUP_SHIFT 3 /* MUA Flag Update Pending */
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#define IMX9_MU_SR_FUP_FLAG (1 << IMX9_MU_SR_FUP_SHIFT) /* MUA Flag Update Pending */
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#define IMX9_MU_SR_GIRP_SHIFT 4 /* MUA General-Purpose Interrupt Pending */
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#define IMX9_MU_SR_GIRP_FLAG (1 << IMX9_MU_SR_GIRP_SHIFT) /* MUA General-Purpose Interrupt Pending */
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#define IMX9_MU_SR_TEP_SHIFT 5 /* MUA Transmit Empty Pending */
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#define IMX9_MU_SR_TEP_FLAG (1 << IMX9_MU_SR_TEP_SHIFT) /* MUA Transmit Empty Pending */
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#define IMX9_MU_SR_RFP_SHIFT 6 /* MUA Receive Full Pending */
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#define IMX9_MU_SR_RFP_FLAG (1 << IMX9_MU_SR_RFP_SHIFT) /* MUA Receive Full Pending */
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/* FCR register */
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#define IMX9_MU_FCR_F0_SHIFT 0 /* MUA to MUB Flag */
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#define IMX9_MU_FCR_F0_FLAG (1 << IMX9_MU_FCR_F0_SHIFT) /* MUA to MUB Flag */
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#define IMX9_MU_FCR_F1_SHIFT 1 /* MUA to MUB Flag */
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#define IMX9_MU_FCR_F1_FLAG (1 << IMX9_MU_FCR_F1_SHIFT) /* MUA to MUB Flag */
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#define IMX9_MU_FCR_F2_SHIFT 2 /* MUA to MUB Flag */
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#define IMX9_MU_FCR_F2_FLAG (1 << IMX9_MU_FCR_F2_SHIFT) /* MUA to MUB Flag */
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/* FSR register */
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#define IMX9_MU_FSR_F0_SHIFT 0 /* MUB to MUA-Side Flag */
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#define IMX9_MU_FSR_F0_FLAG (1 << IMX9_MU_FSR_F0_SHIFT) /* MUB to MUA-Side Flag */
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#define IMX9_MU_FSR_F1_SHIFT 1 /* MUB to MUA-Side Flag */
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#define IMX9_MU_FSR_F1_FLAG (1 << IMX9_MU_FSR_F1_SHIFT) /* MUB to MUA-Side Flag */
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#define IMX9_MU_FSR_F2_SHIFT 2 /* MUB to MUA-Side Flag */
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#define IMX9_MU_FSR_F2_FLAG (1 << IMX9_MU_FSR_F2_SHIFT) /* MUB to MUA-Side Flag */
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/* GIER register */
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#define IMX9_MU_GIER_GIE0_SHIFT 0 /* MUA General-purpose Interrupt Enable */
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#define IMX9_MU_GIER_GIE0_FLAG (1 << IMX9_MU_GIER_GIE0_SHIFT) /* MUA General-purpose Interrupt Enable */
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#define IMX9_MU_GIER_GIE1_SHIFT 1 /* MUA General-purpose Interrupt Enable */
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#define IMX9_MU_GIER_GIE1_FLAG (1 << IMX9_MU_GIER_GIE1_SHIFT) /* MUA General-purpose Interrupt Enable */
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#define IMX9_MU_GIER_GIE2_SHIFT 2 /* MUA General-purpose Interrupt Enable */
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#define IMX9_MU_GIER_GIE2_FLAG (1 << IMX9_MU_GIER_GIE2_SHIFT) /* MUA General-purpose Interrupt Enable */
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#define IMX9_MU_GIER_GIE3_SHIFT 3 /* MUA General-purpose Interrupt Enable */
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#define IMX9_MU_GIER_GIE3_FLAG (1 << IMX9_MU_GIER_GIE3_SHIFT) /* MUA General-purpose Interrupt Enable */
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/* GCR register */
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#define IMX9_MU_GCR_GIR0_SHIFT 0 /* MUA General-Purpose Interrupt Request */
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#define IMX9_MU_GCR_GIR0_FLAG (1 << IMX9_MU_GCR_GIR0_SHIFT) /* MUA General-Purpose Interrupt Request */
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#define IMX9_MU_GCR_GIR1_SHIFT 1 /* MUA General-Purpose Interrupt Request */
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#define IMX9_MU_GCR_GIR1_FLAG (1 << IMX9_MU_GCR_GIR1_SHIFT) /* MUA General-Purpose Interrupt Request */
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#define IMX9_MU_GCR_GIR2_SHIFT 2 /* MUA General-Purpose Interrupt Request */
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#define IMX9_MU_GCR_GIR2_FLAG (1 << IMX9_MU_GCR_GIR2_SHIFT) /* MUA General-Purpose Interrupt Request */
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#define IMX9_MU_GCR_GIR3_SHIFT 3 /* MUA General-Purpose Interrupt Request */
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#define IMX9_MU_GCR_GIR3_FLAG (1 << IMX9_MU_GCR_GIR3_SHIFT) /* MUA General-Purpose Interrupt Request */
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/* GSR register */
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#define IMX9_MU_GSR_GIP0_SHIFT 0 /* MUA General-Purpose Interrupt Request Pending */
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#define IMX9_MU_GSR_GIP0_FLAG (1 << IMX9_MU_GSR_GIP0_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
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#define IMX9_MU_GSR_GIP1_SHIFT 1 /* MUA General-Purpose Interrupt Request Pending */
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#define IMX9_MU_GSR_GIP1_FLAG (1 << IMX9_MU_GSR_GIP1_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
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#define IMX9_MU_GSR_GIP2_SHIFT 2 /* MUA General-Purpose Interrupt Request Pending */
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#define IMX9_MU_GSR_GIP2_FLAG (1 << IMX9_MU_GSR_GIP2_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
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#define IMX9_MU_GSR_GIP3_SHIFT 3 /* MUA General-Purpose Interrupt Request Pending */
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#define IMX9_MU_GSR_GIP3_FLAG (1 << IMX9_MU_GSR_GIP3_SHIFT) /* MUA General-Purpose Interrupt Request Pending */
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/* TCR register */
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#define IMX9_MU_TCR_TIE0_SHIFT 0 /* MUA Transmit Interrupt Enable */
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#define IMX9_MU_TCR_TIE0_FLAG (1 << IMX9_MU_TCR_TIE0_SHIFT) /* MUA Transmit Interrupt Enable */
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#define IMX9_MU_TCR_TIE1_SHIFT 1 /* MUA Transmit Interrupt Enable */
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#define IMX9_MU_TCR_TIE1_FLAG (1 << IMX9_MU_TCR_TIE1_SHIFT) /* MUA Transmit Interrupt Enable */
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#define IMX9_MU_TCR_TIE2_SHIFT 2 /* MUA Transmit Interrupt Enable */
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#define IMX9_MU_TCR_TIE2_FLAG (1 << IMX9_MU_TCR_TIE2_SHIFT) /* MUA Transmit Interrupt Enable */
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#define IMX9_MU_TCR_TIE3_SHIFT 3 /* MUA Transmit Interrupt Enable */
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#define IMX9_MU_TCR_TIE3_FLAG (1 << IMX9_MU_TCR_TIE3_SHIFT) /* MUA Transmit Interrupt Enable */
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/* TSR register */
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#define IMX9_MU_TSR_TE0_SHIFT 0 /* MUA Transmit Empty */
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#define IMX9_MU_TSR_TE0_FLAG (1 << IMX9_MU_TSR_TE0_SHIFT) /* MUA Transmit Empty */
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#define IMX9_MU_TSR_TE1_SHIFT 1 /* MUA Transmit Empty */
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#define IMX9_MU_TSR_TE1_FLAG (1 << IMX9_MU_TSR_TE1_SHIFT) /* MUA Transmit Empty */
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#define IMX9_MU_TSR_TE2_SHIFT 2 /* MUA Transmit Empty */
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#define IMX9_MU_TSR_TE2_FLAG (1 << IMX9_MU_TSR_TE2_SHIFT) /* MUA Transmit Empty */
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#define IMX9_MU_TSR_TE3_SHIFT 3 /* MUA Transmit Empty */
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#define IMX9_MU_TSR_TE3_FLAG (1 << IMX9_MU_TSR_TE3_SHIFT) /* MUA Transmit Empty */
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/* RCR register */
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#define IMX9_MU_RCR_RIE0_SHIFT 0 /* MUA Receive Interrupt Enable */
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#define IMX9_MU_RCR_RIE0_FLAG (1 << IMX9_MU_RCR_RIE0_SHIFT) /* MUA Receive Interrupt Enable */
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#define IMX9_MU_RCR_RIE1_SHIFT 1 /* MUA Receive Interrupt Enable */
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#define IMX9_MU_RCR_RIE1_FLAG (1 << IMX9_MU_RCR_RIE1_SHIFT) /* MUA Receive Interrupt Enable */
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#define IMX9_MU_RCR_RIE2_SHIFT 2 /* MUA Receive Interrupt Enable */
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#define IMX9_MU_RCR_RIE2_FLAG (1 << IMX9_MU_RCR_RIE2_SHIFT) /* MUA Receive Interrupt Enable */
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#define IMX9_MU_RCR_RIE3_SHIFT 3 /* MUA Receive Interrupt Enable */
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#define IMX9_MU_RCR_RIE3_FLAG (1 << IMX9_MU_RCR_RIE3_SHIFT) /* MUA Receive Interrupt Enable */
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/* RSR register */
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#define IMX9_MU_RSR_RF0_SHIFT 0 /* MUA Receive Register Full */
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#define IMX9_MU_RSR_RF0_FLAG (1 << IMX9_MU_RSR_RF0_SHIFT) /* MUA Receive Register Full */
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#define IMX9_MU_RSR_RF1_SHIFT 1 /* MUA Receive Register Full */
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#define IMX9_MU_RSR_RF1_FLAG (1 << IMX9_MU_RSR_RF1_SHIFT) /* MUA Receive Register Full */
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#define IMX9_MU_RSR_RF2_SHIFT 2 /* MUA Receive Register Full */
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#define IMX9_MU_RSR_RF2_FLAG (1 << IMX9_MU_RSR_RF2_SHIFT) /* MUA Receive Register Full */
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#define IMX9_MU_RSR_RF3_SHIFT 3 /* MUA Receive Register Full */
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#define IMX9_MU_RSR_RF3_FLAG (1 << IMX9_MU_RSR_RF3_SHIFT) /* MUA Receive Register Full */
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/* Register array dimensions */
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|
||||
#define IMX9_MU_TR_REGARRAY_SIZE 4
|
||||
#define IMX9_MU_RR_REGARRAY_SIZE 4
|
||||
#define IMX9_NR_OF_GPI 4
|
||||
#define IMX9_MSG_INT_MASK ((1 << IMX9_MU_RR_REGARRAY_SIZE) - 1)
|
||||
#define IMX9_GPI_INT_MASK ((1 << IMX9_NR_OF_GPI) - 1)
|
||||
|
||||
#endif /* __ARCH_ARM64_SRC_IMX9_HARDWARE_IMX9_MU_H */
|
||||
@@ -0,0 +1,392 @@
|
||||
/****************************************************************************
|
||||
* arch/arm64/src/imx9/imx9_mu.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* SPDX-FileCopyrightText: 2024 NXP
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <debug.h>
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/irq.h>
|
||||
#include <sys/types.h>
|
||||
|
||||
#include "imx9_mu.h"
|
||||
#include "arm64_arch.h"
|
||||
#include "arm64_internal.h"
|
||||
#include "hardware/imx95/imx95_memorymap.h"
|
||||
#include "hardware/imx9_mu.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
|
||||
struct imx9_mu_dev_s
|
||||
{
|
||||
uintptr_t mubase;
|
||||
uint32_t irq;
|
||||
imx9_mu_msg_callback_t msg_callback;
|
||||
imx9_mu_gpi_callback_t gpi_callback;
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static struct imx9_mu_dev_s g_mu2_dev =
|
||||
{
|
||||
.mubase = IMX9_MU2_MUA_BASE,
|
||||
.irq = IMX9_IRQ_MU2_A
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
static int imx9_mu_interrupt(int irq, void *context, void *args)
|
||||
{
|
||||
struct imx9_mu_dev_s *dev = args;
|
||||
|
||||
uint32_t sr = getreg32(IMX9_MU_SR(dev->mubase));
|
||||
uint32_t rsr = getreg32(IMX9_MU_RSR(dev->mubase));
|
||||
uint32_t gsr = getreg32(IMX9_MU_GSR(dev->mubase));
|
||||
|
||||
ipcinfo("MU irq=%d, SR=0x%04x, RSR=0x%04x, GSR=0x%04x\n", irq, sr, rsr,
|
||||
gsr);
|
||||
|
||||
if (sr & IMX9_MU_SR_RFP_FLAG)
|
||||
{
|
||||
for (int i = 0; i < IMX9_MU_RR_REGARRAY_SIZE; i++)
|
||||
{
|
||||
if (rsr & (1 << i))
|
||||
{
|
||||
uint32_t msg = imx95_mu_receive_msg_non_blocking(dev, i);
|
||||
|
||||
if (dev->msg_callback)
|
||||
{
|
||||
dev->msg_callback(i, msg, dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
for (int i = 0; i < IMX9_NR_OF_GPI; i++)
|
||||
{
|
||||
if (gsr & (1 << i))
|
||||
{
|
||||
putreg32((1 << i), IMX9_MU_GSR(dev->mubase));
|
||||
|
||||
if (dev->gpi_callback)
|
||||
{
|
||||
dev->gpi_callback(i, dev);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Unknown interrupt flag which occurs when A55 shuts down */
|
||||
|
||||
if (sr & 0x80)
|
||||
{
|
||||
/* TODO how to clear this flag? A W1C doesn't seem to work.. */
|
||||
|
||||
putreg32(0x80, IMX9_MU_SR(dev->mubase));
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize mu
|
||||
*
|
||||
* Input Parameters:
|
||||
* index - The index of mu
|
||||
*
|
||||
* Returned Value:
|
||||
* imx9_mu_dev_s struct is returned on success. NULL is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct imx9_mu_dev_s *imx95_mu_init(int index)
|
||||
{
|
||||
struct imx9_mu_dev_s *priv;
|
||||
|
||||
if (index == 2)
|
||||
{
|
||||
priv = &g_mu2_dev;
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
return NULL;
|
||||
}
|
||||
|
||||
irq_attach(priv->irq, imx9_mu_interrupt, priv);
|
||||
up_enable_irq(priv->irq);
|
||||
|
||||
return priv;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_subscribe_msg
|
||||
*
|
||||
* Description:
|
||||
* Subscribe msg, when the irq occur,the msg callback will be called.
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* msg_int_bitfield - Enable correspond bit receive irq
|
||||
* callback - The call back will called when the irq occur
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imx95_mu_subscribe_msg(struct imx9_mu_dev_s *priv,
|
||||
uint32_t msg_int_bitfield,
|
||||
imx9_mu_msg_callback_t callback)
|
||||
{
|
||||
priv->msg_callback = callback;
|
||||
putreg32(msg_int_bitfield & IMX9_MSG_INT_MASK, IMX9_MU_RCR(priv->mubase));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_subscribe_gpi
|
||||
*
|
||||
* Description:
|
||||
* Subscribe msg, when the irq occur,the msg callback will be called.
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* gpi_int_enable - Enable correspond bit general purpose irq
|
||||
* callback - The call back will called when the irq occur
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imx95_mu_subscribe_gpi(struct imx9_mu_dev_s *priv,
|
||||
uint32_t gpi_int_enable,
|
||||
imx9_mu_gpi_callback_t callback)
|
||||
{
|
||||
priv->gpi_callback = callback;
|
||||
putreg32(gpi_int_enable & IMX9_GPI_INT_MASK, IMX9_MU_GIER(priv->mubase));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_deinit
|
||||
*
|
||||
* Description:
|
||||
* Deinit mu
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be deinit
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imx95_mu_deinit(struct imx9_mu_dev_s *priv)
|
||||
{
|
||||
up_disable_irq(priv->irq);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_send_msg_non_blocking
|
||||
*
|
||||
* Description:
|
||||
* When the mu is busy, will return err
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* reg_index - Which one transmit reg to be used
|
||||
* msg - The msgto be send
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx95_mu_send_msg_non_blocking(struct imx9_mu_dev_s *priv,
|
||||
uint32_t reg_index, uint32_t msg)
|
||||
{
|
||||
assert(reg_index < IMX9_MU_TR_REGARRAY_SIZE);
|
||||
|
||||
ipcinfo("MU send msg nonblocking idx=%d, msg=%d\n", reg_index, msg);
|
||||
|
||||
if ((getreg32(IMX9_MU_TSR(priv->mubase)) & (1UL << reg_index)) == 0UL)
|
||||
{
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
putreg32(msg, IMX9_MU_TR1(priv->mubase) + (reg_index * sizeof(uint32_t)));
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_send_msg
|
||||
*
|
||||
* Description:
|
||||
* Send msg blocking
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* reg_index - Which one transmit reg to be used
|
||||
* msg - The msgto be send
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imx95_mu_send_msg(struct imx9_mu_dev_s *priv, uint32_t reg_index,
|
||||
uint32_t msg)
|
||||
{
|
||||
assert(reg_index < IMX9_MU_TR_REGARRAY_SIZE);
|
||||
|
||||
ipcinfo("MU send msg idx=%d, msg=%d\n", reg_index, msg);
|
||||
|
||||
/* Wait TX register to be empty. */
|
||||
|
||||
while ((getreg32(IMX9_MU_TSR(priv->mubase)) & (1UL << reg_index)) == 0UL);
|
||||
|
||||
putreg32(msg, IMX9_MU_TR1(priv->mubase) + reg_index * sizeof(uint32_t));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_has_received_msg
|
||||
*
|
||||
* Description:
|
||||
* Check Mu if has msg
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* reg_index - Which one receive reg to be used
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx95_mu_has_received_msg(struct imx9_mu_dev_s *priv, uint32_t reg_index)
|
||||
{
|
||||
return getreg32(IMX9_MU_RSR(priv->mubase)) & (1UL << reg_index) ? 0 :
|
||||
-ENODATA;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_receive_msg_non_blocking
|
||||
*
|
||||
* Description:
|
||||
* Non block receive msg
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* reg_index - Which one receive reg to be used
|
||||
*
|
||||
* Returned Value:
|
||||
* The value of index receive reg
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t imx95_mu_receive_msg_non_blocking(struct imx9_mu_dev_s *priv,
|
||||
uint32_t reg_index)
|
||||
{
|
||||
assert(reg_index < IMX9_MU_RR_REGARRAY_SIZE);
|
||||
|
||||
return getreg32(IMX9_MU_RR1(priv->mubase) + reg_index * sizeof(uint32_t));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_receive_msg
|
||||
*
|
||||
* Description:
|
||||
* Block receive msg
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* reg_index - Which one receive reg to be used
|
||||
*
|
||||
* Returned Value:
|
||||
* The value of index receive reg
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t imx95_mu_receive_msg(struct imx9_mu_dev_s *priv, uint32_t reg_index)
|
||||
{
|
||||
assert(reg_index < IMX9_MU_RR_REGARRAY_SIZE);
|
||||
|
||||
/* Wait RX register to be not empty. */
|
||||
|
||||
while (imx95_mu_has_received_msg(priv, reg_index) == -ENODATA);
|
||||
|
||||
return getreg32(IMX9_MU_RR1(priv->mubase) + reg_index * sizeof(uint32_t));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_trigger_interrupts
|
||||
*
|
||||
* Description:
|
||||
* Send irq to MUB
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* interrupts - The number of interrupts
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx95_mu_trigger_interrupts(struct imx9_mu_dev_s *priv,
|
||||
uint32_t interrupts)
|
||||
{
|
||||
int ret = -ECOMM;
|
||||
uint32_t gcr = getreg32(IMX9_MU_GCR(priv->mubase));
|
||||
|
||||
/* Only if previous interrupts has been accepted. */
|
||||
|
||||
if ((gcr & interrupts) == 0)
|
||||
{
|
||||
putreg32(gcr | interrupts, IMX9_MU_GCR(priv->mubase));
|
||||
ret = OK;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -0,0 +1,227 @@
|
||||
/****************************************************************************
|
||||
* arch/arm64/src/imx9/imx9_mu.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* SPDX-FileCopyrightText: 2024 NXP
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM64_SRC_IMX9_MU_H
|
||||
#define __ARCH_ARM64_SRC_IMX9_MU_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
typedef void (*imx9_mu_msg_callback_t)(int id, uint32_t msg, void *arg);
|
||||
typedef void (*imx9_mu_gpi_callback_t)(int id, void *arg);
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_init
|
||||
*
|
||||
* Description:
|
||||
* Initialize mu
|
||||
*
|
||||
* Input Parameters:
|
||||
* index - The index of mu
|
||||
*
|
||||
* Returned Value:
|
||||
* imx9_mu_dev_s struct is returned on success. NULL is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
struct imx9_mu_dev_s *imx95_mu_init(int index);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_subscribe_msg
|
||||
*
|
||||
* Description:
|
||||
* Subscribe msg, when the irq occur,the msg callback will be called.
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* msg_int_bitfield - Enable correspond bit receive irq
|
||||
* callback - The call back will called when the irq occur
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imx95_mu_subscribe_msg(struct imx9_mu_dev_s *priv,
|
||||
uint32_t msg_int_bitfield,
|
||||
imx9_mu_msg_callback_t callback);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_subscribe_gpi
|
||||
*
|
||||
* Description:
|
||||
* Subscribe msg, when the irq occur,the msg callback will be called.
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* gpi_int_enable - Enable correspond bit general purpose irq
|
||||
* callback - The call back will called when the irq occur
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imx95_mu_subscribe_gpi(struct imx9_mu_dev_s *priv,
|
||||
uint32_t gpi_int_enable,
|
||||
imx9_mu_gpi_callback_t callback);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_deinit
|
||||
*
|
||||
* Description:
|
||||
* Deinit mu
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be deinit
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imx95_mu_deinit(struct imx9_mu_dev_s *priv);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_send_msg_non_blocking
|
||||
*
|
||||
* Description:
|
||||
* When the mu is busy, will return err
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* reg_index - Which one transmit reg to be used
|
||||
* msg - The msgto be send
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx95_mu_send_msg_non_blocking(struct imx9_mu_dev_s *priv,
|
||||
uint32_t reg_index, uint32_t msg);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_send_msg
|
||||
*
|
||||
* Description:
|
||||
* Send msg blocking
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* reg_index - Which one transmit reg to be used
|
||||
* msg - The msgto be send
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imx95_mu_send_msg(struct imx9_mu_dev_s *priv, uint32_t reg_index,
|
||||
uint32_t msg);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_has_received_msg
|
||||
*
|
||||
* Description:
|
||||
* Check Mu if has msg
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* reg_index - Which one receive reg to be used
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx95_mu_has_received_msg(struct imx9_mu_dev_s *priv,
|
||||
uint32_t reg_index);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_receive_msg_non_blocking
|
||||
*
|
||||
* Description:
|
||||
* Non block receive msg
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* reg_index - Which one receive reg to be used
|
||||
*
|
||||
* Returned Value:
|
||||
* The value of index receive reg
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t imx95_mu_receive_msg_non_blocking(struct imx9_mu_dev_s *priv,
|
||||
uint32_t reg_index);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_receive_msg
|
||||
*
|
||||
* Description:
|
||||
* Block receive msg
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* reg_index - Which one receive reg to be used
|
||||
*
|
||||
* Returned Value:
|
||||
* The value of index receive reg
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t imx95_mu_receive_msg(struct imx9_mu_dev_s *priv,
|
||||
uint32_t reg_index);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx95_mu_trigger_interrupts
|
||||
*
|
||||
* Description:
|
||||
* Send irq to MUB
|
||||
*
|
||||
* Input Parameters:
|
||||
* priv - The mu dev will be used
|
||||
* interrupts - The number of interrupts
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx95_mu_trigger_interrupts(struct imx9_mu_dev_s *priv,
|
||||
uint32_t interrupts);
|
||||
|
||||
#endif /* __ARCH_ARM64_SRC_IMX9_MU_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,333 @@
|
||||
/****************************************************************************
|
||||
* arch/arm64/src/imx9/imx9_scmi.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* SPDX-FileCopyrightText: 2024 NXP
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_IMX9_IMX9_SCMI_H
|
||||
#define __ARCH_ARM_SRC_IMX9_IMX9_SCMI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define SCMI_PLATFORM_A2P 0 /* Agent -> Platform */
|
||||
#define SCMI_PLATFORM_NOTIFY 1 /* Platform -> Agent */
|
||||
#define SCMI_PLATFORM_PRIORITY 2
|
||||
|
||||
#define SCMI_CLOCK_RATE_MASK 0xFFFFFFFFU
|
||||
|
||||
/* SCMI clock round options */
|
||||
|
||||
#define SCMI_CLOCK_ROUND_DOWN 0U /* Round down */
|
||||
#define SCMI_CLOCK_ROUND_UP 1U /* Round up */
|
||||
#define SCMI_CLOCK_ROUND_AUTO 2U /* Round to nearest */
|
||||
|
||||
/* SCMI clock rate flags */
|
||||
|
||||
/* Round up/down */
|
||||
|
||||
#define SCMI_CLOCK_RATE_FLAGS_ROUND(x) (((x) & 0x3U) << 2U)
|
||||
|
||||
/* Ignore delayed response */
|
||||
|
||||
#define SCMI_CLOCK_RATE_FLAGS_NO_RESP(x) (((x) & 0x1U) << 1U)
|
||||
|
||||
/* Async flag */
|
||||
|
||||
#define SCMI_CLOCK_RATE_FLAGS_ASYNC(x) (((x) & 0x1U) << 0U)
|
||||
|
||||
/* SCMI clock config attributes */
|
||||
|
||||
/* OEM specified config type */
|
||||
|
||||
#define SCMI_CLOCK_CONFIG_SET_OEM(x) (((x) & 0xFFU) << 16U)
|
||||
|
||||
/* Enable/Disable */
|
||||
|
||||
#define SCMI_CLOCK_CONFIG_SET_ENABLE(x) (((x) & 0x3U) << 0U)
|
||||
|
||||
/* SCMI pin control types */
|
||||
|
||||
#define SCMI_PINCTRL_SEL_PIN 0U
|
||||
#define SCMI_PINCTRL_SEL_GROUP 1U
|
||||
#define SCMI_PINCTRL_TYPE_MUX 192U /* Mux type */
|
||||
#define SCMI_PINCTRL_TYPE_CONFIG 193U /* Config type */
|
||||
#define SCMI_PINCTRL_TYPE_DAISY_ID 194U /* Daisy ID type */
|
||||
#define SCMI_PINCTRL_TYPE_DAISY_CFG 195U /* Daisy config type */
|
||||
#define SCMI_PINCTRL_SET_ATTR_NUM_CONFIGS(x) (((x) & 0xFFU) << 2U)
|
||||
#define SCMI_PINCTRL_SET_ATTR_SELECTOR(x) (((x) & 0x3U) << 0U)
|
||||
|
||||
/* Pinctrl */
|
||||
|
||||
#define SCMI_PLATFORM_PINCTRL_MUX_MODE_MASK (0x7U)
|
||||
#define SCMI_PLATFORM_PINCTRL_MUX_MODE_SHIFT (0U)
|
||||
#define SCMI_PLATFORM_PINCTRL_MUX_MODE(x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << SCMI_PLATFORM_PINCTRL_MUX_MODE_SHIFT)) \
|
||||
& SCMI_PLATFORM_PINCTRL_MUX_MODE_MASK)
|
||||
|
||||
#define SCMI_PLATFORM_PINCTRL_SION_MASK (0x10)
|
||||
#define SCMI_PLATFORM_PINCTRL_SION_SHIFT (4U)
|
||||
#define SCMI_PLATFORM_PINCTRL_SION(x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << SCMI_PLATFORM_PINCTRL_SION_SHIFT)) \
|
||||
& SCMI_PLATFORM_PINCTRL_SION_MASK)
|
||||
|
||||
#define SCMI_PLATFORM_PINCTRL_BASE IMX9_IOMUXC1_BASE
|
||||
#define SCMI_PLATFORM_PINCTRL_MUXREG_OFF (SCMI_PLATFORM_PINCTRL_BASE)
|
||||
#define SCMI_PLATFORM_PINCTRL_CFGREG_OFF (SCMI_PLATFORM_PINCTRL_BASE + 0x204)
|
||||
#define SCMI_PLATFORM_PINCTRL_DAISYREG_OFF (SCMI_PLATFORM_PINCTRL_BASE + 0x408)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t channel; /* Channel id: SCMI_A2P, SCMI_NOTIRY, SCMI_P2A, */
|
||||
uint32_t rateu;
|
||||
uint32_t ratel;
|
||||
uint32_t clk_id; /* Clock device id */
|
||||
uint32_t pclk_id; /* Parent clock device id */
|
||||
uint32_t div; /* Clock divider */
|
||||
uint32_t attributes; /* Clock attributes */
|
||||
uint32_t oem_config_val;
|
||||
uint32_t flags;
|
||||
} scmi_clock_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t channel;
|
||||
uint32_t mux_register;
|
||||
uint32_t mux_mode;
|
||||
uint32_t input_register;
|
||||
uint32_t input_daisy;
|
||||
uint32_t config_register;
|
||||
uint32_t config_value;
|
||||
uint32_t input_on_field;
|
||||
} scmi_pinctrl_t;
|
||||
|
||||
/* SCMI clock rate */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t lower; /* Lower 32 bits of the physical rate in Hz */
|
||||
uint32_t upper; /* Upper 32 bits of the physical rate in Hz */
|
||||
} scmi_clock_rate_t;
|
||||
|
||||
/* SCMI pin control config */
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t type; /* The type of config */
|
||||
uint32_t value; /* The configuration value */
|
||||
} scmi_pin_config_t;
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx9_scmi_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the scmi
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void imx9_scmi_initialize(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx9_scmi_get_clock_parent
|
||||
*
|
||||
* Description:
|
||||
* Use scmi get clockid's parentid
|
||||
*
|
||||
* Input Parameters:
|
||||
* channel - Channel id
|
||||
* clockid - Identifier for the clock
|
||||
* parentid - Identifier for the parent clock id
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx9_scmi_get_clock_parent(uint32_t channel, uint32_t clockid,
|
||||
uint32_t *parentid);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx9_scmi_set_clock_parent
|
||||
*
|
||||
* Description:
|
||||
* Use scmi set clockid's parentid
|
||||
*
|
||||
* Input Parameters:
|
||||
* channel - Channel id
|
||||
* clockid - Identifier for the clock
|
||||
* parentid - Identifier for the parent clock id
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx9_scmi_set_clock_parent(uint32_t channel, uint32_t clockid,
|
||||
uint32_t parentid);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx9_scmi_get_clock_rate
|
||||
*
|
||||
* Description:
|
||||
* Use scmi get clock rate.
|
||||
*
|
||||
* Input Parameters:
|
||||
* channel - Channel id
|
||||
* clockid - Identifier for the clock
|
||||
* rate - Returned rate
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx9_scmi_get_clock_rate(uint32_t channel, uint32_t clockid,
|
||||
scmi_clock_rate_t *rate);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx9_scmi_set_clock_rate
|
||||
*
|
||||
* Description:
|
||||
* Use scmi set clock rate.
|
||||
*
|
||||
* Input Parameters:
|
||||
* channel - Channel id
|
||||
* clockid - Identifier for the clock
|
||||
* flags - Rate flags
|
||||
* rate - The rate to be set
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx9_scmi_set_clock_rate(uint32_t channel, uint32_t clockid,
|
||||
uint32_t flags, scmi_clock_rate_t rate);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx9_scmi_set_clock_config
|
||||
*
|
||||
* Description:
|
||||
* Use scmi set clock config
|
||||
*
|
||||
* Input Parameters:
|
||||
* channel - Channel id
|
||||
* clockid - Identifier for the clock
|
||||
* attributes - The attributes to be set
|
||||
* oem_config_val - The oem config val
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx9_scmi_set_clock_config(uint32_t channel, uint32_t clockid,
|
||||
uint32_t attributes,
|
||||
uint32_t oem_config_val);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx9_scmi_set_pinctrl_config
|
||||
*
|
||||
* Description:
|
||||
* Use scmi set pinctrl config.
|
||||
*
|
||||
* Input Parameters:
|
||||
* channel - Channel id
|
||||
* identifier - Identifier for the pin or group
|
||||
* attributes - Pin control attributes
|
||||
* configs - Array of configurations: sorted in numerically
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx9_scmi_set_pinctrl_config(uint32_t channel, uint32_t identifier,
|
||||
uint32_t attributes,
|
||||
const scmi_pin_config_t *configs);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx9_scmi_get_power_state
|
||||
*
|
||||
* Description:
|
||||
* Use scmi set powerdomain state.
|
||||
*
|
||||
* Input Parameters:
|
||||
* channel - Channel id
|
||||
* domain - The power domain id
|
||||
* state - The returnrd power state
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx9_scmi_get_power_state(uint32_t channel, uint32_t domain,
|
||||
uint32_t *state);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx9_scmi_set_power_state
|
||||
*
|
||||
* Description:
|
||||
* Use scmi set powerdomain state.
|
||||
*
|
||||
* Input Parameters:
|
||||
* channel - Channel id
|
||||
* domain - The power domain id
|
||||
* state - The power state
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success. A negated errno value is returned on
|
||||
* failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int imx9_scmi_set_power_state(uint32_t channel, uint32_t domain,
|
||||
uint32_t state);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_IMX9_IMX9_SCMI_H */
|
||||
Reference in New Issue
Block a user