mirror of
https://github.com/apache/nuttx.git
synced 2026-05-22 22:20:01 +08:00
SAM4E: Add support for the Cortex-M Cache Control block
This commit is contained in:
Gregory Nutt
+207
-202
@@ -249,32 +249,206 @@ config ARCH_CHIP_SAM4S
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menu "AT91SAM3/4 Peripheral Support"
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config SAM_PICOCACHE
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bool "PICOCACHE"
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default y
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depends on ARCH_CHIP_SAM4L
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config SAM34_OCD
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bool "On-chip DEBUG"
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depends on ARCH_CHIP_SAM4L
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default y if DEBUG_SYMBOLS
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default n if !DEBUG_SYMBOLS
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config SAM34_APBA
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bool "APBA bridge"
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config SAM34_ABDACB
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bool "Audio Bitstream DAC (ABDAC)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_ACC
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bool "Analog Comparator (ACC/ACMP)"
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default n
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depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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config SAM34_ADC
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bool "10-bit ADC Controller (ADC)"
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default n
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depends on ARCH_CHIP_SAM3U
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config SAM34_ADC12B
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bool "12-bit ADC Controller (ADC12)"
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default n
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depends on !ARCH_CHIP_SAM4E
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config SAM34_AES
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bool "AES"
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default n
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depends on ARCH_CHIP_SAM4E
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config SAM34_AESA
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bool "Advanced Encryption Standard (AESA)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_AFEC0
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bool "Analog Front End 0 (AFEC0)"
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default n
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depends on ARCH_CHIP_SAM4E
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config SAM34_AFEC1
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bool "Analog Front End 1 (AFEC1)"
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default n
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depends on ARCH_CHIP_SAM4E
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config SAM34_APBA
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bool "APBA bridge (APBA)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_AST
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bool "Asynchronous Timer (AST)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_CAN0
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bool "CAN0"
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
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config SAM34_CAN1
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bool "CAN1"
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
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config SAM34_CATB
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bool "Capacitive Touch Module B (CATB)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_CHIPID
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bool "Chip ID"
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default n
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depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4E
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config SAM34_CMCC
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bool "Cortex M Cache Controller (CMCC)"
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default n
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depends on ARCH_CHIP_SAM4E
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config SAM34_CRCCU
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bool "CRC Calculation Unit (CRCCU)"
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default n
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depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S
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config SAM34_DACC
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bool "Digital To Analog Converter (DACC)"
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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config SAM34_EIC
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bool "External Interrupt Controller (EIC)"
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default n
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depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4E
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config SAM34_DMAC
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bool "DMA controller"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
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select ARCH_DMA
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config SAM34_EMAC
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bool "Ethernet MAC (EMAC)"
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
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config SAM34_FREQM
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bool "Frequency Meter (FREQM)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_GLOC
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bool "GLOC"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_HMATRIX
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bool "HMATRIX"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_HRAMC1
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bool "HRAMC1 (picoCache RAM)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_HSMCI
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bool "High Speed Multimedia Card Interface (HSMCI)"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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select ARCH_HAVE_SDIO
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config SAM34_IISC
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bool "Inter-IC Sound (I2S) Controller"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_LCDCA
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bool "LCD Controller A (LCDCA)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_NAND
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bool "NAND support"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4E
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config SAM34_OCD
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bool "On-chip DEBUG (OCD)"
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depends on ARCH_CHIP_SAM4L
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default y if DEBUG_SYMBOLS
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default n if !DEBUG_SYMBOLS
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config SAM34_PARC
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bool "Parallel Capture (PARC)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_PDCA
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bool "Peripheral DMA controller (PDC)"
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default n
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depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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select ARCH_DMA
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config SAM34_PEVC
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bool "Peripheral Event Controller"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM_PICOCACHE
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bool "PicoCACHE"
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default y
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depends on ARCH_CHIP_SAM4L
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config SAM34_PICOUART
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bool "PicoUART"
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default n
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depends on ARCH_CHIP_SAM4L
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select ARCH_HAVE_UART
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config SAM34_PWM
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bool "Pulse Width Modulation (PWM) Controller"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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config SAM34_RTC
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bool "Real Time Clock (RTC)"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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config SAM34_RTT
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bool "Real Time Timer (RTT)"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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config SAM34_SDRAMC
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bool "SDRAM Controller (SDRAMC)"
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
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config SAM34_SMC
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bool "Static Memory Controller (SMC)"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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config SAM34_SPI0
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bool "Serial Peripheral Interface 0 (SPI0)"
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default n
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@@ -332,10 +506,10 @@ config SAM34_TC8
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
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config SAM34_PWM
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bool "Pulse Width Modulation (PWM) Controller"
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config SAM34_TRNG
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bool "True Random Number Generator (TRNG)"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
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config SAM34_TWIM0
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bool "Two-wire Master Interface 0 (TWIM0)"
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@@ -375,11 +549,25 @@ config SAM34_UART1
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depends on ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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select ARCH_HAVE_UART1
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config SAM34_PICOUART
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bool "PicoUART"
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config SAM34_UDP
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bool "USB Device Full Speed (UDP)"
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default n
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depends on ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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config SAM34_UDPHS
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bool "USB Device High Speed (UDPHS)"
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default n
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depends on ARCH_CHIP_SAM3U
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config SAM34_UOTGHS
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bool "USB OTG High Speed (UOTGHS)"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X
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config SAM34_USBC
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bool "USB 2.0 Interface (USBC)"
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default n
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depends on ARCH_CHIP_SAM4L
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select ARCH_HAVE_UART
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config SAM34_USART0
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bool "USART 0"
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@@ -403,193 +591,10 @@ config SAM34_USART3
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select ARCH_HAVE_USART3
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
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config SAM34_ADC12B
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bool "12-bit ADC Controller"
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default n
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depends on !ARCH_CHIP_SAM4E
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config SAM34_ADC
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bool "10-bit ADC Controller"
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default n
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depends on ARCH_CHIP_SAM3U
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config SAM34_AFEC0
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bool "Analog Front End 0"
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default n
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depends on ARCH_CHIP_SAM4E
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config SAM34_AFEC1
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bool "Analog Front End 1"
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default n
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depends on ARCH_CHIP_SAM4E
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config SAM34_DACC
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bool "Digital To Analog Converter (DAC)"
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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config SAM34_ACC
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bool "Analog Comparator (AC)"
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default n
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depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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config SAM34_GLOC
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bool "GLOC"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_ABDACB
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bool "Audio Bitstream DAC (ABDAC)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_TRNG
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bool "True Random Number Generator (TRNG)"
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4L
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config SAM34_AES
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bool "AES"
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default n
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depends on ARCH_CHIP_SAM4E
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config SAM34_EMAC
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bool "Ethernet MAC (EMAC)"
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
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config SAM34_CAN0
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bool "CAN0"
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
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config SAM34_CAN1
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bool "CAN1"
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
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config SAM34_PARC
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bool "Parallel Capture (PARC)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_CATB
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bool "Capacitive Touch Module B (CATB)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_LCDCA
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bool "LCD Controller A (LCDCA)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_HRAMC1
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bool "HRAMC1 (picoCache RAM)"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_SMC
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bool "Static Memory Controller (SMC)"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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config SAM34_SDRAMC
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bool "SDRAM Controller (SDRAMC)"
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default n
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depends on ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A
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config SAM34_NAND
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bool "NAND support"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM4E
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config SAM34_HMATRIX
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bool "HMATRIX"
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default n
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depends on ARCH_CHIP_SAM4L
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config SAM34_PDCA
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bool "Peripheral DMA controller (PDC)"
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default n
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depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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select ARCH_DMA
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config SAM34_DMAC
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bool "DMA controller"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4E
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select ARCH_DMA
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config SAM34_CRCCU
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bool "CRC Calculation Unit"
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default n
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depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4S
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config SAM34_UDPHS
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bool "USB Device High Speed"
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default n
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depends on ARCH_CHIP_SAM3U
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config SAM34_UOTGHS
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bool "USB OTG High Speed"
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default n
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depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X
|
||||
|
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config SAM34_UDP
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bool "USB Device Full Speed"
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default n
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depends on ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
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||||
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config SAM34_USBC
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bool "USB 2.0 Interface"
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default n
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depends on ARCH_CHIP_SAM4L
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||||
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config SAM34_PEVC
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bool "Peripheral Event Controller"
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||||
default n
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||||
depends on ARCH_CHIP_SAM4L
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||||
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||||
config SAM34_CHIPID
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bool "Chip ID"
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default n
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depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4E
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||||
|
||||
config SAM34_FREQM
|
||||
bool "Frequency Meter (FREQM)"
|
||||
default n
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||||
depends on ARCH_CHIP_SAM4L
|
||||
|
||||
config SAM34_AST
|
||||
bool "Asynchronous Timer (AST)"
|
||||
default n
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||||
depends on ARCH_CHIP_SAM4L
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||||
|
||||
config SAM34_RTC
|
||||
bool "Real Time Clock (RTC)"
|
||||
default n
|
||||
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
|
||||
|
||||
config SAM34_RTT
|
||||
bool "Real Time Timer (RTT)"
|
||||
default n
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||||
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
|
||||
|
||||
config SAM34_WDT
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bool "Watchdog Timer (WDT)"
|
||||
default n
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|
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config SAM34_EIC
|
||||
bool "External Interrupt Controller (EIC)"
|
||||
default n
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||||
depends on ARCH_CHIP_SAM4L || ARCH_CHIP_SAM4E
|
||||
|
||||
config SAM34_HSMCI
|
||||
bool "High Speed Multimedia Card Interface (HSMCI)"
|
||||
default n
|
||||
depends on ARCH_CHIP_SAM3U || ARCH_CHIP_SAM3X || ARCH_CHIP_SAM3A || ARCH_CHIP_SAM4S || ARCH_CHIP_SAM4E
|
||||
select ARCH_HAVE_SDIO
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||||
|
||||
endmenu # AT91SAM3/4 Peripheral Support
|
||||
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||||
if ARCH_CHIP_SAM4L
|
||||
|
||||
@@ -92,6 +92,10 @@ ifeq ($(CONFIG_NUTTX_KERNEL),y)
|
||||
CHIP_CSRCS += sam_userspace.c sam_mpuinit.c
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||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SAM34_CMCC),y)
|
||||
CHIP_CSRCS += sam_cmcc.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_SAM34_DMAC),y)
|
||||
CHIP_CSRCS += sam_dmac.c
|
||||
endif
|
||||
|
||||
@@ -49,6 +49,15 @@
|
||||
/****************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************************/
|
||||
/* This information is available in the Cache Type Register. How every, it is more
|
||||
* efficient if we do not to do the decoding on each cache access.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARCH_CHIP_SAM4E
|
||||
# define CMCC_CACHE_SIZE 2048
|
||||
# define CMCC_CACHE_LINE_SIZE 16
|
||||
# define CMCC_NWAYS 4
|
||||
#endif
|
||||
|
||||
/* CMCC register offsets ****************************************************************/
|
||||
|
||||
@@ -100,7 +109,7 @@
|
||||
# define CMCC_TYPE_CSIZE_2KB (1 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 2 Kbytes */
|
||||
# define CMCC_TYPE_CSIZE_4KB (2 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 4 Kbytes */
|
||||
# define CMCC_TYPE_CSIZE_8KB (3 << CMCC_TYPE_CSIZE_SHIFT) /* Cache Size 8 Kbytes */
|
||||
#define CMCC_TYPE_CLSIZE_SHIFT (11) /* Bits 11-13: Cache Size */
|
||||
#define CMCC_TYPE_CLSIZE_SHIFT (11) /* Bits 11-13: Cache Line Size */
|
||||
#define CMCC_TYPE_CLSIZE_MASK (7 << CMCC_TYPE_CLSIZE_SHIFT)
|
||||
# define CMCC_TYPE_CLSIZE_4B (0 << CMCC_TYPE_CLSIZE_SHIFT) /* 4 Bytes */
|
||||
# define CMCC_TYPE_CLSIZE_8B (1 << CMCC_TYPE_CLSIZE_SHIFT) /* 8 Bytes */
|
||||
@@ -130,6 +139,7 @@
|
||||
# define CMCC_MAINT1_INDEX(n) ((uint32_t)(n) << CMCC_MAINT1_INDEX_SHIFT)
|
||||
#define CMCC_MAINT1_WAY_SHIFT (30) /* Bits 30-31: Invalidate Way */
|
||||
#define CMCC_MAINT1_WAY_MASK (3 << CMCC_MAINT1_WAY_SHIFT)
|
||||
# define CMCC_MAINT1_WAY(n) ((uint32_t)(n) << CMCC_MAINT1_WAY_SHIFT)
|
||||
# define CMCC_MAINT1_WAY0 (0 << CMCC_MAINT1_WAY_SHIFT) /* Way 0 selected */
|
||||
# define CMCC_MAINT1_WAY1 (1 << CMCC_MAINT1_WAY_SHIFT) /* Way 1 selected */
|
||||
# define CMCC_MAINT1_WAY2 (2 << CMCC_MAINT1_WAY_SHIFT) /* Way 2 selected */
|
||||
|
||||
@@ -0,0 +1,211 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/sam34/sam_cmcc.c
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "chip/sam_cmcc.h"
|
||||
#include "sam_cmcc.h"
|
||||
|
||||
#ifdef CONFIG_SAM34_CMCC
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define CMCC_MASK (CMCC_CACHE_LINE_SIZE-1)
|
||||
|
||||
#if CMCC_CACHE_LINE_SIZE == 4
|
||||
# define CMCC_SHIFT 2
|
||||
#elif CMCC_CACHE_LINE_SIZE == 8
|
||||
# define CMCC_SHIFT 3
|
||||
#elif CMCC_CACHE_LINE_SIZE == 16
|
||||
# define CMCC_SHIFT 4
|
||||
#elif CMCC_CACHE_LINE_SIZE == 32
|
||||
# define CMCC_SHIFT 5
|
||||
#else
|
||||
# error Unknown cache line size
|
||||
#endif
|
||||
|
||||
#define ALIGN_UP(a) (((a)+CMCC_MASK) & ~CMCC_MASK)
|
||||
#define ALIGN_DOWN(a) ((a) & ~CMCC_MASK)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_cmcc_enable
|
||||
*
|
||||
* Description:
|
||||
* Enable the Cortex-M Cache Controller
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_cmcc_enable(void)
|
||||
{
|
||||
/* "On reset, the cache controller data entries are all invalidated and the
|
||||
* cache is disabled. The cache is transparent to processor operations. The
|
||||
* cache controller is activated with its configuration registers. The
|
||||
* configuration interface is memory mapped in the private peripheral bus.
|
||||
*
|
||||
* "Use the following sequence to enable the cache controller.
|
||||
*
|
||||
* "1. Verify that the cache controller is disabled, reading the value of the
|
||||
* CSTS (cache status) field of the CMCC_SR register.
|
||||
* "2. Enable the cache controller, writing 1 to the CEN (cache enable) field
|
||||
* of the CMCC_CTRL register."
|
||||
*/
|
||||
|
||||
if ((getreg32(SAM_CMCC_SR) & CMCC_SR_CSTS) == 0)
|
||||
{
|
||||
putreg32(CMCC_CTRL_CEN, SAM_CMCC_CTRL);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_cmcc_disable
|
||||
*
|
||||
* Description:
|
||||
* Disable the Cortex-M Cache Controller
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_cmcc_disable(void)
|
||||
{
|
||||
/* "1. Disable the cache controller, writing 0 to the CEN field of the
|
||||
* CMCC_CTRL register.
|
||||
* "2. Check CSTS field of the CMCC_SR to verify that the cache is
|
||||
* successfully disabled.
|
||||
*/
|
||||
|
||||
putreg32(0, SAM_CMCC_CTRL);
|
||||
while ((getreg32(SAM_CMCC_SR) & CMCC_SR_CSTS) != 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_cmcc_invalidate
|
||||
*
|
||||
* Description:
|
||||
* Invalidate a range of addresses. Note: These addresses should be
|
||||
* aligned with the beginning and end of cache lines. Otherwise, values
|
||||
* at the edges of the region will also be invalidated!
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_cmcc_invalidate(uintptr_t start, uintptr_t end)
|
||||
{
|
||||
uintptr_t addr;
|
||||
uint32_t regval;
|
||||
uint32_t way
|
||||
uint32_t index;
|
||||
int nlines;
|
||||
|
||||
/* "When an invalidate by line command is issued the cache controller resets
|
||||
* the valid bit information of the decoded cache line. As the line is no
|
||||
* longer valid the replacement counter points to that line.
|
||||
*
|
||||
* "Use the following sequence to invalidate one line of cache.
|
||||
*
|
||||
* "1. Disable the cache controller, writing 0 to the CEN field of the
|
||||
* CMCC_CTRL register.
|
||||
* "2. Check CSTS field of the CMCC_SR to verify that the cache is
|
||||
* successfully disabled.
|
||||
* "3. Perform an invalidate by line writing the bit set {index, way} in
|
||||
* the CMCC_MAINT1 register.
|
||||
* "4. Enable the cache controller, writing 1 to the CEN field of the
|
||||
* CMCC_CTRL register."
|
||||
*/
|
||||
|
||||
/* Disable the cache controller */
|
||||
|
||||
sam_cmcc_disable();
|
||||
|
||||
/* Invalidate the address region */
|
||||
|
||||
start = ALIGN_DOWN(start);
|
||||
end = ALIGN_up(end);
|
||||
|
||||
index = (start >> CMCC_SHIFT)
|
||||
nlines = ((end - start) >> CMCC_SHIFT);
|
||||
|
||||
for (addr = start; addr < end; addr += CMCC_CACHE_LINE_SIZE, index++)
|
||||
{
|
||||
regval = CMCC_MAINT1_INDEX(index);
|
||||
for (way = 0; way < CMCC_NWAYS; way++)
|
||||
{
|
||||
putreg32(regval | CMCC_MAINT1_WAY(way), SAM_CMCC_MAINT1);
|
||||
}
|
||||
}
|
||||
|
||||
/* Re-enable the cache controller */
|
||||
|
||||
sam_cmcc_enable();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_cmcc_invalidateall
|
||||
*
|
||||
* Description:
|
||||
* Invalidate the entire cache
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_cmcc_invalidateall(void)
|
||||
{
|
||||
/* "To invalidate all cache entries:
|
||||
*
|
||||
* " Write 1 to the INVALL field of the CMCC_MAINT0 register."
|
||||
*/
|
||||
|
||||
putreg32(CMCC_MAINT0_INVALL, SAM_CMCC_MAINT0);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_SAM34_CMCC */
|
||||
@@ -0,0 +1,129 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/sam34/sam_cmcc.h
|
||||
*
|
||||
* Copyright (C) 2014 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_SAM34_SAM_CMCC_H
|
||||
#define __ARCH_ARM_SRC_SAM34_SAM_CMCC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef CONFIG_SAM34_CMCC
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Inline Functions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Function Prototypes
|
||||
************************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_cmcc_enable
|
||||
*
|
||||
* Description:
|
||||
* Enable the Cortex-M Cache Controller
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_cmcc_enable(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_cmcc_disable
|
||||
*
|
||||
* Description:
|
||||
* Disable the Cortex-M Cache Controller
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_cmcc_disable(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_cmcc_invalidate
|
||||
*
|
||||
* Description:
|
||||
* Invalidate a range of addresses. Note: These addresses should be
|
||||
* aligned with the beginning and end of cache lines. Otherwise, values
|
||||
* at the edges of the region will also be invalidated!
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_cmcc_invalidate(uintptr_t start, uintptr_t end);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: sam_cmcc_invalidateall
|
||||
*
|
||||
* Description:
|
||||
* Invalidate the entire cache
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void sam_cmcc_invalidateall(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* CONFIG_SAM34_CMCC */
|
||||
#endif /* __ARCH_ARM_SRC_SAM34_SAM_CMCC_H */
|
||||
@@ -171,6 +171,17 @@ void __start(void)
|
||||
sam_boardinitialize();
|
||||
showprogress('D');
|
||||
|
||||
#ifdef CONFIG_SAM34_CMCC
|
||||
/* Enable the Cortex-M Cache
|
||||
*
|
||||
* REVISIT: This logic is complete but I have not yet tried to enable it.
|
||||
* I have some questions about how the cache will effect memory mapped
|
||||
* register accesses.
|
||||
*/
|
||||
|
||||
sam_cmcc_enable();
|
||||
#endif
|
||||
|
||||
/* Then start NuttX */
|
||||
|
||||
showprogress('\r');
|
||||
|
||||
Reference in New Issue
Block a user