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Merged in pnb990/nuttx-kernel-arch (pull request #12)

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efm32 addons
This commit is contained in:
Gregory Nutt
2015-09-05 07:09:28 -06:00
parent 544ed7cdbd 1314f60caf
commit 906965e17b
12 changed files with 3140 additions and 50 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/src/efm32/Kconfig
+9
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@@ -132,6 +132,11 @@ config EFM32_RMU
bool "Reset Management Unit (RMU) "
default n
config EFM32_FLASHPROG
bool "Enable Erase/Write flash function (MSC) "
default n
select ARCH_HAVE_RAMFUNCS
config EFM32_RMU_DEBUG
bool "Reset Management Unit (RMU) DEBUG "
default n
@@ -145,6 +150,10 @@ config EFM32_I2C1
bool "I2C1"
default n
config EFM32_BITBAND
bool "BITBAND"
default n
config EFM32_USART0
bool "USART0"
default n
arch/arm/src/efm32/Make.defs
+8
View File
@@ -105,6 +105,14 @@ endif
CHIP_CSRCS = efm32_start.c efm32_clockconfig.c efm32_irq.c efm32_timerisr.c
CHIP_CSRCS += efm32_gpio.c efm32_lowputc.c efm32_timer.c efm32_i2c.c
ifeq ($(CONFIG_EFM32_FLASHPROG),y)
CHIP_CSRCS += efm32_flash.c
endif
ifeq ($(CONFIG_EFM32_BITBAND),y)
CHIP_CSRCS += efm32_bitband.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += efm32_idle.c
endif
arch/arm/src/efm32/efm32_adc.c
+1256
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File diff suppressed because it is too large Load Diff
arch/arm/src/efm32/efm32_adc.h
+607
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File diff suppressed because it is too large Load Diff
arch/arm/src/efm32/efm32_bitband.c
+189
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@@ -0,0 +1,189 @@
/****************************************************************************
* arch/arm/src/efm32/efm32_bitband.c
*
* Copyright (C) 2014 Bouteville Pierre-Noel. All rights reserved.
* Authors: Bouteville Pierre-Noel <pnb990@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "stdint.h"
#include "efm32_bitband.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#if defined(CONFIG_EFM32_BITBAND)
#ifndef EFM32_BITBAND_PER_BASE
# error "EFM32_BITBAND_PER_BASE not declared bitband may be not supported?"
#endif
#ifndef EFM32_BITBAND_RAM_BASE
# error "EFM32_BITBAND_RAM_BASE not declared bitband may be not supported?"
#endif
/****************************************************************************
* Private Types
****************************************************************************/
/****************************************************************************
* Private Function Prototypes
****************************************************************************/
/****************************************************************************
* Private Data
****************************************************************************/
/****************************************************************************
* Private Functions
****************************************************************************/
/******************************************************************************
* Name: bitband_set_peripheral
* Perform bit-band write operation on peripheral memory location.
*
* Description
* Bit-banding provides atomic read-modify-write cycle for single bit
* modification. Please refer to the reference manual for further details
* about bit-banding.
*
* Note
* This function is only atomic on cores which fully support bitbanding.
*
* Parameters
* addr Peripheral address location to modify bit in.
* bit Bit position to modify, 0-31.
* val Value to set bit to, 0 or 1.
*
******************************************************************************/
inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val)
{
uint32_t regval;
regval = EFM32_BITBAND_PER_BASE + ((addr-EFM32_PER_MEM_BASE)*32) + (bit*4);
*((volatile uint32_t *)regval) = (uint32_t)val;
}
/******************************************************************************
* Name: bitband_get_peripheral
* Perform bit-band operation on peripheral memory location.
*
* Description
* This function reads a single bit from the peripheral bit-band alias region.
* Bit-banding provides atomic read-modify-write cycle for single bit
* modification. Please refer to the reference manual for further details
* about bit-banding.
*
* Note
* This function is only atomic on cores which fully support bitbanding.
*
* Parameters
* addr Peripheral address location to read.
* bit Bit position to modify, 0-31.
*
* Return bit value read, 0 or 1.
*
******************************************************************************/
inline uint32_t bitband_get_peripheral(uint32_t addr, uint32_t bit)
{
uint32_t regval;
regval = EFM32_BITBAND_PER_BASE + ((addr-EFM32_PER_MEM_BASE)*32) + (bit*4);
return *((volatile uint32_t *)regval);
}
/******************************************************************************
* Name: bitband_set_sram
* Perform bit-band write operation on SRAM memory location.
*
* Description
* Bit-banding provides atomic read-modify-write cycle for single bit
* modification. Please refer to the reference manual for further details
* about bit-banding.
*
* Note
* This function is only atomic on cores which fully support bitbanding.
*
* Parameters
* addr SRAM address location to modify bit in.
* bit Bit position to modify, 0-31.
* val Value to set bit to, 0 or 1.
*
******************************************************************************/
inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val)
{
uint32_t regval;
regval = EFM32_BITBAND_RAM_BASE + ((addr-EFM32_RAM_MEM_BASE)*32) + (bit*4);
*((volatile uint32_t *)regval) = (uint32_t)val;
}
/******************************************************************************
* Name: bitband_get_sram
* Perform bit-band operation on SRAM memory location.
*
* Description
* This function reads a single bit from the RAM bit-band alias region.
* Bit-banding provides atomic read-modify-write cycle for single bit
* modification. Please refer to the reference manual for further details
* about bit-banding.
*
* Note
* This function is only atomic on cores which fully support bitbanding.
*
* Parameters
* addr Peripheral address location to read.
* bit Bit position to modify, 0-31.
*
* Return bit value read, 0 or 1.
*
******************************************************************************/
inline uint32_t bitband_get_sram(uint32_t addr, uint32_t bit)
{
uint32_t regval;
regval = EFM32_BITBAND_RAM_BASE + ((addr-EFM32_RAM_MEM_BASE)*32) + (bit*4);
return *((volatile uint32_t *)regval);
}
#endif
arch/arm/src/efm32/efm32_bitband.h
+81
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@@ -0,0 +1,81 @@
/*****************************************************************************
* arch/arm/src/efm32/efm32_bitband.h
*
* Copyright (C) 2015 Pierre-noel Bouteville . All rights reserved.
* Authors: Pierre-noel Bouteville <pnb990@gmail.com>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* 3. Neither the name NuttX nor the names of its contributors may be
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_EFM32_EFM32_BITBAND_H
#define __ARCH_ARM_SRC_EFM32_EFM32_BITBAND_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip/efm32_memorymap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Configuration ************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#if defined(CONFIG_EFM32_BITBAND)
inline void bitband_set_peripheral(uint32_t addr, uint32_t bit, uint32_t val);
inline uint32_t bitband_get_peripheral(uint32_t addr, uint32_t bit);
inline void bitband_set_sram(uint32_t addr, uint32_t bit, uint32_t val);
inline uint32_t bitband_get_sram(uint32_t addr, uint32_t bit);
#else
# define bitband_set_peripheral(addr,bit,val)\
modifyreg32(addr,~(1<<bit),(1<<bit))
# define bitband_get_peripheral(addr,bit) (((getreg32(addr)) >> bit) & 1)
# define bitband_set_sram(add,bit,val)\
modifyreg32(addr,~(1<<bit),(1<<bit))
# define bitband_get_sram(addr,bit) (((getreg32(addr)) >> bit) & 1)
#endif
#endif /* __ARCH_ARM_SRC_EFM32_EFM32_BITBAND_H */
arch/arm/src/efm32/efm32_flash.c
+849
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File diff suppressed because it is too large Load Diff
arch/arm/src/efm32/efm32_gpio.c
+5 -3
View File
@@ -171,9 +171,11 @@ static inline void efm32_setdrive(uintptr_t base, uint8_t pin, uint8_t drive)
* REVISIT: Is there any sane way to manage this for multiple pins in the port
* with different drive values?
*/
putreg32((uint32_t)drive << _GPIO_P_CTRL_DRIVEMODE_SHIFT,
base + EFM32_GPIO_Pn_CTRL_OFFSET);
if (drive != _GPIO_DRIVE_STANDARD)
{
putreg32((uint32_t)drive << _GPIO_P_CTRL_DRIVEMODE_SHIFT,
base + EFM32_GPIO_Pn_CTRL_OFFSET);
}
}
/************************************************************************************
arch/arm/src/efm32/efm32_gpio.h
+19 -5
View File
@@ -141,15 +141,15 @@
*/
#define GPIO_DRIVE_SHIFT (9) /* Bits 9-10: Output drive strength */
#define GPIO_DRIVE_MASK (3 << GPIO_MODE_SHIFT)
#define GPIO_DRIVE_MASK (3 << GPIO_DRIVE_SHIFT)
# define _GPIO_DRIVE_STANDARD (0) /* 6 mA drive current */
# define _GPIO_DRIVE_LOWEST (1) /* 0.5 mA drive current */
# define _GPIO_DRIVE_HIGH (2) /* 20 mA drive current */
# define _GPIO_DRIVE_LOW (3) /* 2 mA drive current */
# define GPIO_DRIVE_STANDARD (_GPIO_DRIVE_STANDARD << GPIO_MODE_SHIFT)
# define GPIO_DRIVE_LOWEST (_GPIO_DRIVE_LOWEST << GPIO_MODE_SHIFT)
# define GPIO_DRIVE_HIGH (_GPIO_DRIVE_HIGH << GPIO_MODE_SHIFT)
# define GPIO_DRIVE_LOW (_GPIO_DRIVE_LOW << GPIO_MODE_SHIFT)
# define GPIO_DRIVE_STANDARD (_GPIO_DRIVE_STANDARD << GPIO_DRIVE_SHIFT)
# define GPIO_DRIVE_LOWEST (_GPIO_DRIVE_LOWEST << GPIO_DRIVE_SHIFT)
# define GPIO_DRIVE_HIGH (_GPIO_DRIVE_HIGH << GPIO_DRIVE_SHIFT)
# define GPIO_DRIVE_LOW (_GPIO_DRIVE_LOW << GPIO_DRIVE_SHIFT)
/* Interrupt Mode (Input only):
*
@@ -328,6 +328,20 @@ void efm32_gpioirqdisable(int irq);
# define efm32_gpioirqdisable(irq)
#endif
/************************************************************************************
* Name: efm32_gpioirqclear
*
* Description:
* clear the interrupt for specified PIO IRQ
*
************************************************************************************/
#ifdef CONFIG_EFM32_GPIO_IRQ
void efm32_gpioirqclear(int irq);
#else
# define efm32_gpioirqclear(irq)
#endif
/************************************************************************************
* Function: efm32_dumpgpio
*
arch/arm/src/efm32/efm32_gpioirq.c
+47 -6
View File
@@ -49,6 +49,7 @@
#include "up_arch.h"
#include "chip/efm32_gpio.h"
#include "efm32_gpio.h"
#include "efm32_bitband.h"
#ifdef CONFIG_EFM32_GPIO_IRQ
@@ -270,20 +271,24 @@ void efm32_gpioirq(gpio_pinset_t pinset)
void efm32_gpioirqenable(int irq)
{
irqstate_t flags;
uint32_t regval;
uint32_t bit;
if (irq >= EFM32_IRQ_EXTI0 && irq <= EFM32_IRQ_EXTI15)
{
/* Enable the interrupt associated with the pin */
#ifndef CONFIG_EFM32_BITBAND
irqstate_t flags;
uint32_t regval;
uint32_t bit;
bit = ((uint32_t)1 << (irq - EFM32_IRQ_EXTI0));
flags = irqsave();
regval = getreg32(EFM32_GPIO_IEN);
regval |= bit;
putreg32(regval, EFM32_GPIO_IEN);
irqrestore(flags);
#else
bitband_set_peripheral(EFM32_GPIO_IEN,(irq - EFM32_IRQ_EXTI0),1);
#endif
}
}
@@ -297,20 +302,56 @@ void efm32_gpioirqenable(int irq)
void efm32_gpioirqdisable(int irq)
{
irqstate_t flags;
uint32_t regval;
uint32_t bit;
if (irq >= EFM32_IRQ_EXTI0 && irq <= EFM32_IRQ_EXTI15)
{
/* Enable the interrupt associated with the pin */
#ifndef CONFIG_EFM32_BITBAND
irqstate_t flags;
uint32_t regval;
uint32_t bit;
bit = ((uint32_t)1 << (irq - EFM32_IRQ_EXTI0));
flags = irqsave();
regval = getreg32(EFM32_GPIO_IEN);
regval &= ~bit;
putreg32(regval, EFM32_GPIO_IEN);
irqrestore(flags);
#else
bitband_set_peripheral(EFM32_GPIO_IEN,(irq - EFM32_IRQ_EXTI0),0);
#endif
}
}
/************************************************************************************
* Name: efm32_gpioirqclear
*
* Description:
* Disable the interrupt for specified PIO IRQ
*
************************************************************************************/
void efm32_gpioirqclear(int irq)
{
if (irq >= EFM32_IRQ_EXTI0 && irq <= EFM32_IRQ_EXTI15)
{
/* Enable the interrupt associated with the pin */
#ifndef CONFIG_EFM32_BITBAND
irqstate_t flags;
uint32_t regval;
uint32_t bit;
bit = ((uint32_t)1 << (irq - EFM32_IRQ_EXTI0));
flags = irqsave();
regval = getreg32(EFM32_GPIO_IFC);
regval |= bit;
putreg32(regval, EFM32_GPIO_IFC);
irqrestore(flags);
#else
bitband_set_peripheral(EFM32_GPIO_IFC,(irq - EFM32_IRQ_EXTI0),1);
#endif
}
}
arch/arm/src/efm32/efm32_i2c.c
+66 -32
View File
@@ -212,6 +212,7 @@ struct efm32_trace_s
uint32_t i2c_reg_state; /* I2C register I2Cx_STATES */
uint32_t i2c_reg_if; /* I2C register I2Cx_IF */
uint32_t count; /* Interrupt count when status change */
int dcnt; /* Interrupt count when status change */
uint32_t time; /* First of event or first status */
};
@@ -242,7 +243,7 @@ struct efm32_i2c_priv_s
sem_t sem_isr; /* Interrupt wait semaphore */
#endif
volatile uint8_t result; /* result of transfer */
volatile int8_t result; /* result of transfer */
uint8_t i2c_state; /* i2c state machine */
uint32_t i2c_reg_if; /* Current state of I2Cx_IF register. */
@@ -346,7 +347,9 @@ static int efm32_i2c_transfer(FAR struct i2c_dev_s *dev,
FAR struct i2c_msg_s *msgs, int count);
#endif /* CONFIG_I2C_TRANSFER */
#ifdef CONFIG_I2C_TRACE
static const char *efm32_i2c_state_str(int i2c_state);
#endif
/*******************************************************************************
* Private Data
@@ -485,6 +488,7 @@ static inline void efm32_i2c_modifyreg(FAR struct efm32_i2c_priv_s *priv,
*
******************************************************************************/
#ifdef CONFIG_I2C_TRACE
static const char *efm32_i2c_state_str(int i2c_state)
{
switch (i2c_state)
@@ -515,6 +519,7 @@ static const char *efm32_i2c_state_str(int i2c_state)
return "Unknown state!";
}
}
#endif
/*******************************************************************************
* Name: efm32_i2c_sem_wait
@@ -779,6 +784,7 @@ static void efm32_i2c_tracenew(FAR struct efm32_i2c_priv_s *priv)
if ((trace->count == 0) ||
(priv->i2c_reg_if != trace->i2c_reg_if) ||
(priv->i2c_reg_state != trace->i2c_reg_state) ||
(priv->dcnt != trace->dcnt) ||
(priv->i2c_state != trace->i2c_state))
{
/* Yes.. Was it the states changed? */
@@ -804,6 +810,7 @@ static void efm32_i2c_tracenew(FAR struct efm32_i2c_priv_s *priv)
trace->i2c_reg_state = priv->i2c_reg_state;
trace->i2c_reg_if = priv->i2c_reg_if;
trace->count = 1;
trace->dcnt = priv->dcnt;
trace->time = clock_systimer();
}
else
@@ -821,15 +828,15 @@ static void efm32_i2c_tracedump(FAR struct efm32_i2c_priv_s *priv)
syslog(LOG_DEBUG, "Elapsed time: %d\n", clock_systimer() - priv->start_time);
for (i = 0; i <= priv->tndx; i++)
for (i = 0; i < priv->tndx; i++)
{
trace = &priv->trace[i];
syslog(LOG_DEBUG,
"%2d. I2Cx_STATE: %08x I2Cx_PENDING: %08x COUNT: %3d "
"STATE: %s(%2d) PARM: %08x TIME: %d\n",
i + 1, trace->i2c_reg_state, trace->i2c_reg_if, trace->count,
efm32_i2c_state_str(trace->i2c_state), trace->i2c_state,
trace->time - priv->start_time);
"%2d. I2Cx_STATE: %08x I2Cx_PENDING: %08x dcnt %3d COUNT: %3d "
"STATE: %s(%2d) TIME: %d\n",
i + 1, trace->i2c_reg_state, trace->i2c_reg_if, trace->dcnt,
trace->count, efm32_i2c_state_str(trace->i2c_state),
trace->i2c_state, trace->time - priv->start_time);
}
}
#endif /* CONFIG_I2C_TRACE */
@@ -1233,19 +1240,22 @@ static int efm32_i2c_isr(struct efm32_i2c_priv_s *priv)
efm32_i2c_putreg(priv, EFM32_I2C_CMD_OFFSET, I2C_CMD_STOP);
}
else if (priv->dcnt == 1)
{
/* If there is only one byte to receive we need to transmit
* the NACK now, before the stop.
*/
efm32_i2c_putreg(priv, EFM32_I2C_CMD_OFFSET, I2C_CMD_NACK);
}
else
{
/* Send ACK and wait for next byte */
efm32_i2c_putreg(priv, EFM32_I2C_CMD_OFFSET, I2C_CMD_ACK);
if (priv->dcnt == 1)
{
/* If there is more than one byte to receive and this is
* the next to last byte we need to transmit the NACK
* now, before receiving the last byte.
*/
efm32_i2c_putreg(priv,EFM32_I2C_CMD_OFFSET,I2C_CMD_NACK);
}
}
}
goto done;
@@ -1595,23 +1605,47 @@ static int efm32_i2c_process(FAR struct i2c_dev_s *dev,
efm32_i2c_putreg(priv, EFM32_I2C_CMD_OFFSET, I2C_CMD_ABORT);
}
else
{
/* Check for error status conditions */
/* Check for error status conditions */
#if 0
/* Arbitration Lost (master mode) */
errval = EAGAIN;
/* Acknowledge Failure */
errval = ENXIO;
/* Overrun/Underrun */
errval = EIO;
/* PEC Error in reception */
errval = EPROTO;
/* Timeout or Tlow Error */
errval = ETIME;
/* I2C Bus is for some reason busy */
errval = EBUSY;
#endif
switch(priv->result)
{
/* Arbitration lost during transfer. */
case I2CRESULT_ARBLOST:
errval = EAGAIN;
break;
/* NACK received during transfer. */
case I2CRESULT_NACK:
errval = ENXIO;
break;
/* SW fault. */
case I2CRESULT_SWFAULT:
errval = EIO;
break;
/* Usage fault. */
case I2CRESULT_USAGEFAULT:
errval = EINTR;
break;
/* Bus error during transfer (misplaced START/STOP).
* I2C Bus is for some reason busy
*/
case I2CRESULT_BUSERR:
errval = EBUSY;
break;
}
}
/* Dump the trace result */
@@ -1738,7 +1772,7 @@ FAR struct i2c_dev_s *up_i2cinitialize(int port)
struct efm32_i2c_priv_s *priv = NULL; /* Private data of device with multiple
* instances */
struct efm32_i2c_inst_s *inst = NULL; /* Device, single instance */
int irqs;
irqstate_t irqs;
/* Get I2C private structure */
@@ -1801,7 +1835,7 @@ FAR struct i2c_dev_s *up_i2cinitialize(int port)
int up_i2cuninitialize(FAR struct i2c_dev_s *dev)
{
int irqs;
irqstate_t irqs;
ASSERT(dev);
arch/arm/src/efm32/efm32_rmu.c
+4 -4
View File
@@ -80,13 +80,13 @@ typedef struct
static efm32_reset_cause_list_t efm32_reset_cause_list[] =
{
{
0x0001, // 0bXXXX XXXX XXXX XXX1
0x0001, // 0bXXXX XXXX XXXX XXX1
0x0001, //0bXXXX XXXX XXXX XXX1
0x0001, //0bXXXX XXXX XXXX XXX1
"A Power-on Reset has been performed. X bits are don't care."
},
{
0x0002, // 0bXXXX XXXX 0XXX XX10
0x0003, // 0bXXXX XXXX 1XXX XX11
0x0002, //0bXXXX XXXX 0XXX XX10
0x0003, //0bXXXX XXXX 1XXX XX11
"A Brown-out has been detected on the unregulated power."
},
{