mirror of
https://github.com/apache/nuttx.git
synced 2026-05-19 20:06:24 +08:00
H5 with NSH support for Nucleo-H563ZI.
Made fixes to issues from CI. Nxstyle and defconfig syntax. This is a combination of 6 commits. Adding STM32H5 arch files. With comments addressed. Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board. Remove board/docs changes for PR update. Squash commits into one for PR guideline conformity. trying to fix build issues Fix format from review Nucleo-H563ZI support for NSH. Created stm32h5 directory to add support for the H5 chip, and used a Nucleo-H563ZI dev board during development. The goal was to get a working nutshell through the STLink connector on the board. Fix switch default case placement. NXstyle fixes Renaming files rename stm32h5_gpio.x files rename h5 hsi48 files Rename h5 idle file rename stm32h5_irq.c Rename some rcc functions and stm32h5_rcc.c rename stm32h5_rcc.h Rename stm32h5_pwr.x lowputc renames timerisr renames uart renamed rename serial file rename start Turn off the defines that enable DMA on serial remove DMA Kconfig options Remove H5 documentation. Will add in a future PR. Fix styling and defconfig improper syntax.
This commit is contained in:
stbenn
Xiang Xiao
File diff suppressed because it is too large
Load Diff
@@ -26,3 +26,26 @@ HEAD_ASRC =
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# Common ARM and Cortex-M4 files (copied from stm32/Make.defs)
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include armv8-m/Make.defs
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# Required STM32H5 files
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CHIP_ASRCS =
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CHIP_CSRCS = stm32_gpio.c
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CHIP_CSRCS += stm32_irq.c stm32_lowputc.c stm32_rcc.c
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CHIP_CSRCS += stm32_serial.c stm32_start.c
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CHIP_CSRCS += stm32_pwr.c stm32_timerisr.c
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CHIP_CSRCS += stm32_lse.c stm32_lsi.c
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ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
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CHIP_CSRCS += stm32_idle.c
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endif
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ifeq ($(CONFIG_TIMER),y)
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CHIP_CSRCS += stm32h5_tim_lowerhalf.c
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endif
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# Required chip type specific files
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ifeq ($(CONFIG_STM32H5_STM32H5XXXX),y)
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CHIP_CSRCS += stm32h5xx_rcc.c
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endif
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@@ -36,5 +36,10 @@
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#include "chip.h"
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#include "stm32_flash.h"
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#include "stm32_dbgmcu.h"
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#include "stm32_gpio.h"
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#include "stm32_pwr.h"
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#include "stm32_rcc.h"
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#include "stm32_uart.h"
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#include "stm32_lowputc.h"
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#endif /* __ARCH_ARM_SRC_STM32H5_STM32_H */
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@@ -0,0 +1,38 @@
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/****************************************************************************
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* arch/arm/src/stm32h5/stm32_dbgmcu.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
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||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32H5_STM32_DBGMCU_H
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#define __ARCH_ARM_SRC_STM32H5_STM32_DBGMCU_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#if defined(CONFIG_STM32H5_STM32H5XXXX)
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# include "hardware/stm32_dbgmcu.h"
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#else
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# error "Unsupported STM32H5 chip"
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#endif
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#endif /* __ARCH_ARM_SRC_STM32H5_STM32_DBGMCU_H */
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@@ -0,0 +1,397 @@
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/****************************************************************************
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* arch/arm/src/stm32h5/stm32_gpio.c
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
|
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
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* under the License.
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||||
*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <errno.h>
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#include <debug.h>
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#include <arch/irq.h>
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#include <arch/stm32h5/chip.h>
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#include "arm_internal.h"
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#include "chip.h"
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#include "stm32_gpio.h"
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* Base addresses for each GPIO block */
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const uint32_t g_gpiobase[STM32H5_NPORTS] =
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{
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#if STM32H5_NPORTS > 0
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STM32_GPIOA_BASE,
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#endif
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#if STM32H5_NPORTS > 1
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STM32_GPIOB_BASE,
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#endif
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#if STM32H5_NPORTS > 2
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STM32_GPIOC_BASE,
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#endif
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#if STM32H5_NPORTS > 3
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STM32_GPIOD_BASE,
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#endif
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#if STM32H5_NPORTS > 4
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STM32_GPIOE_BASE,
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#endif
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#if STM32H5_NPORTS > 5
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STM32_GPIOF_BASE,
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#endif
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#if STM32H5_NPORTS > 6
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STM32_GPIOG_BASE,
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#endif
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#if STM32H5_NPORTS > 7
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STM32_GPIOH_BASE,
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#endif
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Function: stm32_gpioinit
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*
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* Description:
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* Based on configuration within the .config file, it does:
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* - Remaps positions of alternative functions.
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*
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* Typically called from stm32h5_start().
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*
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* Assumptions:
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* This function is called early in the initialization sequence so that
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* no mutual exclusion is necessary.
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*
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****************************************************************************/
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void stm32_gpioinit(void)
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{
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}
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/****************************************************************************
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* Name: stm32_configgpio
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*
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* Description:
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* Configure a GPIO pin based on bit-encoded description of the pin.
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* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
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* function, it must be unconfigured with stm32_unconfiggpio() with
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* the same cfgset first before it can be set to non-alternative function.
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*
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* Returned Value:
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* OK on success
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* A negated errno value on invalid port, or when pin is locked as ALT
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* function.
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*
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* To-Do: Auto Power Enable
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****************************************************************************/
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int stm32_configgpio(uint32_t cfgset)
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{
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uintptr_t base;
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uint32_t regval;
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uint32_t setting;
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unsigned int regoffset;
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unsigned int port;
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unsigned int pin;
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unsigned int pos;
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unsigned int pinmode;
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irqstate_t flags;
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/* Verify that this hardware supports the select GPIO port */
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port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
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if (port >= STM32H5_NPORTS)
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{
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return -EINVAL;
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}
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/* Get the port base address */
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base = g_gpiobase[port];
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/* Get the pin number and select the port configuration register for that
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* pin
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*/
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pin = (cfgset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
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/* Set up the mode register (and remember whether the pin mode) */
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switch (cfgset & GPIO_MODE_MASK)
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{
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default:
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case GPIO_INPUT: /* Input mode */
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pinmode = GPIO_MODER_INPUT;
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break;
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case GPIO_OUTPUT: /* General purpose output mode */
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/* Set the initial output value */
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stm32_gpiowrite(cfgset, (cfgset & GPIO_OUTPUT_SET) != 0);
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pinmode = GPIO_MODER_OUTPUT;
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break;
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case GPIO_ALT: /* Alternate function mode */
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pinmode = GPIO_MODER_ALT;
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break;
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case GPIO_ANALOG: /* Analog mode */
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pinmode = GPIO_MODER_ANALOG;
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break;
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}
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/* Interrupts must be disabled from here on out so that we have mutually
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* exclusive access to all of the GPIO configuration registers.
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*/
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flags = enter_critical_section();
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/* Now apply the configuration to the mode register */
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regval = getreg32(base + STM32_GPIO_MODER_OFFSET);
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regval &= ~GPIO_MODER_MASK(pin);
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regval |= ((uint32_t)pinmode << GPIO_MODER_SHIFT(pin));
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putreg32(regval, base + STM32_GPIO_MODER_OFFSET);
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/* Set up the pull-up/pull-down configuration (all but analog pins) */
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setting = GPIO_PUPDR_NONE;
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if (pinmode != GPIO_MODER_ANALOG)
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{
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switch (cfgset & GPIO_PUPD_MASK)
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{
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default:
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case GPIO_FLOAT: /* No pull-up, pull-down */
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break;
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case GPIO_PULLUP: /* Pull-up */
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setting = GPIO_PUPDR_PULLUP;
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break;
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case GPIO_PULLDOWN: /* Pull-down */
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setting = GPIO_PUPDR_PULLDOWN;
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break;
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}
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}
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regval = getreg32(base + STM32_GPIO_PUPDR_OFFSET);
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regval &= ~GPIO_PUPDR_MASK(pin);
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regval |= (setting << GPIO_PUPDR_SHIFT(pin));
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putreg32(regval, base + STM32_GPIO_PUPDR_OFFSET);
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/* Set the alternate function (Only alternate function pins) */
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if (pinmode == GPIO_MODER_ALT)
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{
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setting = (cfgset & GPIO_AF_MASK) >> GPIO_AF_SHIFT;
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}
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else
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{
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setting = 0;
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}
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if (pin < 8)
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{
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regoffset = STM32_GPIO_AFRL_OFFSET;
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pos = pin;
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}
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else
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{
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regoffset = STM32_GPIO_AFRH_OFFSET;
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pos = pin - 8;
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}
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regval = getreg32(base + regoffset);
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regval &= ~GPIO_AFR_MASK(pos);
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regval |= (setting << GPIO_AFR_SHIFT(pos));
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putreg32(regval, base + regoffset);
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/* Set speed (Only outputs and alternate function pins) */
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if (pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT)
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{
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switch (cfgset & GPIO_SPEED_MASK)
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{
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||||
default:
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case GPIO_SPEED_2MHZ: /* 2 MHz Low speed output */
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setting = GPIO_OSPEED_2MHZ;
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break;
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|
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case GPIO_SPEED_25MHZ: /* 25 MHz Medium speed output */
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setting = GPIO_OSPEED_25MHZ;
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break;
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case GPIO_SPEED_50MHZ: /* 50 MHz High speed output */
|
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setting = GPIO_OSPEED_50MHZ;
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||||
break;
|
||||
|
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case GPIO_SPEED_100MHZ: /* 100 MHz Very High speed output */
|
||||
setting = GPIO_OSPEED_100MHZ;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
setting = 0;
|
||||
}
|
||||
|
||||
regval = getreg32(base + STM32_GPIO_OSPEED_OFFSET);
|
||||
regval &= ~GPIO_OSPEED_MASK(pin);
|
||||
regval |= (setting << GPIO_OSPEED_SHIFT(pin));
|
||||
putreg32(regval, base + STM32_GPIO_OSPEED_OFFSET);
|
||||
|
||||
/* Set push-pull/open-drain (Only outputs and alternate function pins) */
|
||||
|
||||
regval = getreg32(base + STM32_GPIO_OTYPER_OFFSET);
|
||||
setting = GPIO_OTYPER_OD(pin);
|
||||
|
||||
if ((pinmode == GPIO_MODER_OUTPUT || pinmode == GPIO_MODER_ALT) &&
|
||||
(cfgset & GPIO_OPENDRAIN) != 0)
|
||||
{
|
||||
regval |= setting;
|
||||
}
|
||||
else
|
||||
{
|
||||
regval &= ~setting;
|
||||
}
|
||||
|
||||
putreg32(regval, base + STM32_GPIO_OTYPER_OFFSET);
|
||||
|
||||
leave_critical_section(flags);
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_unconfiggpio
|
||||
*
|
||||
* Description:
|
||||
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
|
||||
* it into default HiZ state (and possibly mark it's unused) and unlock it
|
||||
* whether it was previously selected as alternative function
|
||||
* (GPIO_ALT|GPIO_CNF_AFPP|...).
|
||||
*
|
||||
* This is a safety function and prevents hardware from shocks, as
|
||||
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
|
||||
* while it should operate in PWM mode could produce excessive on-board
|
||||
* currents and trigger over-current/alarm function.
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success
|
||||
* A negated errno value on invalid port
|
||||
*
|
||||
* To-Do: Auto Power Disable
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_unconfiggpio(uint32_t cfgset)
|
||||
{
|
||||
/* Reuse port and pin number and set it to default HiZ INPUT */
|
||||
|
||||
cfgset &= GPIO_PORT_MASK | GPIO_PIN_MASK;
|
||||
cfgset |= GPIO_INPUT | GPIO_FLOAT;
|
||||
|
||||
/* To-Do: Mark its unuse for automatic power saving options */
|
||||
|
||||
return stm32_configgpio(cfgset);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_gpiowrite(uint32_t pinset, bool value)
|
||||
{
|
||||
uint32_t base;
|
||||
uint32_t bit;
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < STM32H5_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
base = g_gpiobase[port];
|
||||
|
||||
/* Get the pin number */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
|
||||
/* Set or clear the output on the pin */
|
||||
|
||||
if (value)
|
||||
{
|
||||
bit = GPIO_BSRR_SET(pin);
|
||||
}
|
||||
else
|
||||
{
|
||||
bit = GPIO_BSRR_RESET(pin);
|
||||
}
|
||||
|
||||
putreg32(bit, base + STM32_GPIO_BSRR_OFFSET);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool stm32_gpioread(uint32_t pinset)
|
||||
{
|
||||
uint32_t base;
|
||||
unsigned int port;
|
||||
unsigned int pin;
|
||||
|
||||
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
|
||||
if (port < STM32H5_NPORTS)
|
||||
{
|
||||
/* Get the port base address */
|
||||
|
||||
base = g_gpiobase[port];
|
||||
|
||||
/* Get the pin number and return the input state of that pin */
|
||||
|
||||
pin = (pinset & GPIO_PIN_MASK) >> GPIO_PIN_SHIFT;
|
||||
return ((getreg32(base + STM32_GPIO_IDR_OFFSET) & (1 << pin)) != 0);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -0,0 +1,326 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_gpio.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_GPIO_H
|
||||
#define __ARCH_ARM_SRC_STM32H5_STM32_GPIO_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
# include <stdbool.h>
|
||||
#endif
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <arch/stm32h5/chip.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32H5_STM32H5XXXX)
|
||||
# include "hardware/stm32_gpio.h"
|
||||
#else
|
||||
# error "Unsupported STM32H5 chip"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-Processor Declarations
|
||||
****************************************************************************/
|
||||
|
||||
/* Bit-encoded input to stm32_configgpio() */
|
||||
|
||||
/* Each port bit of the general-purpose I/O (GPIO) ports can be individually
|
||||
* configured by software in several modes:
|
||||
*
|
||||
* - Input floating
|
||||
* - Input pull-up
|
||||
* - Input-pull-down
|
||||
* - Output open-drain with pull-up or pull-down capability
|
||||
* - Output push-pull with pull-up or pull-down capability
|
||||
* - Alternate function push-pull with pull-up or pull-down capability
|
||||
* - Alternate function open-drain with pull-up or pull-down capability
|
||||
* - Analog
|
||||
*
|
||||
* 20-bit Encoding: 1111 1111 1100 0000 0000
|
||||
* 9876 5432 1098 7654 3210
|
||||
* ---- ---- ---- ---- ----
|
||||
* Inputs: MMUU .... ...X PPPP BBBB
|
||||
* Outputs: MMUU .... FFOV PPPP BBBB
|
||||
* Alternate Functions: MMUU AAAA FFO. PPPP BBBB
|
||||
* Analog: MM.. .... .... PPPP BBBB
|
||||
*/
|
||||
|
||||
/* Mode:
|
||||
*
|
||||
* 1111 1111 1100 0000 0000
|
||||
* 9876 5432 1098 7654 3210
|
||||
* ---- ---- ---- ---- ----
|
||||
* MM.. .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_MODE_SHIFT (18) /* Bits 18-19: GPIO port mode */
|
||||
#define GPIO_MODE_MASK (3 << GPIO_MODE_SHIFT)
|
||||
# define GPIO_INPUT (0 << GPIO_MODE_SHIFT) /* Input mode */
|
||||
# define GPIO_OUTPUT (1 << GPIO_MODE_SHIFT) /* General purpose output mode */
|
||||
# define GPIO_ALT (2 << GPIO_MODE_SHIFT) /* Alternate function mode */
|
||||
# define GPIO_ANALOG (3 << GPIO_MODE_SHIFT) /* Analog mode */
|
||||
|
||||
/* Input/output pull-ups/downs (not used with analog):
|
||||
*
|
||||
* 1111 1111 1100 0000 0000
|
||||
* 9876 5432 1098 7654 3210
|
||||
* ---- ---- ---- ---- ----
|
||||
* ..UU .... .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_PUPD_SHIFT (16) /* Bits 16-17: Pull-up/pull down */
|
||||
#define GPIO_PUPD_MASK (3 << GPIO_PUPD_SHIFT)
|
||||
# define GPIO_FLOAT (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */
|
||||
# define GPIO_PULLUP (1 << GPIO_PUPD_SHIFT) /* Pull-up */
|
||||
# define GPIO_PULLDOWN (2 << GPIO_PUPD_SHIFT) /* Pull-down */
|
||||
|
||||
/* Alternate Functions:
|
||||
*
|
||||
* 1111 1111 1100 0000 0000
|
||||
* 9876 5432 1098 7654 3210
|
||||
* ---- ---- ---- ---- ----
|
||||
* .... AAAA .... .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_AF_SHIFT (12) /* Bits 12-15: Alternate function */
|
||||
#define GPIO_AF_MASK (15 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF(n) ((n) << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF0 (0 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF1 (1 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF2 (2 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF3 (3 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF4 (4 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF5 (5 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF6 (6 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF7 (7 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF8 (8 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF9 (9 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF10 (10 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF11 (11 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF12 (12 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF13 (13 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF14 (14 << GPIO_AF_SHIFT)
|
||||
# define GPIO_AF15 (15 << GPIO_AF_SHIFT)
|
||||
|
||||
/* Output/Alt function frequency selection:
|
||||
*
|
||||
* 1111 1111 1100 0000 0000
|
||||
* 9876 5432 1098 7654 3210
|
||||
* ---- ---- ---- ---- ----
|
||||
* .... .... FF.. .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_SPEED_SHIFT (10) /* Bits 10-11: GPIO frequency selection */
|
||||
#define GPIO_SPEED_MASK (3 << GPIO_SPEED_SHIFT)
|
||||
# define GPIO_SPEED_2MHZ (0 << GPIO_SPEED_SHIFT) /* 2 MHz Low speed output */
|
||||
# define GPIO_SPEED_25MHZ (1 << GPIO_SPEED_SHIFT) /* 25 MHz Medium speed output */
|
||||
# define GPIO_SPEED_50MHZ (2 << GPIO_SPEED_SHIFT) /* 50 MHz High speed output */
|
||||
# define GPIO_SPEED_100MHZ (3 << GPIO_SPEED_SHIFT) /* 100 MHz Very High speed output */
|
||||
|
||||
/* Output/Alt function type selection:
|
||||
*
|
||||
* 1111 1111 1100 0000 0000
|
||||
* 9876 5432 1098 7654 3210
|
||||
* ---- ---- ---- ---- ----
|
||||
* .... .... ..O. .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_OPENDRAIN (1 << 9) /* Bit9: 1=Open-drain output */
|
||||
#define GPIO_PUSHPULL (0) /* Bit9: 0=Push-pull output */
|
||||
|
||||
/* If the pin is a GPIO digital output, then this identifies the initial
|
||||
* output value. If the pin is an input, this bit is overloaded to provide
|
||||
* the qualifier to distinguish input pull-up and -down:
|
||||
*
|
||||
* 1111 1111 1100 0000 0000
|
||||
* 9876 5432 1098 7654 3210
|
||||
* ---- ---- ---- ---- ----
|
||||
* .... .... ...V .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_OUTPUT_SET (1 << 8) /* Bit 8: If output, initial value of output */
|
||||
#define GPIO_OUTPUT_CLEAR (0)
|
||||
|
||||
/* External interrupt selection (GPIO inputs only):
|
||||
*
|
||||
* 1111 1111 1100 0000 0000
|
||||
* 9876 5432 1098 7654 3210
|
||||
* ---- ---- ---- ---- ----
|
||||
* .... .... ...X .... ....
|
||||
*/
|
||||
|
||||
#define GPIO_EXTI (1 << 8) /* Bit 8: Configure as EXTI interrupt */
|
||||
|
||||
/* This identifies the GPIO port:
|
||||
*
|
||||
* 1111 1111 1100 0000 0000
|
||||
* 9876 5432 1098 7654 3210
|
||||
* ---- ---- ---- ---- ----
|
||||
* .... .... .... PPPP ....
|
||||
*/
|
||||
|
||||
#define GPIO_PORT_SHIFT (4) /* Bit 4-7: Port number */
|
||||
#define GPIO_PORT_MASK (15 << GPIO_PORT_SHIFT)
|
||||
# define GPIO_PORTA (0 << GPIO_PORT_SHIFT) /* GPIOA */
|
||||
# define GPIO_PORTB (1 << GPIO_PORT_SHIFT) /* GPIOB */
|
||||
# define GPIO_PORTC (2 << GPIO_PORT_SHIFT) /* GPIOC */
|
||||
# define GPIO_PORTD (3 << GPIO_PORT_SHIFT) /* GPIOD */
|
||||
# define GPIO_PORTE (4 << GPIO_PORT_SHIFT) /* GPIOE */
|
||||
# define GPIO_PORTF (5 << GPIO_PORT_SHIFT) /* GPIOF */
|
||||
# define GPIO_PORTG (6 << GPIO_PORT_SHIFT) /* GPIOG */
|
||||
# define GPIO_PORTH (7 << GPIO_PORT_SHIFT) /* GPIOH */
|
||||
|
||||
/* This identifies the bit in the port:
|
||||
*
|
||||
* 1111 1111 1100 0000 0000
|
||||
* 9876 5432 1098 7654 3210
|
||||
* ---- ---- ---- ---- ----
|
||||
* .... .... .... .... BBBB
|
||||
*/
|
||||
|
||||
#define GPIO_PIN_SHIFT (0) /* Bits 0-3: GPIO number: 0-15 */
|
||||
#define GPIO_PIN_MASK (15 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN0 (0 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN1 (1 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN2 (2 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN3 (3 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN4 (4 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN5 (5 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN6 (6 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN7 (7 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN8 (8 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN9 (9 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN10 (10 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN11 (11 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN12 (12 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN13 (13 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN14 (14 << GPIO_PIN_SHIFT)
|
||||
# define GPIO_PIN15 (15 << GPIO_PIN_SHIFT)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* Base addresses for each GPIO block */
|
||||
|
||||
EXTERN const uint32_t g_gpiobase[STM32H5_NPORTS];
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_configgpio
|
||||
*
|
||||
* Description:
|
||||
* Configure a GPIO pin based on bit-encoded description of the pin.
|
||||
* Once it is configured as Alternative (GPIO_ALT|GPIO_CNF_AFPP|...)
|
||||
* function, it must be unconfigured with stm32_unconfiggpio() with
|
||||
* the same cfgset first before it can be set to non-alternative function.
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success
|
||||
* ERROR on invalid port, or when pin is locked as ALT function.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_configgpio(uint32_t cfgset);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_unconfiggpio
|
||||
*
|
||||
* Description:
|
||||
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
|
||||
* it into default HiZ state (and possibly mark it's unused) and unlock it
|
||||
* whether it was previously selected as alternative function
|
||||
* (GPIO_ALT|GPIO_CNF_AFPP|...).
|
||||
*
|
||||
* This is a safety function and prevents hardware from shocks, as
|
||||
* unexpected write to the Timer Channel Output GPIO to fixed '1' or '0'
|
||||
* while it should operate in PWM mode could produce excessive on-board
|
||||
* currents and trigger over-current/alarm function.
|
||||
*
|
||||
* Returned Value:
|
||||
* OK on success
|
||||
* ERROR on invalid port
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_unconfiggpio(uint32_t cfgset);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_gpiowrite
|
||||
*
|
||||
* Description:
|
||||
* Write one or zero to the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_gpiowrite(uint32_t pinset, bool value);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_gpioread
|
||||
*
|
||||
* Description:
|
||||
* Read one or zero from the selected GPIO pin
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool stm32_gpioread(uint32_t pinset);
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_gpioinit
|
||||
*
|
||||
* Description:
|
||||
* Based on configuration within the .config file, it does:
|
||||
* - Remaps positions of alternative functions.
|
||||
*
|
||||
* Typically called from stm32h5_start().
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_gpioinit(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_GPIO_H */
|
||||
@@ -0,0 +1,169 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_hsi48.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_rcc.h"
|
||||
#include "hardware/stm32_crs.h"
|
||||
|
||||
#include "stm32_hsi48.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32H5_HAVE_HSI48
|
||||
/****************************************************************************
|
||||
* Name: stm32h5_enable_hsi48
|
||||
*
|
||||
* Description:
|
||||
* The HSI48
|
||||
* clock signal is generated from an internal 48 MHz RC oscillator and can
|
||||
* be used directly as a system clock or divided and be used as PLL input.
|
||||
*
|
||||
* The internal 48MHz RC oscillator is mainly dedicated to provide a high
|
||||
* precision clock to the USB peripheral by means of a special Clock
|
||||
* Recovery System (CRS) circuitry, which could use the USB SOF signal or
|
||||
* the LSE or an external signal to automatically adjust the oscillator
|
||||
* frequency on-fly, in a very small steps. This oscillator can also be
|
||||
* used as a system clock source when the system is in run mode; it will
|
||||
* be disabled as soon as the system enters in Stop or Standby mode. When
|
||||
* the CRS is not used, the HSI48 RC oscillator runs on its default
|
||||
* frequency which is subject to manufacturing process variations.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Identifies the syncrhonization source for the HSI48. When used as the
|
||||
* USB source clock, this must be set to SYNCSRC_USB.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h5_enable_hsi48(enum syncsrc_e syncsrc)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Enable the HSI48 clock.
|
||||
*
|
||||
* The HSI48 RC can be switched on and off using the HSI48ON bit in the
|
||||
* Clock control register (RCC_CRRCR).
|
||||
*
|
||||
* The USB clock may be derived from either the PLL clock or from the
|
||||
* HSI48 clock. This oscillator will be also automatically enabled (by
|
||||
* hardware forcing HSI48ON bit to one) as soon as it is chosen as a clock
|
||||
* source for the USB and the peripheral is
|
||||
* enabled.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval |= RCC_CR_HSI48ON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Wait for the HSI48 clock to stabilize */
|
||||
|
||||
while ((getreg32(STM32_RCC_CRRCR) & RCC_CRRCR_HSI48RDY) == 0);
|
||||
|
||||
/* Return if no synchronization */
|
||||
|
||||
if (syncsrc == SYNCSRC_NONE)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/* The CRS synchronization (SYNC) source, selectable through the CRS_CFGR
|
||||
* register, can be the signal from the external CRS_SYNC pin, the LSE
|
||||
* clock or the USB SOF signal.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_CRS_CFGR);
|
||||
regval &= ~CRS_CFGR_SYNCSRC_MASK;
|
||||
|
||||
switch (syncsrc)
|
||||
{
|
||||
default:
|
||||
case SYNCSRC_GPIO: /* GPIO selected as SYNC signal source */
|
||||
regval |= CRS_CFGR_SYNCSRC_GPIO;
|
||||
break;
|
||||
|
||||
case SYNCSRC_LSE: /* LSE selected as SYNC signal source */
|
||||
regval |= CRS_CFGR_SYNCSRC_LSE;
|
||||
break;
|
||||
|
||||
case SYNCSRC_USB: /* USB SOF selected as SYNC signal source */
|
||||
regval |= CRS_CFGR_SYNCSRC_USBSOF;
|
||||
break;
|
||||
}
|
||||
|
||||
putreg32(regval, STM32_CRS_CFGR);
|
||||
|
||||
/* Set the AUTOTRIMEN bit the CRS_CR register to enables the automatic
|
||||
* hardware adjustment of TRIM bits according to the measured frequency
|
||||
* error between the selected SYNC event. Also enable CEN bit to enable
|
||||
* frequency error counter and SYNC events.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_CRS_CR);
|
||||
regval |= CRS_CR_AUTOTRIMEN | CRS_CR_CEN;
|
||||
putreg32(regval, STM32_CRS_CR);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h5_disable_hsi48
|
||||
*
|
||||
* Description:
|
||||
* Disable the HSI48 clock.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h5_disable_hsi48(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Disable the HSI48 clock */
|
||||
|
||||
regval = getreg32(STM32_RCC_CR);
|
||||
regval &= ~RCC_CR_HSI48ON;
|
||||
putreg32(regval, STM32_RCC_CR);
|
||||
|
||||
/* Set other registers to the default settings. */
|
||||
|
||||
regval = getreg32(STM32_CRS_CFGR);
|
||||
regval &= ~CRS_CFGR_SYNCSRC_MASK;
|
||||
putreg32(regval, STM32_CRS_CFGR);
|
||||
|
||||
regval = getreg32(STM32_CRS_CR);
|
||||
regval &= ~CRS_CR_AUTOTRIMEN;
|
||||
putreg32(regval, STM32_CRS_CR);
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32H5_HAVE_HSI48 */
|
||||
@@ -0,0 +1,94 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_hsi48.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_HSI48_H
|
||||
#define __ARCH_ARM_SRC_STM32H5_STM32_HSI48_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifdef CONFIG_STM32H5_HAVE_HSI48
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
enum syncsrc_e
|
||||
{
|
||||
SYNCSRC_NONE = 0, /* No SYNC signal */
|
||||
SYNCSRC_GPIO, /* GPIO selected as SYNC signal source */
|
||||
SYNCSRC_LSE, /* LSE selected as SYNC signal source */
|
||||
SYNCSRC_USB, /* USB SOF selected as SYNC signal source */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h5_enable_hsi48
|
||||
*
|
||||
* Description:
|
||||
* On STM32H5X3, STM32H596xx/4A6xx and STM32H5XR devices only, the HSI48
|
||||
* clock signal is generated from an internal 48 MHz RC oscillator and can
|
||||
* be used directly as a system clock or divided and be used as PLL input.
|
||||
*
|
||||
* The internal 48MHz RC oscillator is mainly dedicated to provide a high
|
||||
* precision clock to the USB peripheral by means of a special Clock
|
||||
* Recovery System (CRS) circuitry, which could use the USB SOF signal or
|
||||
* the LSE or an external signal to automatically adjust the oscillator
|
||||
* frequency on-fly, in a very small steps. This oscillator can also be
|
||||
* used as a system clock source when the system is in run mode; it will
|
||||
* be disabled as soon as the system enters in Stop or Standby mode. When
|
||||
* the CRS is not used, the HSI48 RC oscillator runs on its default
|
||||
* frequency which is subject to manufacturing process variations.
|
||||
*
|
||||
* Input Parameters:
|
||||
* Identifies the syncrhonization source for the HSI48. When used as the
|
||||
* USB source clock, this must be set to SYNCSRC_USB.
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h5_enable_hsi48(enum syncsrc_e syncsrc);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32h5_disable_hsi48
|
||||
*
|
||||
* Description:
|
||||
* Disable the HSI48 clock.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32h5_disable_hsi48(void);
|
||||
|
||||
#endif /* CONFIG_STM32H5_HAVE_HSI48 */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_HSI48_H */
|
||||
@@ -0,0 +1,100 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_idle.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <arch/board/board.h>
|
||||
#include <nuttx/config.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/power/pm.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_rcc.h"
|
||||
#include "arm_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Does the board support an IDLE LED to indicate that the board is in the
|
||||
* IDLE state?
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
|
||||
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
|
||||
# define END_IDLE() board_autoled_off(LED_IDLE)
|
||||
#else
|
||||
# define BEGIN_IDLE()
|
||||
# define END_IDLE()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
#define up_idlepm()
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_idle
|
||||
*
|
||||
* Description:
|
||||
* up_idle() is the logic that will be executed when their is no other
|
||||
* ready-to-run task. This is processor idle time and will continue until
|
||||
* some interrupt occurs to cause a context switch from the idle task.
|
||||
*
|
||||
* Processing in this state may be processor-specific. e.g., this is where
|
||||
* power management operations might be performed.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_idle(void)
|
||||
{
|
||||
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
|
||||
/* If the system is idle and there are no timer interrupts, then process
|
||||
* "fake" timer interrupts. Hopefully, something will wake up.
|
||||
*/
|
||||
|
||||
nxsched_process_timer();
|
||||
#else
|
||||
|
||||
/* Perform IDLE mode power management */
|
||||
|
||||
up_idlepm();
|
||||
|
||||
/* Sleep until an interrupt occurs to save power. */
|
||||
|
||||
#if !(defined(CONFIG_DEBUG_SYMBOLS) && defined(CONFIG_STM32H5_DISABLE_IDLE_SLEEP_DURING_DEBUG))
|
||||
BEGIN_IDLE();
|
||||
asm("WFI");
|
||||
END_IDLE();
|
||||
#endif
|
||||
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,474 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_irq.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/irq.h>
|
||||
#include <arch/armv8-m/nvicpri.h>
|
||||
|
||||
#include "nvic.h"
|
||||
#include "ram_vectors.h"
|
||||
#include "arm_internal.h"
|
||||
#include "stm32.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Get a 32-bit version of the default priority */
|
||||
|
||||
#define DEFPRIORITY32 \
|
||||
(NVIC_SYSH_PRIORITY_DEFAULT << 24 | \
|
||||
NVIC_SYSH_PRIORITY_DEFAULT << 16 | \
|
||||
NVIC_SYSH_PRIORITY_DEFAULT << 8 | \
|
||||
NVIC_SYSH_PRIORITY_DEFAULT)
|
||||
|
||||
/* Given the address of a NVIC ENABLE register, this is the offset to
|
||||
* the corresponding CLEAR ENABLE register.
|
||||
*/
|
||||
|
||||
#define NVIC_ENA_OFFSET (0)
|
||||
#define NVIC_CLRENA_OFFSET (NVIC_IRQ0_31_CLEAR - NVIC_IRQ0_31_ENABLE)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_dumpnvic
|
||||
*
|
||||
* Description:
|
||||
* Dump some interesting NVIC registers
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_DEBUG_IRQ_INFO)
|
||||
static void stm32_dumpnvic(const char *msg, int irq)
|
||||
{
|
||||
irqstate_t flags;
|
||||
|
||||
flags = enter_critical_section();
|
||||
|
||||
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
|
||||
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
|
||||
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
|
||||
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
|
||||
getreg32(NVIC_IRQ0_31_ENABLE), getreg32(NVIC_IRQ32_63_ENABLE),
|
||||
getreg32(NVIC_IRQ64_95_ENABLE));
|
||||
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
|
||||
getreg32(NVIC_SYSH4_7_PRIORITY), getreg32(NVIC_SYSH8_11_PRIORITY),
|
||||
getreg32(NVIC_SYSH12_15_PRIORITY));
|
||||
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
|
||||
getreg32(NVIC_IRQ0_3_PRIORITY), getreg32(NVIC_IRQ4_7_PRIORITY),
|
||||
getreg32(NVIC_IRQ8_11_PRIORITY), getreg32(NVIC_IRQ12_15_PRIORITY));
|
||||
irqinfo(" %08x %08x %08x %08x\n",
|
||||
getreg32(NVIC_IRQ16_19_PRIORITY), getreg32(NVIC_IRQ20_23_PRIORITY),
|
||||
getreg32(NVIC_IRQ24_27_PRIORITY),
|
||||
getreg32(NVIC_IRQ28_31_PRIORITY));
|
||||
irqinfo(" %08x %08x %08x %08x\n",
|
||||
getreg32(NVIC_IRQ32_35_PRIORITY), getreg32(NVIC_IRQ36_39_PRIORITY),
|
||||
getreg32(NVIC_IRQ40_43_PRIORITY),
|
||||
getreg32(NVIC_IRQ44_47_PRIORITY));
|
||||
irqinfo(" %08x %08x %08x %08x\n",
|
||||
getreg32(NVIC_IRQ48_51_PRIORITY), getreg32(NVIC_IRQ52_55_PRIORITY),
|
||||
getreg32(NVIC_IRQ56_59_PRIORITY),
|
||||
getreg32(NVIC_IRQ60_63_PRIORITY));
|
||||
irqinfo(" %08x\n",
|
||||
getreg32(NVIC_IRQ64_67_PRIORITY));
|
||||
|
||||
leave_critical_section(flags);
|
||||
}
|
||||
#else
|
||||
# define stm32_dumpnvic(msg, irq)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_nmi, stm32_pendsv, stm32_pendsv, stm32_reserved
|
||||
*
|
||||
* Description:
|
||||
* Handlers for various exceptions. None are handled and all are fatal
|
||||
* error conditions. The only advantage these provide over the default
|
||||
* unexpected interrupt handler is that they provide a diagnostic output.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
static int stm32_nmi(int irq, void *context, void *arg)
|
||||
{
|
||||
up_irq_save();
|
||||
_err("PANIC!!! NMI received\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_pendsv(int irq, void *context, void *arg)
|
||||
{
|
||||
up_irq_save();
|
||||
_err("PANIC!!! PendSV received\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int stm32_reserved(int irq, void *context, void *arg)
|
||||
{
|
||||
up_irq_save();
|
||||
_err("PANIC!!! Reserved interrupt\n");
|
||||
PANIC();
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_prioritize_syscall
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an exception. This function may be needed
|
||||
* internally even if support for prioritized interrupts is not enabled.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARMV8M_USEBASEPRI
|
||||
static inline void stm32_prioritize_syscall(int priority)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* SVCALL is system handler 11 */
|
||||
|
||||
regval = getreg32(NVIC_SYSH8_11_PRIORITY);
|
||||
regval &= ~NVIC_SYSH_PRIORITY_PR11_MASK;
|
||||
regval |= (priority << NVIC_SYSH_PRIORITY_PR11_SHIFT);
|
||||
putreg32(regval, NVIC_SYSH8_11_PRIORITY);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_irqinfo
|
||||
*
|
||||
* Description:
|
||||
* Given an IRQ number, provide the register and bit setting to enable or
|
||||
* disable the irq.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
|
||||
uintptr_t offset)
|
||||
{
|
||||
int n;
|
||||
|
||||
DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS);
|
||||
|
||||
/* Check for external interrupt */
|
||||
|
||||
if (irq >= STM32_IRQ_FIRST)
|
||||
{
|
||||
n = irq - STM32_IRQ_FIRST;
|
||||
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
|
||||
*bit = (uint32_t)1 << (n & 0x1f);
|
||||
}
|
||||
|
||||
/* Handle processor exceptions. Only a few can be disabled */
|
||||
|
||||
else
|
||||
{
|
||||
*regaddr = NVIC_SYSHCON;
|
||||
if (irq == STM32_IRQ_MEMFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_MEMFAULTENA;
|
||||
}
|
||||
else if (irq == STM32_IRQ_BUSFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_BUSFAULTENA;
|
||||
}
|
||||
else if (irq == STM32_IRQ_USAGEFAULT)
|
||||
{
|
||||
*bit = NVIC_SYSHCON_USGFAULTENA;
|
||||
}
|
||||
else if (irq == STM32_IRQ_SYSTICK)
|
||||
{
|
||||
*regaddr = NVIC_SYSTICK_CTRL;
|
||||
*bit = NVIC_SYSTICK_CTRL_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
return ERROR; /* Invalid or unsupported exception */
|
||||
}
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irqinitialize
|
||||
****************************************************************************/
|
||||
|
||||
void up_irqinitialize(void)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
int num_priority_registers;
|
||||
int i;
|
||||
|
||||
/* Disable all interrupts */
|
||||
|
||||
for (i = 0; i < NR_IRQS - STM32_IRQ_FIRST; i += 32)
|
||||
{
|
||||
putreg32(0xffffffff, NVIC_IRQ_CLEAR(i));
|
||||
}
|
||||
|
||||
/* The standard location for the vector table is at the beginning of FLASH
|
||||
* at address 0x0800:0000. If we are using the STMicro DFU bootloader,
|
||||
* then the vector table will be offset to a different location in FLASH
|
||||
* and we will need to set the NVIC vector location to this alternative
|
||||
* location.
|
||||
*/
|
||||
|
||||
putreg32((uint32_t)_vectors, NVIC_VECTAB);
|
||||
|
||||
#ifdef CONFIG_ARCH_RAMVECTORS
|
||||
/* If CONFIG_ARCH_RAMVECTORS is defined, then we are using a RAM-based
|
||||
* vector table that requires special initialization.
|
||||
*/
|
||||
|
||||
up_ramvec_initialize();
|
||||
#endif
|
||||
|
||||
/* Set all interrupts (and exceptions) to the default priority */
|
||||
|
||||
putreg32(DEFPRIORITY32, NVIC_SYSH4_7_PRIORITY);
|
||||
putreg32(DEFPRIORITY32, NVIC_SYSH8_11_PRIORITY);
|
||||
putreg32(DEFPRIORITY32, NVIC_SYSH12_15_PRIORITY);
|
||||
|
||||
/* The NVIC ICTR register (bits 0-4) holds the number of of interrupt
|
||||
* lines that the NVIC supports:
|
||||
*
|
||||
* 0 -> 32 interrupt lines, 8 priority registers
|
||||
* 1 -> 64 " " " ", 16 priority registers
|
||||
* 2 -> 96 " " " ", 32 priority registers
|
||||
* ...
|
||||
*/
|
||||
|
||||
num_priority_registers = (getreg32(NVIC_ICTR) + 1) * 8;
|
||||
|
||||
/* Now set all of the interrupt lines to the default priority */
|
||||
|
||||
regaddr = NVIC_IRQ0_3_PRIORITY;
|
||||
while (num_priority_registers--)
|
||||
{
|
||||
putreg32(DEFPRIORITY32, regaddr);
|
||||
regaddr += 4;
|
||||
}
|
||||
|
||||
/* Attach the SVCall and Hard Fault exception handlers. The SVCall
|
||||
* exception is used for performing context switches; The Hard Fault
|
||||
* must also be caught because a SVCall may show up as a Hard Fault
|
||||
* under certain conditions.
|
||||
*/
|
||||
|
||||
irq_attach(STM32_IRQ_SVCALL, arm_svcall, NULL);
|
||||
irq_attach(STM32_IRQ_HARDFAULT, arm_hardfault, NULL);
|
||||
|
||||
/* Set the priority of the SVCall interrupt */
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
|
||||
/* up_prioritize_irq(STM32_IRQ_PENDSV, NVIC_SYSH_PRIORITY_MIN); */
|
||||
|
||||
#endif
|
||||
#ifdef CONFIG_ARMV8M_USEBASEPRI
|
||||
stm32_prioritize_syscall(NVIC_SYSH_SVCALL_PRIORITY);
|
||||
#endif
|
||||
|
||||
/* If the MPU is enabled, then attach and enable the Memory Management
|
||||
* Fault handler.
|
||||
*/
|
||||
|
||||
#ifdef CONFIG_ARM_MPU
|
||||
irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
up_enable_irq(STM32_IRQ_MEMFAULT);
|
||||
#endif
|
||||
|
||||
/* Attach all other processor exceptions (except reset and sys tick) */
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
irq_attach(STM32_IRQ_NMI, stm32_nmi, NULL);
|
||||
#ifndef CONFIG_ARM_MPU
|
||||
irq_attach(STM32_IRQ_MEMFAULT, arm_memfault, NULL);
|
||||
#endif
|
||||
irq_attach(STM32_IRQ_BUSFAULT, arm_busfault, NULL);
|
||||
irq_attach(STM32_IRQ_USAGEFAULT, arm_usagefault, NULL);
|
||||
irq_attach(STM32_IRQ_PENDSV, stm32_pendsv, NULL);
|
||||
arm_enable_dbgmonitor();
|
||||
irq_attach(STM32_IRQ_DBGMONITOR, arm_dbgmonitor, NULL);
|
||||
irq_attach(STM32_IRQ_RESERVED, stm32_reserved, NULL);
|
||||
#endif
|
||||
|
||||
stm32_dumpnvic("initial", NR_IRQS);
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
|
||||
/* And finally, enable interrupts */
|
||||
|
||||
up_irq_enable();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_disable_irq
|
||||
*
|
||||
* Description:
|
||||
* Disable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_disable_irq(int irq)
|
||||
{
|
||||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t bit;
|
||||
|
||||
if (stm32_irqinfo(irq, ®addr, &bit, NVIC_CLRENA_OFFSET) == 0)
|
||||
{
|
||||
/* Modify the appropriate bit in the register to disable the interrupt.
|
||||
* For normal interrupts, we need to set the bit in the associated
|
||||
* Interrupt Clear Enable register. For other exceptions, we need to
|
||||
* clear the bit in the System Handler Control and State Register.
|
||||
*/
|
||||
|
||||
if (irq >= STM32_IRQ_FIRST)
|
||||
{
|
||||
putreg32(bit, regaddr);
|
||||
}
|
||||
else
|
||||
{
|
||||
regval = getreg32(regaddr);
|
||||
regval &= ~bit;
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_enable_irq
|
||||
*
|
||||
* Description:
|
||||
* Enable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_enable_irq(int irq)
|
||||
{
|
||||
uintptr_t regaddr;
|
||||
uint32_t regval;
|
||||
uint32_t bit;
|
||||
|
||||
if (stm32_irqinfo(irq, ®addr, &bit, NVIC_ENA_OFFSET) == 0)
|
||||
{
|
||||
/* Modify the appropriate bit in the register to enable the interrupt.
|
||||
* For normal interrupts, we need to set the bit in the associated
|
||||
* Interrupt Set Enable register. For other exceptions, we need to
|
||||
* set the bit in the System Handler Control and State Register.
|
||||
*/
|
||||
|
||||
if (irq >= STM32_IRQ_FIRST)
|
||||
{
|
||||
putreg32(bit, regaddr);
|
||||
}
|
||||
else
|
||||
{
|
||||
regval = getreg32(regaddr);
|
||||
regval |= bit;
|
||||
putreg32(regval, regaddr);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm_ack_irq
|
||||
*
|
||||
* Description:
|
||||
* Acknowledge the IRQ
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void arm_ack_irq(int irq)
|
||||
{
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an IRQ.
|
||||
*
|
||||
* Since this API is not supported on all architectures, it should be
|
||||
* avoided in common implementations where possible.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_IRQPRIO
|
||||
int up_prioritize_irq(int irq, int priority)
|
||||
{
|
||||
uint32_t regaddr;
|
||||
uint32_t regval;
|
||||
int shift;
|
||||
|
||||
DEBUGASSERT(irq >= STM32_IRQ_MEMFAULT && irq < NR_IRQS &&
|
||||
(unsigned)priority <= NVIC_SYSH_PRIORITY_MIN);
|
||||
|
||||
if (irq < STM32_IRQ_FIRST)
|
||||
{
|
||||
/* NVIC_SYSH_PRIORITY() maps {0..15} to one of three priority
|
||||
* registers (0-3 are invalid)
|
||||
*/
|
||||
|
||||
regaddr = NVIC_SYSH_PRIORITY(irq);
|
||||
irq -= 4;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* NVIC_IRQ_PRIORITY() maps {0..} to one of many priority registers */
|
||||
|
||||
irq -= STM32_IRQ_FIRST;
|
||||
regaddr = NVIC_IRQ_PRIORITY(irq);
|
||||
}
|
||||
|
||||
regval = getreg32(regaddr);
|
||||
shift = ((irq & 3) << 3);
|
||||
regval &= ~(0xff << shift);
|
||||
regval |= (priority << shift);
|
||||
putreg32(regval, regaddr);
|
||||
|
||||
stm32_dumpnvic("prioritize", irq);
|
||||
return OK;
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,64 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_lowputc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_LOWPUTC_H
|
||||
#define __ARCH_ARM_SRC_STM32H5_STM32_LOWPUTC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_lowsetup
|
||||
*
|
||||
* Description:
|
||||
* Called at the very beginning of _start. Performs low level
|
||||
* initialization of serial console.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_lowsetup(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_LOWPUTC_H */
|
||||
@@ -0,0 +1,163 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_lse.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "stm32_pwr.h"
|
||||
#include "stm32_rcc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC)
|
||||
|
||||
#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY
|
||||
# if CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
|
||||
CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
|
||||
# error "Invalid LSE drive capability setting"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
|
||||
static const uint32_t drives[4] =
|
||||
{
|
||||
RCC_BDCR_LSEDRV_LOW,
|
||||
RCC_BDCR_LSEDRV_MEDLO,
|
||||
RCC_BDCR_LSEDRV_MEDHI,
|
||||
RCC_BDCR_LSEDRV_HIGH
|
||||
};
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enablelse
|
||||
*
|
||||
* Description:
|
||||
* Enable the External Low-Speed (LSE) oscillator and the LSE system clock.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_enablelse(void)
|
||||
{
|
||||
bool writable;
|
||||
uint32_t regval;
|
||||
volatile int32_t timeout;
|
||||
#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
|
||||
volatile int32_t drive = 0;
|
||||
#endif
|
||||
|
||||
/* Check if both the External Low-Speed (LSE) oscillator and the LSE system
|
||||
* clock are already running.
|
||||
*/
|
||||
|
||||
regval = getreg32(STM32_RCC_BDCR);
|
||||
|
||||
if ((regval & (RCC_BDCR_LSEON | RCC_BDCR_LSERDY)) !=
|
||||
(RCC_BDCR_LSEON | RCC_BDCR_LSERDY))
|
||||
{
|
||||
/* The LSE is in the RTC domain and write access is denied to this
|
||||
* domain after reset, you have to enable write access using DBP bit in
|
||||
* the PWR CR register before to configuring the LSE.
|
||||
*/
|
||||
|
||||
writable = stm32_pwr_enablebkp(true);
|
||||
|
||||
/* Enable the External Low-Speed (LSE) oscillator by setting the LSEON
|
||||
* bit the RCC BDCR register.
|
||||
*/
|
||||
|
||||
regval |= RCC_BDCR_LSEON;
|
||||
|
||||
#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY
|
||||
/* Set start-up drive capability for LSE oscillator. LSE must be OFF
|
||||
* to change drive strength.
|
||||
*/
|
||||
|
||||
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
|
||||
regval |= CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY <<
|
||||
RCC_BDCR_LSEDRV_SHIFT;
|
||||
putreg32(regval, STM32_RCC_BDCR);
|
||||
regval |= RCC_BDCR_LSEON;
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
|
||||
do
|
||||
{
|
||||
regval &= ~(RCC_BDCR_LSEDRV_MASK | RCC_BDCR_LSEON);
|
||||
regval |= drives[drive++];
|
||||
putreg32(regval, STM32_RCC_BDCR);
|
||||
regval |= RCC_BDCR_LSEON;
|
||||
#endif
|
||||
|
||||
putreg32(regval, STM32_RCC_BDCR);
|
||||
|
||||
/* Wait for the LSE clock to be ready (or until a timeout elapsed)
|
||||
*/
|
||||
|
||||
for (timeout = LSERDY_TIMEOUT; timeout > 0; timeout--)
|
||||
{
|
||||
/* Check if the LSERDY flag is the set in the BDCR */
|
||||
|
||||
regval = getreg32(STM32_RCC_BDCR);
|
||||
|
||||
if (regval & RCC_BDCR_LSERDY)
|
||||
{
|
||||
/* If so, then break-out with timeout > 0 */
|
||||
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
|
||||
if (timeout != 0)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
while (drive < sizeof(drives) / sizeof(drives[0]));
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_RTC_LSECLOCK_LOWER_RUN_DRV_CAPABILITY
|
||||
|
||||
/* Set running drive capability for LSE oscillator. */
|
||||
|
||||
regval &= ~RCC_BDCR_LSEDRV_MASK;
|
||||
regval |= RCC_BDCR_LSEDRV_LOW << RCC_BDCR_LSEDRV_SHIFT;
|
||||
putreg32(regval, STM32_RCC_BDCR);
|
||||
#endif
|
||||
|
||||
/* Disable backup domain access if it was disabled on entry */
|
||||
|
||||
stm32_pwr_enablebkp(writable);
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,71 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_lsi.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "arm_internal.h"
|
||||
#include "stm32_rcc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enablelsi
|
||||
*
|
||||
* Description:
|
||||
* Enable the Internal Low-Speed (LSI) RC Oscillator.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_enablelsi(void)
|
||||
{
|
||||
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
|
||||
* bit the RCC CSR register.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_LSION);
|
||||
|
||||
/* Wait for the internal LSI oscillator to be stable. */
|
||||
|
||||
while ((getreg32(STM32_RCC_BDCR) & RCC_BDCR_LSIRDY) == 0);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_disablelsi
|
||||
*
|
||||
* Description:
|
||||
* Disable the Internal Low-Speed (LSI) RC Oscillator.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_disablelsi(void)
|
||||
{
|
||||
/* Enable the Internal Low-Speed (LSI) RC Oscillator by setting the LSION
|
||||
* bit the RCC CSR register.
|
||||
*/
|
||||
|
||||
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_LSION, 0);
|
||||
|
||||
/* LSIRDY should go low after 3 LSI clock cycles */
|
||||
}
|
||||
@@ -0,0 +1,309 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_pwr.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
#include <stdbool.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "stm32_pwr.h"
|
||||
#include "stm32_rcc.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define PWR_TIMEOUT (10 * CONFIG_BOARD_LOOPSPERMSEC)
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
static inline uint32_t stm32h5_pwr_getreg(uint16_t offset)
|
||||
{
|
||||
return getreg32(STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
static inline void stm32h5_pwr_putreg(uint16_t offset, uint16_t value)
|
||||
{
|
||||
putreg32(value, STM32_PWR_BASE + (uint32_t)offset);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_pwr_enablebkp
|
||||
*
|
||||
* Description:
|
||||
* Enables access to the backup domain (RTC registers, RTC backup data
|
||||
* registers and backup SRAM).
|
||||
*
|
||||
* Input Parameters:
|
||||
* writable True: enable ability to write to backup domain registers
|
||||
*
|
||||
* Returned Value:
|
||||
* True: The backup domain was previously writable.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool stm32_pwr_enablebkp(bool writable)
|
||||
{
|
||||
uint16_t regval;
|
||||
bool waswritable;
|
||||
|
||||
/* Get the current state of the PWR disable Backup domain register */
|
||||
|
||||
regval = stm32h5_pwr_getreg(STM32_PWR_DBPCR_OFFSET);
|
||||
waswritable = ((regval & PWR_DBPCR_DBP) != 0);
|
||||
|
||||
/* Enable or disable the ability to write */
|
||||
|
||||
if (waswritable && !writable)
|
||||
{
|
||||
/* Disable backup domain access */
|
||||
|
||||
regval &= ~PWR_DBPCR_DBP;
|
||||
stm32h5_pwr_putreg(STM32_PWR_DBPCR_OFFSET, regval);
|
||||
}
|
||||
else if (!waswritable && writable)
|
||||
{
|
||||
/* Enable backup domain access */
|
||||
|
||||
regval |= PWR_DBPCR_DBP;
|
||||
stm32h5_pwr_putreg(STM32_PWR_DBPCR_OFFSET, regval);
|
||||
|
||||
/* Enable does not happen right away */
|
||||
|
||||
up_udelay(4);
|
||||
}
|
||||
|
||||
return waswritable;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name stm32_pwr_adjustvcore
|
||||
*
|
||||
* Description:
|
||||
* Adjusts the voltage used for digital peripherals (V_CORE) before
|
||||
* raising or after decreasing the system clock frequency. Compare
|
||||
* [RM0481], section 10.7 Dynamic voltage scaling management.
|
||||
*
|
||||
* Note: Use only for VCore supplied with internal LDO or SMPS.
|
||||
* For supplying VCore externally, use stm32_pwr_adjustvos_ext.
|
||||
*
|
||||
* Input Parameters:
|
||||
* sysclock - The frequency in Hertz the system clock will or has been set
|
||||
* to.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_pwr_adjustvcore(unsigned sysclock)
|
||||
{
|
||||
volatile int timeout;
|
||||
uint32_t vos_range;
|
||||
uint32_t actvos;
|
||||
|
||||
/* Select the applicable V_CORE voltage range depending on the new system
|
||||
* clock frequency.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(sysclock <= 250000000);
|
||||
|
||||
if (sysclock > 200000000)
|
||||
{
|
||||
vos_range = PWR_VOSCR_VOS_RANGE0;
|
||||
}
|
||||
else if (sysclock > 150000000)
|
||||
{
|
||||
vos_range = PWR_VOSCR_VOS_RANGE1;
|
||||
}
|
||||
else if (sysclock > 100000000)
|
||||
{
|
||||
vos_range = PWR_VOSCR_VOS_RANGE2;
|
||||
}
|
||||
else
|
||||
{
|
||||
vos_range = PWR_VOSCR_VOS_RANGE3;
|
||||
}
|
||||
|
||||
actvos = (getreg32(STM32_PWR_VOSSR) & PWR_VOSSR_ACTVOS_MASK);
|
||||
modreg32(vos_range, PWR_VOSCR_VOS_MASK, STM32_PWR_VOSCR);
|
||||
|
||||
if (vos_range > actvos)
|
||||
{
|
||||
/* Wait until the new V_CORE voltage range has been applied. */
|
||||
|
||||
for (timeout = PWR_TIMEOUT; timeout; timeout--)
|
||||
{
|
||||
if (getreg32(STM32_PWR_VOSSR) & PWR_VOSSR_VOSRDY)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
DEBUGASSERT(timeout > 0);
|
||||
}
|
||||
else if (vos_range < actvos)
|
||||
{
|
||||
/* Wait until the voltage level for the currently used VOS is ready. */
|
||||
|
||||
for (timeout = PWR_TIMEOUT; timeout; timeout--)
|
||||
{
|
||||
if (getreg32(STM32_PWR_VOSSR) & PWR_VOSSR_ACTVOSRDY)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
DEBUGASSERT(timeout > 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* actvos == vos_range. Do nothing. */
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name stm32_pwr_adjustvos_ext
|
||||
*
|
||||
* Description:
|
||||
* When changing VCore with an external supply, VOS must
|
||||
* incrementally select intermediate levels.
|
||||
*
|
||||
* When increasing the performance:
|
||||
* 1. First, voltage scaling must be incremented (for example when
|
||||
* changing from VOS3 to VOS0, lower levels must be selected in the
|
||||
* VOS[1:0] bits: VOS2, VOS1, and then VOS0).
|
||||
* 2. The external voltage can be increased.
|
||||
* 3. The system frequency can be increased.
|
||||
*
|
||||
* When decreasing the performance:
|
||||
* 1. The system frequency MUST be decreased.
|
||||
* 2. The external voltage MUST be decreased.
|
||||
* 3. The voltage scaling can be decremented (for example when changing
|
||||
* from VOS1 to VOS3, lower levels must be selected in the VOS[1:0]
|
||||
* bits: VOS2, and then VOS3)
|
||||
*
|
||||
* Input Parameters:
|
||||
* sysclock - The frequency in Hertz the system clock will or has been set
|
||||
* to.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_pwr_adjustvos_ext(unsigned sysclock)
|
||||
{
|
||||
uint32_t vos_range;
|
||||
uint32_t vos_range_val;
|
||||
uint32_t vos_range_set;
|
||||
uint32_t actvos_val;
|
||||
|
||||
/* Select the applicable V_CORE voltage range depending on the new system
|
||||
* clock frequency.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(sysclock <= 250000000);
|
||||
|
||||
if (sysclock > 200000000)
|
||||
{
|
||||
vos_range = PWR_VOSCR_VOS_RANGE0;
|
||||
}
|
||||
else if (sysclock > 150000000)
|
||||
{
|
||||
vos_range = PWR_VOSCR_VOS_RANGE1;
|
||||
}
|
||||
else if (sysclock > 100000000)
|
||||
{
|
||||
vos_range = PWR_VOSCR_VOS_RANGE2;
|
||||
}
|
||||
else
|
||||
{
|
||||
vos_range = PWR_VOSCR_VOS_RANGE3;
|
||||
}
|
||||
|
||||
vos_range_val = (vos_range & PWR_VOSCR_VOS_MASK) >> PWR_VOSCR_VOS_SHIFT;
|
||||
|
||||
actvos_val = ((getreg32(STM32_PWR_VOSSR) & PWR_VOSSR_ACTVOS_MASK) >>
|
||||
PWR_VOSSR_ACTVOS_SHIFT);
|
||||
|
||||
if (vos_range_val > actvos_val)
|
||||
{
|
||||
/* Gradually Increase VOS Scale */
|
||||
|
||||
for (int i = actvos_val; i < vos_range_val; ++i)
|
||||
{
|
||||
if (i == 0)
|
||||
{
|
||||
vos_range_set = PWR_VOSCR_VOS_RANGE2;
|
||||
}
|
||||
else if (i == 1)
|
||||
{
|
||||
vos_range_set = PWR_VOSCR_VOS_RANGE1;
|
||||
}
|
||||
else /* (i == 2) */
|
||||
{
|
||||
vos_range_set = PWR_VOSCR_VOS_RANGE0;
|
||||
}
|
||||
|
||||
modreg32(vos_range_set, PWR_VOSCR_VOS_MASK, STM32_PWR_VOSCR);
|
||||
up_udelay(1);
|
||||
}
|
||||
}
|
||||
else if (vos_range_val < actvos_val)
|
||||
{
|
||||
/* Gradually Decrease VOS Scale */
|
||||
|
||||
for (int i = actvos_val; i > vos_range_val; --i)
|
||||
{
|
||||
if (i == 1)
|
||||
{
|
||||
vos_range_set = PWR_VOSCR_VOS_RANGE3;
|
||||
}
|
||||
else if (i == 2)
|
||||
{
|
||||
vos_range_set = PWR_VOSCR_VOS_RANGE2;
|
||||
}
|
||||
else /* (i == 3) */
|
||||
{
|
||||
vos_range_set = PWR_VOSCR_VOS_RANGE1;
|
||||
}
|
||||
|
||||
modreg32(vos_range_set, PWR_VOSCR_VOS_MASK, STM32_PWR_VOSCR);
|
||||
up_udelay(1);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* actvos == new vos. Do nothing. */
|
||||
|
||||
return;
|
||||
}
|
||||
}
|
||||
@@ -0,0 +1,95 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_pwr.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_PWR_H
|
||||
#define __ARCH_ARM_SRC_STM32H5_STM32_PWR_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "hardware/stm32_pwr.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_pwr_enablebkp
|
||||
*
|
||||
* Description:
|
||||
* Enables write access to the backup domain (RTC registers, RTC backup
|
||||
* data registers and backup SRAM). Compare [RM0456], section 10.4.7
|
||||
* Battery Backup domain, Backup domain access.
|
||||
*
|
||||
* Input Parameters:
|
||||
* writable - True: enable ability to write to backup domain registers
|
||||
*
|
||||
* Returned Value:
|
||||
* True: The backup domain was previously writable.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
bool stm32_pwr_enablebkp(bool writable);
|
||||
|
||||
/****************************************************************************
|
||||
* Name stm32_pwr_adjustvcore
|
||||
*
|
||||
* Description:
|
||||
* Adjusts the voltage used for digital peripherals (V_CORE) before
|
||||
* raising or after decreasing the system clock frequency. Compare
|
||||
* [RM0456], section 10.5.4 Dynamic voltage scaling management.
|
||||
*
|
||||
* Input Parameters:
|
||||
* sysclock - The frequency in Hertz the system clock will be raised to.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_pwr_adjustvcore(unsigned sysclock);
|
||||
|
||||
void stm32_pwr_adjustvos_ext(unsigned sysclock);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_PWR_H */
|
||||
@@ -0,0 +1,252 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_rcc.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "chip.h"
|
||||
#include "stm32_rcc.h"
|
||||
#include "hardware/stm32_flash.h"
|
||||
#include "stm32.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Allow up to 100 milliseconds for the high speed clock to become ready.
|
||||
* that is a very long delay, but if the clock does not become ready we are
|
||||
* hosed anyway.
|
||||
*/
|
||||
|
||||
#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
|
||||
|
||||
#define LSERDY_TIMEOUT (500 * CONFIG_BOARD_LOOPSPERMSEC)
|
||||
|
||||
#ifdef CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY
|
||||
# if CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY < 0 || \
|
||||
CONFIG_STM32H5_RTC_LSECLOCK_START_DRV_CAPABILITY > 3
|
||||
# error "Invalid LSE drive capability setting"
|
||||
# endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_STM32H5_RTC_AUTO_LSECLOCK_START_DRV_CAPABILITY
|
||||
static const uint32_t drives[4] =
|
||||
{
|
||||
RCC_BDCR_LSEDRV_LOW,
|
||||
RCC_BDCR_LSEDRV_MEDLO,
|
||||
RCC_BDCR_LSEDRV_MEDHI,
|
||||
RCC_BDCR_LSEDRV_HIGH
|
||||
};
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name
|
||||
*
|
||||
* Description
|
||||
* The RTC needs to reset the Backup Domain to change RTCSEL and resetting
|
||||
* the Backup Domain renders to disabling the LSE as consequence. In
|
||||
* order to avoid resetting the Backup Domain when we already configured
|
||||
* LSE we will reset the Backup Domain early (here).
|
||||
*
|
||||
* Input Parameters
|
||||
* None
|
||||
*
|
||||
* Returned Value
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_STM32H5_PWR) && defined(CONFIG_STM32H5_RTC)
|
||||
static inline void rcc_resetbkp(void)
|
||||
{
|
||||
bool init_stat;
|
||||
|
||||
/* Check if the RTC is already configured */
|
||||
|
||||
init_stat = stm32h5_rtc_is_initialized();
|
||||
if (!init_stat)
|
||||
{
|
||||
uint32_t bkregs[STM32H5_RTC_BKCOUNT];
|
||||
int i;
|
||||
|
||||
/* Backup backup-registers before RTC reset. */
|
||||
|
||||
for (i = 0; i < STM32H5_RTC_BKCOUNT; i++)
|
||||
{
|
||||
bkregs[i] = getreg32(STM32H5_RTC_BKR(i));
|
||||
}
|
||||
|
||||
/* Enable write access to the backup domain (RTC registers, RTC
|
||||
* backup data registers and backup SRAM).
|
||||
*/
|
||||
|
||||
stm32_pwr_enablebkp(true);
|
||||
|
||||
/* We might be changing RTCSEL - to ensure such changes work, we must
|
||||
* reset the backup domain (having backed up the RTC_MAGIC token)
|
||||
*/
|
||||
|
||||
modifyreg32(STM32_RCC_BDCR, 0, RCC_BDCR_BDRST);
|
||||
modifyreg32(STM32_RCC_BDCR, RCC_BDCR_BDRST, 0);
|
||||
|
||||
/* Restore backup-registers, except RTC related. */
|
||||
|
||||
for (i = 0; i < STM32H5_RTC_BKCOUNT; i++)
|
||||
{
|
||||
if (RTC_MAGIC_REG == STM32H5_RTC_BKR(i))
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
putreg32(bkregs[i], STM32H5_RTC_BKR(i));
|
||||
}
|
||||
|
||||
stm32_pwr_enablebkp(false);
|
||||
}
|
||||
}
|
||||
#else
|
||||
# define rcc_resetbkp()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name
|
||||
*
|
||||
* Description
|
||||
* Called to establish the clock settings based on the values in board.h.
|
||||
* This function (by default) will reset most everything, enable the PLL,
|
||||
* and enable peripheral clocking for all peripherals enabled in the NuttX
|
||||
* configuration file.
|
||||
*
|
||||
* If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then
|
||||
* clocking will be enabled by an externally provided, board-specific
|
||||
* function called stm32_board_clockconfig().
|
||||
*
|
||||
* Input Parameters
|
||||
* None
|
||||
*
|
||||
* Returned Value
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_clockconfig(void)
|
||||
{
|
||||
#if 0
|
||||
/* Make sure that we are starting in the reset state */
|
||||
|
||||
rcc_reset();
|
||||
|
||||
/* Reset backup domain if appropriate */
|
||||
|
||||
rcc_resetbkp();
|
||||
#endif
|
||||
#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG)
|
||||
|
||||
/* Invoke Board Custom Clock Configuration */
|
||||
|
||||
stm32_board_clockconfig();
|
||||
|
||||
#else
|
||||
|
||||
/* Invoke standard, fixed clock configuration based on definitions in
|
||||
* board.h
|
||||
*/
|
||||
|
||||
stm32_stdclockconfig();
|
||||
|
||||
#endif
|
||||
|
||||
/* Enable peripheral clocking */
|
||||
|
||||
stm32_rcc_enableperipherals();
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name
|
||||
*
|
||||
* Description
|
||||
* Re-enable the clock and restore the clock settings based on settings in
|
||||
* board.h. This function is only available to support low-power modes of
|
||||
* operation
|
||||
* re-enable/re-start the PLL
|
||||
*
|
||||
* This function performs a subset of the operations performed by
|
||||
* stm32_clockconfig()
|
||||
* reset the currently enabled peripheral clocks.
|
||||
*
|
||||
* If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then
|
||||
* clocking will be enabled by an externally provided, board-specific
|
||||
* function called stm32_board_clockconfig().
|
||||
*
|
||||
* Input Parameters
|
||||
* None
|
||||
*
|
||||
* Returned Value
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
void stm32_clockenable(void)
|
||||
{
|
||||
#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG)
|
||||
|
||||
/* Invoke Board Custom Clock Configuration */
|
||||
|
||||
stm32_board_clockconfig();
|
||||
|
||||
#else
|
||||
|
||||
/* Invoke standard, fixed clock configuration based on definitions in
|
||||
* board.h
|
||||
*/
|
||||
|
||||
stm32_stdclockconfig();
|
||||
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,251 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_rcc.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_RCC_H
|
||||
#define __ARCH_ARM_SRC_STM32H5_STM32_RCC_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "chip.h"
|
||||
|
||||
#if defined(CONFIG_STM32H5_STM32H5XXXX)
|
||||
# include "hardware/stm32_rcc.h"
|
||||
#else
|
||||
# error "Unsupported STM32H5 chip"
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_mco1config
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* Input Parameters:
|
||||
* source - One of the definitions for the RCC_CFGR_MCO definitions from
|
||||
* chip/stm32h5_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK,
|
||||
* RCC_CFGR_EXTCLK, RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK,
|
||||
* RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1, RCC_CFGR_PLL3CLK}
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void stm32_mco1config(uint32_t source)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set MCO source */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR1);
|
||||
regval &= ~(RCC_CFGR1_MCO1SEL_MASK);
|
||||
regval |= (source & RCC_CFGR1_MCO1SEL_MASK);
|
||||
putreg32(regval, STM32_RCC_CFGR1);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_mco2config
|
||||
*
|
||||
* Description:
|
||||
*
|
||||
* Input Parameters:
|
||||
* source - One of the definitions for the RCC_CFGR_MCO definitions from
|
||||
* chip/stm32h5_rcc.h {RCC_CFGR_SYSCLK, RCC_CFGR_INTCLK,
|
||||
* RCC_CFGR_EXTCLK, RCC_CFGR_PLLCLKd2, RCC_CFGR_PLL2CLK,
|
||||
* RCC_CFGR_PLL3CLKd2, RCC_CFGR_XT1, RCC_CFGR_PLL3CLK}
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static inline void stm32_mco2config(uint32_t source)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set MCO source */
|
||||
|
||||
regval = getreg32(STM32_RCC_CFGR1);
|
||||
regval &= ~(RCC_CFGR1_MCO2SEL_MASK);
|
||||
regval |= (source & RCC_CFGR1_MCO2SEL_MASK);
|
||||
putreg32(regval, STM32_RCC_CFGR1);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Called to establish the clock settings based on the values in board.h.
|
||||
* This function (by default) will reset most everything, enable the PLL,
|
||||
* and enable peripheral clocking for all periperipherals enabled in the
|
||||
* NuttX configuration file.
|
||||
*
|
||||
* If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then
|
||||
* clocking will be enabled by an externally provided, board-specific
|
||||
* function called stm32_board_clockconfig().
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_clockconfig(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_board_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Any STM32H5 board may replace the "standard" board clock configuration
|
||||
* logic with its own, custom clock configuration logic.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG
|
||||
void stm32_board_clockconfig(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_stdclockconfig
|
||||
*
|
||||
* Description:
|
||||
* The standard logic to configure the clocks based on settings in board.h.
|
||||
* Applicable if no custom clock config is provided. This function is
|
||||
* chip type specific and implemented in corresponding modules such as e.g.
|
||||
* stm32h562xx_rcc.c
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG
|
||||
void stm32_stdclockconfig(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_clockenable
|
||||
*
|
||||
* Description:
|
||||
* Re-enable the clock and restore the clock settings based on settings in
|
||||
* board.h. This function is only available to support low-power modes of
|
||||
* operation: When re-awakening from deep-sleep modes, it is necessary to
|
||||
* re-enable/re-start the PLL
|
||||
*
|
||||
* This function performs a subset of the operations performed by
|
||||
* stm32_clockconfig(): It does not reset any devices, and it does not
|
||||
* reset the currently enabled peripheral clocks.
|
||||
*
|
||||
* If CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG is defined, then
|
||||
* clocking will be enabled by an externally provided, board-specific
|
||||
* function called stm32_board_clockconfig().
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
void stm32_clockenable(void);
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enablelse
|
||||
*
|
||||
* Description:
|
||||
* Enable the External Low-Speed (LSE) Oscillator.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_enablelse(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enablelsi
|
||||
*
|
||||
* Description:
|
||||
* Enable the Internal Low-Speed (LSI) RC Oscillator.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_enablelsi(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_disablelsi
|
||||
*
|
||||
* Description:
|
||||
* Disable the Internal Low-Speed (LSI) RC Oscillator.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_disablelsi(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_rcc_enableperipherals
|
||||
*
|
||||
* Description:
|
||||
* Enable all the chip peripherals according to configuration. This is
|
||||
* chip type specific and thus implemented in corresponding modules such as
|
||||
* e.g. stm32h562xx_rcc.c
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_rcc_enableperipherals(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_RCC_H */
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,240 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_start.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/init.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "nvic.h"
|
||||
|
||||
#include "stm32.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_start.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* STM32H523/533 Memory Map *************************************************/
|
||||
|
||||
/* 0x0800:0000 - Beginning of the internal FLASH. Address of vectors.
|
||||
* Mapped as boot memory address 0x0000:0000 at reset.
|
||||
* 0x080f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
|
||||
* 0x2000:0000 - Start of internal SRAM1 and start of .data (_sdata)
|
||||
* - End of .data (_edata) and start of .bss (_sbss)
|
||||
* - End of .bss (_ebss) and bottom of idle stack
|
||||
* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
|
||||
* start of heap. NOTE that the ARM uses a decrement before
|
||||
* store stack so that the correct initial value is the end of
|
||||
* the stack + 4;
|
||||
* 0x2003:ffff - End of internal SRAM1
|
||||
* 0x2004:0000 - Start of internal SRAM2
|
||||
* 0x2004:ffff - End of internal SRAM2
|
||||
* 0x2005:0000 - Start of internal SRAM3
|
||||
* 0x2009:ffff - End of internal SRAM3
|
||||
*/
|
||||
|
||||
/* STM32H562/563/573 Memory Map *********************************************/
|
||||
|
||||
/* 0x0800:0000 - Beginning of the internal FLASH. Address of vectors.
|
||||
* Mapped as boot memory address 0x0000:0000 at reset.
|
||||
* 0x080f:ffff - End of flash region (assuming the max of 2MiB of FLASH).
|
||||
* 0x2000:0000 - Start of internal SRAM1 and start of .data (_sdata)
|
||||
* - End of .data (_edata) and start of .bss (_sbss)
|
||||
* - End of .bss (_ebss) and bottom of idle stack
|
||||
* - _ebss + CONFIG_IDLETHREAD_STACKSIZE = end of idle stack,
|
||||
* start of heap. NOTE that the ARM uses a decrement before
|
||||
* store stack so that the correct initial value is the end of
|
||||
* the stack + 4;
|
||||
* 0x2001:ffff - End of internal SRAM1
|
||||
* 0x2002:0000 - Start of internal SRAM2
|
||||
* 0x2002:ffff - End of internal SRAM2
|
||||
* 0x2003:0000 - Start of internal SRAM3
|
||||
* 0x2003:ffff - End of internal SRAM3
|
||||
*/
|
||||
|
||||
#define SRAM2_START STM32_SRAM2_BASE
|
||||
#define SRAM2_END (SRAM2_START + STM32H5_SRAM2_SIZE)
|
||||
|
||||
#define SRAM3_START STM32_SRAM3_BASE
|
||||
#define SRAM3_END (SRAM3_START + STM32H5_SRAM3_SIZE)
|
||||
|
||||
#define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE)
|
||||
|
||||
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
|
||||
* linker script. _ebss lies at the end of the BSS region. The idle task
|
||||
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
|
||||
* The IDLE thread is the thread that the system boots on and, eventually,
|
||||
* becomes the IDLE, do nothing task that runs only when there is nothing
|
||||
* else to run. The heap continues from there until the end of memory.
|
||||
* g_idle_topstack is a read-only variable the provides this computed
|
||||
* address.
|
||||
*/
|
||||
|
||||
const uintptr_t g_idle_topstack = HEAP_BASE;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: showprogress
|
||||
*
|
||||
* Description:
|
||||
* Print a character on the UART to show boot status.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_DEBUG_FEATURES
|
||||
# define showprogress(c) arm_lowputc(c)
|
||||
#else
|
||||
# define showprogress(c)
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ARMV8M_STACKCHECK
|
||||
/* we need to get r10 set before we can allow instrumentation calls */
|
||||
|
||||
void __start(void) noinstrument_function;
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: __start
|
||||
*
|
||||
* Description:
|
||||
* This is the reset entry point.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void __start(void)
|
||||
{
|
||||
const uint32_t *src;
|
||||
uint32_t *dest;
|
||||
|
||||
#ifdef CONFIG_ARMV8M_STACKCHECK
|
||||
/* Set the stack limit before we attempt to call any functions */
|
||||
|
||||
__asm__ volatile
|
||||
("sub r10, sp, %0" : : "r" (CONFIG_IDLETHREAD_STACKSIZE - 64) :);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SRAM2_INIT
|
||||
/* NOTE: this is optional because this may be inappropriate, especially
|
||||
* if the memory is being used for it's battery backed purpose. In that
|
||||
* case, the first-time initialization needs to be performed by the board
|
||||
* under application-specific circumstances. On the other hand, if we're
|
||||
* using this memory for, say, additional heap space, then this is handy.
|
||||
*/
|
||||
|
||||
for (dest = (uint32_t *)SRAM2_START; dest < (uint32_t *)SRAM2_END; )
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32H5_SRAM3_INIT
|
||||
for (dest = (uint32_t *)SRAM3_START; dest < (uint32_t *)SRAM3_END; )
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Configure the UART so that we can get debug output as soon as possible */
|
||||
|
||||
stm32_clockconfig();
|
||||
arm_fpuconfig();
|
||||
stm32_lowsetup();
|
||||
stm32_gpioinit();
|
||||
showprogress('A');
|
||||
|
||||
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
|
||||
* certain that there are no issues with the state of global variables.
|
||||
*/
|
||||
|
||||
for (dest = (uint32_t *)_sbss; dest < (uint32_t *)_ebss; )
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
|
||||
showprogress('B');
|
||||
|
||||
/* Move the initialized data section from his temporary holding spot in
|
||||
* FLASH into the correct place in SRAM. The correct place in SRAM is
|
||||
* give by _sdata and _edata. The temporary location is in FLASH at the
|
||||
* end of all of the other read-only data (.text, .rodata) at _eronly.
|
||||
*/
|
||||
|
||||
for (src = (const uint32_t *)_eronly,
|
||||
dest = (uint32_t *)_sdata; dest < (uint32_t *)_edata;
|
||||
)
|
||||
{
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
showprogress('C');
|
||||
|
||||
#ifdef CONFIG_ARMV8M_STACKCHECK
|
||||
arm_stack_check_init();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_PERF_EVENTS
|
||||
up_perf_init((void *)STM32_SYSCLK_FREQUENCY);
|
||||
#endif
|
||||
|
||||
/* Perform early serial initialization */
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
arm_earlyserialinit();
|
||||
#endif
|
||||
showprogress('D');
|
||||
|
||||
/* Initialize onboard resources */
|
||||
|
||||
stm32_board_initialize();
|
||||
showprogress('F');
|
||||
|
||||
/* Then start NuttX */
|
||||
|
||||
showprogress('\r');
|
||||
showprogress('\n');
|
||||
|
||||
nx_start();
|
||||
|
||||
/* Shoulnd't get here */
|
||||
|
||||
for (; ; );
|
||||
}
|
||||
@@ -0,0 +1,45 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_start.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32H5_STM32_START_H
|
||||
#define __ARCH_ARM_SRC_STM32H5_STM32_START_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_board_initialize
|
||||
*
|
||||
* Description:
|
||||
* All STM32H5 architectures must provide the following entry point. This
|
||||
* entry point is called early in the initialization -- after all memory
|
||||
* has been configured and mapped but before any devices have been
|
||||
* initialized.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_board_initialize(void);
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_START_H */
|
||||
@@ -0,0 +1,147 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/stm32h5/stm32_timerisr.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <time.h>
|
||||
#include <debug.h>
|
||||
#include <nuttx/arch.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "nvic.h"
|
||||
#include "clock/clock.h"
|
||||
#include "arm_internal.h"
|
||||
#include "chip.h"
|
||||
#include "stm32.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* The desired timer interrupt frequency is provided by the definition
|
||||
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
|
||||
* system clock ticks per second. That value is a user configurable setting
|
||||
* that defaults to 100 (100 ticks per second = 10 MS interval).
|
||||
*
|
||||
* The RCC feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
|
||||
* divided by 8. The SysTick can work either with this clock or with the
|
||||
* Cortex clock (HCLK), configurable in the SysTick Control and Status
|
||||
* register.
|
||||
*/
|
||||
|
||||
/* Power up default is HCLK, not HCLK/8.
|
||||
* And I don't know now to re-configure it yet
|
||||
*/
|
||||
|
||||
#undef CONFIG_STM32H5_SYSTICK_HCLKd8
|
||||
|
||||
#ifdef CONFIG_STM32H5_SYSTICK_HCLKd8
|
||||
# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / 8 / CLK_TCK) - 1)
|
||||
#else
|
||||
# define SYSTICK_RELOAD ((STM32_HCLK_FREQUENCY / CLK_TCK) - 1)
|
||||
#endif
|
||||
|
||||
/* The size of the reload field is 24 bits. Verify that the reload value
|
||||
* will fit in the reload register.
|
||||
*/
|
||||
|
||||
#if SYSTICK_RELOAD > 0x00ffffff
|
||||
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: stm32_timerisr
|
||||
*
|
||||
* Description:
|
||||
* The timer ISR will perform a variety of services for various portions
|
||||
* of the systems.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int stm32_timerisr(int irq, uint32_t *regs, void *arg)
|
||||
{
|
||||
/* Process timer interrupt */
|
||||
|
||||
nxsched_process_timer();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* This function is called during start-up to initialize
|
||||
* the timer interrupt.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_timer_initialize(void)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
/* Set the SysTick interrupt to the default priority */
|
||||
|
||||
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
|
||||
regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
|
||||
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
|
||||
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
|
||||
|
||||
/* Make sure that the SYSTICK clock source is set correctly */
|
||||
|
||||
#if 0 /* Does not work. Comes up with HCLK source and I can't change it */
|
||||
regval = getreg32(NVIC_SYSTICK_CTRL);
|
||||
#ifdef CONFIG_STM32H5_SYSTICK_HCLKd8
|
||||
regval &= ~NVIC_SYSTICK_CTRL_CLKSOURCE;
|
||||
#else
|
||||
regval |= NVIC_SYSTICK_CTRL_CLKSOURCE;
|
||||
#endif
|
||||
putreg32(regval, NVIC_SYSTICK_CTRL);
|
||||
#endif
|
||||
|
||||
/* Configure SysTick to interrupt at the requested rate */
|
||||
|
||||
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
|
||||
|
||||
/* Attach the timer interrupt vector */
|
||||
|
||||
irq_attach(STM32_IRQ_SYSTICK, (xcpt_t)stm32_timerisr, NULL);
|
||||
|
||||
/* Enable SysTick interrupts */
|
||||
|
||||
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
|
||||
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
|
||||
|
||||
/* And enable the timer interrupt */
|
||||
|
||||
up_enable_irq(STM32_IRQ_SYSTICK);
|
||||
}
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@@ -2795,6 +2795,14 @@ config ARCH_BOARD_STM32L476_MDK
|
||||
The STM32L476ME is a Cortex-M4 optimised for low-power operation
|
||||
at up to 80MHz operation with 1024Kb Flash memory and 96+32Kb SRAM.
|
||||
|
||||
config ARCH_BOARD_NUCLEO_H563ZI
|
||||
bool "NUCLEO_H563ZI"
|
||||
depends on ARCH_CHIP_STM32H563ZI
|
||||
select ARCH_HAVE_LEDS
|
||||
select ARCH_HAVE_BUTTONS
|
||||
select ARCH_HAVE_IRQBUTTONS
|
||||
---help---
|
||||
STMicro Nucleo-H563ZI board based on the STMicro STM32H563ZI MCU.
|
||||
|
||||
config ARCH_BOARD_STM32L562E_DK
|
||||
bool "STM32L562E-DK"
|
||||
@@ -4092,6 +4100,9 @@ endif
|
||||
if ARCH_BOARD_STM32L4R9AI_DISCO
|
||||
source "boards/arm/stm32l4/stm32l4r9ai-disco/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_NUCLEO_H563ZI
|
||||
source "boards/arm/stm32h5/nucleo-h563zi/Kconfig"
|
||||
endif
|
||||
if ARCH_BOARD_STM32L562E_DK
|
||||
source "boards/arm/stm32l5/stm32l562e-dk/Kconfig"
|
||||
endif
|
||||
|
||||
@@ -0,0 +1,8 @@
|
||||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see the file kconfig-language.txt in the NuttX tools repository.
|
||||
#
|
||||
|
||||
if ARCH_BOARD_NUCLEO_H563ZI
|
||||
|
||||
endif
|
||||
@@ -0,0 +1,49 @@
|
||||
#
|
||||
# This file is autogenerated: PLEASE DO NOT EDIT IT.
|
||||
#
|
||||
# You can use "make menuconfig" to make any modifications to the installed .config file.
|
||||
# You can then do "make savedefconfig" to generate a new defconfig file that includes your
|
||||
# modifications.
|
||||
#
|
||||
# CONFIG_NSH_ARGCAT is not set
|
||||
# CONFIG_STANDARD_SERIAL is not set
|
||||
CONFIG_ARCH="arm"
|
||||
CONFIG_ARCH_BOARD="nucleo-h563zi"
|
||||
CONFIG_ARCH_BOARD_NUCLEO_H563ZI=y
|
||||
CONFIG_ARCH_BUTTONS=y
|
||||
CONFIG_ARCH_CHIP="stm32h5"
|
||||
CONFIG_ARCH_CHIP_STM32H563ZI=y
|
||||
CONFIG_ARCH_CHIP_STM32H5=y
|
||||
CONFIG_ARCH_INTERRUPTSTACK=2048
|
||||
CONFIG_ARCH_STACKDUMP=y
|
||||
CONFIG_ARMV8M_STACKCHECK=y
|
||||
CONFIG_BOARD_LOOPSPERMSEC=8499
|
||||
CONFIG_BUILTIN=y
|
||||
CONFIG_DEBUG_ASSERTIONS=y
|
||||
CONFIG_DEBUG_FEATURES=y
|
||||
CONFIG_DEBUG_SYMBOLS=y
|
||||
CONFIG_FS_PROCFS=y
|
||||
CONFIG_FS_PROCFS_REGISTER=y
|
||||
CONFIG_HAVE_CXX=y
|
||||
CONFIG_HAVE_CXXINITIALIZE=y
|
||||
CONFIG_IDLETHREAD_STACKSIZE=2048
|
||||
CONFIG_INIT_ENTRYPOINT="nsh_main"
|
||||
CONFIG_NSH_ARCHINIT=y
|
||||
CONFIG_NSH_BUILTIN_APPS=y
|
||||
CONFIG_NSH_DISABLE_IFUPDOWN=y
|
||||
CONFIG_NSH_FILEIOSIZE=512
|
||||
CONFIG_NSH_LINELEN=64
|
||||
CONFIG_NSH_READLINE=y
|
||||
CONFIG_PREALLOC_TIMERS=4
|
||||
CONFIG_RAM_SIZE=655360
|
||||
CONFIG_RAM_START=0x20000000
|
||||
CONFIG_RAW_BINARY=y
|
||||
CONFIG_READLINE_CMD_HISTORY=y
|
||||
CONFIG_READLINE_TABCOMPLETION=y
|
||||
CONFIG_RR_INTERVAL=200
|
||||
CONFIG_SCHED_WAITPID=y
|
||||
CONFIG_STACK_COLORATION=y
|
||||
CONFIG_STM32H5_USART3=y
|
||||
CONFIG_SYSTEM_NSH=y
|
||||
CONFIG_TASK_NAME_SIZE=0
|
||||
CONFIG_USART3_SERIAL_CONSOLE=y
|
||||
@@ -0,0 +1,339 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32h5/nucleo-h563zi/include/board.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H
|
||||
#define __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <stdint.h>
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Clocking *****************************************************************/
|
||||
|
||||
/* The NUCLEO-H563ZI-Q supports both HSE and LSE crystals (X2 and X3).
|
||||
* However, as shipped, the X3 crystal is not populated. Therefore the
|
||||
* Nucleo-H563ZI-Q will need to run off the 16MHz HSI clock, or the
|
||||
* 32kHz-synced CSI. This configuration uses the CSI.
|
||||
*
|
||||
* System Clock source : PLL (CSI)
|
||||
* SYSCLK(Hz) : 250000000 Determined by PLL1 configuration
|
||||
* HCLK(Hz) : 250000000 (STM32_RCC_CFGR_HPRE) (Max 250MHz)
|
||||
* AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) (Max 250MHz)
|
||||
* APB1 Prescaler : 1 (STM32_RCC_CFGR_PPRE1) (Max 250MHz)
|
||||
* APB2 Prescaler : 1 (STM32_RCC_CFGR_PPRE2) (Max 250MHz)
|
||||
* CSI Frequency(Hz) : 4000000 (nominal)
|
||||
* PLL1M : 2 (STM32_PLL1CFGR_PLLM)
|
||||
* PLL1N : 125 (STM32_PLL1CFGR_PLLN)
|
||||
* PLL1P : 0 (STM32_PLL1CFGR_PLLP)
|
||||
* PLL1Q : 0 (STM32_PLL1CFGR_PLLQ)
|
||||
* PLL1R : 1 (STM32_PLL1CFGR_PLLR)
|
||||
* PLL2M : 2 (STM32_PLL2CFGR_PLLM)
|
||||
* PLL2N : 125 (STM32_PLL2CFGR_PLLN)
|
||||
* PLL2P : 0 (STM32_PLL2CFGR_PLLP)
|
||||
* PLL2Q : 0 (STM32_PLL2CFGR_PLLQ)
|
||||
* PLL2R : 1 (STM32_PLL2CFGR_PLLR)
|
||||
* PLL3M : 2 (STM32_PLL3CFGR_PLLM)
|
||||
* PLL3N : 125 (STM32_PLL3CFGR_PLLN)
|
||||
* PLL3P : 0 (STM32_PLL3CFGR_PLLP)
|
||||
* PLL3Q : 0 (STM32_PLL3CFGR_PLLQ)
|
||||
* PLL3R : 1 (STM32_PLL3CFGR_PLLR)
|
||||
* Flash Latency(WS) : 5
|
||||
*/
|
||||
|
||||
/* HSI - 32 MHz RC factory-trimmed
|
||||
* LSI - 32 KHz RC
|
||||
* CSI - 4 MHz, autotrimmed via LSE
|
||||
* HSE - not installed
|
||||
* LSE - 32.768 kHz installed
|
||||
* SYSCLK = 250 MHz
|
||||
*/
|
||||
|
||||
#define STM32_SYSCLK_FREQUENCY 250000000ul
|
||||
#define STM32_HSI_FREQUENCY 32000000ul
|
||||
#define STM32_LSI_FREQUENCY 32000
|
||||
#define STM32_LSE_FREQUENCY 32768
|
||||
|
||||
#define STM32_BOARD_USEHSI 1
|
||||
#define STM32_CR_HSIDIV RCC_CR_HSIDIV(1)
|
||||
|
||||
/* prescaler common to all PLL inputs */
|
||||
|
||||
/* 'main' PLL1 config; we use this to generate our system clock */
|
||||
|
||||
/* Use 32 MHz HSI, set M to 2, N to 15, FRAC to 0x1400 (5120)
|
||||
* SYSCLK = (32000000 / 2) * (15 + (5120/8192)) = 250000000
|
||||
*/
|
||||
|
||||
#define STM32_PLL1CFGR_PLL1FRACEN RCC_PLL1CFGR_PLL1FRACEN
|
||||
#define STM32_PLL1CFGR_PLL1VCOSEL 0
|
||||
#define STM32_PLL1CFGR_PLL1RGE RCC_PLL1CFGR_PLL1RGE_8_16M
|
||||
|
||||
#define STM32_PLL1CFGR_PLL1M RCC_PLL1CFGR_PLL1M(2)
|
||||
#define STM32_PLL1DIVR_PLL1N RCC_PLL1DIVR_PLL1N(15)
|
||||
|
||||
#define STM32_PLL1DIVR_PLL1P RCC_PLL1DIVR_PLL1P(1)
|
||||
#define STM32_PLL1CFGR_PLL1P_ENABLED 1
|
||||
#define STM32_PLL1DIVR_PLL1Q 0
|
||||
#undef STM32_PLL1CFGR_PLL1Q_ENABLED
|
||||
#define STM32_PLL1DIVR_PLL1R 0
|
||||
#undef STM32_PLL1CFGR_PLL1R_ENABLED
|
||||
|
||||
#define STM32_PLL1FRACR_PLL1FRACN 5120ul
|
||||
|
||||
/* PLL2 config */
|
||||
|
||||
#define STM32_PLL2CFGR_PLL2M RCC_PLL2CFGR_PLL2M(4)
|
||||
#define STM32_PLL2CFGR_PLL2FRACEN RCC_PLL2CFGR_PLL2FRACEN
|
||||
#define STM32_PLL2CFGR_PLL2VCOSEL RCC_PLL2CFGR_PLL2VCOSEL
|
||||
#define STM32_PLL2CFGR_PLL2RGE RCC_PLL2CFGR_PLL2RGE_8_16M
|
||||
|
||||
#define STM32_PLL2DIVR_PLL2N RCC_PLL2DIVR_PLL2N(15)
|
||||
|
||||
#define STM32_PLL2DIVR_PLL2P RCC_PLL2DIVR_PLL2P(1)
|
||||
#define STM32_PLL2CFGR_PLL2P_ENABLED
|
||||
#define STM32_PLL2DIVR_PLL2Q 0
|
||||
#undef STM32_PLL2CFGR_PLL2Q_ENABLED
|
||||
#define STM32_PLL2DIVR_PLL2R 0
|
||||
#undef STM32_PLL2CFGR_PLL2R_ENABLED
|
||||
|
||||
#define STM32_PLL2FRACR_PLL2FRACN 5120ul
|
||||
|
||||
/* PLL3 config */
|
||||
|
||||
#define STM32_PLL3CFGR_PLL3M RCC_PLL3CFGR_PLL3M(4)
|
||||
#define STM32_PLL3CFGR_PLL3FRACEN RCC_PLL3CFGR_PLL3FRACEN
|
||||
#define STM32_PLL3CFGR_PLL3VCOSEL RCC_PLL3CFGR_PLL3VCOSEL
|
||||
#define STM32_PLL3CFGR_PLL3RGE RCC_PLL3CFGR_PLL3RGE_8_16M
|
||||
|
||||
#define STM32_PLL3DIVR_PLL3N RCC_PLL3DIVR_PLL3N(15)
|
||||
|
||||
#define STM32_PLL3DIVR_PLL3P RCC_PLL3DIVR_PLL3P(1)
|
||||
#define STM32_PLL3CFGR_PLL3P_ENABLED
|
||||
#define STM32_PLL3DIVR_PLL3Q 0
|
||||
#undef STM32_PLL3CFGR_PLL3Q_ENABLED
|
||||
#define STM32_PLL3DIVR_PLL3R 0
|
||||
#undef STM32_PLL3CFGR_PLL3R_ENABLED
|
||||
|
||||
#define STM32_PLL3FRACR_PLL3FRACN 5120ul
|
||||
|
||||
/* Enable CLK48; get it from HSI48 */
|
||||
|
||||
#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG)
|
||||
# define STM32H5_USE_CLK48 1
|
||||
# define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK
|
||||
# define STM32H5_HSI48_SYNCSRC SYNCSRC_NONE
|
||||
#endif
|
||||
|
||||
/* Enable LSE (for the RTC) */
|
||||
|
||||
#define STM32_USE_LSE 1
|
||||
|
||||
/* Configure the HCLK divisor (for the AHB bus, core, memory, and DMA */
|
||||
|
||||
#define STM32_RCC_CFGR2_HPRE RCC_CFGR2_HPRE_SYSCLK /* HCLK = SYSCLK / 1 */
|
||||
#define STM32_HCLK_FREQUENCY STM32_SYSCLK_FREQUENCY
|
||||
|
||||
/* Configure the APB1 prescaler */
|
||||
|
||||
#define STM32_RCC_CFGR2_PPRE1 RCC_CFGR2_PPRE1_HCLK1 /* PCLK1 = HCLK / 1 */
|
||||
#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
|
||||
|
||||
#define STM32_APB1_TIM2_CLKIN (STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM3_CLKIN (STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM4_CLKIN (STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM5_CLKIN (STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM6_CLKIN (STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM7_CLKIN (STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM12_CLKIN (STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM13_CLKIN (STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_TIM14_CLKIN (STM32_PCLK1_FREQUENCY)
|
||||
#define STM32_APB1_LPTIM2_CLKIN (STM32_PCLK1_FREQUENCY)
|
||||
|
||||
/* Configure the APB2 prescaler */
|
||||
|
||||
#define STM32_RCC_CFGR2_PPRE2 RCC_CFGR2_PPRE2_HCLK1 /* PCLK2 = HCLK / 1 */
|
||||
#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
|
||||
|
||||
#define STM32_APB2_TIM1_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM8_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM15_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM16_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
#define STM32_APB2_TIM17_CLKIN (STM32_PCLK2_FREQUENCY)
|
||||
|
||||
/* Configure the APB3 prescaler */
|
||||
|
||||
#define STM32_RCC_CFGR2_PPRE3 RCC_CFGR2_PPRE3_HCLK1 /* PCLK2 = HCLK / 1 */
|
||||
#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY / 1)
|
||||
|
||||
#define STM32_APB3_LPTIM1_CLKIN (STM32_PCLK3_FREQUENCY)
|
||||
#define STM32_APB3_LPTIM3_CLKIN (STM32_PCLK3_FREQUENCY)
|
||||
#define STM32_APB3_LPTIM4_CLKIN (STM32_PCLK3_FREQUENCY)
|
||||
#define STM32_APB3_LPTIM5_CLKIN (STM32_PCLK3_FREQUENCY)
|
||||
#define STM32_APB3_LPTIM6_CLKIN (STM32_PCLK3_FREQUENCY)
|
||||
/* The timer clock frequencies are automatically defined by hardware. If the
|
||||
* APB prescaler equals 1, the timer clock frequencies are set to the same
|
||||
* frequency as that of the APB domain. Otherwise they are set to twice.
|
||||
*/
|
||||
|
||||
#define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM3_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM4_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM5_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM6_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM12_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM13_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM14_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM15_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_TIM16_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM1_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM2_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM3_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM4_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM5_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
#define BOARD_LPTIM6_FREQUENCY STM32_HCLK_FREQUENCY
|
||||
|
||||
/* Configure the Kernel clocks */
|
||||
|
||||
/* DMA Channel/Stream Selections ********************************************/
|
||||
|
||||
/* Alternate function pin selections ****************************************/
|
||||
|
||||
/* USART3: Connected to Arduino connector D0/D1 (or to STLink VCP if solder
|
||||
* bridges SB123 to SB130 are re-worked accordingly).
|
||||
*/
|
||||
|
||||
#define GPIO_USART3_RX GPIO_USART3_RX_4 /* PD9 */
|
||||
#define GPIO_USART3_TX GPIO_USART3_TX_4 /* PD8 */
|
||||
|
||||
/* LED definitions **********************************************************/
|
||||
|
||||
/* The Nucleo board has numerous LEDs but only three, LD1 a Green LED,
|
||||
* LD2 a Yellow LED, and LD3 a Red LED, that can be controlled by software.
|
||||
* The following definitions assume the default Solder Bridges are installed.
|
||||
*
|
||||
* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs
|
||||
* in any way.
|
||||
* The following definitions are used to access individual LEDs.
|
||||
*/
|
||||
|
||||
/* LED index values for use with board_userled() */
|
||||
|
||||
#define BOARD_LED1 0
|
||||
#define BOARD_LED2 1
|
||||
#define BOARD_LED3 2
|
||||
#define BOARD_NLEDS 3
|
||||
|
||||
#define BOARD_LED_GREEN BOARD_LED1
|
||||
#define BOARD_LED_YELLOW BOARD_LED2
|
||||
#define BOARD_LED_RED BOARD_LED3
|
||||
|
||||
/* LED bits for use with board_userled_all() */
|
||||
|
||||
#define BOARD_LED1_BIT (1 << BOARD_LED1)
|
||||
#define BOARD_LED2_BIT (1 << BOARD_LED2)
|
||||
#define BOARD_LED3_BIT (1 << BOARD_LED3)
|
||||
|
||||
/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
|
||||
* include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS-
|
||||
* related events as follows:
|
||||
*
|
||||
*
|
||||
* SYMBOL Meaning LED state
|
||||
* Red Green Blue
|
||||
* ---------------------- -------------------------- ------ ------ ----
|
||||
*/
|
||||
#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
|
||||
#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
|
||||
#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
|
||||
#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
|
||||
#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
|
||||
#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
|
||||
#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
|
||||
#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
|
||||
#define LED_IDLE 8 /* MCU is is sleep mode ON OFF OFF */
|
||||
|
||||
/* Thus if the Green LED is statically on, NuttX has successfully booted and
|
||||
* is, apparently, running normally. If the Red LED is flashing at
|
||||
* approximately 2Hz, then a fatal error has been detected and the system
|
||||
* has halted.
|
||||
*/
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
|
||||
/* The Nucleo-H563ZI supports one button: Pushbutton B1, labeled "User", is
|
||||
* connected to GPIO PC13.
|
||||
* A high value will be sensed when the button is pressed.
|
||||
*/
|
||||
|
||||
#define BUTTON_USER 0
|
||||
#define NUM_BUTTONS 1
|
||||
#define BUTTON_USER_BIT (1 << BUTTON_USER)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_board_initialize
|
||||
*
|
||||
* Description:
|
||||
* All STM32H5 architectures must provide the following entry point.
|
||||
* This entry point is called early in the initialization -- after all
|
||||
* memory has been configured and mapped but before any devices
|
||||
* have been initialized.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_board_initialize(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_INCLUDE_BOARD_H */
|
||||
@@ -0,0 +1,38 @@
|
||||
##############################################################################
|
||||
# boards/arm/stm32h5/nucleo-h563zi/scripts/Make.defs
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
##############################################################################
|
||||
|
||||
include ${TOPDIR}/.config
|
||||
include ${TOPDIR}/tools/Config.mk
|
||||
include ${TOPDIR}/arch/arm/src/armv8-m/Toolchain.defs
|
||||
|
||||
ARCHSCRIPT = $(BOARD_DIR)$(DELIM)scripts$(DELIM)flash.ld
|
||||
|
||||
ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
|
||||
|
||||
CFLAGS := $(ARCHCFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
|
||||
CXXFLAGS := $(ARCHCXXFLAGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
|
||||
CPPFLAGS := $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRAFLAGS)
|
||||
AFLAGS := $(CFLAGS) -D__ASSEMBLY__
|
||||
|
||||
NXFLATLDFLAGS1 = -r -d -warn-common
|
||||
NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)$(DELIM)binfmt$(DELIM)libnxflat$(DELIM)gnu-nxflat-pcrel.ld -no-check-sections
|
||||
LDNXFLATFLAGS = -e main -s 2048
|
||||
@@ -0,0 +1,104 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32u5/nucleo-u5a5zj-q/scripts/flash.ld
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* The STM32H562/563/573 has 1 MiB of FLASH beginning at address 0x0800:0000 and
|
||||
* 256 KiB of SRAM beginning at address 0x2000:0000. When booting from
|
||||
* FLASH, FLASH memory is aliased to address 0x0000:0000 where the code
|
||||
* expects to begin execution by jumping to the entry point in the
|
||||
* 0x0800:0000 address range.
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
|
||||
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_stext)
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.vectors)
|
||||
*(.text .text.*)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.got)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.r.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.init_section : {
|
||||
_sinit = ABSOLUTE(.);
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
|
||||
_einit = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.ARM.extab : {
|
||||
*(.ARM.extab*)
|
||||
} > flash
|
||||
|
||||
__exidx_start = ABSOLUTE(.);
|
||||
.ARM.exidx : {
|
||||
*(.ARM.exidx*)
|
||||
} > flash
|
||||
__exidx_end = ABSOLUTE(.);
|
||||
|
||||
_eronly = ABSOLUTE(.);
|
||||
|
||||
.data : {
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
CONSTRUCTORS
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
} > sram AT > flash
|
||||
|
||||
.bss : {
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > sram
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
@@ -0,0 +1,115 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32h5/nucleo-h563zi/scripts/tfm-ns.ld
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* This linker script supports running NuttX in the 'Non-Secure' (ns) domain
|
||||
* in conjunction with TrustedFirmware-M (tfm).
|
||||
*
|
||||
* NuttX will run as the 'Non secure application' in the 'Non-Secure Image
|
||||
* primary primary slot Area 1' in external flash. Compare [UM2671],
|
||||
* Figure 8. Furthermore, see Figure 15 for the SRAM area used for 'Non-
|
||||
* Secure application volatile data'
|
||||
*
|
||||
* While the 'Non-Secure Image primary slot Area 1' is actually one MiB large
|
||||
* in the referenced setup, the image will be enriched with a header of 0x400
|
||||
* bytes and a trailer of 0x2000 bytes. Thus the 'flash' statement in the
|
||||
* MEMORY definition below.
|
||||
*
|
||||
* References
|
||||
* [UM2671] STMicroelectronics. UM2671: Getting started with STM32CubeL5 TFM
|
||||
* application, 2nd edition, July 2020
|
||||
*/
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flash (rx) : ORIGIN = 0x90000400, LENGTH = 0xFDC00
|
||||
sram (rwx) : ORIGIN = 0x20000000, LENGTH = 192K
|
||||
}
|
||||
|
||||
OUTPUT_ARCH(arm)
|
||||
ENTRY(_stext)
|
||||
SECTIONS
|
||||
{
|
||||
.text : {
|
||||
_stext = ABSOLUTE(.);
|
||||
*(.vectors)
|
||||
*(.text .text.*)
|
||||
*(.fixup)
|
||||
*(.gnu.warning)
|
||||
*(.rodata .rodata.*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
*(.glue_7)
|
||||
*(.glue_7t)
|
||||
*(.got)
|
||||
*(.gcc_except_table)
|
||||
*(.gnu.linkonce.r.*)
|
||||
_etext = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.init_section : {
|
||||
_sinit = ABSOLUTE(.);
|
||||
KEEP(*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP(*(.init_array EXCLUDE_FILE(*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o) .ctors))
|
||||
_einit = ABSOLUTE(.);
|
||||
} > flash
|
||||
|
||||
.ARM.extab : {
|
||||
*(.ARM.extab*)
|
||||
} > flash
|
||||
|
||||
__exidx_start = ABSOLUTE(.);
|
||||
.ARM.exidx : {
|
||||
*(.ARM.exidx*)
|
||||
} > flash
|
||||
__exidx_end = ABSOLUTE(.);
|
||||
|
||||
_eronly = ABSOLUTE(.);
|
||||
|
||||
.data : {
|
||||
_sdata = ABSOLUTE(.);
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
CONSTRUCTORS
|
||||
. = ALIGN(4);
|
||||
_edata = ABSOLUTE(.);
|
||||
} > sram AT > flash
|
||||
|
||||
.bss : {
|
||||
_sbss = ABSOLUTE(.);
|
||||
*(.bss .bss.*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON)
|
||||
. = ALIGN(4);
|
||||
_ebss = ABSOLUTE(.);
|
||||
} > sram
|
||||
|
||||
/* Stabs debugging sections. */
|
||||
.stab 0 : { *(.stab) }
|
||||
.stabstr 0 : { *(.stabstr) }
|
||||
.stab.excl 0 : { *(.stab.excl) }
|
||||
.stab.exclstr 0 : { *(.stab.exclstr) }
|
||||
.stab.index 0 : { *(.stab.index) }
|
||||
.stab.indexstr 0 : { *(.stab.indexstr) }
|
||||
.comment 0 : { *(.comment) }
|
||||
.debug_abbrev 0 : { *(.debug_abbrev) }
|
||||
.debug_info 0 : { *(.debug_info) }
|
||||
.debug_line 0 : { *(.debug_line) }
|
||||
.debug_pubnames 0 : { *(.debug_pubnames) }
|
||||
.debug_aranges 0 : { *(.debug_aranges) }
|
||||
}
|
||||
@@ -0,0 +1,2 @@
|
||||
/.depend
|
||||
/Make.dep
|
||||
@@ -0,0 +1,40 @@
|
||||
##############################################################################
|
||||
# boards/arm/stm32h5/nucleo-h563zi/src/Makefile
|
||||
#
|
||||
# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
||||
# http://www.apache.org/licenses/LICENSE-2.0
|
||||
#
|
||||
# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
|
||||
##############################################################################
|
||||
|
||||
-include $(TOPDIR)/Make.defs
|
||||
|
||||
ASRCS =
|
||||
CSRCS = stm32_boot.c stm32_bringup.c stm32_clockconfig.c
|
||||
|
||||
ifeq ($(CONFIG_ARCH_LEDS),y)
|
||||
CSRCS += stm32_autoleds.c
|
||||
else
|
||||
CSRCS += stm32_userleds.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_ARCH_BUTTONS),y)
|
||||
CSRCS += stm32_buttons.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_BOARDCTL),y)
|
||||
CSRCS += stm32_appinit.c
|
||||
endif
|
||||
|
||||
include $(TOPDIR)/boards/Board.mk
|
||||
@@ -0,0 +1,120 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32h5/nucleo-h563zi/src/nucleo-h563zi.h
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H
|
||||
#define __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Configuration ************************************************************/
|
||||
|
||||
#define HAVE_PROC 1
|
||||
#define HAVE_RTC_DRIVER 1
|
||||
|
||||
#if !defined(CONFIG_FS_PROCFS)
|
||||
# undef HAVE_PROC
|
||||
#endif
|
||||
|
||||
#if defined(HAVE_PROC) && defined(CONFIG_DISABLE_MOUNTPOINT)
|
||||
# warning Mountpoints disabled. No procfs support
|
||||
# undef HAVE_PROC
|
||||
#endif
|
||||
|
||||
/* Check if we can support the RTC driver */
|
||||
|
||||
#if !defined(CONFIG_RTC) || !defined(CONFIG_RTC_DRIVER)
|
||||
# undef HAVE_RTC_DRIVER
|
||||
#endif
|
||||
|
||||
/* NUCLEO-H563ZI GPIOs ******************************************************/
|
||||
|
||||
/* LED I/O Color
|
||||
* LD1 PB0 Green
|
||||
* LD2 PF4 Yellow
|
||||
* LD3 PG4 Red
|
||||
*
|
||||
* - When the I/O is LOW, the LED is on.
|
||||
* - When the I/O is HIGH value, the LED is off
|
||||
*/
|
||||
|
||||
#define GPIO_LD1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHZ | \
|
||||
GPIO_OUTPUT_SET | GPIO_PORTB | GPIO_PIN0)
|
||||
#define GPIO_LD2 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHZ | \
|
||||
GPIO_OUTPUT_SET | GPIO_PORTF | GPIO_PIN4)
|
||||
#define GPIO_LD3 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_2MHZ | \
|
||||
GPIO_OUTPUT_SET | GPIO_PORTG | GPIO_PIN4)
|
||||
|
||||
/* Button definitions *******************************************************/
|
||||
|
||||
/* B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
|
||||
* microcontroller.
|
||||
*/
|
||||
|
||||
#define MIN_IRQBUTTON BUTTON_USER
|
||||
#define MAX_IRQBUTTON BUTTON_USER
|
||||
#define NUM_IRQBUTTONS 1
|
||||
|
||||
#define GPIO_BTN_USER (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \
|
||||
GPIO_PORTC | GPIO_PIN13)
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_bringup
|
||||
*
|
||||
* Description:
|
||||
* Perform architecture-specific initialization
|
||||
*
|
||||
* CONFIG_BOARD_LATE_INITIALIZE=y :
|
||||
* Called from board_late_initialize().
|
||||
*
|
||||
* CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y :
|
||||
* Called from the NSH library
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_bringup(void);
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __BOARDS_ARM_STM32H5_NUCLEO_H563ZI_SRC_NUCLEO_H563ZI_H */
|
||||
@@ -0,0 +1,71 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32h5/nucleo-h563zi/src/stm32_appinit.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "nucleo-h563zi.h"
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_app_initialize
|
||||
*
|
||||
* Description:
|
||||
* Perform application specific initialization. This function is never
|
||||
* called directly from application code, but only indirectly via the
|
||||
* (non-standard) boardctl() interface using the command BOARDIOC_INIT.
|
||||
*
|
||||
* Input Parameters:
|
||||
* arg - The boardctl() argument is passed to the board_app_initialize()
|
||||
* implementation without modification. The argument has no
|
||||
* meaning to NuttX; the meaning of the argument is a contract
|
||||
* between the board-specific initialization logic and the
|
||||
* matching application logic. The value cold be such things as a
|
||||
* mode enumeration value, a set of DIP switch switch settings, a
|
||||
* pointer to configuration data read from a file or serial FLASH,
|
||||
* or whatever you would like to do with it. Every implementation
|
||||
* should accept zero/NULL as a default configuration.
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero (OK) is returned on success; a negated errno value is returned on
|
||||
* any failure to indicate the nature of the failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int board_app_initialize(uintptr_t arg)
|
||||
{
|
||||
/* Did we already initialize via board_late_initialize()? */
|
||||
|
||||
#ifndef CONFIG_BOARD_LATE_INITIALIZE
|
||||
return stm32_bringup();
|
||||
#else
|
||||
return OK;
|
||||
#endif
|
||||
}
|
||||
@@ -0,0 +1,186 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32h5/nucleo-h563zi/src/stm32_autoleds.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <sys/param.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "arm_internal.h"
|
||||
#include "stm32_gpio.h"
|
||||
#include "nucleo-h563zi.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* Indexed by BOARD_LED_<color> */
|
||||
|
||||
static const uint32_t g_ledmap[BOARD_NLEDS] =
|
||||
{
|
||||
GPIO_LD1,
|
||||
GPIO_LD2,
|
||||
GPIO_LD3,
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
static void phy_set_led(int led, bool state)
|
||||
{
|
||||
/* Active High */
|
||||
|
||||
stm32_gpiowrite(g_ledmap[led], state);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_initialize
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_initialize(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Configure the LD1, LD2, and LD3 GPIOs for output. Initial state is OFF */
|
||||
|
||||
for (i = 0; i < nitems(g_ledmap); i++)
|
||||
{
|
||||
stm32_configgpio(g_ledmap[i]);
|
||||
stm32_gpiowrite(g_ledmap[i], false);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_on
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_on(int led)
|
||||
{
|
||||
switch (led)
|
||||
{
|
||||
case LED_HEAPALLOCATE:
|
||||
phy_set_led(BOARD_LED_GREEN, false);
|
||||
phy_set_led(BOARD_LED_YELLOW, false);
|
||||
phy_set_led(BOARD_LED_RED, false);
|
||||
break;
|
||||
|
||||
case LED_IDLE:
|
||||
phy_set_led(BOARD_LED_GREEN, true);
|
||||
phy_set_led(BOARD_LED_YELLOW, false);
|
||||
phy_set_led(BOARD_LED_RED, false);
|
||||
break;
|
||||
|
||||
case LED_IRQSENABLED:
|
||||
phy_set_led(BOARD_LED_GREEN, false);
|
||||
phy_set_led(BOARD_LED_YELLOW, true);
|
||||
phy_set_led(BOARD_LED_RED, false);
|
||||
break;
|
||||
|
||||
case LED_STACKCREATED:
|
||||
phy_set_led(BOARD_LED_GREEN, true);
|
||||
phy_set_led(BOARD_LED_YELLOW, true);
|
||||
phy_set_led(BOARD_LED_RED, false);
|
||||
break;
|
||||
|
||||
case LED_INIRQ:
|
||||
phy_set_led(BOARD_LED_GREEN, false);
|
||||
phy_set_led(BOARD_LED_YELLOW, false);
|
||||
phy_set_led(BOARD_LED_RED, true);
|
||||
break;
|
||||
|
||||
case LED_SIGNAL:
|
||||
phy_set_led(BOARD_LED_GREEN, true);
|
||||
phy_set_led(BOARD_LED_YELLOW, false);
|
||||
phy_set_led(BOARD_LED_RED, true);
|
||||
break;
|
||||
|
||||
case LED_ASSERTION:
|
||||
phy_set_led(BOARD_LED_GREEN, false);
|
||||
phy_set_led(BOARD_LED_YELLOW, true);
|
||||
phy_set_led(BOARD_LED_RED, true);
|
||||
break;
|
||||
|
||||
case LED_PANIC:
|
||||
phy_set_led(BOARD_LED_GREEN, true);
|
||||
phy_set_led(BOARD_LED_YELLOW, true);
|
||||
phy_set_led(BOARD_LED_RED, true);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_autoled_off
|
||||
****************************************************************************/
|
||||
|
||||
void board_autoled_off(int led)
|
||||
{
|
||||
switch (led)
|
||||
{
|
||||
case LED_SIGNAL:
|
||||
phy_set_led(BOARD_LED_RED, false);
|
||||
phy_set_led(BOARD_LED_GREEN, false);
|
||||
break;
|
||||
|
||||
case LED_INIRQ:
|
||||
phy_set_led(BOARD_LED_RED, false);
|
||||
break;
|
||||
|
||||
case LED_ASSERTION:
|
||||
phy_set_led(BOARD_LED_YELLOW, false);
|
||||
break;
|
||||
|
||||
case LED_PANIC:
|
||||
phy_set_led(BOARD_LED_GREEN, false);
|
||||
phy_set_led(BOARD_LED_RED, false);
|
||||
phy_set_led(BOARD_LED_YELLOW, false);
|
||||
break;
|
||||
|
||||
case LED_IDLE:
|
||||
phy_set_led(BOARD_LED_GREEN, false);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARCH_LEDS */
|
||||
@@ -0,0 +1,82 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32h5/nucleo-h563zi/src/stm32_boot.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include "arm_internal.h"
|
||||
#include "nucleo-h563zi.h"
|
||||
#include "stm32_pwr.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_board_initialize
|
||||
*
|
||||
* Description:
|
||||
* All STM32 architectures must provide the following entry point. This
|
||||
* entry point is called early in the initialization -- after all memory
|
||||
* has been configured and mapped but before any devices have been
|
||||
* initialized.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void stm32_board_initialize(void)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_LEDS
|
||||
/* Configure on-board LEDs if LED support has been selected. */
|
||||
|
||||
board_autoled_initialize();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_late_initialize
|
||||
*
|
||||
* Description:
|
||||
* If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional
|
||||
* initialization call will be performed in the boot-up sequence to a
|
||||
* function called board_late_initialize(). board_late_initialize() will
|
||||
* be called immediately after up_initialize() is called and just before
|
||||
* the initial application is started. This additional initialization
|
||||
* phase may be used, for example, to initialize board-specific device
|
||||
* drivers.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_BOARD_LATE_INITIALIZE
|
||||
void board_late_initialize(void)
|
||||
{
|
||||
/* Perform board-specific initialization here if so configured */
|
||||
|
||||
stm32_bringup();
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,105 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32h5/nucleo-h563zi/src/stm32_bringup.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <sys/mount.h>
|
||||
#include <sys/types.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/input/buttons.h>
|
||||
#include <nuttx/leds/userled.h>
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include "nucleo-h563zi.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_bringup
|
||||
*
|
||||
* Description:
|
||||
* Perform architecture-specific initialization
|
||||
*
|
||||
* CONFIG_BOARD_LATE_INITIALIZE=y :
|
||||
* Called from board_late_initialize().
|
||||
*
|
||||
* CONFIG_BOARD_LATE_INITIALIZE=n && CONFIG_BOARDCTL=y :
|
||||
* Called from the NSH library
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int stm32_bringup(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
#ifdef CONFIG_FS_PROCFS
|
||||
/* Mount the procfs file system */
|
||||
|
||||
ret = mount(NULL, "/proc", "procfs", 0, NULL);
|
||||
if (ret < 0)
|
||||
{
|
||||
ferr("ERROR: Failed to mount procfs at /proc: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_ARCH_LEDS) && defined(CONFIG_USERLED_LOWER)
|
||||
/* Register the LED driver */
|
||||
|
||||
ret = userled_lower_initialize("/dev/userleds");
|
||||
if (ret < 0)
|
||||
{
|
||||
syslog(LOG_ERR, "ERROR: userled_lower_initialize() failed: %d\n", ret);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_INPUT_BUTTONS
|
||||
#ifdef CONFIG_INPUT_BUTTONS_LOWER
|
||||
iinfo("Initializing button driver\n");
|
||||
|
||||
/* Register the BUTTON driver */
|
||||
|
||||
ret = btn_lower_initialize("/dev/buttons");
|
||||
if (ret < 0)
|
||||
{
|
||||
ierr("ERROR: btn_lower_initialize() failed: %d\n", ret);
|
||||
}
|
||||
#else
|
||||
/* Enable BUTTON support for some other purpose */
|
||||
|
||||
board_button_initialize();
|
||||
#endif
|
||||
#endif /* CONFIG_INPUT_BUTTONS */
|
||||
|
||||
UNUSED(ret);
|
||||
return OK;
|
||||
}
|
||||
@@ -0,0 +1,77 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32h5/nucleo-h563zi/src/stm32_buttons.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/board.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
#include "nucleo-h563zi.h"
|
||||
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#ifdef CONFIG_ARCH_BUTTONS
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_button_initialize
|
||||
*
|
||||
* Description:
|
||||
* board_button_initialize() must be called to initialize button resources.
|
||||
* After that, board_buttons() may be called to collect the current state
|
||||
* of all buttons or board_button_irq() may be called to register button
|
||||
* interrupt handlers.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t board_button_initialize(void)
|
||||
{
|
||||
/* Configure the single button as an input. NOTE that EXTI interrupts are
|
||||
* also configured for the pin.
|
||||
*/
|
||||
|
||||
stm32_configgpio(GPIO_BTN_USER);
|
||||
return NUM_BUTTONS;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_buttons
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t board_buttons(void)
|
||||
{
|
||||
/* Check the state of the USER button. */
|
||||
|
||||
return stm32_gpioread(GPIO_BTN_USER) ? BUTTON_USER_BIT : 0;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_ARCH_BUTTONS */
|
||||
@@ -0,0 +1,48 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32h5/nucleo-h563zi/src/stm32_clockconfig.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_board_clockconfig
|
||||
*
|
||||
* Description:
|
||||
* Currently the NUCLEO-H563ZI board support is restricted to running NuttX
|
||||
* in the Non-Secure domain together with TrustedFirmware-M (TFM). In this
|
||||
* setup the clock configuration is done by TFM, not by NuttX. Thus, the
|
||||
* board's configuration sets CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG
|
||||
* to avoid the standard clock config logic to run and instead do just
|
||||
* nothing in this function.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_ARCH_BOARD_STM32H5_CUSTOM_CLOCKCONFIG)
|
||||
void stm32_board_clockconfig(void)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,124 @@
|
||||
/****************************************************************************
|
||||
* boards/arm/stm32h5/nucleo-h563zi/src/stm32_userleds.c
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <sys/param.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <arch/board/board.h>
|
||||
|
||||
#include "stm32_gpio.h"
|
||||
#include "nucleo-h563zi.h"
|
||||
|
||||
#ifndef CONFIG_ARCH_LEDS
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* This array maps an LED number to GPIO pin configuration and is indexed by
|
||||
* BOARD_LED_<color>
|
||||
*/
|
||||
|
||||
static const uint32_t g_ledcfg[BOARD_NLEDS] =
|
||||
{
|
||||
GPIO_LD1,
|
||||
GPIO_LD2,
|
||||
GPIO_LD3,
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_userled_initialize
|
||||
*
|
||||
* Description:
|
||||
* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board
|
||||
* LEDs. If CONFIG_ARCH_LEDS is not defined, then the
|
||||
* board_userled_initialize() is available to initialize the LEDs from user
|
||||
* application logic.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
uint32_t board_userled_initialize(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Configure LED1-2 GPIOs for output */
|
||||
|
||||
for (i = 0; i < nitems(g_ledcfg); i++)
|
||||
{
|
||||
stm32_configgpio(g_ledcfg[i]);
|
||||
}
|
||||
|
||||
return BOARD_NLEDS;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_userled
|
||||
*
|
||||
* Description:
|
||||
* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board
|
||||
* LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled() is
|
||||
* available to control the LEDs from user application logic.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void board_userled(int led, bool ledon)
|
||||
{
|
||||
if ((unsigned)led < nitems(g_ledcfg))
|
||||
{
|
||||
stm32_gpiowrite(g_ledcfg[led], ledon);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_userled_all
|
||||
*
|
||||
* Description:
|
||||
* If CONFIG_ARCH_LEDS is defined, then NuttX will control the on-board
|
||||
* LEDs. If CONFIG_ARCH_LEDS is not defined, then the board_userled_all()
|
||||
* is available to control the LED from user application logic.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void board_userled_all(uint32_t ledset)
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Configure LED1-2 GPIOs for output */
|
||||
|
||||
for (i = 0; i < nitems(g_ledcfg); i++)
|
||||
{
|
||||
stm32_gpiowrite(g_ledcfg[i], (ledset & (1 << i)));
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* !CONFIG_ARCH_LEDS */
|
||||
Reference in New Issue
Block a user