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arch/arm/src/lpc54xx: The basic SPI driver is code complete but still untested. This driver is 'basic' in that in only supports polled mode operations.
This commit is contained in:
Gregory Nutt
@@ -667,6 +667,24 @@ endif # LPC54_EMC_DYNAMIC
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endmenu # EMC Configuration
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menu "SPI Master configuration"
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depends on LPC54_HAVE_SPI_MASTER
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config LPC54_SPI_WIDEDATA
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bool "Enable wide data"
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default n
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---help---
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The LPC54xxx SPI supports data widths from 4 through 16 bits. For
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data from 4 through 8 bits; the receive and transmit data is
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represented with a uint8_t type. For the wider data, data is
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represented with a uint16_t. There is duplication of logic for this
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different widths. By default, SPI wide data is disabled since that
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is the less frequently used data type and disabling wide data can
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result in some size reduction. Select this option if you need wide
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SPI data.
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endmenu # SPI Master configuration
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menu "Ethernet configuration"
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depends on LPC54_ETHERNET
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@@ -288,11 +288,18 @@
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# define SPI_DLY_TRANSFER_DELAY(n) ((uint32_t)(n) << SPI_DLY_TRANSFER_DELAY_SHIFT)
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/* SPI Status register */
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#define SPI_STAT_
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/* SPI Interrupt Enable read and set */
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#define SPI_INTENSET_
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/* SPI Interrupt Enable Clear */
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#define SPI_INTENCLR_
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#define SPI_STAT_SSA (1 << 4) /* Bit 4: Slave Select Assert */
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#define SPI_STAT_SSD (1 << 5) /* Bit 5: Slave Select Deassert */
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#define SPI_STAT_STALLED (1 << 6) /* Bit 6: Stalled status flag */
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#define SPI_STAT_ENDTRANSFER (1 << 7) /* Bit 7: End Transfer control bit */
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#define SPI_STAT_MSTIDLE (1 << 8) /* Bit 8: Master idle status flag */
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/* SPI Interrupt Enable read and set, SPI Interrupt Enable Clear, and SPI Interrupt Status */
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#define SPI_INT_SSA (1 << 4) /* Bit 4: Slave select assert interrupt */
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#define SPI_INT_SSD (1 << 5) /* Bit 5: Slave select deassert interrupt */
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#define SPI_INT_MSTIDLE (1 << 8) /* Bit 8: Master idle interrupt */
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/* SPI clock Divider */
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@@ -300,9 +307,6 @@
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#define SPI_DIV_MASK (0xffff << SPI_DIV_SHIFT)
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# define SPI_DIV(n) ((uint32_t)((n)-1) << SPI_DIV_SHIFT)
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/* SPI Interrupt Status */
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#define SPI_INTSTAT_
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/* FIFO configuration and enable register */
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#define SPI_FIFOCFG_ENABLETX (1 << 0) /* Bit 0: Enable the transmit FIFO) */
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@@ -318,12 +322,23 @@
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#define SPI_FIFOCFG_EMPTYRX (1 << 17) /* Bit 17: Empty command for the receive FIFO) */
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/* FIFO status register */
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#define SPI_FIFOSTAT_
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#define SPI_FIFOSTAT_TXERR (1 << 0) /* Bit 0: TX FIFO error */
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#define SPI_FIFOSTAT_RXERR (1 << 1) /* Bit 1: RX FIFO error */
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#define SPI_FIFOSTAT_PERINT (1 << 3) /* Bit 3: Peripheral interrupt */
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#define SPI_FIFOSTAT_TXEMPTY (1 << 4) /* Bit 4: Transmit FIFO empty */
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#define SPI_FIFOSTAT_TXNOTFULL (1 << 5) /* Bit 5: Transmit FIFO not full */
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#define SPI_FIFOSTAT_RXNOTEMPTY (1 << 6) /* Bit 6: Receive FIFO not empty */
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#define SPI_FIFOSTAT_RXFULL (1 << 7) /* Bit 7: Receive FIFO full */
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#define SPI_FIFOSTAT_TXLVL_SHIFT (8) /* Bits 8-12: Transmit FIFO current level */
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#define SPI_FIFOSTAT_TXLVL_MASK (31 << SPI_FIFOSTAT_TXLVL_SHIFT)
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#define SPI_FIFOSTAT_RXLVL_SHIFT (16) /* Bits 16-20: Receive FIFO current level */
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#define SPI_FIFOSTAT_RXLVL_MASK (31 << SPI_FIFOSTAT_RXLVL_SHIFT)
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/* FIFO trigger level settings for interrupt and DMA request */
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#define SPI_FIFOTRIG_TXLVLENA (1 << 0) /* Bit 0 Transmit FIFO level trigger enable */
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#define SPI_FIFOTRIG_RXLVLENA (1 << 1) /* Bit 1 Receive FIFO level trigger enable */
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#define SPI_FIFOTRIG_TXLVLENA (1 << 0) /* Bit 0: Transmit FIFO level trigger enable */
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#define SPI_FIFOTRIG_RXLVLENA (1 << 1) /* Bit 1: Receive FIFO level trigger enable */
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#define SPI_FIFOTRIG_TXLVL_SHIFT (8) /* Bits 8-11: Transmit FIFO level trigger point */
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#define SPI_FIFOTRIG_TXLVL_MASK (15 << SPI_FIFOTRIG_TXLVL_SHIFT)
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# define SPI_FIFOTRIG_TXLVL(n) ((uint32_t)(n) << SPI_FIFOTRIG_TXLVL_SHIFT)
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@@ -335,22 +350,28 @@
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# define SPI_FIFOTRIG_RXLVL_NOTEMPTY (0 << SPI_FIFOTRIG_RXLVL_SHIFT)
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# define SPI_FIFOTRIG_RXLVL_FULL (7 << SPI_FIFOTRIG_RXLVL_SHIFT)
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/* FIFO interrupt enable set (enable) and read register */
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#define SPI_FIFOINTENSET_
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/* FIFO interrupt enable clear (disable) and read register */
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#define SPI_FIFOINTENCLR_
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/* FIFO interrupt status register */
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#define SPI_FIFOINTSTAT_
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/* FIFO interrupt enable set (enable) and read register, FIFO interrupt enable clear (disable)
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* and read register, and FIFO interrupt status register
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*/
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#define SPI_FIFOINT_TXERR (1 << 0) /* Bit 0: Transmit error interrupt */
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#define SPI_FIFOINT_RXERR (1 << 1) /* Bit 1: Receive error interrupt */
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#define SPI_FIFOINT_TXLVL (1 << 2) /* Bit 2: Tx FIFO level reached interrupt */
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#define SPI_FIFOINT_RXLVL (1 << 3) /* Bit 3: Rx FIFO level reached interrupt */
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#define SPI_FIFOINTSTAT_PERINT (1 << 4) /* Bit 4: Peripheral interrupt (status only) */
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/* FIFO write data */
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#define SPI_FIFOWR_TXDATA_SHIFT (0) /* Bits 0-15: Transmit data to the FIFO */
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#define SPI_FIFOWR_TXDATA_MASK (0xffff << SPI_FIFOWR_TXDATA_SHIFT)
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# define SPI_FIFOWR_TXDATA(n) ((uint32_t)(n) << SPI_FIFOWR_TXDATA_SHIFT)
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#define SPI_FIFOWR_TXSSEL0_N (1 << 16) /* Bit 16: Transmit Slave Select */
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#define SPI_FIFOWR_TXSSEL1_N (1 << 17) /* Bit 17: Transmit Slave Select */
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#define SPI_FIFOWR_TXSSEL2_N (1 << 18) /* Bit 18: Transmit Slave Select */
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#define SPI_FIFOWR_TXSSEL3_N (1 << 19) /* Bit 19: Transmit Slave Select */
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#define SPI_FIFOWR_TXSSELN_SHIFT (16) /* Bits 16-19: Transmit Slave Selects */
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#define SPI_FIFOWR_TXSSELN_MASK (15 << SPI_FIFOWR_TXSSELN_SHIFT)
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# define SPI_FIFOWR_TXSSELN_ALL (15 << SPI_FIFOWR_TXSSELN_SHIFT)
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# define SPI_FIFOWR_TXSSEL0N (1 << 16) /* Bit 16: Transmit Slave Select */
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# define SPI_FIFOWR_TXSSEL1N (1 << 17) /* Bit 17: Transmit Slave Select */
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# define SPI_FIFOWR_TXSSEL2N (1 << 18) /* Bit 18: Transmit Slave Select */
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# define SPI_FIFOWR_TXSSEL3N (1 << 19) /* Bit 19: Transmit Slave Select */
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#define SPI_FIFOWR_EOT (1 << 20) /* Bit 20: End of Transfer */
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#define SPI_FIFOWR_EOF (1 << 21) /* Bit 21: End of Frame */
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#define SPI_FIFOWR_RXIGNORE (1 << 22) /* Bit 22: Receive Ignore */
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@@ -358,11 +379,27 @@
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#define SPI_FIFOWR_LEN_MASK (15 << SPI_FIFOWR_LEN_SHIFT)
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# define SPI_FIFOWR_LEN(n) ((uint32_t)((n)-1) << SPI_FIFOWR_LEN_SHIFT)
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/* FIFO read data */
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#define SPI_FIFORD_
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/* FIFO data read with no FIFO pop */
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#define SPI_FIFORDNOPOP_
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/* FIFO read data and FIFO data read with no FIFO pop */
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#define SPI_FIFORD_RXDATA_SHIFT (0) /* Bits 0-15: Received data from the FIFO */
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#define SPI_FIFORD_RXDATA_MASK (0xffff << SPI_FIFORD_RXDATA_SHIFT)
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#define SPI_FIFORD_RXSSELN_SHIFT (16) /* Bits 16-19: Slave Selects for receive */
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#define SPI_FIFORD_RXSSELN_MASK (15 << SPI_FIFORD_RXSSELN_SHIFT)
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# define SPI_FIFORD_RXSSEL0N (1 << 16) /* Bit 16: Slave Select for receive */
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# define SPI_FIFORD_RXSSEL1N (1 << 17) /* Bit 17: Slave Select for receive */
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# define SPI_FIFORD_RXSSEL2N (1 << 18) /* Bit 18: Slave Select for receive */
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# define SPI_FIFORD_RXSSEL3N (1 << 19) /* Bit 19: Slave Select for receive */
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#define SPI_FIFORD_SOT (1 << 20) /* Bit 20: Start of Transfer flag */
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/* SPI module Identification */
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#define SPI_ID_
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#define SPI_ID_APERTURE_SHIFT (0) /* Bits 0-7: Aperture encoded as (aperture size/4K) -1 */
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#define SPI_ID_APERTURE_MASK (0xff << SPI_ID_APERTURE_SHIFT)
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#define SPI_ID_MINORREV_SHIFT (8) /* Bits 8-11: Minor revision of module implementation */
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#define SPI_ID_MINORREV_MASK (15 << SPI_ID_MINORREV_SHIFT)
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#define SPI_ID_MAJORREV_SHIFT (12) /* Bits 12-15: Major revision of module implementation */
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#define SPI_ID_MAJORREV_MASK (15 << SPI_ID_MAJORREV_SHIFT)
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#define SPI_ID_ID_SHIFT (15) /* Bits 16-31: Unique module identifier for this IP block */
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#define SPI_ID_ID_MASK (0xffff << SPI_ID_ID_SHIFT)
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#endif /* __ARCH_ARM_SRC_LPC54XX_CHIP_LPC54_SPI_H */
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File diff suppressed because it is too large
Load Diff
@@ -263,7 +263,7 @@ int lpc54_spi8_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, v
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#ifdef CONFIG_LPC54_SPI9_MASTER
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int lpc54_spi9_register(FAR struct spi_dev_s *dev, spi_mediachange_t callback, void *arg);
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#endif
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#endif
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#endif /* CONFIG_SPI_CALLBACK */
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#undef EXTERN
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#if defined(__cplusplus)
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@@ -86,20 +86,13 @@ STATUS
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of this writing. Also added the netnsh configuration will, eventually,
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be used to test the Ethernet driver.
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2018-01-01: There Ethernet driver appears to be fully functional although
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more testing is certainly needed. I believe that there is a memory
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corruption issue in the current configuration that cause problems
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occasionally. For example, after a longer Telnet session, I sometimes
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see the following DEBUGASSERT after exiting the session from the host:
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more testing is certainly needed.
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2018-01-14: The basic SPI driver is code complete but still untested. It
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is "basic" in the sense that it supports only polled mode (no DMA).
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up_assert: Assertion failed at file:mm_heap/mm_free.c line: 129
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which is a clear indication heap corruption. Increasing the size of some
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stacks might correct this problem, but I have not yet experimented with
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that. I have not seen the problem in any other context.
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There is still no support for the Accelerometer, SPIFI, or USB. There is a
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complete but not-yet-functional SD card. There is a partial SPI driver,
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but no on-board SPI devices to test it.
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There is still no support for the Accelerometer, SPIFI, or USB. There are
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complete but not-yet-functional SD card and SPI drivers. There are no
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on-board devices to support SPI testing.
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Configurations
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==============
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@@ -70,8 +70,8 @@
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* Name: SPI_LOCK
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*
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* Description:
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* On SPI busses where there are multiple devices, it will be necessary to
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* lock SPI to have exclusive access to the busses for a sequence of
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* On SPI buses where there are multiple devices, it will be necessary to
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* lock SPI to have exclusive access to the buses for a sequence of
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* transfers. The bus should be locked before the chip is selected. After
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* locking the SPI bus, the caller should then also call the setfrequency,
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* setbits, and setmode methods to make sure that the SPI is properly
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