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SAMV7: Port the WDT driver from the SAMA5 to the SAMV7
This commit is contained in:
Gregory Nutt
@@ -535,13 +535,15 @@ config SAMV7_USART2
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select ARCH_HAVE_USART2
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select ARCH_HAVE_SERIAL_TERMIOS
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config SAMV7_WDT0
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bool "Watchdog Timer (WDT0)"
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config SAMV7_WDT
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bool "Watchdog Timer (WDT)"
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default n
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select WATCHDOG
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config SAMV7_WDT1
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bool "Watchdog Timer (WDT1)"
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config SAMV7_RSWDT
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bool "Reinforced Safety Watchdog Timer (RSWDT)"
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default n
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select WATCHDOG
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endmenu # SAMV7 Peripheral Selection
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@@ -136,6 +136,10 @@ ifeq ($(CONFIG_SAMV7_XDMAC),y)
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CHIP_CSRCS += sam_xdmac.c
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endif
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ifeq ($(CONFIG_SAMV7_WDT),y)
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CHIP_CSRCS += sam_wdt.c
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endif
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ifeq ($(CONFIG_SAMV7_SPI_MASTER),y)
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CHIP_CSRCS += sam_spi.c
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endif
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@@ -58,17 +58,17 @@
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/* WDT register addresses ***************************************************************/
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/* WDT0: Legacy Watchdog Timer */
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/* WDT: Legacy Watchdog Timer */
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#define SAM_WDT0_CR (SAM_WDT0_BASE+SAM_WDT_CR_OFFSET)
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#define SAM_WDT0_MR (SAM_WDT0_BASE+SAM_WDT_MR_OFFSET)
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#define SAM_WDT0_SR (SAM_WDT0_BASE+SAM_WDT_SR_OFFSET)
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#define SAM_WDT_CR (SAM_WDT_BASE+SAM_WDT_CR_OFFSET)
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#define SAM_WDT_MR (SAM_WDT_BASE+SAM_WDT_MR_OFFSET)
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#define SAM_WDT_SR (SAM_WDT_BASE+SAM_WDT_SR_OFFSET)
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/* WDT1: Reinforced Safety Watchdog Timer */
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/* RSWDT: Reinforced Safety Watchdog Timer */
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#define SAM_WDT1_CR (SAM_WDT1_BASE+SAM_WDT_CR_OFFSET)
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#define SAM_WDT1_MR (SAM_WDT1_BASE+SAM_WDT_MR_OFFSET)
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#define SAM_WDT1_SR (SAM_WDT1_BASE+SAM_WDT_SR_OFFSET)
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#define SAM_RSWDT_CR (SAM_RSWDT_BASE+SAM_WDT_CR_OFFSET)
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#define SAM_RSWDT_MR (SAM_RSWDT_BASE+SAM_WDT_MR_OFFSET)
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#define SAM_RSWDT_SR (SAM_RSWDT_BASE+SAM_WDT_SR_OFFSET)
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/* WDT register bit definitions *********************************************************/
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/* Watchdog Timer Control Register */
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@@ -76,8 +76,8 @@
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#define WDT_CR_WDRSTT (1 << 0) /* Bit 0: Watchdog Rest */
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#define WDT_CR_KEY_SHIFT (24) /* Bits 24-31: Password */
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#define WDT_CR_KEY_MASK (0xff << WDT_CR_KEY_SHIFT)
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# define WDT0_CR_KEY (0xa5 << WDT_CR_KEY_SHIFT)
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# define WDT1_CR_KEY (0xc4 << WDT_CR_KEY_SHIFT)
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# define WDT_CR_KEY (0xa5 << WDT_CR_KEY_SHIFT)
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# define RSWDT_CR_KEY (0xc4 << WDT_CR_KEY_SHIFT)
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/* Watchdog Timer Mode Register */
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@@ -87,20 +87,20 @@
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# define WDT_MR_WDV(n) ((uint32_t)(n) << WDT_MR_WDV_SHIFT)
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#define WDT_MR_WDFIEN (1 << 12) /* Bit 12: Watchdog Fault Interrupt Enable */
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#define WDT_MR_WDRSTEN (1 << 13) /* Bit 13: Watchdog Reset Enable */
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#define WDT1_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor (WDT1 only) */
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#define RSWDT_MR_WDRPROC (1 << 14) /* Bit 14: Watchdog Reset Processor (RSWDT only) */
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#define WDT_MR_WDDIS (1 << 15) /* Bit 15: Watchdog Disable */
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#define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value (WDT0 only) */
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#define WDT_MR_WDD_SHIFT (16) /* Bits 16-27: Watchdog Delta Value (WDT only) */
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#define WDT_MR_WDD_MAX 0xfff
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#define WDT_MR_WDD_MASK (WDT_MR_WDD_MAX << WDT_MR_WDD_SHIFT)
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# define WDT0_MR_WDD(n) ((uint32_t)(n) << WDT_MR_WDD_SHIFT)
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# define WDT1_MR_WDD_ALLONES (0xfff << WDT_MR_WDD_SHIFT)
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# define WDT_MR_WDD(n) ((uint32_t)(n) << WDT_MR_WDD_SHIFT)
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# define RSWDT_MR_WDD_ALLONES (0xfff << WDT_MR_WDD_SHIFT)
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#define WDT_MR_WDDBGHLT (1 << 28) /* Bit 28: Watchdog Debug Halt */
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#define WDT_MR_WDIDLEHLT (1 << 29) /* Bit 29: Watchdog Idle Halt */
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/* Watchdog Timer Status Register */
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#define WDT_SR_WDUNF (1 << 0) /* Bit 0: Watchdog Underflow */
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#define WDT0_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error (WDT0 only) */
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#define WDT_SR_WDERR (1 << 1) /* Bit 1: Watchdog Error (WDT only) */
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/****************************************************************************************
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* Public Types
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@@ -140,11 +140,11 @@
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# define SAM_RSTC_BASE 0x400e1800 /* 0x400e1800-0x400e180f: Reset Controller (RSTC) */
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# define SAM_SUPC_BASE 0x400e1810 /* 0x400e1810-0x400e182f: Supply Controller (SUPC) */
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# define SAM_RTT_BASE 0x400e1830 /* 0x400e1830-0x400e184f: Real Time Timer (RTT) */
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# define SAM_WDT0_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer 0 (WDT0) */
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# define SAM_WDT_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer (WDT) */
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# define SAM_RTC_BASE 0x400e1860 /* 0x400e1860-0x400e188f: Real Time Clock (RTC) */
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# define SAM_GPBR_BASE 0x400e1890 /* 0x400e1890-0x400e18ff: GPBR */
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# define SAM_SYSC_BASE 0x400e18e0 /* 0x400e1890-0x400e18ff: System Controller Common */
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# define SAM_WDT1_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Watchdog Timer 1 (WDT1) */
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# define SAM_RSWDT_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Reinforced Safety Watchdog Timer (RSWDT) */
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#define SAM_UART2_BASE 0x400e1a00 /* 0x400e1a00-0x400e1bff: UART 2 */
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#define SAM_UART3_BASE 0x400e1c00 /* 0x400e1c00-0x400e1dff: UART 3 */
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#define SAM_UART4_BASE 0x400e1e00 /* 0x400e1e00-0x400e1fff: UART 4 */
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@@ -140,11 +140,11 @@
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# define SAM_RSTC_BASE 0x400e1800 /* 0x400e1800-0x400e180f: Reset Controller (RSTC) */
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# define SAM_SUPC_BASE 0x400e1810 /* 0x400e1810-0x400e182f: Supply Controller (SUPC) */
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# define SAM_RTT_BASE 0x400e1830 /* 0x400e1830-0x400e184f: Real Time Timer (RTT) */
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# define SAM_WDT0_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer 0 (WDT0) */
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# define SAM_WDT_BASE 0x400e1850 /* 0x400e1850-0x400e185f: Watchdog Timer(WDT) */
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# define SAM_RTC_BASE 0x400e1860 /* 0x400e1860-0x400e188f: Real Time Clock (RTC) */
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# define SAM_GPBR_BASE 0x400e1890 /* 0x400e1890-0x400e18ff: GPBR */
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# define SAM_SYSC_BASE 0x400e18e0 /* 0x400e1890-0x400e18ff: System Controller Common */
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# define SAM_WDT1_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Watchdog Timer 1 (WDT1) */
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# define SAM_RSWDT_BASE 0x400e1900 /* 0x400e1900-0x400e19ff: Reinforced Safety Watchdog Timer (RSWDT) */
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#define SAM_UART2_BASE 0x400e1a00 /* 0x400e1a00-0x400e1bff: UART 2 */
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#define SAM_UART3_BASE 0x400e1c00 /* 0x400e1c00-0x400e1dff: UART 3 */
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#define SAM_UART4_BASE 0x400e1e00 /* 0x400e1e00-0x400e1fff: UART 4 */
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@@ -110,14 +110,14 @@ static inline void sam_efcsetup(void)
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static inline void sam_wdtsetup(void)
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{
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#if !defined(CONFIG_SAMV7_WDT0) || \
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(defined(CONFIG_WDT0_ENABLED_ON_RESET) && defined(CONFIG_WDT0_DISABLE_ON_RESET))
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putreg32(WDT_MR_WDDIS, SAM_WDT0_MR);
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#if !defined(CONFIG_SAMV7_WDT) || \
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(defined(CONFIG_WDT_ENABLED_ON_RESET) && defined(CONFIG_WDT_DISABLE_ON_RESET))
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putreg32(WDT_MR_WDDIS, SAM_WDT_MR);
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#endif
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#if !defined(CONFIG_SAMV7_WDT1) || \
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(defined(CONFIG_WDT1_ENABLED_ON_RESET) && defined(CONFIG_WDT1_DISABLE_ON_RESET))
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putreg32(WDT_MR_WDDIS, SAM_WDT1_MR);
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#if !defined(CONFIG_SAMV7_RSWDT) || \
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(defined(CONFIG_RSWDT_ENABLED_ON_RESET) && defined(CONFIG_RSWDT_DISABLE_ON_RESET))
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putreg32(WDT_MR_WDDIS, SAM_RSWDT_MR);
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#endif
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}
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,76 @@
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/****************************************************************************
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* arch/arm/src/samv7/sam_wdt.h
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*
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* Copyright (C) 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_SRC_SAMV7_SAM_WDT_H
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#define __ARCH_ARM_SRC_SAMV7_SAM_WDT_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include "chip.h"
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#include "chip/sam_wdt.h"
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#ifdef CONFIG_WATCHDOG
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_WATCHDOG */
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#endif /* __ARCH_ARM_SRC_SAMV7_SAM_WDT_H */
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