xtensa/esp32s3: SPI support quad I/O mode

arch/xtensa/src/esp32s3/Kconfig

@@ -594,9 +594,22 @@ config ESP32S3_RTCIO_IRQ
 menu "SPI configuration"
 	depends on ESP32S3_SPI
 
+choice
+	prompt "SPI I/O Mode"
+	default ESP32S3_SPI_IO_SPI
+
+config ESP32S3_SPI_IO_SPI
+	bool "SPI (4-line)"
+
+config ESP32S3_SPI_IO_QIO
+	bool "QIO (6-line)"
+
+endchoice # SPI I/O Mode
+
 config ESP32S3_SPI_SWCS
 	bool "SPI software CS"
 	default n
+	depends on ESP32S3_SPI_IO_SPI
 	---help---
 		Use SPI software CS.
 
@@ -607,36 +620,34 @@ config ESP32S3_SPI_UDCS
 	---help---
 		Use user-defined CS.
 
-config ESP32S3_SPI_SLAVE_BUFSIZE
+config ESP32S3_SPI_DMA
-	int "SPI slave buffer size"
+	bool "SPI use GDMA"
-	default 2048
-	depends on SPI_SLAVE
-
-if ESP32S3_SPI2
-
-config ESP32S3_SPI2_DMA
-	bool "SPI2 use GDMA"
 	default n
-	depends on ESP32S3_DMA
+	select ESP32S3_DMA
 	---help---
 		Enable support for transfers using the GDMA engine.
 
-config ESP32S3_SPI2_DMADESC_NUM
+config ESP32S3_SPI_DMA_BUFSIZE
-	int "SPI2 Master GDMA maximum number of descriptors"
+	int "SPI Master GDMA buffer size"
-	default 2
+	default 2048
-	depends on ESP32S3_SPI2_DMA
+	depends on ESP32S3_SPI_DMA
 	---help---
-		Configure the maximum number of out-link/in-link descriptors to
+		This is used to calculate and allocate DMA description buffer,
-		be chained for a GDMA transfer.
+		not really allocate TX/RX buffer.
 
-config ESP32S3_SPI2_DMATHRESHOLD
+config ESP32S3_SPI_DMATHRESHOLD
-	int "SPI2 Master GDMA threshold"
+	int "SPI Master GDMA threshold"
 	default 64
-	depends on ESP32S3_SPI2_DMA
+	depends on ESP32S3_SPI_DMA && ESP32S3_SPI_IO_SPI
 	---help---
 		When SPI GDMA is enabled, GDMA transfers whose size are below the
 		defined threshold will be performed by polling logic.
 
+config ESP32S3_SPI_SLAVE_BUFSIZE
+	int "SPI Slave buffer size"
+	default 2048
+	depends on SPI_SLAVE
+
 config ESP32S3_SPI2_CSPIN
 	int "SPI2 CS Pin"
 	default 10
@@ -657,16 +668,17 @@ config ESP32S3_SPI2_MISOPIN
 	default 13
 	range 0 48
 
-endif # ESP32S3_SPI2
+config ESP32S3_SPI2_IO2PIN
+	int "SPI2 IO2 Pin"
+	default 14
+	range 0 48
+	depends on ESP32S3_SPI_IO_QIO
 
-if ESP32S3_SPI3
+config ESP32S3_SPI2_IO3PIN
-
+	int "SPI2 IO3 Pin"
-config ESP32S3_SPI3_DMA
+	default 9
-	bool "SPI3 use GDMA"
+	range 0 48
-	default n
+	depends on ESP32S3_SPI_IO_QIO
-	depends on ESP32S3_DMA
-	---help---
-		Enable support for transfers using the GDMA engine.
 
 config ESP32S3_SPI3_CSPIN
 	int "SPI3 CS Pin"
@@ -688,7 +700,17 @@ config ESP32S3_SPI3_MISOPIN
 	default 2
 	range 0 48
 
-endif # ESP32S3_SPI3
+config ESP32S3_SPI3_IO2PIN
+	int "SPI3 IO2 Pin"
+	default 3
+	range 0 48
+	depends on ESP32S3_SPI_IO_QIO
+
+config ESP32S3_SPI3_IO3PIN
+	int "SPI3 IO3 Pin"
+	default 4
+	range 0 48
+	depends on ESP32S3_SPI_IO_QIO
 
 endmenu # SPI configuration
 

arch/xtensa/src/esp32s3/Make.defs

@@ -106,10 +106,15 @@ CHIP_CSRCS += esp32s3_i2c.c
 endif
 
 ifeq ($(CONFIG_ESP32S3_SPI),y)
-CHIP_CSRCS += esp32s3_spi.c
+  ifeq ($(CONFIG_ESP32S3_SPI_IO_SPI),y)
-ifeq ($(CONFIG_SPI_SLAVE),y)
+    CHIP_CSRCS += esp32s3_spi.c
-CHIP_CSRCS += esp32s3_spi_slave.c
+  else
-endif
+    CHIP_CSRCS += esp32s3_qspi.c
+  endif
+
+  ifeq ($(CONFIG_SPI_SLAVE),y)
+    CHIP_CSRCS += esp32s3_spi_slave.c
+  endif
 endif
 
 ifeq ($(CONFIG_ESP32S3_SPIFLASH),y)

arch/xtensa/src/esp32s3/esp32s3_qspi.h

@@ -0,0 +1,126 @@
+/****************************************************************************
+ * arch/xtensa/src/esp32s3/esp32s3_qspi.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_QSPI_H
+#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_QSPI_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/spi/qspi.h>
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#ifdef CONFIG_ESP32S3_SPI
+
+#ifdef CONFIG_ESP32S3_SPI2
+#  define ESP32S3_SPI2 2
+#endif
+
+#ifdef CONFIG_ESP32S3_SPI3
+#  define ESP32S3_SPI3 3
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+ * Name: esp32s3_qspibus_set_attr
+ *
+ * Description:
+ *   Set attribution of QSPI bus transfer.
+ *
+ * Input Parameters:
+ *   dev        - Device-specific state data
+ *   dummies    - Number of dummy cycles, this only works in command
+ *                transfer, not works in memory transfer
+ *   addr_lines - Number of address transmiting I/O pins
+ *   data_lines - Number of data transmiting I/O pins
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success.  Otherwise -1 (ERROR).
+ *
+ ****************************************************************************/
+
+int esp32s3_qspibus_set_attr(struct qspi_dev_s *dev,
+                             uint8_t dummies,
+                             uint8_t addr_lines,
+                             uint8_t data_lines);
+
+/****************************************************************************
+ * Name: esp32s3_qspibus_initialize
+ *
+ * Description:
+ *   Initialize the selected QSPI bus.
+ *
+ * Input Parameters:
+ *   port - Port number (for hardware that has multiple QSPI interfaces)
+ *
+ * Returned Value:
+ *   Valid QSPI device structure reference on success; NULL on failure
+ *
+ ****************************************************************************/
+
+struct qspi_dev_s *esp32s3_qspibus_initialize(int port);
+
+/****************************************************************************
+ * Name: esp32s3_qspibus_uninitialize
+ *
+ * Description:
+ *   Uninitialize an QSPI bus.
+ *
+ * Input Parameters:
+ *   dev - Device-specific state data
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success.  Otherwise -1 (ERROR).
+ *
+ ****************************************************************************/
+
+int esp32s3_qspibus_uninitialize(struct qspi_dev_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+#undef EXTERN
+
+#endif /* __ASSEMBLY__ */
+#endif /* CONFIG_ESP32S3_SPI */
+#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_QSPI_H */

arch/xtensa/src/esp32s3/esp32s3_spi.c

@@ -48,7 +48,7 @@
 #include "esp32s3_irq.h"
 #include "esp32s3_gpio.h"
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
 #include "esp32s3_dma.h"
 #endif
 
@@ -71,11 +71,15 @@
 #  define SPI_HAVE_SWCS 0
 #endif
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
 
-/* SPI DMA RX/TX number of descriptors */
+/* QSPI DMA RX/TX number of descriptors */
 
-#define SPI_DMA_DESC_NUM    (CONFIG_ESP32S3_SPI2_DMADESC_NUM)
+#  if (CONFIG_ESP32S3_SPI_DMA_BUFSIZE % ESP32S3_DMA_BUFLEN_MAX) > 0
+#    define SPI_DMA_DESC_NUM (CONFIG_ESP32S3_SPI_DMA_BUFSIZE / ESP32S3_DMA_BUFLEN_MAX + 1)
+#  else
+#    define SPI_DMA_DESC_NUM (CONFIG_ESP32S3_SPI_DMA_BUFSIZE / ESP32S3_DMA_BUFLEN_MAX)
+#  endif
 
 /* SPI DMA reset before exchange */
 
@@ -123,13 +127,13 @@ struct esp32s3_spi_config_s
   uint8_t mosi_pin;           /* GPIO configuration for MOSI */
   uint8_t miso_pin;           /* GPIO configuration for MISO */
   uint8_t clk_pin;            /* GPIO configuration for CLK */
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
   uint8_t periph;             /* Peripheral ID */
   uint8_t irq;                /* Interrupt ID */
 #endif
   uint32_t clk_bit;           /* Clock enable bit */
   uint32_t rst_bit;           /* SPI reset bit */
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
   uint32_t dma_clk_bit;       /* DMA clock enable bit */
   uint32_t dma_rst_bit;       /* DMA reset bit */
 #endif
@@ -154,11 +158,16 @@ struct esp32s3_spi_priv_s
   const struct esp32s3_spi_config_s *config;
   int refs;             /* Reference count */
   mutex_t lock;         /* Held while chip is selected for mutual exclusion */
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
   sem_t sem_isr;        /* Interrupt wait semaphore */
   int cpu;              /* CPU ID */
   int cpuint;           /* SPI interrupt ID */
   int32_t dma_channel;  /* Channel assigned by the GDMA driver */
+
+  /* DMA RX/TX description */
+
+  struct esp32s3_dmadesc_s *dma_rxdesc;
+  struct esp32s3_dmadesc_s *dma_txdesc;
 #endif
   uint32_t frequency;   /* Requested clock frequency */
   uint32_t actual;      /* Actual clock frequency */
@@ -188,7 +197,7 @@ static uint32_t esp32s3_spi_send(struct spi_dev_s *dev, uint32_t wd);
 static void esp32s3_spi_exchange(struct spi_dev_s *dev,
                                  const void *txbuffer,
                                  void *rxbuffer, size_t nwords);
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
 static int esp32s3_spi_interrupt(int irq, void *context, void *arg);
 static int esp32s3_spi_sem_waitdone(struct esp32s3_spi_priv_s *priv);
 static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
@@ -212,7 +221,7 @@ static void esp32s3_spi_recvblock(struct spi_dev_s *dev,
 #ifdef CONFIG_SPI_TRIGGER
 static int esp32s3_spi_trigger(struct spi_dev_s *dev);
 #endif
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
 static void esp32s3_spi_dma_init(struct spi_dev_s *dev);
 #endif
 static void esp32s3_spi_init(struct spi_dev_s *dev);
@@ -233,13 +242,13 @@ static const struct esp32s3_spi_config_s esp32s3_spi2_config =
   .mosi_pin     = CONFIG_ESP32S3_SPI2_MOSIPIN,
   .miso_pin     = CONFIG_ESP32S3_SPI2_MISOPIN,
   .clk_pin      = CONFIG_ESP32S3_SPI2_CLKPIN,
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
   .periph       = ESP32S3_PERIPH_SPI2,
   .irq          = ESP32S3_IRQ_SPI2,
 #endif
   .clk_bit      = SYSTEM_SPI2_CLK_EN,
   .rst_bit      = SYSTEM_SPI2_RST,
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
   .dma_clk_bit  = SYSTEM_SPI2_DMA_CLK_EN,
   .dma_rst_bit  = SYSTEM_SPI2_DMA_RST,
 #endif
@@ -284,6 +293,15 @@ static const struct spi_ops_s esp32s3_spi2_ops =
   .registercallback  = NULL,
 };
 
+#ifdef CONFIG_ESP32S3_SPI_DMA
+
+/* SPI DMA RX/TX description */
+
+static struct esp32s3_dmadesc_s esp32s3_spi2_dma_txdesc[SPI_DMA_DESC_NUM];
+static struct esp32s3_dmadesc_s esp32s3_spi2_dma_rxdesc[SPI_DMA_DESC_NUM];
+
+#endif
+
 static struct esp32s3_spi_priv_s esp32s3_spi2_priv =
 {
   .spi_dev     =
@@ -293,10 +311,12 @@ static struct esp32s3_spi_priv_s esp32s3_spi2_priv =
   .config      = &esp32s3_spi2_config,
   .refs        = 0,
   .lock        = NXMUTEX_INITIALIZER,
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
   .sem_isr     = SEM_INITIALIZER(0),
   .cpuint      = -ENOMEM,
   .dma_channel = -1,
+  .dma_rxdesc  = esp32s3_spi2_dma_rxdesc,
+  .dma_txdesc  = esp32s3_spi2_dma_txdesc,
 #endif
   .frequency   = 0,
   .actual      = 0,
@@ -316,8 +336,16 @@ static const struct esp32s3_spi_config_s esp32s3_spi3_config =
   .mosi_pin     = CONFIG_ESP32S3_SPI3_MOSIPIN,
   .miso_pin     = CONFIG_ESP32S3_SPI3_MISOPIN,
   .clk_pin      = CONFIG_ESP32S3_SPI3_CLKPIN,
+#ifdef CONFIG_ESP32S3_SPI_DMA
+  .periph       = ESP32S3_PERIPH_SPI3,
+  .irq          = ESP32S3_IRQ_SPI3,
+#endif
   .clk_bit      = SYSTEM_SPI3_CLK_EN,
   .rst_bit      = SYSTEM_SPI3_RST,
+#ifdef CONFIG_ESP32S3_SPI_DMA
+  .dma_clk_bit  = SYSTEM_SPI3_DMA_CLK_EN,
+  .dma_rst_bit  = SYSTEM_SPI3_DMA_RST,
+#endif
   .cs_insig     = FSPICS0_IN_IDX,
   .cs_outsig    = FSPICS0_OUT_IDX,
   .mosi_insig   = FSPID_IN_IDX,
@@ -359,6 +387,15 @@ static const struct spi_ops_s esp32s3_spi3_ops =
   .registercallback  = NULL,
 };
 
+#ifdef CONFIG_ESP32S3_SPI_DMA
+
+/* SPI DMA RX/TX description */
+
+static struct esp32s3_dmadesc_s esp32s3_spi3_dma_txdesc[SPI_DMA_DESC_NUM];
+static struct esp32s3_dmadesc_s esp32s3_spi3_dma_rxdesc[SPI_DMA_DESC_NUM];
+
+#endif
+
 static struct esp32s3_spi_priv_s esp32s3_spi3_priv =
 {
   .spi_dev     =
@@ -368,6 +405,13 @@ static struct esp32s3_spi_priv_s esp32s3_spi3_priv =
   .config      = &esp32s3_spi3_config,
   .refs        = 0,
   .lock        = NXMUTEX_INITIALIZER,
+#ifdef CONFIG_ESP32S3_SPI_DMA
+  .sem_isr     = SEM_INITIALIZER(0),
+  .cpuint      = -ENOMEM,
+  .dma_channel = -1,
+  .dma_rxdesc  = esp32s3_spi3_dma_rxdesc,
+  .dma_txdesc  = esp32s3_spi3_dma_txdesc,
+#endif
   .frequency   = 0,
   .actual      = 0,
   .mode        = 0,
@@ -375,15 +419,6 @@ static struct esp32s3_spi_priv_s esp32s3_spi3_priv =
 };
 #endif /* CONFIG_ESP32S3_SPI3 */
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
-
-/* SPI DMA RX/TX description */
-
-static struct esp32s3_dmadesc_s dma_rxdesc[SPI_DMA_DESC_NUM];
-static struct esp32s3_dmadesc_s dma_txdesc[SPI_DMA_DESC_NUM];
-
-#endif
-
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -515,7 +550,7 @@ static int esp32s3_spi_lock(struct spi_dev_s *dev, bool lock)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
 static int esp32s3_spi_sem_waitdone(struct esp32s3_spi_priv_s *priv)
 {
   return nxsem_tickwait_uninterruptible(&priv->sem_isr, SEC2TICK(10));
@@ -824,7 +859,7 @@ static int esp32s3_spi_hwfeatures(struct spi_dev_s *dev,
  *
  ****************************************************************************/
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
 static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
                                      const void *txbuffer,
                                      void *rxbuffer,
@@ -869,8 +904,8 @@ static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
       esp32s3_spi_set_regbits(SPI_DMA_CONF_REG(priv->config->id),
                               SPI_DMA_TX_ENA_M);
 
-      n = esp32s3_dma_setup(channel, true, dma_txdesc, SPI_DMA_DESC_NUM,
+      n = esp32s3_dma_setup(channel, true, priv->dma_txdesc,
-                            tp, bytes);
+                            SPI_DMA_DESC_NUM, tp, bytes);
       esp32s3_dma_enable(channel, true);
 
       putreg32((n * 8 - 1), SPI_MS_DLEN_REG(priv->config->id));
@@ -886,8 +921,8 @@ static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
           esp32s3_spi_set_regbits(SPI_DMA_CONF_REG(priv->config->id),
                                   SPI_DMA_RX_ENA_M);
 
-          esp32s3_dma_setup(channel, false, dma_rxdesc, SPI_DMA_DESC_NUM,
+          esp32s3_dma_setup(channel, false, priv->dma_rxdesc,
-                            rp, bytes);
+                            SPI_DMA_DESC_NUM, rp, bytes);
           esp32s3_dma_enable(channel, false);
 
           esp32s3_spi_set_regbits(SPI_USER_REG(priv->config->id),
@@ -1158,8 +1193,8 @@ static void esp32s3_spi_exchange(struct spi_dev_s *dev,
 {
   struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
-  size_t thld = CONFIG_ESP32S3_SPI2_DMATHRESHOLD;
+  size_t thld = CONFIG_ESP32S3_SPI_DMATHRESHOLD;
 
   if (nwords > thld)
     {
@@ -1270,7 +1305,7 @@ static int esp32s3_spi_trigger(struct spi_dev_s *dev)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
 void esp32s3_spi_dma_init(struct spi_dev_s *dev)
 {
   struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
@@ -1389,7 +1424,7 @@ static void esp32s3_spi_init(struct spi_dev_s *dev)
   putreg32(VALUE_MASK(0, SPI_CS_HOLD_TIME),
            SPI_USER1_REG(priv->config->id));
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
   esp32s3_spi_dma_init(dev);
 #endif
 
@@ -1416,7 +1451,7 @@ static void esp32s3_spi_deinit(struct spi_dev_s *dev)
 {
   struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
   modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, priv->config->dma_clk_bit, 0);
 #endif
 
@@ -1445,7 +1480,7 @@ static void esp32s3_spi_deinit(struct spi_dev_s *dev)
  *
  ****************************************************************************/
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
 static int esp32s3_spi_interrupt(int irq, void *context, void *arg)
 {
   struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)arg;
@@ -1505,7 +1540,7 @@ struct spi_dev_s *esp32s3_spibus_initialize(int port)
       return spi_dev;
     }
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
   /* If a CPU Interrupt was previously allocated, then deallocate it */
 
   if (priv->cpuint != -ENOMEM)
@@ -1591,7 +1626,7 @@ int esp32s3_spibus_uninitialize(struct spi_dev_s *dev)
       return OK;
     }
 
-#ifdef CONFIG_ESP32S3_SPI2_DMA
+#ifdef CONFIG_ESP32S3_SPI_DMA
   up_disable_irq(priv->config->irq);
   esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
   irq_detach(priv->config->irq);