mirror of
https://github.com/apache/nuttx.git
synced 2026-05-20 04:16:35 +08:00
xtensa/esp32s3: SPI support quad I/O mode
This commit is contained in:
Dong Heng
committed by
Alan Carvalho de Assis
Alan Carvalho de Assis
parent
fa5db655cd
commit
8f25329260
@@ -594,9 +594,22 @@ config ESP32S3_RTCIO_IRQ
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menu "SPI configuration"
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depends on ESP32S3_SPI
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choice
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prompt "SPI I/O Mode"
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default ESP32S3_SPI_IO_SPI
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config ESP32S3_SPI_IO_SPI
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bool "SPI (4-line)"
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config ESP32S3_SPI_IO_QIO
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bool "QIO (6-line)"
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endchoice # SPI I/O Mode
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config ESP32S3_SPI_SWCS
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bool "SPI software CS"
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default n
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depends on ESP32S3_SPI_IO_SPI
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---help---
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Use SPI software CS.
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@@ -607,36 +620,34 @@ config ESP32S3_SPI_UDCS
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---help---
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Use user-defined CS.
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config ESP32S3_SPI_SLAVE_BUFSIZE
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int "SPI slave buffer size"
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default 2048
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depends on SPI_SLAVE
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if ESP32S3_SPI2
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config ESP32S3_SPI2_DMA
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bool "SPI2 use GDMA"
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config ESP32S3_SPI_DMA
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bool "SPI use GDMA"
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default n
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depends on ESP32S3_DMA
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select ESP32S3_DMA
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---help---
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Enable support for transfers using the GDMA engine.
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config ESP32S3_SPI2_DMADESC_NUM
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int "SPI2 Master GDMA maximum number of descriptors"
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default 2
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depends on ESP32S3_SPI2_DMA
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config ESP32S3_SPI_DMA_BUFSIZE
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int "SPI Master GDMA buffer size"
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default 2048
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depends on ESP32S3_SPI_DMA
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---help---
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Configure the maximum number of out-link/in-link descriptors to
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be chained for a GDMA transfer.
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This is used to calculate and allocate DMA description buffer,
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not really allocate TX/RX buffer.
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config ESP32S3_SPI2_DMATHRESHOLD
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int "SPI2 Master GDMA threshold"
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config ESP32S3_SPI_DMATHRESHOLD
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int "SPI Master GDMA threshold"
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default 64
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depends on ESP32S3_SPI2_DMA
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depends on ESP32S3_SPI_DMA && ESP32S3_SPI_IO_SPI
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---help---
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When SPI GDMA is enabled, GDMA transfers whose size are below the
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defined threshold will be performed by polling logic.
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config ESP32S3_SPI_SLAVE_BUFSIZE
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int "SPI Slave buffer size"
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default 2048
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depends on SPI_SLAVE
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config ESP32S3_SPI2_CSPIN
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int "SPI2 CS Pin"
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default 10
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@@ -657,16 +668,17 @@ config ESP32S3_SPI2_MISOPIN
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default 13
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range 0 48
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endif # ESP32S3_SPI2
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config ESP32S3_SPI2_IO2PIN
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int "SPI2 IO2 Pin"
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default 14
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range 0 48
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depends on ESP32S3_SPI_IO_QIO
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if ESP32S3_SPI3
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config ESP32S3_SPI3_DMA
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bool "SPI3 use GDMA"
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default n
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depends on ESP32S3_DMA
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---help---
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Enable support for transfers using the GDMA engine.
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config ESP32S3_SPI2_IO3PIN
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int "SPI2 IO3 Pin"
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default 9
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range 0 48
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depends on ESP32S3_SPI_IO_QIO
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config ESP32S3_SPI3_CSPIN
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int "SPI3 CS Pin"
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@@ -688,7 +700,17 @@ config ESP32S3_SPI3_MISOPIN
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default 2
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range 0 48
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endif # ESP32S3_SPI3
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config ESP32S3_SPI3_IO2PIN
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int "SPI3 IO2 Pin"
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default 3
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range 0 48
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depends on ESP32S3_SPI_IO_QIO
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config ESP32S3_SPI3_IO3PIN
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int "SPI3 IO3 Pin"
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default 4
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range 0 48
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depends on ESP32S3_SPI_IO_QIO
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endmenu # SPI configuration
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@@ -106,10 +106,15 @@ CHIP_CSRCS += esp32s3_i2c.c
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endif
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ifeq ($(CONFIG_ESP32S3_SPI),y)
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CHIP_CSRCS += esp32s3_spi.c
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ifeq ($(CONFIG_SPI_SLAVE),y)
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CHIP_CSRCS += esp32s3_spi_slave.c
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endif
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ifeq ($(CONFIG_ESP32S3_SPI_IO_SPI),y)
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CHIP_CSRCS += esp32s3_spi.c
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else
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CHIP_CSRCS += esp32s3_qspi.c
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endif
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ifeq ($(CONFIG_SPI_SLAVE),y)
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CHIP_CSRCS += esp32s3_spi_slave.c
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endif
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endif
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ifeq ($(CONFIG_ESP32S3_SPIFLASH),y)
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,126 @@
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/****************************************************************************
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* arch/xtensa/src/esp32s3/esp32s3_qspi.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_QSPI_H
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#define __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_QSPI_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/spi/qspi.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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#ifdef CONFIG_ESP32S3_SPI
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#ifdef CONFIG_ESP32S3_SPI2
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# define ESP32S3_SPI2 2
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#endif
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#ifdef CONFIG_ESP32S3_SPI3
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# define ESP32S3_SPI3 3
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Name: esp32s3_qspibus_set_attr
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*
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* Description:
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* Set attribution of QSPI bus transfer.
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*
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* Input Parameters:
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* dev - Device-specific state data
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* dummies - Number of dummy cycles, this only works in command
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* transfer, not works in memory transfer
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* addr_lines - Number of address transmiting I/O pins
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* data_lines - Number of data transmiting I/O pins
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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int esp32s3_qspibus_set_attr(struct qspi_dev_s *dev,
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uint8_t dummies,
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uint8_t addr_lines,
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uint8_t data_lines);
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/****************************************************************************
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* Name: esp32s3_qspibus_initialize
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*
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* Description:
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* Initialize the selected QSPI bus.
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*
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* Input Parameters:
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* port - Port number (for hardware that has multiple QSPI interfaces)
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*
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* Returned Value:
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* Valid QSPI device structure reference on success; NULL on failure
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*
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****************************************************************************/
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struct qspi_dev_s *esp32s3_qspibus_initialize(int port);
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/****************************************************************************
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* Name: esp32s3_qspibus_uninitialize
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*
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* Description:
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* Uninitialize an QSPI bus.
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*
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* Input Parameters:
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* dev - Device-specific state data
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*
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* Returned Value:
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* Zero (OK) is returned on success. Otherwise -1 (ERROR).
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*
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****************************************************************************/
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int esp32s3_qspibus_uninitialize(struct qspi_dev_s *dev);
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#ifdef __cplusplus
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}
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#endif
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#undef EXTERN
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#endif /* __ASSEMBLY__ */
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#endif /* CONFIG_ESP32S3_SPI */
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#endif /* __ARCH_XTENSA_SRC_ESP32S3_ESP32S3_QSPI_H */
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@@ -48,7 +48,7 @@
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#include "esp32s3_irq.h"
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#include "esp32s3_gpio.h"
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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#ifdef CONFIG_ESP32S3_SPI_DMA
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#include "esp32s3_dma.h"
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#endif
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@@ -71,11 +71,15 @@
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# define SPI_HAVE_SWCS 0
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#endif
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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#ifdef CONFIG_ESP32S3_SPI_DMA
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/* SPI DMA RX/TX number of descriptors */
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/* QSPI DMA RX/TX number of descriptors */
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#define SPI_DMA_DESC_NUM (CONFIG_ESP32S3_SPI2_DMADESC_NUM)
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# if (CONFIG_ESP32S3_SPI_DMA_BUFSIZE % ESP32S3_DMA_BUFLEN_MAX) > 0
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# define SPI_DMA_DESC_NUM (CONFIG_ESP32S3_SPI_DMA_BUFSIZE / ESP32S3_DMA_BUFLEN_MAX + 1)
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# else
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# define SPI_DMA_DESC_NUM (CONFIG_ESP32S3_SPI_DMA_BUFSIZE / ESP32S3_DMA_BUFLEN_MAX)
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# endif
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/* SPI DMA reset before exchange */
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@@ -123,13 +127,13 @@ struct esp32s3_spi_config_s
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uint8_t mosi_pin; /* GPIO configuration for MOSI */
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uint8_t miso_pin; /* GPIO configuration for MISO */
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uint8_t clk_pin; /* GPIO configuration for CLK */
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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#ifdef CONFIG_ESP32S3_SPI_DMA
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uint8_t periph; /* Peripheral ID */
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uint8_t irq; /* Interrupt ID */
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#endif
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uint32_t clk_bit; /* Clock enable bit */
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uint32_t rst_bit; /* SPI reset bit */
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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#ifdef CONFIG_ESP32S3_SPI_DMA
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uint32_t dma_clk_bit; /* DMA clock enable bit */
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uint32_t dma_rst_bit; /* DMA reset bit */
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#endif
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@@ -154,11 +158,16 @@ struct esp32s3_spi_priv_s
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const struct esp32s3_spi_config_s *config;
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int refs; /* Reference count */
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mutex_t lock; /* Held while chip is selected for mutual exclusion */
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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#ifdef CONFIG_ESP32S3_SPI_DMA
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sem_t sem_isr; /* Interrupt wait semaphore */
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int cpu; /* CPU ID */
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int cpuint; /* SPI interrupt ID */
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int32_t dma_channel; /* Channel assigned by the GDMA driver */
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/* DMA RX/TX description */
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struct esp32s3_dmadesc_s *dma_rxdesc;
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struct esp32s3_dmadesc_s *dma_txdesc;
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#endif
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uint32_t frequency; /* Requested clock frequency */
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uint32_t actual; /* Actual clock frequency */
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@@ -188,7 +197,7 @@ static uint32_t esp32s3_spi_send(struct spi_dev_s *dev, uint32_t wd);
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static void esp32s3_spi_exchange(struct spi_dev_s *dev,
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const void *txbuffer,
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void *rxbuffer, size_t nwords);
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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#ifdef CONFIG_ESP32S3_SPI_DMA
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static int esp32s3_spi_interrupt(int irq, void *context, void *arg);
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static int esp32s3_spi_sem_waitdone(struct esp32s3_spi_priv_s *priv);
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static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
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@@ -212,7 +221,7 @@ static void esp32s3_spi_recvblock(struct spi_dev_s *dev,
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#ifdef CONFIG_SPI_TRIGGER
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static int esp32s3_spi_trigger(struct spi_dev_s *dev);
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#endif
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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#ifdef CONFIG_ESP32S3_SPI_DMA
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static void esp32s3_spi_dma_init(struct spi_dev_s *dev);
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#endif
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static void esp32s3_spi_init(struct spi_dev_s *dev);
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@@ -233,13 +242,13 @@ static const struct esp32s3_spi_config_s esp32s3_spi2_config =
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.mosi_pin = CONFIG_ESP32S3_SPI2_MOSIPIN,
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.miso_pin = CONFIG_ESP32S3_SPI2_MISOPIN,
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.clk_pin = CONFIG_ESP32S3_SPI2_CLKPIN,
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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#ifdef CONFIG_ESP32S3_SPI_DMA
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.periph = ESP32S3_PERIPH_SPI2,
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.irq = ESP32S3_IRQ_SPI2,
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#endif
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.clk_bit = SYSTEM_SPI2_CLK_EN,
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.rst_bit = SYSTEM_SPI2_RST,
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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#ifdef CONFIG_ESP32S3_SPI_DMA
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.dma_clk_bit = SYSTEM_SPI2_DMA_CLK_EN,
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.dma_rst_bit = SYSTEM_SPI2_DMA_RST,
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#endif
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@@ -284,6 +293,15 @@ static const struct spi_ops_s esp32s3_spi2_ops =
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.registercallback = NULL,
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};
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#ifdef CONFIG_ESP32S3_SPI_DMA
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/* SPI DMA RX/TX description */
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static struct esp32s3_dmadesc_s esp32s3_spi2_dma_txdesc[SPI_DMA_DESC_NUM];
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static struct esp32s3_dmadesc_s esp32s3_spi2_dma_rxdesc[SPI_DMA_DESC_NUM];
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#endif
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static struct esp32s3_spi_priv_s esp32s3_spi2_priv =
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{
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.spi_dev =
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@@ -293,10 +311,12 @@ static struct esp32s3_spi_priv_s esp32s3_spi2_priv =
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.config = &esp32s3_spi2_config,
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.refs = 0,
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.lock = NXMUTEX_INITIALIZER,
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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#ifdef CONFIG_ESP32S3_SPI_DMA
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.sem_isr = SEM_INITIALIZER(0),
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.cpuint = -ENOMEM,
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.dma_channel = -1,
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.dma_rxdesc = esp32s3_spi2_dma_rxdesc,
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.dma_txdesc = esp32s3_spi2_dma_txdesc,
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#endif
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.frequency = 0,
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.actual = 0,
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@@ -316,8 +336,16 @@ static const struct esp32s3_spi_config_s esp32s3_spi3_config =
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.mosi_pin = CONFIG_ESP32S3_SPI3_MOSIPIN,
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.miso_pin = CONFIG_ESP32S3_SPI3_MISOPIN,
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.clk_pin = CONFIG_ESP32S3_SPI3_CLKPIN,
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#ifdef CONFIG_ESP32S3_SPI_DMA
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.periph = ESP32S3_PERIPH_SPI3,
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.irq = ESP32S3_IRQ_SPI3,
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#endif
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.clk_bit = SYSTEM_SPI3_CLK_EN,
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.rst_bit = SYSTEM_SPI3_RST,
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#ifdef CONFIG_ESP32S3_SPI_DMA
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.dma_clk_bit = SYSTEM_SPI3_DMA_CLK_EN,
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.dma_rst_bit = SYSTEM_SPI3_DMA_RST,
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#endif
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.cs_insig = FSPICS0_IN_IDX,
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.cs_outsig = FSPICS0_OUT_IDX,
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.mosi_insig = FSPID_IN_IDX,
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@@ -359,6 +387,15 @@ static const struct spi_ops_s esp32s3_spi3_ops =
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.registercallback = NULL,
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};
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#ifdef CONFIG_ESP32S3_SPI_DMA
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/* SPI DMA RX/TX description */
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static struct esp32s3_dmadesc_s esp32s3_spi3_dma_txdesc[SPI_DMA_DESC_NUM];
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static struct esp32s3_dmadesc_s esp32s3_spi3_dma_rxdesc[SPI_DMA_DESC_NUM];
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#endif
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static struct esp32s3_spi_priv_s esp32s3_spi3_priv =
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{
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.spi_dev =
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@@ -368,6 +405,13 @@ static struct esp32s3_spi_priv_s esp32s3_spi3_priv =
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.config = &esp32s3_spi3_config,
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.refs = 0,
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.lock = NXMUTEX_INITIALIZER,
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#ifdef CONFIG_ESP32S3_SPI_DMA
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.sem_isr = SEM_INITIALIZER(0),
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.cpuint = -ENOMEM,
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.dma_channel = -1,
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.dma_rxdesc = esp32s3_spi3_dma_rxdesc,
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.dma_txdesc = esp32s3_spi3_dma_txdesc,
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#endif
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.frequency = 0,
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.actual = 0,
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.mode = 0,
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@@ -375,15 +419,6 @@ static struct esp32s3_spi_priv_s esp32s3_spi3_priv =
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};
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#endif /* CONFIG_ESP32S3_SPI3 */
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#ifdef CONFIG_ESP32S3_SPI2_DMA
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/* SPI DMA RX/TX description */
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static struct esp32s3_dmadesc_s dma_rxdesc[SPI_DMA_DESC_NUM];
|
||||
static struct esp32s3_dmadesc_s dma_txdesc[SPI_DMA_DESC_NUM];
|
||||
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
@@ -515,7 +550,7 @@ static int esp32s3_spi_lock(struct spi_dev_s *dev, bool lock)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
#ifdef CONFIG_ESP32S3_SPI_DMA
|
||||
static int esp32s3_spi_sem_waitdone(struct esp32s3_spi_priv_s *priv)
|
||||
{
|
||||
return nxsem_tickwait_uninterruptible(&priv->sem_isr, SEC2TICK(10));
|
||||
@@ -824,7 +859,7 @@ static int esp32s3_spi_hwfeatures(struct spi_dev_s *dev,
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
#ifdef CONFIG_ESP32S3_SPI_DMA
|
||||
static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
|
||||
const void *txbuffer,
|
||||
void *rxbuffer,
|
||||
@@ -869,8 +904,8 @@ static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
|
||||
esp32s3_spi_set_regbits(SPI_DMA_CONF_REG(priv->config->id),
|
||||
SPI_DMA_TX_ENA_M);
|
||||
|
||||
n = esp32s3_dma_setup(channel, true, dma_txdesc, SPI_DMA_DESC_NUM,
|
||||
tp, bytes);
|
||||
n = esp32s3_dma_setup(channel, true, priv->dma_txdesc,
|
||||
SPI_DMA_DESC_NUM, tp, bytes);
|
||||
esp32s3_dma_enable(channel, true);
|
||||
|
||||
putreg32((n * 8 - 1), SPI_MS_DLEN_REG(priv->config->id));
|
||||
@@ -886,8 +921,8 @@ static void esp32s3_spi_dma_exchange(struct esp32s3_spi_priv_s *priv,
|
||||
esp32s3_spi_set_regbits(SPI_DMA_CONF_REG(priv->config->id),
|
||||
SPI_DMA_RX_ENA_M);
|
||||
|
||||
esp32s3_dma_setup(channel, false, dma_rxdesc, SPI_DMA_DESC_NUM,
|
||||
rp, bytes);
|
||||
esp32s3_dma_setup(channel, false, priv->dma_rxdesc,
|
||||
SPI_DMA_DESC_NUM, rp, bytes);
|
||||
esp32s3_dma_enable(channel, false);
|
||||
|
||||
esp32s3_spi_set_regbits(SPI_USER_REG(priv->config->id),
|
||||
@@ -1158,8 +1193,8 @@ static void esp32s3_spi_exchange(struct spi_dev_s *dev,
|
||||
{
|
||||
struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
size_t thld = CONFIG_ESP32S3_SPI2_DMATHRESHOLD;
|
||||
#ifdef CONFIG_ESP32S3_SPI_DMA
|
||||
size_t thld = CONFIG_ESP32S3_SPI_DMATHRESHOLD;
|
||||
|
||||
if (nwords > thld)
|
||||
{
|
||||
@@ -1270,7 +1305,7 @@ static int esp32s3_spi_trigger(struct spi_dev_s *dev)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
#ifdef CONFIG_ESP32S3_SPI_DMA
|
||||
void esp32s3_spi_dma_init(struct spi_dev_s *dev)
|
||||
{
|
||||
struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
|
||||
@@ -1389,7 +1424,7 @@ static void esp32s3_spi_init(struct spi_dev_s *dev)
|
||||
putreg32(VALUE_MASK(0, SPI_CS_HOLD_TIME),
|
||||
SPI_USER1_REG(priv->config->id));
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
#ifdef CONFIG_ESP32S3_SPI_DMA
|
||||
esp32s3_spi_dma_init(dev);
|
||||
#endif
|
||||
|
||||
@@ -1416,7 +1451,7 @@ static void esp32s3_spi_deinit(struct spi_dev_s *dev)
|
||||
{
|
||||
struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)dev;
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
#ifdef CONFIG_ESP32S3_SPI_DMA
|
||||
modifyreg32(SYSTEM_PERIP_CLK_EN0_REG, priv->config->dma_clk_bit, 0);
|
||||
#endif
|
||||
|
||||
@@ -1445,7 +1480,7 @@ static void esp32s3_spi_deinit(struct spi_dev_s *dev)
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
#ifdef CONFIG_ESP32S3_SPI_DMA
|
||||
static int esp32s3_spi_interrupt(int irq, void *context, void *arg)
|
||||
{
|
||||
struct esp32s3_spi_priv_s *priv = (struct esp32s3_spi_priv_s *)arg;
|
||||
@@ -1505,7 +1540,7 @@ struct spi_dev_s *esp32s3_spibus_initialize(int port)
|
||||
return spi_dev;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
#ifdef CONFIG_ESP32S3_SPI_DMA
|
||||
/* If a CPU Interrupt was previously allocated, then deallocate it */
|
||||
|
||||
if (priv->cpuint != -ENOMEM)
|
||||
@@ -1591,7 +1626,7 @@ int esp32s3_spibus_uninitialize(struct spi_dev_s *dev)
|
||||
return OK;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ESP32S3_SPI2_DMA
|
||||
#ifdef CONFIG_ESP32S3_SPI_DMA
|
||||
up_disable_irq(priv->config->irq);
|
||||
esp32s3_teardown_irq(priv->cpu, priv->config->periph, priv->cpuint);
|
||||
irq_detach(priv->config->irq);
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user