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Update DMA header file for the STM32F40xxx
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4108 42af7a65-404d-4744-a932-0658087f49c3
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patacongo
@@ -1,8 +1,8 @@
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/************************************************************************************
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* arch/arm/src/stm32/chip/stm32_dma.h
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* arch/arm/src/stm32/chip/stm32f10xxx_dma.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -33,8 +33,8 @@
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*
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************************************************************************************/
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H
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#ifndef __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H
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#define __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H
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/************************************************************************************
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* Pre-processor Definitions
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@@ -52,8 +52,8 @@
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/* Register Offsets *****************************************************************/
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#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
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#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
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#define STM32_DMA_ISR_OFFSET 0x0000 /* DMA interrupt status register */
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#define STM32_DMA_IFCR_OFFSET 0x0004 /* DMA interrupt flag clear register */
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#define STM32_DMACHAN_OFFSET(n) (0x0014*(n))
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#define STM32_DMACHAN_CCR_OFFSET 0x0008
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@@ -230,31 +230,31 @@
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/* DMA channel configuration register */
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#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
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#define DMA_CCR_PL_SHIFT (12) /* Bits 13-12: Channel Priority level */
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#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
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#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
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#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
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#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
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#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
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#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
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#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
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#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
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#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 8-9: Peripheral size */
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#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
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# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
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# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
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# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
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#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 10-11: Memory size */
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#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
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# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
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# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
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# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
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#define DMA_CCR_PL_SHIFT (12) /* Bits 12-13: Channel Priority level */
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#define DMA_CCR_PL_MASK (3 << DMA_CCR_PL_SHIFT)
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# define DMA_CCR_PRILO (0 << DMA_CCR_PL_SHIFT) /* 00: Low */
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# define DMA_CCR_PRIMED (1 << DMA_CCR_PL_SHIFT) /* 01: Medium */
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# define DMA_CCR_PRIHI (2 << DMA_CCR_PL_SHIFT) /* 10: High */
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# define DMA_CCR_PRIVERYHI (3 << DMA_CCR_PL_SHIFT) /* 11: Very high */
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#define DMA_CCR_MSIZE_SHIFT (10) /* Bits 11-10: Memory size */
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#define DMA_CCR_MSIZE_MASK (3 << DMA_CCR_MSIZE_SHIFT)
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# define DMA_CCR_MSIZE_8BITS (0 << DMA_CCR_MSIZE_SHIFT) /* 00: 8-bits */
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# define DMA_CCR_MSIZE_16BITS (1 << DMA_CCR_MSIZE_SHIFT) /* 01: 16-bits */
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# define DMA_CCR_MSIZE_32BITS (2 << DMA_CCR_MSIZE_SHIFT) /* 10: 32-bits */
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#define DMA_CCR_PSIZE_SHIFT (8) /* Bits 9-8: Peripheral size */
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#define DMA_CCR_PSIZE_MASK (3 << DMA_CCR_PSIZE_SHIFT)
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# define DMA_CCR_PSIZE_8BITS (0 << DMA_CCR_PSIZE_SHIFT) /* 00: 8-bits */
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# define DMA_CCR_PSIZE_16BITS (1 << DMA_CCR_PSIZE_SHIFT) /* 01: 16-bits */
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# define DMA_CCR_PSIZE_32BITS (2 << DMA_CCR_PSIZE_SHIFT) /* 10: 32-bits */
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#define DMA_CCR_MINC (1 << 7) /* Bit 7: Memory increment mode */
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#define DMA_CCR_PINC (1 << 6) /* Bit 6: Peripheral increment mode */
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#define DMA_CCR_CIRC (1 << 5) /* Bit 5: Circular mode */
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#define DMA_CCR_DIR (1 << 4) /* Bit 4: Data transfer direction */
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#define DMA_CCR_TEIE (1 << 3) /* Bit 3: Transfer error interrupt enable */
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#define DMA_CCR_HTIE (1 << 2) /* Bit 2: Half Transfer interrupt enable */
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#define DMA_CCR_TCIE (1 << 1) /* Bit 1: Transfer complete interrupt enable */
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#define DMA_CCR_EN (1 << 0) /* Bit 0: Channel enable */
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#define DMA_CCR_MEM2MEM (1 << 14) /* Bit 14: Memory to memory mode */
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#define DMA_CCR_ALLINTS (DMA_CCR_TEIE|DMA_CCR_HTIE|DMA_CCR_TCIE)
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@@ -347,5 +347,5 @@
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#define DMACHAN_TIM5_CH1 STM32_DMA2_CHAN5
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#define DMACHAN_TIM8_CH2 STM32_DMA2_CHAN5
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32_DMA_H */
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#endif /* __ARCH_ARM_SRC_STM32_CHIP_STM32F10XXX_DMA_H */
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File diff suppressed because it is too large
Load Diff
@@ -2,7 +2,7 @@
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* arch/arm/src/stm32/stm32_dma.c
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*
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* Copyright (C) 2009 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -2,7 +2,7 @@
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* arch/arm/src/stm32/stm32_dma.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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@@ -44,7 +44,14 @@
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#include <sys/types.h>
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#include "chip.h"
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#include "chip/stm32_dma.h"
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#if defined(CONFIG_STM32_STM32F10XX)
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# include "chip/stm32f10xxx_dma.h"
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#elif defined(CONFIG_STM32_STM32F40XX)
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# include "chip/stm32f40xxx_dma.h"
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#else
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# error "Unknown STM32 DMA"
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#endif
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/************************************************************************************
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* Public Types
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