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Remove trailing spaces at the end of lines.

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This commit is contained in:
Gregory Nutt
2018-08-13 07:39:38 -06:00
parent 81c6bda341
commit 8c61c2f31b
71 changed files with 153 additions and 153 deletions
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ChangeLog
+3 -3
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@@ -18170,7 +18170,7 @@
almost complete... still lacking GPIO support and LED support. There are
still no significant drivers available.
* SMP: Introduce spin_lock_irqsave() and spin_unlock_irqrestore(). These
APIs are simplified version of enter_critical_section() and
APIs are simplified version of enter_critical_section() and
leave_critical_section() to protect data (e.g. registers) in SMP mode. By
using these APIs inside drivers, performance will be improved. From
Masayuki Ishikawa (2017-12-07).
@@ -18660,7 +18660,7 @@
longer returns an errno. From Gregory Nutt (2018-01-31).
* graphics/: Review return values for all calls to kthread_start() because
it no longer returns an errno. From Gregory Nutt (2018-01-31).
* sched/: Convert legitimate uses of task_create() to nxtask_create().
* sched/: Convert legitimate uses of task_create() to nxtask_create().
Review handling of returned values from all uses of kthread_create() (as
well as nxtask_create()). From Gregory Nutt (2018-01-31).
* arm/src/kinetis: Correct some Ethernet PHY register bit tests for the
@@ -18815,7 +18815,7 @@
Mayencourt (2018-02-19).
* drivers/mtd: mtd_config.c: Add still more error handling (to detect bad
underlying flash implementations). Remove MTD_ERASE that was erasing data
block instead of erase block. This is a partial revert of 4f18b4.
block instead of erase block. This is a partial revert of 4f18b4.
Reported-by: Pascal Speck <iktek01@yahoo.com>
* arch/arm/src/stm32l4: stm32l4_flash: change flash programming to use
page buffer for unaligned writes. From Juha Niskanen (2018-02-19).
Documentation/NuttxPortingGuide.html
+1 -1
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@@ -487,7 +487,7 @@
As an example, all ARM processor architectures are provided under the <code>arch/arm/</code> directory which is selected with the <code>CONFIG_ARCH=&quot;arm&quot;</code> configuration option.
</p>
<p>
Variants of the processor architecture may be provided in sub-directories of the
Variants of the processor architecture may be provided in sub-directories of the
Extending this example, the ARMv7-M ARM family is supported by logic in <code>arch/arm/include/armv7-m</code> and <code>arch/arm/src/armv7-m</code> directories which are selected by the <code>CONFIG_ARCH_CORTEXM3=y</code>, <code>CONFIG_ARCH_CORTEXM4=y</code>, or <code>CONFIG_ARCH_CORTEXM7=y</code> configuration options
</p>
</li>
arch/arm/include/stm32f7/stm32f72xx73xx_irq.h
+2 -2
View File
@@ -33,8 +33,8 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*Change Record:
* bf20171107 Created file. It's identical to stm32f74xx75xx_irq except for the
* exclusions noted by this tag, and the addition of the last IRQ
* bf20171107 Created file. It's identical to stm32f74xx75xx_irq except for the
* exclusions noted by this tag, and the addition of the last IRQ
* for SDMMC2 (IRQ103).
****************************************************************************************************/
arch/arm/src/armv7-a/arm_vectors.S
+1 -1
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@@ -62,7 +62,7 @@ g_undeftmp:
g_aborttmp:
.word 0 /* Saved lr */
.word 0 /* Saved spsr */
#ifdef CONFIG_ARMV7A_DECODEFIQ
g_fiqtmp:
.word 0 /* Saved lr */
arch/arm/src/lc823450/lc823450_mtd.h
+1 -1
View File
@@ -71,7 +71,7 @@
#define LC823450_PART5_START (LC823450_PART4_START + LC823450_PART4_NBLOCKS)
#define LC823450_PART5_NBLOCKS 32768
#define LC823450_PART6_START (LC823450_PART5_START + LC823450_PART5_NBLOCKS)
#define LC823450_PART6_NBLOCKS 131072
#define LC823450_PART6_NBLOCKS 131072
#define LC823450_PART7_START (LC823450_PART6_START + LC823450_PART6_NBLOCKS)
#define LC823450_PART7_NBLOCKS 32768
#define LC823450_PART8_START (LC823450_PART7_START + LC823450_PART7_NBLOCKS)
arch/arm/src/lc823450/lc823450_sddrv_if.h
+1 -1
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@@ -251,7 +251,7 @@ SINT_T fixedSdDrReadSector(UI_32 addr, UI_32 cnt, void *buf, SINT_T type,
struct SdDrCfg_s *cfg);
UI_32 sdif_get_status(UI_32);
#if defined(__cplusplus)
}
#endif
arch/arm/src/lc823450/lc823450_serial.c
+1 -1
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@@ -280,7 +280,7 @@ static uart_dev_t g_uart0port =
.size = CONFIG_UART0_RXBUFSIZE,
.buffer = g_uart0rxbuffer,
},
.xmit =
.xmit =
{
.size = CONFIG_UART0_TXBUFSIZE,
.buffer = g_uart0txbuffer,
arch/arm/src/lpc54xx/lpc54_emc.c
+1 -1
View File
@@ -491,7 +491,7 @@ void lpc54_emc_sram_initialize(FAR uint32_t *extwait,
unsigned int i;
/* Initialize extended wait. */
DEBUGASSERT(statconfig != NULL && nchips > 0);
if (extwait)
arch/arm/src/lpc54xx/lpc54_emc.h
+1 -1
View File
@@ -175,7 +175,7 @@ struct emc_static_chip_config_s
* read access in units of nanoseconds */
uint32_t waitreadpage; /* In page mode, the read after the first read
* wait states in units of nanoseconds */
uint32_t waitwrite; /* The delay from chip select to write access in
uint32_t waitwrite; /* The delay from chip select to write access in
* units of nanoseconds */
uint32_t waitturn; /* The Bus turn-around time in units of
* nanoseconds */
arch/arm/src/samd2l2/sam_usb.c
+3 -3
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@@ -3793,16 +3793,16 @@ static void sam_hw_setup(struct sam_usbdev_s *priv)
/* Load USB factory calibration values from NVRAM */
calib_transn = getreg32(SYSCTRL_FUSES_USBTRANSN_ADDR) &
calib_transn = getreg32(SYSCTRL_FUSES_USBTRANSN_ADDR) &
SYSCTRL_FUSES_USBTRANSN_MASK >> SYSCTRL_FUSES_USBTRANSN_SHIFT;
calib_transp = getreg32(SYSCTRL_FUSES_USBTRANSP_ADDR) &
calib_transp = getreg32(SYSCTRL_FUSES_USBTRANSP_ADDR) &
SYSCTRL_FUSES_USBTRANSP_MASK >> SYSCTRL_FUSES_USBTRANSP_SHIFT;
calib_trim = getreg32(SYSCTRL_FUSES_USBTRIM_ADDR) &
SYSCTRL_FUSES_USBTRIM_MASK >> SYSCTRL_FUSES_USBTRIM_SHIFT;
padcalib = USB_PADCAL_TRANSP(calib_transp) |
padcalib = USB_PADCAL_TRANSP(calib_transp) |
USB_PADCAL_TRANSN(calib_transn) |
USB_PADCAL_TRIM(calib_trim);
arch/arm/src/samd5e5/chip/sam_usart.h
+1 -1
View File
@@ -294,7 +294,7 @@
#define USART_CTRLC_BRKLEN_SHIFT (8) /* Bits 8-9: LIN Master Break Length */
#define USART_CTRLC_BRKLEN_MASK (3 << USART_CTRLC_BRKLEN_SHIFT)
# define USART_CTRLC_BRKLEN_13BITS (0 << USART_CTRLC_BRKLEN_SHIFT) /* 13 bit times */
# define USART_CTRLC_BRKLEN_17BITS (1 << USART_CTRLC_BRKLEN_SHIFT) /* 17 bit times */
# define USART_CTRLC_BRKLEN_17BITS (1 << USART_CTRLC_BRKLEN_SHIFT) /* 17 bit times */
# define USART_CTRLC_BRKLEN_21BITS (2 << USART_CTRLC_BRKLEN_SHIFT) /* 21 bit times */
# define USART_CTRLC_BRKLEN_26BITS (3 << USART_CTRLC_BRKLEN_SHIFT) /* 26 bit times */
#define USART_CTRLC_HDRDLY_SHIFT (10) /* Bits 10-11: LIN Master Header Delay */
arch/arm/src/stm32/chip.h
+1 -1
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@@ -47,7 +47,7 @@
#include <arch/stm32/chip.h>
/* Include the chip interrupt definition file */
#include <arch/stm32/irq.h>
/* Include the chip pin configuration file */
arch/arm/src/stm32f7/chip/stm32f72xx73xx_rcc.h
+1 -1
View File
@@ -140,7 +140,7 @@
# define RCC_PLLCFG_PLLN(n) ((n) << RCC_PLLCFG_PLLN_SHIFT) /* n = 2..432 */
#define RCC_PLLCFG_PLLP_SHIFT (16) /* Bits 16-17: Main PLL (PLL) main system clock divider */
#define RCC_PLLCFG_PLLP_MASK (3 << RCC_PLLCFG_PLLP_SHIFT)
# define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */
# define RCC_PLLCFG_PLLP(n) ((((n)>>1)-1)<< RCC_PLLCFG_PLLP_SHIFT) /* n=2,4,6,8 */
# define RCC_PLLCFG_PLLP_2 (0 << RCC_PLLCFG_PLLP_SHIFT) /* 00: PLLP = 2 */
# define RCC_PLLCFG_PLLP_4 (1 << RCC_PLLCFG_PLLP_SHIFT) /* 01: PLLP = 4 */
# define RCC_PLLCFG_PLLP_6 (2 << RCC_PLLCFG_PLLP_SHIFT) /* 10: PLLP = 6 */
arch/arm/src/stm32f7/chip/stm32f72xx73xx_syscfg.h
+1 -1
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@@ -54,7 +54,7 @@
#define STM32_SYSCFG_MEMRMP_OFFSET 0x0000 /* SYSCFG memory remap register */
#define STM32_SYSCFG_PMC_OFFSET 0x0004 /* SYSCFG peripheral mode configuration register */
#define STM32_SYSCFG_EXTICR_OFFSET(p) (0x0008 + ((p) & 0x000c)) /* Registers are displaced by 4! */
#define STM32_SYSCFG_EXTICR1_OFFSET 0x0008 /* SYSCFG external interrupt configuration register 1 */
#define STM32_SYSCFG_EXTICR2_OFFSET 0x000c /* SYSCFG external interrupt configuration register 2 */
arch/arm/src/stm32f7/chip/stm32f72xx73xx_uart.h
+1 -1
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@@ -44,7 +44,7 @@
#include <nuttx/config.h>
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
#if defined(CONFIG_STM32F7_STM32F72XX) || defined(CONFIG_STM32F7_STM32F73XX)
/************************************************************************************
* Pre-processor Definitions
arch/arm/src/stm32f7/stm32_dma2d.c
+1 -1
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@@ -735,7 +735,7 @@ static void stm32_dma2d_lpfc(int lid, uint32_t blendmode, uint8_t alpha,
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: stm32_dma2d_setclut
*
arch/avr/include/avr32/irq.h
+1 -1
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@@ -185,7 +185,7 @@ static inline irqstate_t up_irq_save(void)
/* Restore saved interrupt state */
static inline void up_irq_restore(irqstate_t flags)
{
{
if ((flags & AVR32_SR_GM_MASK) == 0)
{
__asm__ __volatile__ (
arch/or1k/include/spr.h
+1 -1
View File
@@ -232,7 +232,7 @@
#define SPR_CPUCFGR_NSGF_SHIFT (0)
#define SPR_CPUCFGR_NSGF_MASK (0xf << SPR_CPUCFGR_NSGF_SHIFT)
#define SPR_CPUCFGR_CGF (1 << 4)
#define SPR_CPUCFGR_CGF (1 << 4)
#define SPR_CPUCFGR_OB32S (1 << 5) /* ORBIS32 Supported */
#define SPR_CPUCFGR_OB64S (1 << 6) /* ORBIS64 Supported */
#define SPR_CPUCFGR_OF32S (1 << 7) /* ORFPX32 Supported */
arch/or1k/src/common/up_task_start.c
+1 -1
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@@ -77,7 +77,7 @@
void up_task_start(main_t taskentry, int argc, FAR char *argv[])
{
/* Let sys_call3() do all of the work */
sinfo("entry %p argc %d\n", taskentry, argc);
sys_call3(SYS_task_start, (uintptr_t)taskentry, (uintptr_t)argc,
arch/or1k/src/common/up_timer.c
+4 -4
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@@ -77,7 +77,7 @@ static int or1k_timer_isr(int irq, uint32_t *regs, void *arg)
mtspr(SPR_TICK_TTMR, ttmr);
sched_process_timer();
return OK;
}
@@ -89,7 +89,7 @@ static int or1k_timer_isr(int irq, uint32_t *regs, void *arg)
* Name: or1k_timer_initialize
*
* Description:
* Initialize the OpenRISC Tick Timer unit
* Initialize the OpenRISC Tick Timer unit
*
****************************************************************************/
@@ -104,6 +104,6 @@ void or1k_timer_initialize(void)
mtspr(SPR_TICK_TTCR, 0);
/* Write TTMR */
mtspr(SPR_TICK_TTMR, ttmr);
mtspr(SPR_TICK_TTMR, ttmr);
}
arch/or1k/src/mor1kx/Make.defs
+1 -1
View File
@@ -81,7 +81,7 @@ ifeq ($(CONFIG_DEBUG_FEATURES),y)
endif
CHIP_ASRCS =
CHIP_CSRCS =
CHIP_CSRCS =
ifneq ($(CONFIG_SCHED_TICKLESS),y)
#CHIP_CSRCS += sam_timerisr.c
arch/or1k/src/mor1kx/up_vectortab.S
+5 -5
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@@ -250,7 +250,7 @@ _reset_vector:
/* Set the stack pointer */
l.movhi r1,hi(_ebss);
l.ori r1,r1,lo(_ebss);
l.ori r1,r1,lo(_ebss);
l.addi r1,r1,CONFIG_IDLETHREAD_STACKSIZE-4;
l.ori r2,r1,0;
l.nop
@@ -262,7 +262,7 @@ _reset_vector:
l.nop;
/* Should never reach here */
l.j 0;
l.nop;
@@ -281,7 +281,7 @@ _data_page_fault:
l.nop;
l.j 0;
l.nop;
/* Instruction page fault */
.org 0x400
@@ -289,7 +289,7 @@ _instruction_page_fault:
l.nop;
l.j 0;
l.nop;
/* Tick Timer */
.org 0x500
@@ -354,7 +354,7 @@ _itlb_miss:
/* Range exception */
.org 0xB00
.org 0xB00
_range_exception:
l.nop;
l.j 0;
configs/bambino-200e/src/lpc43_max31855.c
+1 -1
View File
@@ -96,7 +96,7 @@ int lpc43_max31855initialize(FAR const char *devpath, int bus, uint16_t devid)
{
snerr("ERROR: Error registering MAX31855\n");
}
return ret;
}
configs/bambino-200e/src/lpc43_ssp.c
+4 -4
View File
@@ -76,12 +76,12 @@ void weak_function lpc43_sspdev_initialize(void)
{
snerr("ERROR: Error configuring chip select GPIO pin\n");
}
lpc43_pin_config(PINCONFIG_MAX31855_CS2);
ret = lpc43_gpio_config(GPIO_MAX31855_CS2);
if (ret < 0)
{
snerr("ERROR: Error configuring chip select GPIO pin\n")
snerr("ERROR: Error configuring chip select GPIO pin\n")
}
#endif
}
@@ -108,7 +108,7 @@ void lpc43_ssp0select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
{
lpc43_gpio_write(GPIO_MAX31855_CS1, !selected);
}
if (devid == SPIDEV_TEMPERATURE(1))
{
lpc43_gpio_write(GPIO_MAX31855_CS2, !selected);
@@ -157,7 +157,7 @@ void lpc43_ssp1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected)
{
lpc43_gpio_write(GPIO_MAX31855_CS1, !selected);
}
if (devid == SPIDEV_TEMPERATURE(1))
{
lpc43_gpio_write(GPIO_MAX31855_CS2, !selected);
configs/imxrt1050-evk/src/imxrt_buttons.c
+1 -1
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@@ -18,7 +18,7 @@
* used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORSMULTILINK
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
configs/lc823450-xgevk/README.txt
+2 -2
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@@ -57,12 +57,12 @@ index 687f50ca..8418eff8 100644
+++ b/examples/ostest/waitpid.c
@@ -54,7 +54,7 @@
****************************************************************************/
#define RETURN_STATUS 14
-#define NCHILDREN 3
+#define NCHILDREN 2
#define PRIORITY 100
/****************************************************************************
Other Status
configs/lpc4357-evb/README.txt
+1 -1
View File
@@ -373,7 +373,7 @@ FPU Configuration Options
-------------------------
There are two version of the FPU support built into the most NuttX Cortex-M4
ports.
ports.
1. Non-Lazy Floating Point Register Save
configs/metro-m4/src/sam_autoleds.c
+1 -1
View File
@@ -53,7 +53,7 @@
* ------------------- ---------------------------- ------
* SYMBOL Meaning LED
* ------------------- ---------------------------- ------
*
*
* LED_STARTED NuttX has been started OFF
* LED_HEAPALLOCATE Heap has been allocated OFF
* LED_IRQSENABLED Interrupts enabled OFF
configs/metro-m4/src/sam_boot.c
+1 -1
View File
@@ -55,7 +55,7 @@
* Name: sam_board_initialize
*
* Description:
* All SAMD5/E5 architectures must provide the following entry point.
* All SAMD5/E5 architectures must provide the following entry point.
* This entry point is called early in the initialization -- after all
* memory has been configured and mapped but before any devices have been
* initialized.
configs/nucleo-f410rb/include/board.h
+1 -1
View File
@@ -146,7 +146,7 @@
#define STM32_APB2_TIM11_CLKIN (STM32_PCLK2_FREQUENCY)
/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
* otherwise frequency is 2xAPBx.
* otherwise frequency is 2xAPBx.
* Note: TIM1,9,11 are on APB2, others on APB1
*/
/* REVISIT */
configs/nucleo-f410rb/src/stm32_boot.c
+1 -1
View File
@@ -80,7 +80,7 @@ void stm32_boardinitialize(void)
#ifdef CONFIG_ARCH_BUTTONS
/* Configure on-board BUTTONs if BUTTON support has been selected. */
board_button_initialize();
#endif
}
configs/nucleo-l476rg/src/stm32_gpio.c
+1 -1
View File
@@ -330,7 +330,7 @@ int stm32l4_gpio_initialize(void)
pincount++;
}
#endif
return 0;
}
#endif /* CONFIG_DEV_GPIO && !CONFIG_GPIO_LOWER_HALF */
configs/or1k/src/or1k_autoled.c
+1 -1
View File
@@ -78,7 +78,7 @@ void board_autoled_initialize(void)
/* Set the or1k GPIO direction register to output */
/* The Terasic C5G has 18 LEDs on GPIO0[0:17] */
*led_dir = 0x3fff;
*led_data = 0x0;
}
configs/stm32f4discovery/README.txt
+1 -1
View File
@@ -1204,7 +1204,7 @@ Configuration Sub-directories
1. Prepare USB flash storage. This configuration depends on .WAV files
provided to the system via a USB flash stick. There are some sample
audio files at https://github.com/tdrozdovskiy/CS43L22-Audio-driver
and these steps will put those sample .WAV files onto the USB flash:
and these steps will put those sample .WAV files onto the USB flash:
a. Format the USB flash storage into FAT. For example by next command
configs/stm32f4discovery/src/stm32_lis3dsh.c
+2 -2
View File
@@ -105,7 +105,7 @@ int attach_disc_lis3dsh(FAR struct lis3dsh_config_s *config, xcpt_t interrupt_ha
* Zero (OK) on success; a negated errno value on failure.
*
************************************************************************************/
int stm32_lis3dshinitialize(FAR const char *devpath)
{
static struct lis3dsh_config_s acc0_config;
@@ -113,7 +113,7 @@ int stm32_lis3dshinitialize(FAR const char *devpath)
int ret;
sninfo("Initializing LIS3DSH\n");
acc0_config.irq=22;
acc0_config.spi_devid=0;
acc0_config.attach = &attach_disc_lis3dsh;
configs/stm32f746g-disco/include/board.h
+1 -1
View File
@@ -406,7 +406,7 @@
/* Vertical Sync Polarity */
#define BOARD_LTDC_GCR_VSPOL 0 /* !LTDC_GCR_VSPOL */
/* Horicontal Sync Polarity */
#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */
#define BOARD_LTDC_GCR_HSPOL 0 /* !LTDC_GCR_HSPOL */
/* GPIO pinset */
configs/stm32l476-mdk/src/stm32_autoleds.c
+1 -1
View File
@@ -54,7 +54,7 @@
*
* ------------------ ------------------------ ------
* SYMBOL Meaning LED
* ------------------ ------------------------ ------
* ------------------ ------------------------ ------
*
* LED_STARTED NuttX has been started OFF
* LED_HEAPALLOCATE Heap has been allocated OFF
drivers/analog/dac7571.c
+1 -1
View File
@@ -222,7 +222,7 @@ static int dac7571_send(FAR struct dac_dev_s *dev, FAR struct dac_msg_s *msg)
/* Then perform the transfer. */
ret = i2c_write(priv->i2c, &config, buffer, BUFFER_SIZE);
ret = i2c_write(priv->i2c, &config, buffer, BUFFER_SIZE);
if (ret < 0)
{
aerr("ERROR: dac7571_send failed code:%d\n", ret);
drivers/lcd/max7219.c
+1 -1
View File
@@ -841,7 +841,7 @@ static inline void up_clear(FAR struct max7219_dev_s *priv)
* spi - An instance of the SPI interface to use to communicate
* with the MAX7219.
* devno - Device number to identify current display.
*
*
* Returned Value:
* Zero (OK) on success; a negated errno value on failure.
*
drivers/sensors/adxl372.c
+1 -1
View File
@@ -570,7 +570,7 @@ static ssize_t adxl372_dvr_read(FAR void *instance_handle, FAR char *buffer,
size_t buflen)
{
FAR struct adxl372_dev_s *priv = ((FAR struct adxl372_dev_s *)instance_handle);
union
union
{
int16_t d16;
char d8[2];
drivers/sensors/apds9960.c
+23 -23
View File
@@ -218,16 +218,16 @@ static void apds9960_resetgesture(FAR struct apds9960_dev_s *priv)
{
priv->gesture_data.index = 0;
priv->gesture_data.total_gestures = 0;
priv->gesture_ud_delta = 0;
priv->gesture_lr_delta = 0;
priv->gesture_ud_count = 0;
priv->gesture_lr_count = 0;
priv->gesture_near_count = 0;
priv->gesture_far_count = 0;
priv->gesture_state = 0;
}
@@ -288,7 +288,7 @@ static int apds9960_setdefault(FAR struct apds9960_dev_s *priv)
}
/* Set LED driver strength to 100mA, AGAIN 4X and PGAIN 4X */
ret = apds9960_i2c_write8(priv, APDS9960_CONTROL, DEFAULT_CONTROL);
if (ret < 0)
{
@@ -443,7 +443,7 @@ static int apds9960_setdefault(FAR struct apds9960_dev_s *priv)
return ret;
}
return OK;
return OK;
}
/****************************************************************************
@@ -600,7 +600,7 @@ static bool apds9960_isgestureavailable(FAR struct apds9960_dev_s *priv)
{
int ret;
uint8_t val;
/* Read value from GSTATUS register */
ret = apds9960_i2c_read8(priv, APDS9960_GSTATUS, &val);
@@ -656,7 +656,7 @@ static bool apds9960_processgesture(FAR struct apds9960_dev_s *priv)
priv->gesture_data.total_gestures);
return false;
}
/* Check to make sure our data isn't out of bounds */
if ((priv->gesture_data.total_gestures <= 32) && \
@@ -678,7 +678,7 @@ static bool apds9960_processgesture(FAR struct apds9960_dev_s *priv)
break;
}
}
/* If one of the _first values is 0, then there is no good data */
if ((u_first == 0) || (d_first == 0) || \
@@ -712,14 +712,14 @@ static bool apds9960_processgesture(FAR struct apds9960_dev_s *priv)
}
}
}
/* Calculate the first vs. last ratio of up/down and left/right */
ud_ratio_first = ((u_first - d_first) * 100) / (u_first + d_first);
lr_ratio_first = ((l_first - r_first) * 100) / (l_first + r_first);
ud_ratio_last = ((u_last - d_last) * 100) / (u_last + d_last);
lr_ratio_last = ((l_last - r_last) * 100) / (l_last + r_last);
sninfo("Last Values: \n");
sninfo("U: %03d\n", u_last);
sninfo("D: %03d\n", d_last);
@@ -736,7 +736,7 @@ static bool apds9960_processgesture(FAR struct apds9960_dev_s *priv)
ud_delta = ud_ratio_last - ud_ratio_first;
lr_delta = lr_ratio_last - lr_ratio_first;
sninfo("Deltas: \n");
sninfo("UD: %03d\n", ud_delta);
sninfo("LR: %03d\n", lr_delta);
@@ -745,11 +745,11 @@ static bool apds9960_processgesture(FAR struct apds9960_dev_s *priv)
priv->gesture_ud_delta += ud_delta;
priv->gesture_lr_delta += lr_delta;
sninfo("Accumulations: \n");
sninfo("UD: %03d\n", priv->gesture_ud_delta);
sninfo("LR: %03d\n", priv->gesture_lr_delta);
/* Determine U/D gesture */
if (priv->gesture_ud_delta >= GESTURE_SENSITIVITY_1)
@@ -767,7 +767,7 @@ static bool apds9960_processgesture(FAR struct apds9960_dev_s *priv)
priv->gesture_ud_count = 0;
}
}
/* Determine L/R gesture */
if (priv->gesture_lr_delta >= GESTURE_SENSITIVITY_1)
@@ -804,7 +804,7 @@ static bool apds9960_processgesture(FAR struct apds9960_dev_s *priv)
priv->gesture_far_count++;
}
}
if ((priv->gesture_near_count >= 10) && \
(priv->gesture_far_count >= 2))
{
@@ -833,7 +833,7 @@ static bool apds9960_processgesture(FAR struct apds9960_dev_s *priv)
{
priv->gesture_near_count++;
}
if (priv->gesture_near_count >= 10)
{
priv->gesture_ud_count = 0;
@@ -843,13 +843,13 @@ static bool apds9960_processgesture(FAR struct apds9960_dev_s *priv)
}
}
}
sninfo(" UD_CT: %03d\n", priv->gesture_ud_count);
sninfo(" LR_CT: %03d\n", priv->gesture_lr_count);
sninfo(" NEAR_CT: %03d\n", priv->gesture_near_count);
sninfo(" FAR_CT: %03d\n", priv->gesture_far_count);
sninfo("----------------------\n");
return false;
}
@@ -996,7 +996,7 @@ static int apds9960_readgesture(FAR struct apds9960_dev_s *priv)
int motion;
int ret;
int i;
/* Make sure that power and gesture is on and data is valid */
if (!apds9960_isgestureavailable(priv))
@@ -1011,7 +1011,7 @@ static int apds9960_readgesture(FAR struct apds9960_dev_s *priv)
/* Wait some time to collect next batch of FIFO data */
nxsig_usleep(FIFO_PAUSE_TIME);
/* Get the contents of the STATUS register. Is data still valid? */
ret = apds9960_i2c_read8(priv, APDS9960_GSTATUS, &gstatus);
@@ -1020,7 +1020,7 @@ static int apds9960_readgesture(FAR struct apds9960_dev_s *priv)
snerr("ERROR: Failed to read APDS9960_GSTATUS!\n");
return ret;
}
/* If we have valid data, read in FIFO */
if ((gstatus & GVALID) == GVALID)
@@ -1091,7 +1091,7 @@ static int apds9960_readgesture(FAR struct apds9960_dev_s *priv)
//sninfo("gesture_motion = %d\n", gesture_motion);
}
}
/* Reset data */
priv->gesture_data.index = 0;
drivers/sensors/lsm330_spi.c
+1 -1
View File
@@ -1095,7 +1095,7 @@ static int lsm330_dvr_ioctl(FAR void *instance_handle, int cmd,
* None
*
******************************************************************************/
static void lsm330_dvr_exchange(FAR void *instance_handle,
FAR const void *txbuffer,
FAR void *rxbuffer, size_t nwords)
drivers/usbdev/rndis_std.h
+1 -1
View File
@@ -173,7 +173,7 @@ struct rndis_query_cmplt
uint32_t buffer[]; /* Buffer */
};
struct rndis_set_msg
struct rndis_set_msg
{
struct rndis_command_header hdr;
uint32_t objid; /* ObjectID */
drivers/usbdev/usbmsc.h
+1 -1
View File
@@ -310,7 +310,7 @@
#define USBMSC_MKEPBULKOUT(devDesc) ((devDesc)->epno[USBMSC_EP_BULKOUT_IDX])
#define USBMSC_EPOUTBULK_ATTR (USB_EP_ATTR_XFER_BULK)
#define USBMSC_MKEPBULKIN(devDesc) (USB_DIR_IN | (devDesc)->epno[USBMSC_EP_BULKIN_IDX])
#define USBMSC_MKEPBULKIN(devDesc) (USB_DIR_IN | (devDesc)->epno[USBMSC_EP_BULKIN_IDX])
#define USBMSC_EPINBULK_ATTR (USB_EP_ATTR_XFER_BULK)
#define USBMSC_HSBULKMAXPACKET (512)
drivers/wireless/spirit/include/spirit_aes.h
+5 -5
View File
@@ -54,7 +54,7 @@
* In order to decrypt data, the user must manage the AES_END IRQ and have a
* decryption key. There are two operative modes to make the data
* decryption:
*
*
* 1. Derive the decryption key from the encryption key and decrypt data
* directly using the spirit_aes_derivekey_decrypt() function
*
@@ -126,7 +126,7 @@ int spirit_aes_enable(FAR struct spirit_library_s *spirit,
enum spirit_functional_state_e newstate);
/******************************************************************************
* Name:
* Name: spirit_aes_write_datain
*
* Description:
* Writes the data to encrypt or decrypt, or the encryption key for the
@@ -151,7 +151,7 @@ int spirit_aes_write_datain(FAR struct spirit_library_s *spirit,
FAR const uint8_t *buffer, uint8_t buflen);
/******************************************************************************
* Name:
* Name: spirit_aes_read_dataout
*
* Description:
* Returns the encrypted or decrypted data or the decription key from the
@@ -195,7 +195,7 @@ int spirit_aes_write_key(FAR struct spirit_library_s *spirit,
FAR const uint8_t *key);
/******************************************************************************
* Name:
* Name: spirit_aes_read_key
*
* Description:
* Returns the encryption/decryption key from the AES_KEY_IN register.
@@ -247,7 +247,7 @@ int spirit_aes_enc2deckey(FAR struct spirit_library_s *spirit);
int spirit_aes_encrypt(FAR struct spirit_library_s *spirit);
/******************************************************************************
* Name:
* Name: spirit_aes_decrypt
*
* Description:
* Executes the decryption operation.
drivers/wireless/spirit/include/spirit_directrf.h
+3 -3
View File
@@ -124,7 +124,7 @@ int spirit_directrf_set_rxmode(FAR struct spirit_library_s *spirit,
enum spirit_directrx_e directrx);
/******************************************************************************
* Name:
* Name: spirit_directrf_get_rxmode
*
* Description:
* Returns the DirectRF RX mode of SPIRIT.
@@ -141,7 +141,7 @@ enum spirit_directrx_e
spirit_directrf_get_rxmode(FAR struct spirit_library_s *spirit);
/******************************************************************************
* Name:
* Name: spirit_directrf_set_txmode
*
* Description:
* Sets the TX mode of SPIRIT.
@@ -159,7 +159,7 @@ int spirit_directrf_set_txmode(FAR struct spirit_library_s *spirit,
enum spirit_directtx_e directtx);
/******************************************************************************
* Name:
* Name: spirit_directrf_get_txmode
*
* Description:
* Returns the DirectRF TX mode of SPIRIT.
drivers/wireless/spirit/include/spirit_pktmbus.h
+2 -2
View File
@@ -258,7 +258,7 @@ int spirit_pktmbus_set_postamble(FAR struct spirit_library_s *spirit,
uint8_t postamble);
/******************************************************************************
* Name:
* Name: spirit_pktmbus_get_postamble
*
* Description:
* Returns how many chip sequence "01" are used in the postamble
@@ -274,7 +274,7 @@ int spirit_pktmbus_set_postamble(FAR struct spirit_library_s *spirit,
uint8_t spirit_pktmbus_get_postamble(FAR struct spirit_library_s *spirit);
/******************************************************************************
* Name:
* Name: spirit_pktmbus_set_submode
*
* Description:
* Sets the MBUS submode used.
drivers/wireless/spirit/lib/spirit_aes.c
+4 -4
View File
@@ -98,7 +98,7 @@ int spirit_aes_enable(FAR struct spirit_library_s *spirit,
}
/******************************************************************************
* Name:
* Name: spirit_aes_write_datain
*
* Description:
* Writes the data to encrypt or decrypt, or the encryption key for the
@@ -149,7 +149,7 @@ int spirit_aes_write_datain(FAR struct spirit_library_s *spirit,
}
/******************************************************************************
* Name:
* Name: spirit_aes_read_dataout
*
* Description:
* Returns the encrypted or decrypted data or the decription key from the
@@ -239,7 +239,7 @@ int spirit_aes_write_key(FAR struct spirit_library_s *spirit,
}
/******************************************************************************
* Name:
* Name: spirit_aes_read_key
*
* Description:
* Returns the encryption/decryption key from the AES_KEY_IN register.
@@ -319,7 +319,7 @@ int spirit_aes_encrypt(FAR struct spirit_library_s *spirit)
}
/******************************************************************************
* Name:
* Name: spirit_aes_decrypt
*
* Description:
* Executes the decryption operation.
drivers/wireless/spirit/lib/spirit_directrf.c
+3 -3
View File
@@ -91,7 +91,7 @@ int spirit_directrf_set_rxmode(FAR struct spirit_library_s *spirit,
}
/******************************************************************************
* Name:
* Name: spirit_directrf_get_rxmode
*
* Description:
* Returns the DirectRF RX mode of SPIRIT.
@@ -119,7 +119,7 @@ enum spirit_directrx_e
}
/******************************************************************************
* Name:
* Name: spirit_directrf_set_txmode
*
* Description:
* Sets the TX mode of SPIRIT.
@@ -162,7 +162,7 @@ int spirit_directrf_set_txmode(FAR struct spirit_library_s *spirit,
}
/******************************************************************************
* Name:
* Name: spirit_directrf_get_txmode
*
* Description:
* Returns the DirectRF TX mode of SPIRIT.
drivers/wireless/spirit/lib/spirit_gpio.c
+1 -1
View File
@@ -107,7 +107,7 @@ int spirit_gpio_enable_tempsensor(FAR struct spirit_library_s *spirit,
DEBUGASSERT(IS_SPIRIT_FUNCTIONAL_STATE(newstate));
/* Reads the ANA_FUNC_CONF0 register and mask the result to enable or disable
/* Reads the ANA_FUNC_CONF0 register and mask the result to enable or disable
* the temperature sensor */
ret = spirit_reg_read(spirit, ANA_FUNC_CONF0_BASE, &regval, 1);

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