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!arch/stm32h5: unify non-standard hardware definition prefixes

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BREAKING CHANGE: STM32H5 non-standard hardware definition macros
(IRQ, peripheral-count, SRAM and related) were renamed to the common
STM32_* prefix. Out-of-tree code must update the affected references.

Signed-off-by: raiden00pl <raiden00@railab.me>
This commit is contained in:
raiden00pl
2026-06-17 17:10:28 +08:00
committed by Xiang Xiao
parent 69de43b347
commit 8c4f15d670
20 changed files with 444 additions and 444 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/include/stm32h5/chip.h
+41 -41
View File
@@ -34,65 +34,65 @@
****************************************************************************/
#if defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32H5_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */
# define STM32H5_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */
# define STM32_SRAM1_SIZE (128*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (80*1024) /* 80Kb SRAM2 on AHB bus Matrix */
# define STM32_SRAM3_SIZE (64*1024) /* 64Kb SRAM3 on AHB bus Matrix */
#elif defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32H5_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
# define STM32H5_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */
# define STM32_SRAM1_SIZE (256*1024) /* 192Kb SRAM1 on AHB bus Matrix */
# define STM32_SRAM2_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix */
# define STM32_SRAM3_SIZE (320*1024) /* 320Kb SRAM3 on AHB bus Matrix */
#else
# error "Unsupported STM32H5 chip"
#endif
#define STM32H5_NFSMC (1) /* Have FSMC memory controller */
#define STM32H5_NATIM (2) /* Two advanced timers TIM1 and TIM8 */
#define STM32H5_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */
#define STM32H5_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */
#define STM32H5_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */
#define STM32H5_NBTIM (2) /* Two basic timers, TIM6-7 */
#define STM32H5_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */
#define STM32H5_NRNG (1) /* Random number generator (RNG) */
#define STM32_NFSMC (1) /* Have FSMC memory controller */
#define STM32_NATIM (2) /* Two advanced timers TIM1 and TIM8 */
#define STM32_NGTIM32 (2) /* 32-bit general timers TIM2 and 5 with DMA */
#define STM32_NGTIM16 (2) /* 16-bit general timers TIM3 and 4 with DMA */
#define STM32_NGTIMNDMA (3) /* 16-bit general timers TIM15-17 without DMA */
#define STM32_NBTIM (2) /* Two basic timers, TIM6-7 */
#define STM32_NLPTIM (6) /* Six low-power timers, LPTIM1-LPTIM6. */
#define STM32_NRNG (1) /* Random number generator (RNG) */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_NUART (6) /* UART 4-5, 7-8, 9, 12 */
# define STM32H5_NUSART (5) /* USART 1-3, 6, 10-11 */
# define STM32_NUART (6) /* UART 4-5, 7-8, 9, 12 */
# define STM32_NUSART (5) /* USART 1-3, 6, 10-11 */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_NUART (2) /* UART 4-5 */
# define STM32H5_NUSART (4) /* USART 1-3, 6*/
# define STM32_NUART (2) /* UART 4-5 */
# define STM32_NUSART (4) /* USART 1-3, 6*/
#endif
#define STM32H5_NLPUART (1) /* LPUART 1 */
#define STM32H5_QSPI (0) /* No QuadSPI1 */
#define STM32H5_OCTOSPI (1) /* OCTOSPI1*/
#define STM32_NLPUART (1) /* LPUART 1 */
#define STM32_QSPI (0) /* No QuadSPI1 */
#define STM32_OCTOSPI (1) /* OCTOSPI1*/
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_NSPI (6) /* SPI1-SPI6 */
# define STM32H5_NI2C (4) /* I2C1-4 */
# define STM32_NSPI (6) /* SPI1-SPI6 */
# define STM32_NI2C (4) /* I2C1-4 */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_NSPI (3) /* SPI1-SPI3 */
# define STM32H5_NI2C (3) /* I2C1-3 */
# define STM32_NSPI (3) /* SPI1-SPI3 */
# define STM32_NI2C (3) /* I2C1-3 */
#endif
#define STM32H5_NSWPMI (0) /* No SWPMI1 */
#define STM32H5_NUSBOTGFS (0) /* USB OTG FS */
#define STM32H5_NUSBFS (1) /* No USB FS */
#define STM32H5_NCAN (2) /* CAN1 */
#define STM32H5_NSAI (2) /* SAI1-2 */
#define STM32_NSWPMI (0) /* No SWPMI1 */
#define STM32_NUSBOTGFS (0) /* USB OTG FS */
#define STM32_NUSBFS (1) /* No USB FS */
#define STM32_NCAN (2) /* CAN1 */
#define STM32_NSAI (2) /* SAI1-2 */
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32H5_NSDMMC (2) /* SDMMC interface */
# define STM32_NSDMMC (2) /* SDMMC interface */
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32H5_NSDMMC (1) /* SDMMC interface */
# define STM32_NSDMMC (1) /* SDMMC interface */
#endif
#define STM32H5_NDMA (2) /* DMA1-2 */
#define STM32H5_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */
#define STM32H5_NADC (2) /* 12-bit ADC1, up to 20 channels */
#define STM32H5_NDAC (1) /* 12-bit DAC1 */
#define STM32H5_NCRC (1) /* CRC */
#define STM32H5_NCOMP (0) /* Comparators */
#define STM32H5_NOPAMP (0) /* Operational Amplifiers */
#define STM32_NDMA (2) /* DMA1-2 */
#define STM32_NPORTS (8) /* 8 GPIO ports, GPIOA-GPIOI */
#define STM32_NADC (2) /* 12-bit ADC1, up to 20 channels */
#define STM32_NDAC (1) /* 12-bit DAC1 */
#define STM32_NCRC (1) /* CRC */
#define STM32_NCOMP (0) /* Comparators */
#define STM32_NOPAMP (0) /* Operational Amplifiers */
/* NVIC priority levels *****************************************************/
@@ -104,9 +104,9 @@
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#if defined(CONFIG_STM32H5_HAVE_ETHERNET)
# define STM32H5_NETHERNET 1 /* Ethernet MAC */
# define STM32_NETHERNET 1 /* Ethernet MAC */
#else
# define STM32H5_NETHERNET 0 /* No Ethernet MAC */
# define STM32_NETHERNET 0 /* No Ethernet MAC */
#endif
#endif /* __ARCH_ARM_INCLUDE_STM32H5_CHIP_H */
arch/arm/src/stm32h5/hardware/stm32_qspi.h
+2 -2
View File
@@ -36,8 +36,8 @@
/* General Characteristics **************************************************/
#define STM32H5_QSPI_MINBITS 8 /* Minimum word width */
#define STM32H5_QSPI_MAXBITS 32 /* Maximum word width */
#define STM32_QSPI_MINBITS 8 /* Minimum word width */
#define STM32_QSPI_MAXBITS 32 /* Maximum word width */
/* QSPI register offsets ****************************************************/
arch/arm/src/stm32h5/hardware/stm32h5xxx_gpio.h
+9 -9
View File
@@ -53,7 +53,7 @@
/* Register Addresses *******************************************************/
#if STM32H5_NPORTS > 0
#if STM32_NPORTS > 0
# define STM32_GPIOA_MODER (STM32_GPIOA_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOA_OTYPER (STM32_GPIOA_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOA_OSPEED (STM32_GPIOA_BASE + STM32_GPIO_OSPEED_OFFSET)
@@ -69,7 +69,7 @@
# define STM32_GPIOA_SECCFGR (STM32_GPIOA_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 1
#if STM32_NPORTS > 1
# define STM32_GPIOB_MODER (STM32_GPIOB_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOB_OTYPER (STM32_GPIOB_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOB_OSPEED (STM32_GPIOB_BASE + STM32_GPIO_OSPEED_OFFSET)
@@ -85,7 +85,7 @@
# define STM32_GPIOB_SECCFGR (STM32_GPIOB_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 2
#if STM32_NPORTS > 2
# define STM32_GPIOC_MODER (STM32_GPIOC_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOC_OTYPER (STM32_GPIOC_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOC_OSPEED (STM32_GPIOC_BASE + STM32_GPIO_OSPEED_OFFSET)
@@ -101,7 +101,7 @@
# define STM32_GPIOC_SECCFGR (STM32_GPIOC_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 3
#if STM32_NPORTS > 3
# define STM32_GPIOD_MODER (STM32_GPIOD_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOD_OTYPER (STM32_GPIOD_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOD_OSPEED (STM32_GPIOD_BASE + STM32_GPIO_OSPEED_OFFSET)
@@ -117,7 +117,7 @@
# define STM32_GPIOD_SECCFGR (STM32_GPIOD_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 4
#if STM32_NPORTS > 4
# define STM32_GPIOE_MODER (STM32_GPIOE_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOE_OTYPER (STM32_GPIOE_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOE_OSPEED (STM32_GPIOE_BASE + STM32_GPIO_OSPEED_OFFSET)
@@ -133,7 +133,7 @@
# define STM32_GPIOE_SECCFGR (STM32_GPIOE_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 5
#if STM32_NPORTS > 5
# define STM32_GPIOF_MODER (STM32_GPIOF_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOF_OTYPER (STM32_GPIOF_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOF_OSPEED (STM32_GPIOF_BASE + STM32_GPIO_OSPEED_OFFSET)
@@ -149,7 +149,7 @@
# define STM32_GPIOF_SECCFGR (STM32_GPIOF_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 6
#if STM32_NPORTS > 6
# define STM32_GPIOG_MODER (STM32_GPIOG_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOG_OTYPER (STM32_GPIOG_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOG_OSPEED (STM32_GPIOG_BASE + STM32_GPIO_OSPEED_OFFSET)
@@ -165,7 +165,7 @@
# define STM32_GPIOG_SECCFGR (STM32_GPIOG_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 7
#if STM32_NPORTS > 7
# define STM32_GPIOH_MODER (STM32_GPIOH_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOH_OTYPER (STM32_GPIOH_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOH_OSPEED (STM32_GPIOH_BASE + STM32_GPIO_OSPEED_OFFSET)
@@ -181,7 +181,7 @@
# define STM32_GPIOH_SECCFGR (STM32_GPIOH_BASE + STM32_GPIO_SECCFGR_OFFSET)
#endif
#if STM32H5_NPORTS > 8
#if STM32_NPORTS > 8
# define STM32_GPIOI_MODER (STM32_GPIOI_BASE + STM32_GPIO_MODER_OFFSET)
# define STM32_GPIOI_OTYPER (STM32_GPIOI_BASE + STM32_GPIO_OTYPER_OFFSET)
# define STM32_GPIOI_OSPEED (STM32_GPIOI_BASE + STM32_GPIO_OSPEED_OFFSET)
arch/arm/src/stm32h5/hardware/stm32h5xxx_i2c.h
+4 -4
View File
@@ -43,7 +43,7 @@
/* Register Addresses *******************************************************/
#if STM32H5_NI2C > 0
#if STM32_NI2C > 0
# define STM32_I2C1_CR1 (STM32_I2C1_BASE+STM32_I2C_CR1_OFFSET)
# define STM32_I2C1_CR2 (STM32_I2C1_BASE+STM32_I2C_CR2_OFFSET)
# define STM32_I2C1_OAR1 (STM32_I2C1_BASE+STM32_I2C_OAR1_OFFSET)
@@ -57,7 +57,7 @@
# define STM32_I2C1_TXDR (STM32_I2C1_BASE+STM32_I2C_TXDR_OFFSET)
#endif
#if STM32H5_NI2C > 1
#if STM32_NI2C > 1
# define STM32_I2C2_CR1 (STM32_I2C2_BASE+STM32_I2C_CR1_OFFSET)
# define STM32_I2C2_CR2 (STM32_I2C2_BASE+STM32_I2C_CR2_OFFSET)
# define STM32_I2C2_OAR1 (STM32_I2C2_BASE+STM32_I2C_OAR1_OFFSET)
@@ -71,7 +71,7 @@
# define STM32_I2C2_TXDR (STM32_I2C2_BASE+STM32_I2C_TXDR_OFFSET)
#endif
#if STM32H5_NI2C > 2
#if STM32_NI2C > 2
# define STM32_I2C3_CR1 (STM32_I2C3_BASE+STM32_I2C_CR1_OFFSET)
# define STM32_I2C3_CR2 (STM32_I2C3_BASE+STM32_I2C_CR2_OFFSET)
# define STM32_I2C3_OAR1 (STM32_I2C3_BASE+STM32_I2C_OAR1_OFFSET)
@@ -85,7 +85,7 @@
# define STM32_I2C3_TXDR (STM32_I2C3_BASE+STM32_I2C_TXDR_OFFSET)
#endif
#if STM32H5_NI2C > 3
#if STM32_NI2C > 3
# define STM32_I2C4_CR1 (STM32_I2C4_BASE+STM32_I2C_CR1_OFFSET)
# define STM32_I2C4_CR2 (STM32_I2C4_BASE+STM32_I2C_CR2_OFFSET)
# define STM32_I2C4_OAR1 (STM32_I2C4_BASE+STM32_I2C_OAR1_OFFSET)
arch/arm/src/stm32h5/hardware/stm32h5xxx_spi.h
+6 -6
View File
@@ -60,7 +60,7 @@
/* Register Addresses *******************************************************/
#if STM32H5_NSPI > 0
#if STM32_NSPI > 0
# define STM32_SPI1_CR1 (STM32_SPI1_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI1_CR2 (STM32_SPI1_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI1_CFG1 (STM32_SPI1_BASE+STM32_SPI_CFG1_OFFSET)
@@ -77,7 +77,7 @@
# define STM32_SPI1_I2SCFGR (STM32_SPI1_BASE+STM32_SPI_I2SCFGR_OFFSET)
#endif
#if STM32H5_NSPI > 1
#if STM32_NSPI > 1
# define STM32_SPI2_CR1 (STM32_SPI2_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI2_CR2 (STM32_SPI2_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI2_CFG1 (STM32_SPI2_BASE+STM32_SPI_CFG1_OFFSET)
@@ -94,7 +94,7 @@
# define STM32_SPI2_I2SCFGR (STM32_SPI2_BASE+STM32_SPI_I2SCFGR_OFFSET)
#endif
#if STM32H5_NSPI > 2
#if STM32_NSPI > 2
# define STM32_SPI3_CR1 (STM32_SPI3_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI3_CR2 (STM32_SPI3_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI3_CFG1 (STM32_SPI3_BASE+STM32_SPI_CFG1_OFFSET)
@@ -111,7 +111,7 @@
# define STM32_SPI3_I2SCFGR (STM32_SPI3_BASE+STM32_SPI_I2SCFGR_OFFSET)
#endif
#if STM32H5_NSPI > 3
#if STM32_NSPI > 3
# define STM32_SPI4_CR1 (STM32_SPI4_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI4_CR2 (STM32_SPI4_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI4_CFG1 (STM32_SPI4_BASE+STM32_SPI_CFG1_OFFSET)
@@ -128,7 +128,7 @@
# define STM32_SPI4_I2SCFGR (STM32_SPI4_BASE+STM32_SPI_I2SCFGR_OFFSET)
#endif
#if STM32H5_NSPI > 4
#if STM32_NSPI > 4
# define STM32_SPI5_CR1 (STM32_SPI5_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI5_CR2 (STM32_SPI5_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI5_CFG1 (STM32_SPI5_BASE+STM32_SPI_CFG1_OFFSET)
@@ -145,7 +145,7 @@
# define STM32_SPI5_I2SCFGR (STM32_SPI5_BASE+STM32_SPI_I2SCFGR_OFFSET)
#endif
#if STM32H5_NSPI > 5
#if STM32_NSPI > 5
# define STM32_SPI6_CR1 (STM32_SPI6_BASE+STM32_SPI_CR1_OFFSET)
# define STM32_SPI6_CR2 (STM32_SPI6_BASE+STM32_SPI_CR2_OFFSET)
# define STM32_SPI6_CFG1 (STM32_SPI6_BASE+STM32_SPI_CFG1_OFFSET)
arch/arm/src/stm32h5/hardware/stm32h5xxx_uart.h
+13 -13
View File
@@ -52,7 +52,7 @@
/* Register Addresses *******************************************************/
#if STM32H5_NLPUART > 0
#if STM32_NLPUART > 0
# define STM32_LPUART1_CR1 (STM32_LPUART1_BASE + STM32_USART_CR1_OFFSET)
# define STM32_LPUART1_CR2 (STM32_LPUART1_BASE + STM32_USART_CR2_OFFSET)
# define STM32_LPUART1_CR3 (STM32_LPUART1_BASE + STM32_USART_CR3_OFFSET)
@@ -67,7 +67,7 @@
# define STM32_LPUART1_PRESC (STM32_LPUART1_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 0
#if STM32_NUSART > 0
# define STM32_USART1_CR1 (STM32_USART1_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART1_CR2 (STM32_USART1_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART1_CR3 (STM32_USART1_BASE + STM32_USART_CR3_OFFSET)
@@ -82,7 +82,7 @@
# define STM32_USART1_PRESC (STM32_USART1_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 1
#if STM32_NUSART > 1
# define STM32_USART2_CR1 (STM32_USART2_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART2_CR2 (STM32_USART2_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART2_CR3 (STM32_USART2_BASE + STM32_USART_CR3_OFFSET)
@@ -97,7 +97,7 @@
# define STM32_USART2_PRESC (STM32_USART2_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 2
#if STM32_NUSART > 2
# define STM32_USART3_CR1 (STM32_USART3_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART3_CR2 (STM32_USART3_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART3_CR3 (STM32_USART3_BASE + STM32_USART_CR3_OFFSET)
@@ -112,7 +112,7 @@
# define STM32_USART3_PRESC (STM32_USART3_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 4
#if STM32_NUSART > 4
# define STM32_USART6_CR1 (STM32_USART6_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART6_CR2 (STM32_USART6_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART6_CR3 (STM32_USART6_BASE + STM32_USART_CR3_OFFSET)
@@ -127,7 +127,7 @@
# define STM32_USART6_PRESC (STM32_USART6_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 5
#if STM32_NUSART > 5
# define STM32_USART10_CR1 (STM32_USART10_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART10_CR2 (STM32_USART10_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART10_CR3 (STM32_USART10_BASE + STM32_USART_CR3_OFFSET)
@@ -142,7 +142,7 @@
# define STM32_USART10_PRESC (STM32_USART10_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUSART > 6
#if STM32_NUSART > 6
# define STM32_USART11_CR1 (STM32_USART11_BASE + STM32_USART_CR1_OFFSET)
# define STM32_USART11_CR2 (STM32_USART11_BASE + STM32_USART_CR2_OFFSET)
# define STM32_USART11_CR3 (STM32_USART11_BASE + STM32_USART_CR3_OFFSET)
@@ -157,7 +157,7 @@
# define STM32_USART11_PRESC (STM32_USART11_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 0
#if STM32_NUART > 0
# define STM32_UART4_CR1 (STM32_UART4_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART4_CR2 (STM32_UART4_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART4_CR3 (STM32_UART4_BASE + STM32_USART_CR3_OFFSET)
@@ -172,7 +172,7 @@
# define STM32_UART4_PRESC (STM32_UART4_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 1
#if STM32_NUART > 1
# define STM32_UART5_CR1 (STM32_UART5_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART5_CR2 (STM32_UART5_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART5_CR3 (STM32_UART5_BASE + STM32_USART_CR3_OFFSET)
@@ -187,7 +187,7 @@
# define STM32_UART5_PRESC (STM32_UART5_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 2
#if STM32_NUART > 2
# define STM32_UART7_CR1 (STM32_UART7_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART7_CR2 (STM32_UART7_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART7_CR3 (STM32_UART7_BASE + STM32_USART_CR3_OFFSET)
@@ -202,7 +202,7 @@
# define STM32_UART7_PRESC (STM32_UART7_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 3
#if STM32_NUART > 3
# define STM32_UART8_CR1 (STM32_UART8_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART8_CR2 (STM32_UART8_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART8_CR3 (STM32_UART8_BASE + STM32_USART_CR3_OFFSET)
@@ -217,7 +217,7 @@
# define STM32_UART8_PRESC (STM32_UART8_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 4
#if STM32_NUART > 4
# define STM32_UART9_CR1 (STM32_UART9_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART9_CR2 (STM32_UART9_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART9_CR3 (STM32_UART9_BASE + STM32_USART_CR3_OFFSET)
@@ -232,7 +232,7 @@
# define STM32_UART9_PRESC (STM32_UART9_BASE + STM32_USART_PRESC_OFFSET)
#endif
#if STM32H5_NUART > 5
#if STM32_NUART > 5
# define STM32_UART12_CR1 (STM32_UART12_BASE + STM32_USART_CR1_OFFSET)
# define STM32_UART12_CR2 (STM32_UART12_BASE + STM32_USART_CR2_OFFSET)
# define STM32_UART12_CR3 (STM32_UART12_BASE + STM32_USART_CR3_OFFSET)
arch/arm/src/stm32h5/stm32_ethernet.c
+13 -13
View File
@@ -66,12 +66,12 @@
#include <arch/board/board.h>
/* STM32H5_NETHERNET determines the number of physical interfaces that can
/* STM32_NETHERNET determines the number of physical interfaces that can
* be supported by the hardware. CONFIG_STM32H5_ETHMAC will defined if
* any STM32H5 Ethernet support is enabled in the configuration.
*/
#if STM32H5_NETHERNET > 0 && defined(CONFIG_STM32H5_ETHMAC)
#if STM32_NETHERNET > 0 && defined(CONFIG_STM32H5_ETHMAC)
/****************************************************************************
* Pre-processor Definitions
@@ -79,7 +79,7 @@
/* Configuration ************************************************************/
#if STM32H5_NETHERNET > 1
#if STM32_NETHERNET > 1
# error "Logic to support multiple Ethernet interfaces is incomplete"
#endif
@@ -227,14 +227,14 @@
#define DESC_PADSIZE DMA_ALIGN_UP(DESC_SIZE)
#define ALIGNED_BUFSIZE DMA_ALIGN_UP(ETH_BUFSIZE)
#define RXTABLE_SIZE (STM32H5_NETHERNET * CONFIG_STM32H5_ETH_NRXDESC)
#define TXTABLE_SIZE (STM32H5_NETHERNET * CONFIG_STM32H5_ETH_NTXDESC)
#define RXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H5_ETH_NRXDESC)
#define TXTABLE_SIZE (STM32_NETHERNET * CONFIG_STM32H5_ETH_NTXDESC)
#define RXBUFFER_SIZE (CONFIG_STM32H5_ETH_NRXDESC * ALIGNED_BUFSIZE)
#define RXBUFFER_ALLOC (STM32H5_NETHERNET * RXBUFFER_SIZE)
#define RXBUFFER_ALLOC (STM32_NETHERNET * RXBUFFER_SIZE)
#define TXBUFFER_SIZE (STM32_ETH_NFREEBUFFERS * ALIGNED_BUFSIZE)
#define TXBUFFER_ALLOC (STM32H5_NETHERNET * TXBUFFER_SIZE)
#define TXBUFFER_ALLOC (STM32_NETHERNET * TXBUFFER_SIZE)
/* Extremely detailed register debug that you would normally never want
* enabled.
@@ -653,7 +653,7 @@ aligned_data(ARMV8M_DCACHE_LINESIZE);
/* These are the pre-allocated Ethernet device structures */
static struct stm32_ethmac_s g_stm32ethmac[STM32H5_NETHERNET];
static struct stm32_ethmac_s g_stm32ethmac[STM32_NETHERNET];
/****************************************************************************
* Private Function Prototypes
@@ -4181,7 +4181,7 @@ static int stm32_ethconfig(struct stm32_ethmac_s *priv)
*
****************************************************************************/
#if STM32H5_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT)
#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT)
int stm32_ethinitialize(int intf)
#else
static inline int stm32_ethinitialize(int intf)
@@ -4196,7 +4196,7 @@ static inline int stm32_ethinitialize(int intf)
/* Get the interface structure associated with this interface number. */
DEBUGASSERT(intf < STM32H5_NETHERNET);
DEBUGASSERT(intf < STM32_NETHERNET);
priv = &g_stm32ethmac[intf];
/* Initialize the driver structure */
@@ -4268,7 +4268,7 @@ static inline int stm32_ethinitialize(int intf)
*
* Description:
* This is the "standard" network initialization logic called from the
* low-level initialization logic in arm_initialize.c. If STM32H5_NETHERNET
* low-level initialization logic in arm_initialize.c. If STM32_NETHERNET
* greater than one, then board specific logic will have to supply a
* version of arm_netinitialize() that calls stm32_ethinitialize() with
* the appropriate interface number.
@@ -4283,11 +4283,11 @@ static inline int stm32_ethinitialize(int intf)
*
****************************************************************************/
#if STM32H5_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT)
#if STM32_NETHERNET == 1 && !defined(CONFIG_NETDEV_LATEINIT)
void arm_netinitialize(void)
{
stm32_ethinitialize(0);
}
#endif
#endif /* STM32H5_NETHERNET > 0 && CONFIG_STM32H5_ETHMAC */
#endif /* STM32_NETHERNET > 0 && CONFIG_STM32H5_ETHMAC */
arch/arm/src/stm32h5/stm32_ethernet.h
+3 -3
View File
@@ -29,7 +29,7 @@
#include "hardware/stm32_ethernet.h"
#if STM32H5_NETHERNET > 0
#if STM32_NETHERNET > 0
#ifndef __ASSEMBLY__
/****************************************************************************
@@ -65,7 +65,7 @@ extern "C"
*
****************************************************************************/
#if STM32H5_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT)
#if STM32_NETHERNET > 1 || defined(CONFIG_NETDEV_LATEINIT)
int stm32_ethinitialize(int intf);
#endif
@@ -100,5 +100,5 @@ int stm32_phy_boardinitialize(int intf);
#endif
#endif /* __ASSEMBLY__ */
#endif /* STM32H5_NETHERNET > 0 */
#endif /* STM32_NETHERNET > 0 */
#endif /* __ARCH_ARM_SRC_STM32H5_STM32_ETHERNET_H */
arch/arm/src/stm32h5/stm32_fdcan.c
+4 -4
View File
@@ -328,10 +328,10 @@
# undef CONFIG_STM32H5_FDCAN_REGDEBUG
#endif
#undef STM32H5_FDCAN_LOOPBACK
#undef STM32_FDCAN_LOOPBACK
#if defined(CONFIG_STM32H5_FDCAN1_LOOPBACK) || \
defined(CONFIG_STM32H5_FDCAN2_LOOPBACK)
# define STM32H5_FDCAN_LOOPBACK 1
# define STM32_FDCAN_LOOPBACK 1
#endif
/****************************************************************************
@@ -403,7 +403,7 @@ struct stm32_config_s
uint8_t rxfifo1esize; /* RX FIFO1 element size (words) */
uint8_t txeventesize; /* TXevent element size (words) */
uint8_t txbufferesize; /* TX buffer element size (words) */
#ifdef STM32H5_FDCAN_LOOPBACK
#ifdef STM32_FDCAN_LOOPBACK
bool loopback; /* True: Loopback mode */
#endif
@@ -3282,7 +3282,7 @@ static int fdcan_hw_initialize(struct stm32_fdcan_s *priv)
#endif
fdcan_putreg(priv, STM32_FDCAN_TXBC_OFFSET, regval);
#ifdef STM32H5_FDCAN_LOOPBACK
#ifdef STM32_FDCAN_LOOPBACK
/* Is loopback mode selected for this peripheral? */
if (config->loopback)
arch/arm/src/stm32h5/stm32_gpio.c
+12 -12
View File
@@ -52,30 +52,30 @@ static spinlock_t g_configgpio_lock = SP_UNLOCKED;
/* Base addresses for each GPIO block */
const uint32_t g_gpiobase[STM32H5_NPORTS] =
const uint32_t g_gpiobase[STM32_NPORTS] =
{
#if STM32H5_NPORTS > 0
#if STM32_NPORTS > 0
STM32_GPIOA_BASE,
#endif
#if STM32H5_NPORTS > 1
#if STM32_NPORTS > 1
STM32_GPIOB_BASE,
#endif
#if STM32H5_NPORTS > 2
#if STM32_NPORTS > 2
STM32_GPIOC_BASE,
#endif
#if STM32H5_NPORTS > 3
#if STM32_NPORTS > 3
STM32_GPIOD_BASE,
#endif
#if STM32H5_NPORTS > 4
#if STM32_NPORTS > 4
STM32_GPIOE_BASE,
#endif
#if STM32H5_NPORTS > 5
#if STM32_NPORTS > 5
STM32_GPIOF_BASE,
#endif
#if STM32H5_NPORTS > 6
#if STM32_NPORTS > 6
STM32_GPIOG_BASE,
#endif
#if STM32H5_NPORTS > 7
#if STM32_NPORTS > 7
STM32_GPIOH_BASE,
#endif
};
@@ -139,7 +139,7 @@ int stm32_configgpio(uint32_t cfgset)
/* Verify that this hardware supports the select GPIO port */
port = (cfgset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port >= STM32H5_NPORTS)
if (port >= STM32_NPORTS)
{
return -EINVAL;
}
@@ -350,7 +350,7 @@ void stm32_gpiowrite(uint32_t pinset, bool value)
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32H5_NPORTS)
if (port < STM32_NPORTS)
{
/* Get the port base address */
@@ -390,7 +390,7 @@ bool stm32_gpioread(uint32_t pinset)
unsigned int pin;
port = (pinset & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
if (port < STM32H5_NPORTS)
if (port < STM32_NPORTS)
{
/* Get the port base address */
arch/arm/src/stm32h5/stm32_gpio.h
+1 -1
View File
@@ -242,7 +242,7 @@ extern "C"
/* Base addresses for each GPIO block */
EXTERN const uint32_t g_gpiobase[STM32H5_NPORTS];
EXTERN const uint32_t g_gpiobase[STM32_NPORTS];
/****************************************************************************
* Public Function Prototypes
arch/arm/src/stm32h5/stm32_icache.c
+2 -2
View File
@@ -40,7 +40,7 @@
* Pre-processor Definitions
****************************************************************************/
#define STM32H5_ICACHE_INTERRUPT (defined(CONFIG_STM32H5_ICACHE_INV_INT) ||\
#define STM32_ICACHE_INTERRUPT (defined(CONFIG_STM32H5_ICACHE_INV_INT) ||\
defined(CONFIG_STM32H5_ICACHE_ERR_INT))
/****************************************************************************
@@ -266,7 +266,7 @@ void stm32_icache_initialize(void)
stm32_icache_setup_region(region3);
#endif
#if STM32H5_ICACHE_INTERRUPT
#if STM32_ICACHE_INTERRUPT
/* Attach ISR */
int ret;
arch/arm/src/stm32h5/stm32_lowputc.c
+213 -213
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/stm32h5/stm32_rcc.c
+6 -6
View File
@@ -111,14 +111,14 @@ static inline void rcc_resetbkp(void)
init_stat = stm32h5_rtc_is_initialized();
if (!init_stat)
{
uint32_t bkregs[STM32H5_RTC_BKCOUNT];
uint32_t bkregs[STM32_RTC_BKCOUNT];
int i;
/* Backup backup-registers before RTC reset. */
for (i = 0; i < STM32H5_RTC_BKCOUNT; i++)
for (i = 0; i < STM32_RTC_BKCOUNT; i++)
{
bkregs[i] = getreg32(STM32H5_RTC_BKR(i));
bkregs[i] = getreg32(STM32_RTC_BKR(i));
}
/* Enable write access to the backup domain (RTC registers, RTC
@@ -136,14 +136,14 @@ static inline void rcc_resetbkp(void)
/* Restore backup-registers, except RTC related. */
for (i = 0; i < STM32H5_RTC_BKCOUNT; i++)
for (i = 0; i < STM32_RTC_BKCOUNT; i++)
{
if (RTC_MAGIC_REG == STM32H5_RTC_BKR(i))
if (RTC_MAGIC_REG == STM32_RTC_BKR(i))
{
continue;
}
putreg32(bkregs[i], STM32H5_RTC_BKR(i));
putreg32(bkregs[i], STM32_RTC_BKR(i));
}
stm32_pwr_enablebkp(false);
arch/arm/src/stm32h5/stm32_serial.c
+5 -5
View File
@@ -1429,7 +1429,7 @@ static struct stm32_serial_s g_uart12priv =
/* This table lets us iterate over the configured USARTs */
static struct stm32_serial_s * const
g_uart_devs[STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART] =
g_uart_devs[STM32_NLPUART + STM32_NUSART + STM32_NUART] =
{
#ifdef CONFIG_STM32H5_LPUART1_SERIALDRIVER
[0] = &g_lpuart1priv,
@@ -2012,7 +2012,7 @@ static void stm32serial_pm_setsuspend(bool suspend)
g_serialpm.serial_suspended = suspend;
for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++)
for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++)
{
struct stm32_serial_s *priv = g_uart_devs[n];
@@ -3930,7 +3930,7 @@ static int stm32serial_pmprepare(struct pm_callback_s *cb, int domain,
* buffers.
*/
for (n = 0; n < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; n++)
for (n = 0; n < STM32_NLPUART + STM32_NUSART + STM32_NUART; n++)
{
struct stm32_serial_s *priv = g_uart_devs[n];
@@ -4000,7 +4000,7 @@ void arm_earlyserialinit(void)
/* Disable all USART interrupts */
for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++)
for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++)
{
if (g_uart_devs[i])
{
@@ -4069,7 +4069,7 @@ void arm_serialinit(void)
strlcpy(devname, "/dev/ttySx", sizeof(devname));
for (i = 0; i < STM32H5_NLPUART + STM32H5_NUSART + STM32H5_NUART; i++)
for (i = 0; i < STM32_NLPUART + STM32_NUSART + STM32_NUART; i++)
{
/* Don't create a device for non-configured ports. */
arch/arm/src/stm32h5/stm32_start.c
+2 -2
View File
@@ -83,10 +83,10 @@
*/
#define SRAM2_START STM32_SRAM2_BASE
#define SRAM2_END (SRAM2_START + STM32H5_SRAM2_SIZE)
#define SRAM2_END (SRAM2_START + STM32_SRAM2_SIZE)
#define SRAM3_START STM32_SRAM3_BASE
#define SRAM3_END (SRAM3_START + STM32H5_SRAM3_SIZE)
#define SRAM3_END (SRAM3_START + STM32_SRAM3_SIZE)
#define HEAP_BASE ((uintptr_t)_ebss + CONFIG_IDLETHREAD_STACKSIZE)
arch/arm/src/stm32h5/stm32_usbdrdhost.c
+74 -74
View File
@@ -84,28 +84,28 @@
/* Hardware definitions */
#define STM32H5_NHOST_CHANNELS CONFIG_STM32H5_USBDRD_NCHANNELS
#define STM32H5_EP0_MAX_PACKET_SIZE 64
#define STM32H5_RETRY_COUNT 3 /* Control transfer retries */
#define STM32_NHOST_CHANNELS CONFIG_STM32H5_USBDRD_NCHANNELS
#define STM32_EP0_MAX_PACKET_SIZE 64
#define STM32_RETRY_COUNT 3 /* Control transfer retries */
/* PMA Buffer allocation (fixed-size bitmap allocator) */
#define STM32H5_PMA_BUFFER_SIZE 64 /* Fixed buffer size (bytes) */
#define STM32H5_PMA_NBUFFERS 30 /* Total allocatable buffers */
#define STM32H5_PMA_BUFFER_ALLSET 0x3fffffff /* All 30 buffers available */
#define STM32H5_PMA_BUFFER_BIT(bn) (1U << (bn))
#define STM32H5_PMA_BUFNO2ADDR(bn) (USB_DRD_PMA_START_ADDR + ((bn) * STM32H5_PMA_BUFFER_SIZE))
#define STM32H5_PMA_BUFFER_NONE 0xFF /* Invalid buffer number */
#define STM32_PMA_BUFFER_SIZE 64 /* Fixed buffer size (bytes) */
#define STM32_PMA_NBUFFERS 30 /* Total allocatable buffers */
#define STM32_PMA_BUFFER_ALLSET 0x3fffffff /* All 30 buffers available */
#define STM32_PMA_BUFFER_BIT(bn) (1U << (bn))
#define STM32_PMA_BUFNO2ADDR(bn) (USB_DRD_PMA_START_ADDR + ((bn) * STM32_PMA_BUFFER_SIZE))
#define STM32_PMA_BUFFER_NONE 0xFF /* Invalid buffer number */
/* Delays */
#define STM32H5_DATANAK_DELAY SEC2TICK(5)
#define STM32H5_RESET_DELAY 100 /* ms */
#define STM32_DATANAK_DELAY SEC2TICK(5)
#define STM32_RESET_DELAY 100 /* ms */
/* USB DRD base addresses */
#define STM32H5_USBDRD_BASE STM32_USB_FS_BASE
#define STM32H5_USBDRD_PMA_BASE STM32_USB_FS_RAM_BASE
#define STM32_USBDRD_BASE STM32_USB_FS_BASE
#define STM32_USBDRD_PMA_BASE STM32_USB_FS_RAM_BASE
/* Register access helpers */
@@ -115,7 +115,7 @@
/* Channel register access */
#define STM32H5_USB_CHEP(n) (STM32H5_USBDRD_BASE + ((n) << 2))
#define STM32_USB_CHEP(n) (STM32_USBDRD_BASE + ((n) << 2))
/* Host channel data PID values */
@@ -227,7 +227,7 @@ struct stm32_usbhost_s
/* Host channels */
struct stm32_chan_s chan[STM32H5_NHOST_CHANNELS];
struct stm32_chan_s chan[STM32_NHOST_CHANNELS];
/* PMA allocation */
@@ -416,7 +416,7 @@ static void stm32_pma_write(const uint8_t *buffer, uint16_t pmaaddr,
uint32_t count;
uint32_t remaining;
pdwval = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + pmaaddr);
pdwval = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + pmaaddr);
count = nbytes >> 2; /* Number of 32-bit words */
remaining = nbytes & 0x03; /* Remaining bytes */
@@ -466,7 +466,7 @@ static void stm32_pma_read(uint8_t *buffer, uint16_t pmaaddr,
UP_DSB();
pdwval = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE + pmaaddr);
pdwval = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE + pmaaddr);
count = nbytes >> 2;
remaining = nbytes & 0x03;
@@ -508,9 +508,9 @@ static int stm32_pma_alloc_buffer(struct stm32_usbhost_s *priv)
flags = enter_critical_section();
for (bufndx = 0; bufndx < STM32H5_PMA_NBUFFERS; bufndx++)
for (bufndx = 0; bufndx < STM32_PMA_NBUFFERS; bufndx++)
{
uint32_t bit = STM32H5_PMA_BUFFER_BIT(bufndx);
uint32_t bit = STM32_PMA_BUFFER_BIT(bufndx);
if ((priv->pma_bufavail & bit) != 0)
{
priv->pma_bufavail &= ~bit; /* Mark allocated */
@@ -524,12 +524,12 @@ static int stm32_pma_alloc_buffer(struct stm32_usbhost_s *priv)
if (bufno >= 0)
{
uinfo("PMA buffer allocated: bufno=%d addr=0x%04x\n",
bufno, STM32H5_PMA_BUFNO2ADDR(bufno));
bufno, STM32_PMA_BUFNO2ADDR(bufno));
}
else
{
uerr("ERROR: PMA buffer allocation failed, all %d buffers in use\n",
STM32H5_PMA_NBUFFERS);
STM32_PMA_NBUFFERS);
}
return bufno;
@@ -548,14 +548,14 @@ static void stm32_pma_free_buffer(struct stm32_usbhost_s *priv,
{
irqstate_t flags;
DEBUGASSERT(bufno < STM32H5_PMA_NBUFFERS);
DEBUGASSERT(bufno < STM32_PMA_NBUFFERS);
flags = enter_critical_section();
priv->pma_bufavail |= STM32H5_PMA_BUFFER_BIT(bufno); /* Mark available */
priv->pma_bufavail |= STM32_PMA_BUFFER_BIT(bufno); /* Mark available */
leave_critical_section(flags);
uinfo("PMA buffer freed: bufno=%d addr=0x%04x\n",
bufno, STM32H5_PMA_BUFNO2ADDR(bufno));
bufno, STM32_PMA_BUFNO2ADDR(bufno));
}
/****************************************************************************
@@ -570,7 +570,7 @@ static int stm32_chan_alloc(struct stm32_usbhost_s *priv)
{
int chidx;
for (chidx = 0; chidx < STM32H5_NHOST_CHANNELS; chidx++)
for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++)
{
if (!priv->chan[chidx].inuse)
{
@@ -582,7 +582,7 @@ static int stm32_chan_alloc(struct stm32_usbhost_s *priv)
priv->chan[chidx].inuse = true;
priv->chan[chidx].pmabufno = (uint8_t)bufno;
priv->chan[chidx].pmaaddr = STM32H5_PMA_BUFNO2ADDR(bufno);
priv->chan[chidx].pmaaddr = STM32_PMA_BUFNO2ADDR(bufno);
uinfo("Channel allocated: chidx=%d\n", chidx);
return chidx;
}
@@ -604,18 +604,18 @@ static inline void stm32_chan_free(struct stm32_usbhost_s *priv,
{
struct stm32_chan_s *chan;
DEBUGASSERT((unsigned)chidx < STM32H5_NHOST_CHANNELS);
DEBUGASSERT((unsigned)chidx < STM32_NHOST_CHANNELS);
chan = &priv->chan[chidx];
/* Free PMA buffer if allocated */
if (chan->pmabufno != STM32H5_PMA_BUFFER_NONE)
if (chan->pmabufno != STM32_PMA_BUFFER_NONE)
{
stm32_set_chep_rx_status(priv, chidx, USB_CHEP_RX_STRX_DIS);
stm32_set_chep_tx_status(priv, chidx, USB_CHEP_TX_STTX_DIS);
stm32_pma_free_buffer(priv, chan->pmabufno);
chan->pmabufno = STM32H5_PMA_BUFFER_NONE;
chan->pmabufno = STM32_PMA_BUFFER_NONE;
chan->pmaaddr = 0;
uinfo("Channel freed: chidx=%d\n", chidx);
}
@@ -639,7 +639,7 @@ static void stm32_set_chep_tx_status(struct stm32_usbhost_s *priv,
/* Status changes work by toggling the DTOG bits */
regval = stm32_getreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx))
regval = stm32_getreg(STM32_USB_CHEP(priv->chan[chidx].chidx))
& USB_CHEP_TX_DTOGMASK;
if (status & USB_CHEP_TX_DTOG1)
{
@@ -651,7 +651,7 @@ static void stm32_set_chep_tx_status(struct stm32_usbhost_s *priv,
regval ^= USB_CHEP_TX_DTOG2;
}
stm32_putreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx),
stm32_putreg(STM32_USB_CHEP(priv->chan[chidx].chidx),
regval | USB_CHEP_VTRX | USB_CHEP_VTTX);
}
@@ -671,7 +671,7 @@ static void stm32_set_chep_rx_status(struct stm32_usbhost_s *priv,
/* Status changes work by toggling the DTOG bits */
regval = stm32_getreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx))
regval = stm32_getreg(STM32_USB_CHEP(priv->chan[chidx].chidx))
& USB_CHEP_RX_DTOGMASK;
if (status & USB_CHEP_RX_DTOG1)
{
@@ -683,7 +683,7 @@ static void stm32_set_chep_rx_status(struct stm32_usbhost_s *priv,
regval ^= USB_CHEP_RX_DTOG2;
}
stm32_putreg(STM32H5_USB_CHEP(priv->chan[chidx].chidx),
stm32_putreg(STM32_USB_CHEP(priv->chan[chidx].chidx),
regval | USB_CHEP_VTRX | USB_CHEP_VTTX);
}
@@ -701,7 +701,7 @@ static inline void stm32_chan_freeall(struct stm32_usbhost_s *priv)
/* Free all host channels */
for (chidx = 0; chidx < STM32H5_NHOST_CHANNELS; chidx++)
for (chidx = 0; chidx < STM32_NHOST_CHANNELS; chidx++)
{
if (priv->chan[chidx].inuse)
{
@@ -748,7 +748,7 @@ static void stm32_chan_configure(struct stm32_usbhost_s *priv,
/* Read current register value and mask toggleable bits */
regval = stm32_getreg(STM32H5_USB_CHEP(chidx)) & USB_CH_T_MASK;
regval = stm32_getreg(STM32_USB_CHEP(chidx)) & USB_CH_T_MASK;
/* Set endpoint type */
@@ -772,7 +772,7 @@ static void stm32_chan_configure(struct stm32_usbhost_s *priv,
/* Write the channel register with VT bits preserved */
stm32_putreg(STM32H5_USB_CHEP(chidx),
stm32_putreg(STM32_USB_CHEP(chidx),
regval | USB_CHEP_VTRX | USB_CHEP_VTTX);
}
@@ -944,7 +944,7 @@ static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv,
chan->eptype = USB_EP_ATTR_XFER_CONTROL;
chan->funcaddr = funcaddr;
chan->speed = speed;
chan->maxpacket = STM32H5_EP0_MAX_PACKET_SIZE;
chan->maxpacket = STM32_EP0_MAX_PACKET_SIZE;
chan->indata1 = false;
chan->outdata1 = false;
@@ -956,7 +956,7 @@ static int stm32_ctrlchan_alloc(struct stm32_usbhost_s *priv,
chan->eptype = USB_EP_ATTR_XFER_CONTROL;
chan->funcaddr = funcaddr;
chan->speed = speed;
chan->maxpacket = STM32H5_EP0_MAX_PACKET_SIZE;
chan->maxpacket = STM32_EP0_MAX_PACKET_SIZE;
chan->indata1 = false;
chan->outdata1 = false;
@@ -1092,7 +1092,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv,
bdval |= (nblocks << USB_PMA_RXBD_NUM_BLOCK_SHIFT);
}
pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE +
pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE +
USB_PMA_RXBD_OFFSET(chidx));
*pbd = bdval;
@@ -1104,7 +1104,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv,
/* Clear data toggle if starting new transfer */
regval = stm32_getreg(STM32H5_USB_CHEP(chidx));
regval = stm32_getreg(STM32_USB_CHEP(chidx));
if ((regval & USB_CHEP_DTOG_RX) != 0)
{
if (!chan->indata1)
@@ -1113,7 +1113,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv,
regval = (regval & USB_CHEP_REG_MASK) |
USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX;
stm32_putreg(STM32H5_USB_CHEP(chidx), regval);
stm32_putreg(STM32_USB_CHEP(chidx), regval);
}
}
else
@@ -1124,7 +1124,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv,
regval = (regval & USB_CHEP_REG_MASK) |
USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_RX;
stm32_putreg(STM32H5_USB_CHEP(chidx), regval);
stm32_putreg(STM32_USB_CHEP(chidx), regval);
}
}
@@ -1146,7 +1146,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv,
bdval = chan->pmaaddr; /* chan->pmaaddr is already 4 byte aligned */
bdval |= ((uint32_t)len << USB_PMA_TXBD_COUNT_SHIFT);
pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE +
pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE +
USB_PMA_TXBD_OFFSET(chidx));
*pbd = bdval;
@@ -1154,8 +1154,8 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv,
if (chan->pid == HC_PID_SETUP)
{
regval = stm32_getreg(STM32H5_USB_CHEP(chidx)) & USB_CHEP_REG_MASK;
stm32_putreg(STM32H5_USB_CHEP(chidx),
regval = stm32_getreg(STM32_USB_CHEP(chidx)) & USB_CHEP_REG_MASK;
stm32_putreg(STM32_USB_CHEP(chidx),
regval | USB_CHEP_SETUP |
USB_CHEP_VTRX | USB_CHEP_VTTX);
}
@@ -1164,7 +1164,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv,
* hardware auto-toggles after successful transmit)
*/
regval = stm32_getreg(STM32H5_USB_CHEP(chidx));
regval = stm32_getreg(STM32_USB_CHEP(chidx));
if ((regval & USB_CHEP_DTOG_TX) != 0)
{
if (!chan->outdata1)
@@ -1173,7 +1173,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv,
regval = (regval & USB_CHEP_REG_MASK) |
USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX;
stm32_putreg(STM32H5_USB_CHEP(chidx), regval);
stm32_putreg(STM32_USB_CHEP(chidx), regval);
}
}
else
@@ -1184,7 +1184,7 @@ static void stm32_transfer_start(struct stm32_usbhost_s *priv,
regval = (regval & USB_CHEP_REG_MASK) |
USB_CHEP_VTRX | USB_CHEP_VTTX | USB_CHEP_DTOG_TX;
stm32_putreg(STM32H5_USB_CHEP(chidx), regval);
stm32_putreg(STM32_USB_CHEP(chidx), regval);
}
}
@@ -1460,13 +1460,13 @@ static void stm32_gint_disconnected(struct stm32_usbhost_s *priv)
static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx)
{
struct stm32_chan_s *chan = &priv->chan[chidx];
uint32_t chepval = stm32_getreg(STM32H5_USB_CHEP(chidx));
uint32_t chepval = stm32_getreg(STM32_USB_CHEP(chidx));
uint32_t rx_status = chepval & USB_CHEP_RX_STRX_MASK;
bool wakeup = false;
if ((chepval & USB_CHEP_ERRRX) != 0)
{
chepval = stm32_getreg(STM32H5_USB_CHEP(chidx));
chepval = stm32_getreg(STM32_USB_CHEP(chidx));
uerr("ERRRX chidx=%d chepval=0x%08x rx_status=%d nak=%d\n",
chidx, (unsigned int)chepval,
(int)((chepval & USB_CHEP_RX_STRX_MASK) >>
@@ -1479,7 +1479,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx)
chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK) &
~USB_CHEP_ERRRX) | USB_CHEP_VTTX;
stm32_putreg(STM32H5_USB_CHEP(chidx), chepval);
stm32_putreg(STM32_USB_CHEP(chidx), chepval);
chan->result = EIO;
chan->chreason = CHREASON_TXERR;
@@ -1500,7 +1500,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx)
uint16_t count;
bool transfer_complete;
pbd = (volatile uint32_t *)(STM32H5_USBDRD_PMA_BASE +
pbd = (volatile uint32_t *)(STM32_USBDRD_PMA_BASE +
USB_PMA_RXBD_OFFSET(chidx));
count = (*pbd >> USB_PMA_RXBD_COUNT_SHIFT) & 0x3ff;
@@ -1546,10 +1546,10 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx)
* (toggle bit, write 1 keeps, write 0 clears)
*/
chepval = stm32_getreg(STM32H5_USB_CHEP(chidx));
chepval = stm32_getreg(STM32_USB_CHEP(chidx));
chepval = (chepval &
(0xffff7fff & USB_CHEP_REG_MASK)) | USB_CHEP_VTTX;
stm32_putreg(STM32H5_USB_CHEP(chidx), chepval);
stm32_putreg(STM32_USB_CHEP(chidx), chepval);
/* More data expected - reactivate channel for next packet */
@@ -1598,9 +1598,9 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx)
* (toggle bit, write 1 keeps, write 0 clears)
*/
chepval = stm32_getreg(STM32H5_USB_CHEP(chidx));
chepval = stm32_getreg(STM32_USB_CHEP(chidx));
chepval = (chepval & (0xffff7fff & USB_CHEP_REG_MASK)) | USB_CHEP_VTTX;
stm32_putreg(STM32H5_USB_CHEP(chidx), chepval);
stm32_putreg(STM32_USB_CHEP(chidx), chepval);
if (wakeup)
{
@@ -1620,7 +1620,7 @@ static void stm32_hc_in_irq(struct stm32_usbhost_s *priv, int chidx)
static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx)
{
struct stm32_chan_s *chan = &priv->chan[chidx];
uint32_t chepval = stm32_getreg(STM32H5_USB_CHEP(chidx));
uint32_t chepval = stm32_getreg(STM32_USB_CHEP(chidx));
uint32_t tx_status = chepval & USB_CHEP_TX_STTX_MASK;
bool wakeup = false;
@@ -1630,10 +1630,10 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx)
* write 1 to VTRX/VTTX to preserve
*/
chepval = stm32_getreg(STM32H5_USB_CHEP(chidx));
chepval = stm32_getreg(STM32_USB_CHEP(chidx));
chepval = (chepval & USB_CHEP_REG_MASK & ~USB_CHEP_ERRTX) |
USB_CHEP_VTRX | USB_CHEP_VTTX;
stm32_putreg(STM32H5_USB_CHEP(chidx), chepval);
stm32_putreg(STM32_USB_CHEP(chidx), chepval);
chan->result = EIO;
chan->chreason = CHREASON_TXERR;
@@ -1699,10 +1699,10 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx)
if ((chepval & USB_CHEP_NAK) != 0)
{
chepval = stm32_getreg(STM32H5_USB_CHEP(chidx));
chepval = stm32_getreg(STM32_USB_CHEP(chidx));
chepval = (chepval & USB_CHEP_REG_MASK & ~USB_CHEP_NAK) |
USB_CHEP_VTRX | USB_CHEP_VTTX;
stm32_putreg(STM32H5_USB_CHEP(chidx), chepval);
stm32_putreg(STM32_USB_CHEP(chidx), chepval);
}
if (!chan->waiter && !chan->callback)
@@ -1728,9 +1728,9 @@ static void stm32_hc_out_irq(struct stm32_usbhost_s *priv, int chidx)
/* Clear VTTX by writing 0 to it */
chepval = stm32_getreg(STM32H5_USB_CHEP(chidx));
chepval = stm32_getreg(STM32_USB_CHEP(chidx));
chepval = (chepval & (0xffffff7f & USB_CHEP_REG_MASK)) | USB_CHEP_VTRX;
stm32_putreg(STM32H5_USB_CHEP(chidx), chepval);
stm32_putreg(STM32_USB_CHEP(chidx), chepval);
if (wakeup)
{
@@ -2132,11 +2132,11 @@ static int stm32_epfree(struct usbhost_driver_s *drvr, usbhost_ep_t ep)
}
/* A single channel is represent by an index in the range of 0 to
* STM32H5_NHOST_CHANNELS. Otherwise, the ep must be a pointer to
* STM32_NHOST_CHANNELS. Otherwise, the ep must be a pointer to
* an allocated control endpoint structure.
*/
if ((uintptr_t)ep < STM32H5_NHOST_CHANNELS)
if ((uintptr_t)ep < STM32_NHOST_CHANNELS)
{
/* Halt the channel and mark the channel available */
@@ -2275,7 +2275,7 @@ static int stm32_ctrlin(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
return ret;
}
for (retries = 0; retries < STM32H5_RETRY_COUNT; retries++)
for (retries = 0; retries < STM32_RETRY_COUNT; retries++)
{
/* Send SETUP */
@@ -2351,7 +2351,7 @@ static int stm32_ctrlout(struct usbhost_driver_s *drvr, usbhost_ep_t ep0,
return ret;
}
for (retries = 0; retries < STM32H5_RETRY_COUNT; retries++)
for (retries = 0; retries < STM32_RETRY_COUNT; retries++)
{
/* Send SETUP */
@@ -2409,7 +2409,7 @@ static ssize_t stm32_transfer(struct usbhost_driver_s *drvr,
ssize_t nbytes;
int ret;
DEBUGASSERT(priv && buffer && chidx < STM32H5_NHOST_CHANNELS);
DEBUGASSERT(priv && buffer && chidx < STM32_NHOST_CHANNELS);
ret = nxmutex_lock(&priv->lock);
if (ret < 0)
@@ -2461,7 +2461,7 @@ static int stm32_asynch(struct usbhost_driver_s *drvr, usbhost_ep_t ep,
struct stm32_chan_s *chan;
int ret;
DEBUGASSERT(priv && buffer && chidx < STM32H5_NHOST_CHANNELS);
DEBUGASSERT(priv && buffer && chidx < STM32_NHOST_CHANNELS);
ret = nxmutex_lock(&priv->lock);
if (ret < 0)
@@ -2499,7 +2499,7 @@ static int stm32_cancel(struct usbhost_driver_s *drvr, usbhost_ep_t ep)
struct stm32_chan_s *chan;
irqstate_t flags;
DEBUGASSERT(priv && chidx < STM32H5_NHOST_CHANNELS);
DEBUGASSERT(priv && chidx < STM32_NHOST_CHANNELS);
chan = &priv->chan[chidx];
@@ -2595,7 +2595,7 @@ static void stm32_portreset(struct stm32_usbhost_s *priv)
/* Wait for reset */
nxsched_usleep(STM32H5_RESET_DELAY * 1000);
nxsched_usleep(STM32_RESET_DELAY * 1000);
/* Release reset */
@@ -2722,15 +2722,15 @@ static void stm32_sw_initialize(struct stm32_usbhost_s *priv)
/* Initialize PMA allocation - all buffers available */
priv->pma_bufavail = STM32H5_PMA_BUFFER_ALLSET;
priv->pma_bufavail = STM32_PMA_BUFFER_ALLSET;
/* Initialize channels */
for (i = 0; i < STM32H5_NHOST_CHANNELS; i++)
for (i = 0; i < STM32_NHOST_CHANNELS; i++)
{
priv->chan[i].chidx = i;
priv->chan[i].inuse = false;
priv->chan[i].pmabufno = STM32H5_PMA_BUFFER_NONE;
priv->chan[i].pmabufno = STM32_PMA_BUFFER_NONE;
nxsem_init(&priv->chan[i].waitsem, 0, 0);
}
}
arch/arm/src/stm32h5/stm32h563xx_flash.c
+1 -1
View File
@@ -96,7 +96,7 @@
#elif defined(CONFIG_STM32H5_FLASH_CONFIG_B)
# define H5_FLASH_BANK_NBLOCKS 8
#else
# warning "No valid STM32H5_FLASH_CONFIG_x defined."
# warning "No valid STM32_FLASH_CONFIG_x defined."
#endif
#define H5_FLASH_BANKSIZE (FLASH_BLOCK_SIZE * H5_FLASH_BANK_NBLOCKS)
arch/arm/src/stm32h5/stm32h5xx_rcc.c
+27 -27
View File
@@ -58,19 +58,19 @@ static_assert(CONFIG_BOARD_LOOPSPERMSEC != -1,
/* HSE divisor to yield ~1MHz RTC clock */
#define HSE_DIVISOR (STM32H5_HSE_FREQUENCY + 500000) / 1000000
#define HSE_DIVISOR (STM32_HSE_FREQUENCY + 500000) / 1000000
/* Determine if board wants to use HSI48 as 48 MHz oscillator. */
#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32H5_USE_CLK48)
# if defined(STM32H5_CLKUSB_SEL)
# if (STM32H5_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK)
# define STM32H5_USE_HSI48 1
#if defined(CONFIG_STM32H5_HAVE_HSI48) && defined(STM32_USE_CLK48)
# if defined(STM32_CLKUSB_SEL)
# if (STM32_CLKUSB_SEL == RCC_CCIPR4_USBSEL_HSI48KERCK)
# define STM32_USE_HSI48 1
# endif
# endif
# if defined(STM32H5_CLKRNG_SEL)
# if (STM32H5_CLKRNG_SEL == RCC_CCIPR5_RNGSEL_HSI48KERCK)
# define STM32H5_USE_HSI48 1
# if defined(STM32_CLKRNG_SEL)
# if (STM32_CLKRNG_SEL == RCC_CCIPR5_RNGSEL_HSI48KERCK)
# define STM32_USE_HSI48 1
# endif
# endif
#endif
@@ -203,30 +203,30 @@ static inline void rcc_enableahb2(void)
/* Enable GPIOA, GPIOB, .... GPIOH */
#if STM32H5_NPORTS > 0
#if STM32_NPORTS > 0
regval |= (RCC_AHB2ENR_GPIOAEN
#if STM32H5_NPORTS > 1
#if STM32_NPORTS > 1
| RCC_AHB2ENR_GPIOBEN
#endif
#if STM32H5_NPORTS > 2
#if STM32_NPORTS > 2
| RCC_AHB2ENR_GPIOCEN
#endif
#if STM32H5_NPORTS > 3
#if STM32_NPORTS > 3
| RCC_AHB2ENR_GPIODEN
#endif
#if STM32H5_NPORTS > 4
#if STM32_NPORTS > 4
| RCC_AHB2ENR_GPIOEEN
#endif
#if STM32H5_NPORTS > 5
#if STM32_NPORTS > 5
| RCC_AHB2ENR_GPIOFEN
#endif
#if STM32H5_NPORTS > 6
#if STM32_NPORTS > 6
| RCC_AHB2ENR_GPIOGEN
#endif
#if STM32H5_NPORTS > 7
#if STM32_NPORTS > 7
| RCC_AHB2ENR_GPIOHEN
#endif
#if STM32H5_NPORTS > 7
#if STM32_NPORTS > 7
| RCC_AHB2ENR_GPIOIEN
#endif
@@ -419,8 +419,8 @@ static inline void rcc_enableapb1l(void)
regval |= RCC_APB1LENR_I3C1EN;
#endif
#ifdef STM32H5_USE_HSI48
if (STM32H5_HSI48_SYNCSRC != SYNCSRC_NONE)
#ifdef STM32_USE_HSI48
if (STM32_HSI48_SYNCSRC != SYNCSRC_NONE)
{
/* Bit 24: CRS clock enable */
@@ -842,10 +842,10 @@ void stm32_rcc_enableperipherals(void)
rcc_enableapb2();
rcc_enableapb3();
#ifdef STM32H5_USE_HSI48
#ifdef STM32_USE_HSI48
/* Enable HSI48 clocking to support USB transfers or RNG */
stm32h5_enable_hsi48(STM32H5_HSI48_SYNCSRC);
stm32h5_enable_hsi48(STM32_HSI48_SYNCSRC);
#endif
}
@@ -1097,14 +1097,14 @@ void stm32_stdclockconfig(void)
}
#if defined(CONFIG_STM32H5_IWDG) || defined(CONFIG_STM32H5_RTC_LSICLOCK) || \
defined(STM32H5_USE_LSCO_LSI)
defined(STM32_USE_LSCO_LSI)
/* Low speed internal clock source LSI */
stm32_rcc_enablelsi();
#endif
#if defined(STM32_USE_LSE) || defined(STM32H5_USE_LSCO_LSE)
#if defined(STM32_USE_LSE) || defined(STM32_USE_LSCO_LSE)
/* Low speed external clock source LSE */
stm32_rcc_enablelse();
@@ -1203,19 +1203,19 @@ void stm32_stdclockconfig(void)
/* Configure USB source clock */
#if defined(STM32H5_CLKUSB_SEL)
#if defined(STM32_CLKUSB_SEL)
regval = getreg32(STM32_RCC_CCIPR4);
regval &= ~RCC_CCIPR4_USBSEL_MASK;
regval |= STM32H5_CLKUSB_SEL;
regval |= STM32_CLKUSB_SEL;
putreg32(regval, STM32_RCC_CCIPR4);
#endif
/* Configure RNG source clock */
#if defined(STM32H5_CLKRNG_SEL)
#if defined(STM32_CLKRNG_SEL)
regval = getreg32(STM32_RCC_CCIPR5);
regval &= ~RCC_CCIPR5_RNGSEL_MASK;
regval |= STM32H5_CLKRNG_SEL;
regval |= STM32_CLKRNG_SEL;
putreg32(regval, STM32_RCC_CCIPR5);
#endif
}
boards/arm/stm32h5/nucleo-h563zi/include/board.h
+6 -6
View File
@@ -132,7 +132,7 @@
#define STM32_PLL3Q_FREQUENCY (STM32_VCO3_FRQ / 10) /* 48 MHz */
/* Use PLL3Q (48 MHz) for USB - more stable than HSI48 */
#define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK
#define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_PLL3QCK
#endif /* CONFIG_STM32H5_USBFS_HOST */
@@ -186,18 +186,18 @@
/* Enable CLK48; get it from HSI48 */
#if defined(CONFIG_STM32H5_USBFS) || defined(CONFIG_STM32H5_RNG)
# define STM32H5_USE_CLK48 1
# define STM32_USE_CLK48 1
#endif
#if defined(CONFIG_STM32H5_USBFS)
# define STM32H5_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK
# define STM32H5_HSI48_SYNCSRC SYNCSRC_USB
# define STM32_CLKUSB_SEL RCC_CCIPR4_USBSEL_HSI48KERCK
# define STM32_HSI48_SYNCSRC SYNCSRC_USB
#else
# define STM32H5_HSI48_SYNCSRC SYNCSRC_NONE
# define STM32_HSI48_SYNCSRC SYNCSRC_NONE
#endif
#if defined(CONFIG_STM32H5_RNG)
# define STM32H5_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK
# define STM32_CLKRNG_SEL RCC_CCIPR5_RNGSEL_HSI48KERCK
#endif
/* Enable LSE (for the RTC) */