Merge branch 'master' into l432kc

arch/arm/include/stm32l4/chip.h

@@ -108,8 +108,12 @@
 #  define STM32L4_NSAI                     2   /* SAI1-2 */
 #  define STM32L4_NSDMMC                   1   /* SDMMC interface */
 #  define STM32L4_NDMA                     2   /* DMA1-2 */
+#if defined(CONFIG_STM32L4_STM32L496XX)
+#  define STM32L4_NPORTS                   9   /* 9 GPIO ports, GPIOA-I */
+#else
 #  define STM32L4_NPORTS                   8   /* 8 GPIO ports, GPIOA-H */
-#  define STM32L4_NADC                     3   /* 12-bit ADC1-3, 24 channels (except V series) */
+#endif
+#  define STM32L4_NADC                     3   /* 12-bit ADC1-3, upto 24 channels */
 #  define STM32L4_NDAC                     2   /* 12-bit DAC1-2 */
 #  define STM32L4_NCRC                     1   /* CRC */
 #  define STM32L4_NCOMP                    2   /* Comparators */

arch/arm/src/stm32/Make.defs

@@ -221,6 +221,10 @@ ifeq ($(CONFIG_COMP),y)
 CHIP_CSRCS += stm32_comp.c
 endif
 
+ifeq ($(CONFIG_OPAMP),y)
+CHIP_CSRCS += stm32_opamp.c
+endif
+
 ifeq ($(CONFIG_STM32_1WIREDRIVER),y)
 CHIP_CSRCS += stm32_1wire.c
 endif

arch/arm/src/stm32/chip/stm32f33xxx_opamp.h

@@ -54,7 +54,7 @@
 
 /* Register Addresses *******************************************************************************/
 
-#define STM32_OPAMP2_CSR            (STM32_OPAMP2_BASE+STM32_OPAMP2_CSR_OFFSET)
+#define STM32_OPAMP2_CSR            (STM32_OPAMP_BASE+STM32_OPAMP2_CSR_OFFSET)
 
 /* Register Bitfield Definitions ****************************************************/
 
@@ -66,7 +66,7 @@
 #define OPAMP_CSR_VPSEL_SHIFT       (3)         /* Bits 2-3: OPAMP non inverting input selection */
 #define OPAMP_CSR_VPSEL_MASK        (3 << OPAMP_CSR_VPSEL_SHIFT)
                                                                     /* 00: Reserved  */
-#  define OPAMP_CSR_VPSEL_PB13      (1 << OPAMP_CSR_VPSEL_SHIFT)    /* 01: PB14 */
+#  define OPAMP_CSR_VPSEL_PB14      (1 << OPAMP_CSR_VPSEL_SHIFT)    /* 01: PB14 */
 #  define OPAMP_CSR_VPSEL_PB0       (2 << OPAMP_CSR_VPSEL_SHIFT)    /* 10: PB0 */
 #  define OPAMP_CSR_VPSEL_PA7       (3 << OPAMP_CSR_VPSEL_SHIFT)    /* 11: PA7 */
                                                 /* Bit 4: Reserved  */
@@ -74,7 +74,7 @@
 #define OPAMP_CSR_VMSEL_MASK        (3 << OPAMP_CSR_VMSEL_SHIFT)
 #  define OPAMP_CSR_VMSEL_PC5       (0 << OPAMP_CSR_VMSEL_SHIFT)    /* 00: PC5 */
 #  define OPAMP_CSR_VMSEL_PA5       (1 << OPAMP_CSR_VMSEL_SHIFT)    /* 01: PA5 */
-#  define OPAMP_CSR_VMSEL_RESISTOR  (2 << OPAMP_CSR_VMSEL_SHIFT)    /* 10: Resistor feedback output */
+#  define OPAMP_CSR_VMSEL_PGA       (2 << OPAMP_CSR_VMSEL_SHIFT)    /* 10: Resistor feedback output (PGA mode)*/
 #  define OPAMP_CSR_VMSEL_FOLLOWER  (3 << OPAMP_CSR_VMSEL_SHIFT)    /* 11: Follower mode */
 #define OPAMP_CSR_TCMEN             (1 << 7)    /* Bit 7: Timer controlled Mux mode enable */
 #define OPAMP_CSR_VMSSEL            (1 << 8)    /* Bit 8: OPAMP inverting input secondary selection */

arch/arm/src/stm32/chip/stm32f33xxx_pinmap.h

@@ -337,9 +337,10 @@
 #define GPIO_OPAMP2_VINM_1   (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN5)
 #define GPIO_OPAMP2_VINM_2   (GPIO_ANALOG|GPIO_PORTC|GPIO_PIN5)
 #define GPIO_OPAMP2_VOUT     (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN6)
-#define GPIO_OPAMP2_VINP_1   (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
+#undef  GPIO_OPAMP2_VINP_1      /* not supported in F33XX */
-#define GPIO_OPAMP2_VINP_2   (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_OPAMP2_VINP_2   (GPIO_ANALOG|GPIO_PORTA|GPIO_PIN7)
-#define GPIO_OPAMP2_VINP_3   (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
+#define GPIO_OPAMP2_VINP_3   (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN0)
+#define GPIO_OPAMP2_VINP_4   (GPIO_ANALOG|GPIO_PORTB|GPIO_PIN14)
 
 /* TSC */
 

arch/arm/src/stm32/stm32.h

@@ -69,6 +69,7 @@
 #include "stm32_gpio.h"
 #include "stm32_i2c.h"
 #include "stm32_ltdc.h"
+#include "stm32_opamp.h"
 #include "stm32_pwr.h"
 #include "stm32_rcc.h"
 #include "stm32_rtc.h"

arch/arm/src/stm32/stm32_opamp.h

@@ -0,0 +1,231 @@
+/************************************************************************************
+ * arch/arm/src/stm32/stm32_opamp.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni <raiden00@railab.me>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32_STM32_OPAMP_H
+#define __ARCH_ARM_SRC_STM32_STM32_OPAMP_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+#ifdef CONFIG_STM32_OPAMP
+
+#if defined(CONFIG_STM32_STM32F30XX)
+#  error "OPAMP support for STM32F30XX not implemented yet"
+#elif defined(CONFIG_STM32_STM32F33XX)
+#  include "chip/stm32f33xxx_opamp.h"
+#endif
+
+#include <nuttx/analog/opamp.h>
+
+/************************************************************************************
+ * Pre-processor definitions
+ ************************************************************************************/
+
+/* OPAMP operation mode */
+
+#define OPAMP_MODE_STANDALONE 0
+#define OPAMP_MODE_FOLLOWER 1
+#define OPAMP_MODE_PGA 2
+
+/* Timer controlled Mux mode */
+
+#define OPAMP_MUX_DISABLE 0
+#define OPAMP_MUX_ENABLE 1
+
+/* User callibration  */
+
+#define OPAMP_USERCAL_DISABLE 0
+#define OPAMP_USERCAL_ENABLE  1
+
+/* Default configuration */
+
+#define OPAMP_MODE_DEFAULT    OPAMP_MODE_STANDALONE /* Standalone mode */
+#define OPAMP_MUX_DEFAULT     OPAMP_MUX_DISABLE     /* MUX disabled */
+#define OPAMP_USERCAL_DEFAULT OPAMP_USERCAL_DISABLE /* User calibration disabled */
+#define OPAMP_GAIN_DEFAULT    OPAMP_GAIN_2          /* Gain in PGA mode = 2 */
+#define OPAMP_LOCK_DEFAULT    OPAMP_LOCK_RW         /* Do not lock CSR register */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/* CSR register lock state */
+
+enum stm32_opamp_lock_e
+{
+  OPAMP_LOCK_RW,
+  OPAMP_LOCK_RO
+};
+
+/* Gain in PGA mode */
+
+enum stm32_opamp_gain_e
+{
+  OPAMP_GAIN_2,
+  OPAMP_GAIN_4,
+  OPAMP_GAIN_8,
+  OPAMP_GAIN_2_VM0,
+  OPAMP_GAIN_4_VM0,
+  OPAMP_GAIN_8_VM0,
+  OPAMP_GAIN_16_VM0,
+  OPAMP_GAIN_2_VM1,
+  OPAMP_GAIN_4_VM1,
+  OPAMP_GAIN_8_VM1,
+  OPAMP_GAIN_16_VM1
+};
+
+/* Input selection and secondary input selection use the same GPIOs */
+
+#ifdef CONFIG_STM32_OPAMP1
+enum stm32_opamp1_vpsel_e
+{
+  OPAMP1_VPSEL_PA7,
+  OPAMP1_VPSEL_PA5,
+  OPAMP1_VPSEL_PA3,
+  OPAMP1_VPSEL_PA1
+};
+
+enum stm32_opamp1_vmsel_e
+{
+  OPAMP1_VMSEL_PC5,
+  OPAMP1_VMSEL_PA3,
+  OPAMP1_VMSEL_PGAMODE,
+  OPAMP1_VMSEL_FOLLOWER,
+};
+#endif
+
+#ifdef CONFIG_STM32_OPAMP2
+enum stm32_opamp2_vpsel_e
+{
+#ifndef CONFIG_STM32_STM32F33XX
+  /* TODO: STM32F303xB/C and STM32F358C devices only */
+  OPAMP2_VPSEL_PD14,
+#endif
+  OPAMP2_VPSEL_PB14,
+  OPAMP2_VPSEL_PB0,
+  OPAMP2_VPSEL_PA7
+};
+
+enum stm32_opamp2_vmsel_e
+{
+  OPAMP2_VMSEL_PC5,
+  OPAMP2_VMSEL_PA5,
+  OPAMP2_VMSEL_PGAMODE,
+  OPAMP2_VMSEL_FOLLOWER
+};
+#endif
+
+#ifdef CONFIG_STM32_OPAMP3
+enum stm32_opamp3_vpsel_e
+{
+  OPAMP3_VPSEL_PB13,
+  OPAMP3_VPSEL_PA5,
+  OPAMP3_VPSEL_PA1,
+  OPAMP3_VPSEL_PB0
+};
+
+enum stm32_opamp3_vmsel_e
+{
+  OPAMP3_VMSEL_PB10,
+  OPAMP3_VMSEL_PB2,
+  OPAMP3_VMSEL_PGAMODE,
+  OPAMP3_VMSEL_FOLLOWER
+};
+#endif
+
+#ifdef CONFIG_STM32_OPAMP4
+enum stm32_opamp4_vpsel_e
+{
+  OPAMP4_VPSEL_PD11,
+  OPAMP4_VPSEL_PB11,
+  OPAMP4_VPSEL_PA4,
+  OPAMP4_VPSEL_PB13
+};
+
+enum stm32_opamp4_vmsel_e
+{
+  OPAMP4_VMSEL_PB10,
+  OPAMP4_VMSEL_PD8,
+  OPAMP4_VMSEL_PGAMODE,
+  OPAMP4_VMSEL_FOLLOWER
+};
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/****************************************************************************
+* Name: stm32_opampinitialize
+*
+* Description:
+*   Initialize the OPAMP.
+*
+* Input Parameters:
+*   intf - The OPAMP interface number.
+*
+* Returned Value:
+*   Valid OPAMP device structure reference on succcess; a NULL on failure.
+*
+* Assumptions:
+*   1. Clock to the OPAMP block has enabled,
+*   2. Board-specific logic has already configured
+*
+****************************************************************************/
+
+FAR struct opamp_dev_s* stm32_opampinitialize(int intf);
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif /* __ASSEMBLY__ */
+
+#endif  /* CONFIG_STM32_OPAMP */
+#endif /* __ARCH_ARM_SRC_STM32_STM32_OPAMP_H */

arch/arm/src/stm32l4/Kconfig

@@ -61,6 +61,18 @@ endchoice # STM32 L4 Chip Selection
 # Chip families
 
 config STM32L4_STM32L4X3
+	bool
+	default n
+	select STM32L4_HAVE_USART1
+	select STM32L4_HAVE_USART2
+	select STM32L4_HAVE_USART3 if !(STM32L4_L432XX || STM32L4_L442XX)
+	select STM32L4_HAVE_LPTIM1
+	select STM32L4_HAVE_LPTIM2
+	select STM32L4_HAVE_COMP
+	select STM32L4_HAVE_SAI1
+	select STM32L4_HAVE_LCD if !(STM32L4_STM32L4X1 || STM32L4_STM32L4X2)
+
+config STM32L4_STM32L4X5
 	bool
 	default n
 	select STM32L4_HAVE_USART1
@@ -91,18 +103,12 @@ config STM32L4_STM32L476XX
 	default n
 	select STM32L4_STM32L4X6
 	select ARCH_HAVE_FPU
-	select ARCH_HAVE_DPFPU # REVISIT
-	select ARMV7M_HAVE_ITCM
-	select ARMV7M_HAVE_DTCM
 
 config STM32L4_STM32L486XX
 	bool
 	default n
 	select STM32L4_STM32L4X6
 	select ARCH_HAVE_FPU
-	select ARCH_HAVE_DPFPU # REVISIT
-	select ARMV7M_HAVE_ITCM
-	select ARMV7M_HAVE_DTCM
 	select STM32L4_FLASH_1024KB
 
 config STM32L4_STM32L496XX
@@ -110,9 +116,6 @@ config STM32L4_STM32L496XX
 	default n
 	select STM32L4_STM32L4X6
 	select ARCH_HAVE_FPU
-	select ARCH_HAVE_DPFPU # REVISIT
-	select ARMV7M_HAVE_ITCM
-	select ARMV7M_HAVE_DTCM
 	select STM32L4_HAVE_I2C4
 	select STM32L4_HAVE_CAN2
 	select STM32L4_HAVE_DCMI

arch/arm/src/stm32l4/Make.defs

@@ -127,13 +127,6 @@ ifeq ($(CONFIG_BUILD_PROTECTED),y)
 CHIP_CSRCS += stm32l4_userspace.c stm32l4_mpuinit.c
 endif
 
-ifeq ($(CONFIG_ARMV7M_DTCM),y)
-CHIP_CSRCS += stm32l4_dtcm.c
-ifeq ($(CONFIG_STM32L4_DTCM_PROCFS),y)
-CHIP_CSRCS += stm32l4_procfs_dtcm.c
-endif
-endif
-
 ifeq ($(CONFIG_STM32L4_DMA),y)
 CHIP_CSRCS += stm32l4_dma.c
 endif

arch/arm/src/stm32l4/chip/stm32l4x6xx_gpio.h

@@ -166,6 +166,19 @@
 #  define STM32L4_GPIOH_AFRH         (STM32L4_GPIOH_BASE+STM32L4_GPIO_AFRH_OFFSET)
 #endif
 
+#if STM32L4_NPORTS > 8
+#  define STM32L4_GPIOI_MODER        (STM32L4_GPIOI_BASE+STM32L4_GPIO_MODER_OFFSET)
+#  define STM32L4_GPIOI_OTYPER       (STM32L4_GPIOI_BASE+STM32L4_GPIO_OTYPER_OFFSET)
+#  define STM32L4_GPIOI_OSPEED       (STM32L4_GPIOI_BASE+STM32L4_GPIO_OSPEED_OFFSET)
+#  define STM32L4_GPIOI_PUPDR        (STM32L4_GPIOI_BASE+STM32L4_GPIO_PUPDR_OFFSET)
+#  define STM32L4_GPIOI_IDR          (STM32L4_GPIOI_BASE+STM32L4_GPIO_IDR_OFFSET)
+#  define STM32L4_GPIOI_ODR          (STM32L4_GPIOI_BASE+STM32L4_GPIO_ODR_OFFSET)
+#  define STM32L4_GPIOI_BSRR         (STM32L4_GPIOI_BASE+STM32L4_GPIO_BSRR_OFFSET)
+#  define STM32L4_GPIOI_LCKR         (STM32L4_GPIOI_BASE+STM32L4_GPIO_LCKR_OFFSET)
+#  define STM32L4_GPIOI_AFRL         (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRL_OFFSET)
+#  define STM32L4_GPIOI_AFRH         (STM32L4_GPIOI_BASE+STM32L4_GPIO_AFRH_OFFSET)
+#endif
+
 /* Register Bitfield Definitions ****************************************************/
 
 /* GPIO port mode register */

arch/arm/src/stm32l4/stm32l4_gpio.c

@@ -88,6 +88,9 @@ const uint32_t g_gpiobase[STM32L4_NPORTS] =
 #if STM32L4_NPORTS > 7
   STM32L4_GPIOH_BASE,
 #endif
+#if STM32L4_NPORTS > 8
+  STM32L4_GPIOI_BASE,
+#endif
 };
 
 /****************************************************************************

arch/arm/src/stm32l4/stm32l4_gpio.h

@@ -212,6 +212,7 @@
 #  define GPIO_PORTF                  (5 << GPIO_PORT_SHIFT)     /*   GPIOF */
 #  define GPIO_PORTG                  (6 << GPIO_PORT_SHIFT)     /*   GPIOG */
 #  define GPIO_PORTH                  (7 << GPIO_PORT_SHIFT)     /*   GPIOH */
+#  define GPIO_PORTI                  (8 << GPIO_PORT_SHIFT)     /*   GPIOI */
 
 /* This identifies the bit in the port:
  *

arch/arm/src/stm32l4/stm32l4x6xx_rcc.c

@@ -210,6 +210,9 @@ static inline void rcc_enableahb2(void)
 #endif
 #if STM32L4_NPORTS > 7
              | RCC_AHB2ENR_GPIOHEN
+#endif
+#if STM32L4_NPORTS > 8
+             | RCC_AHB2ENR_GPIOIEN
 #endif
              );
 #endif

binfmt/libelf/libelf_sections.c

@@ -114,7 +114,6 @@ static inline int elf_sectname(FAR struct elf_loadinfo_s *loadinfo,
 
   /* Loop until we get the entire section name into memory */
 
-  buffer    = loadinfo->iobuffer;
   bytesread = 0;
 
   for (; ; )
@@ -136,7 +135,7 @@ static inline int elf_sectname(FAR struct elf_loadinfo_s *loadinfo,
       /* Read that number of bytes into the array */
 
       buffer = &loadinfo->iobuffer[bytesread];
-      ret = elf_read(loadinfo, buffer, readlen, offset);
+      ret = elf_read(loadinfo, buffer, readlen, offset + bytesread);
       if (ret < 0)
         {
           berr("Failed to read section name\n");

configs/Kconfig

@@ -708,7 +708,7 @@ config ARCH_BOARD_NUCLEO_144
 	select ARCH_HAVE_IRQBUTTONS
 	---help---
 		STMicro Nucleo-144 development board featuring STMicroelectronics
-		F2, F3, F4 and F7 MCU families.  The board is a "Hardware pattern"
+		F2, F3, F4, F7 and L4 MCU families.  The board is a "Hardware pattern"
 		that can be populated with the 144 pin package of the following MCUs:
 
 			Target STM32    Order code
@@ -716,14 +716,44 @@ config ARCH_BOARD_NUCLEO_144
 			STM32F303ZET6   NUCLEO-F303ZE
 			STM32F429ZIT6   NUCLEO-F429ZI
 			STM32F446ZET6   NUCLEO-F446ZE
+			STM32F746ZGT6   NUCLEO-F746ZG
+			STM32F767ZIT6   NUCLEO-F767ZI
+			STM32L496ZGT6   NUCLEO-L496ZG
+			STM32L496ZGT6P  NUCLEO-L496ZG-P
 
-		Supported in this release are:
+		Supported in this configuration are:
 
-			NUCLEO-F746ZG - STM32F746ZGT6 a 216MHz Cortex-M7, w/FPU - 1024KiB
+			NUCLEO-F746ZG - STM32F746ZGT6 a 216MHz Cortex-M7, w/FPU -
-				Flash memory and 320KiB SRAM.
+				1024KiB Flash memory and 320KiB SRAM.
 			NUCLEO-F767ZI - STM32F767ZIT6 a 216MHz Cortex-M7, w/DPFPU -
 				2048KiB Flash memory and 512KiB SRAM.
 
+config ARCH_BOARD_NUCLEO_L496ZG
+	bool "STM32L496 Nucleo L496ZG"
+	depends on ARCH_CHIP_STM32L496ZG
+	select ARCH_HAVE_LEDS
+	select ARCH_HAVE_BUTTONS
+	select ARCH_HAVE_IRQBUTTONS
+	---help---
+		STMicro Nucleo-144 development board featuring STMicroelectronics
+		F2, F3, F4, F7 and L4 MCU families.  The board is a "Hardware pattern"
+		that can be populated with the 144 pin package of the following MCUs:
+
+			Target STM32    Order code
+			STM32F207ZGT6   NUCLEO-F207ZG
+			STM32F303ZET6   NUCLEO-F303ZE
+			STM32F429ZIT6   NUCLEO-F429ZI
+			STM32F446ZET6   NUCLEO-F446ZE
+			STM32F746ZGT6   NUCLEO-F746ZG
+			STM32F767ZIT6   NUCLEO-F767ZI
+			STM32L496ZGT6   NUCLEO-L496ZG
+			STM32L496ZGT6P  NUCLEO-L496ZG-P
+
+		Supported in this configuration are:
+
+			NUCLEO-L496ZG - STM32L496ZGT6 a 80MHz Cortex-M4, w/FPU -
+				1024KiB Flash memory and 320KiB SRAM.
+
 config ARCH_BOARD_NUCLEO_F072RB
 	bool "STM32F072 Nucleo F072RB"
 	depends on ARCH_CHIP_STM32F072RB
@@ -733,6 +763,15 @@ config ARCH_BOARD_NUCLEO_F072RB
 	---help---
 		STMicro Nucleo F072RB board based on the STMicro STM32F072RBT6 MCU.
 
+config ARCH_BOARD_NUCLEO_F091RC
+	bool "STM32F091 Nucleo F091RC"
+	depends on ARCH_CHIP_STM32F091RC
+	select ARCH_HAVE_LEDS
+	select ARCH_HAVE_BUTTONS
+	select ARCH_HAVE_IRQBUTTONS
+	---help---
+		STMicro Nucleo F091RC board based on the STMicro STM32F091RCT6 MCU.
+
 config ARCH_BOARD_NUCLEO_F303RE
 	bool "STM32F303 Nucleo F303RE"
 	depends on ARCH_CHIP_STM32F303RE
@@ -1514,10 +1553,12 @@ config ARCH_BOARD
 	default "pic32mz-starterkit"       if ARCH_BOARD_PIC32MZ_STARTERKIT
 	default "nucleo-144"               if ARCH_BOARD_NUCLEO_144
 	default "nucleo-f072rb"            if ARCH_BOARD_NUCLEO_F072RB
+	default "nucleo-f091rc"            if ARCH_BOARD_NUCLEO_F091RC
 	default "nucleo-f303re"            if ARCH_BOARD_NUCLEO_F303RE
 	default "nucleo-f334r8"            if ARCH_BOARD_NUCLEO_F334R8
 	default "nucleo-f4x1re"            if ARCH_BOARD_NUCLEO_F401RE || ARCH_BOARD_NUCLEO_F411RE
 	default "nucleo-l476rg"            if ARCH_BOARD_NUCLEO_L476RG
+	default "nucleo-l496zg"            if ARCH_BOARD_NUCLEO_L496ZG
 	default "qemu-i486"                if ARCH_BOARD_QEMU_I486
 	default "sabre-6quad"              if ARCH_BOARD_SABRE_6QUAD
 	default "sama5d2-xult"             if ARCH_BOARD_SAMA5D2_XULT
@@ -1823,6 +1864,9 @@ endif
 if ARCH_BOARD_NUCLEO_F072RB
 source "configs/nucleo-f072rb/Kconfig"
 endif
+if ARCH_BOARD_NUCLEO_F091RC
+source "configs/nucleo-f091rc/Kconfig"
+endif
 if ARCH_BOARD_NUCLEO_F303RE
 source "configs/nucleo-f303re/Kconfig"
 endif
@@ -1835,6 +1879,9 @@ endif
 if ARCH_BOARD_NUCLEO_L476RG
 source "configs/nucleo-l476rg/Kconfig"
 endif
+if ARCH_BOARD_NUCLEO_L496ZG
+source "configs/nucleo-l496zg/Kconfig"
+endif
 if ARCH_BOARD_QEMU_I486
 source "configs/qemu-i486/Kconfig"
 endif

configs/nucleo-144/README.txt

@@ -32,14 +32,17 @@ Nucleo-144 Boards:
 The Nucleo-144 is a standard board for use with several STM32 parts in the
 LQFP144 package.  Variants include
 
-  STM32 Part    Board Variant Name
+  STM32 Part     Board Variant Name
-  ------------- ------------------
+  -------------  ------------------
-  STM32F207ZGT6 NUCLEO-F207ZG
+  STM32F207ZGT6  NUCLEO-F207ZG
-  STM32F303ZET6 NUCLEO-F303ZE
+  STM32F303ZET6  NUCLEO-F303ZE
-  STM32F429ZIT6 NUCLEO-F429ZI
+  STM32F429ZIT6  NUCLEO-F429ZI
-  STM32F446ZET6 NUCLEO-F446ZE
+  STM32F446ZET6  NUCLEO-F446ZE
-  STM32F746ZGT6 NUCLEO-F746ZG
+  STM32F746ZGT6  NUCLEO-F746ZG
-  STM32F767ZIT6 NUCLEO-F767ZI
+  STM32F767ZIT6  NUCLEO-F767ZI
+  STM32L496ZGT6  NUCLEO-L496ZG
+  STM32L496ZGT6P NUCLEO-L496ZG-P
+
   ------------- ------------------
 
 This directory is intended to support all Nucleo-144 variants since the
@@ -48,9 +51,10 @@ board design provides uniformity in the documentation from ST and should
 allow us to quickly change configurations by just cloning a configuration
 and changing the CPU choice and board initialization.  Unfortunately for
 the developer, the CPU specific information must be extracted from the
-common information in the documentation.
+common information in the documentation. The exception are the STM32L496ZG
+boards, which are supported by configs/nucleo-l496zg
 
-Please read the User Manaul UM1727: Getting started with STM32 Nucleo board
+Please read the User Manual UM1727: Getting started with STM32 Nucleo board
 software development tools and take note of the Powering options for the
 board (6.3 Power supply and power selection) and the Solder bridges based
 hardware configuration changes that are configurable (6.11 Solder bridges).

configs/nucleo-144/src/stm32_appinitialize.c

@@ -1,5 +1,5 @@
 /****************************************************************************
- * config/nucleo-144/src/stm32_appinitilaize.c
+ * config/nucleo-144/src/stm32_appinitialize.c
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
  *   Authors: Gregory Nutt <gnutt@nuttx.org>
@@ -42,6 +42,7 @@
 #include <nuttx/config.h>
 
 #include <sys/types.h>
+#include <sys/mount.h>
 #include <debug.h>
 #include <syslog.h>
 

configs/nucleo-f091rc/Kconfig

@@ -0,0 +1,8 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_NUCLEO_F091RC
+
+endif

configs/nucleo-f091rc/README.txt

@@ -0,0 +1,319 @@
+Nucleo-F091RC README
+====================
+
+  This README file discusess the port of NuttX to the STMicro Nucleo-F091RC
+  board.  That board features the STM32F091RCT6 MCU with 256KiB of FLASH
+  and 32KiB of SRAM.
+
+Contents
+========
+
+  - Nucleo-64 Boards
+  - LEDs
+  - Buttons
+  - Serial Console
+  - Configurations
+
+Nucleo-64 Boards
+================
+
+  The Nucleo-F091RC is a member of the Nucleo-64 board family.  The Nucleo-64
+  is a standard board for use with several STM32 parts in the LQFP64 package.
+  Variants including:
+
+    Order code    Targeted STM32
+    ------------- --------------
+    NUCLEO-F030R8 STM32F030R8T6
+    NUCLEO-F070RB STM32F070RBT6
+    NUCLEO-F072RB STM32F072RBT6
+    NUCLEO-F091RC STM32F091RCT6
+    NUCLEO-F103RB STM32F103RBT6
+    NUCLEO-F302R8 STM32F302R8T6
+    NUCLEO-F303RE STM32F303RET6
+    NUCLEO-F334R8 STM32F334R8T6
+    NUCLEO-F401RE STM32F401RET6
+    NUCLEO-F410RB STM32F410RBT6
+    NUCLEO-F411RE STM32F411RET6
+    NUCLEO-F446RE STM32F446RET6
+    NUCLEO-L053R8 STM32L053R8T6
+    NUCLEO-L073RZ STM32L073RZT6
+    NUCLEO-L152RE STM32L152RET6
+    NUCLEO-L452RE STM32L452RET6
+    NUCLEO-L476RG STM32L476RGT6
+
+LEDs
+====
+
+  The Nucleo-64 board has one user controlable LED, User LD2.  This green
+  LED is a user LED connected to Arduino signal D13 corresponding to STM32
+  I/O PA5 (PB13 on other some other Nucleo-64 boards).
+
+    - When the I/O is HIGH value, the LED is on
+    - When the I/O is LOW, the LED is off
+
+  These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+  defined.  In that case, the usage by the board port is defined in
+  include/board.h and src/stm32_autoleds.c. The LEDs are used to encode
+  OS-related events as follows when the red LED (PE24) is available:
+
+    SYMBOL                Meaning                   LD2
+    -------------------  -----------------------  -----------
+    LED_STARTED          NuttX has been started     OFF
+    LED_HEAPALLOCATE     Heap has been allocated    OFF
+    LED_IRQSENABLED      Interrupts enabled         OFF
+    LED_STACKCREATED     Idle stack created         ON
+    LED_INIRQ            In an interrupt            No change
+    LED_SIGNAL           In a signal handler        No change
+    LED_ASSERTION        An assertion failed        No change
+    LED_PANIC            The system has crashed     Blinking
+    LED_IDLE             MCU is is sleep mode       Not used
+
+  Thus if LD2, NuttX has successfully booted and is, apparently, running
+  normally.  If LD2 is flashing at approximately 2Hz, then a fatal error
+  has been detected and the system has halted.
+
+Buttons
+=======
+
+  B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
+  microcontroller.
+
+Serial Console
+==============
+
+  USART1
+  ------
+  Pins and Connectors:
+
+    RXD: PA10  D3  CN9 pin 3, CN10 pin 33
+         PB7                  CN7  pin 21
+    TXD: PA9   D8  CN5 pin 1, CN10 pin 21
+         PB6   D10 CN5 pin 3, CN10 pin 17
+
+  NOTE:  You may need to edit the include/board.h to select different USART1
+  pin selections.
+
+  TTL to RS-232 converter connection:
+
+    Nucleo CN10 STM32F072RB
+    ----------- ------------
+    Pin 21 PA9  USART1_TX   *Warning you make need to reverse RX/TX on
+    Pin 33 PA10 USART1_RX    some RS-232 converters
+    Pin 20 GND
+    Pin 8  U5V
+
+  To configure USART1 as the console:
+
+    CONFIG_STM32_USART1=y
+    CONFIG_USART1_SERIALDRIVER=y
+    CONFIG_USART1_SERIAL_CONSOLE=y
+    CONFIG_USART1_RXBUFSIZE=256
+    CONFIG_USART1_TXBUFSIZE=256
+    CONFIG_USART1_BAUD=115200
+    CONFIG_USART1_BITS=8
+    CONFIG_USART1_PARITY=0
+    CONFIG_USART1_2STOP=0
+
+  USART2
+  ------
+  Pins and Connectors:
+
+    RXD: PA3  To be provided
+         PA15
+         PD6
+    TXD: PA2
+         PA14
+         PD5
+
+  USART3
+  ------
+  Pins and Connectors:
+
+    RXD: PB11 To be provided
+         PC5
+         PC11
+         D9
+    TXD: PB10
+         PC4
+         PC10
+         D8
+
+  See "Virtual COM Port" and "RS-232 Shield" below.
+
+  USART3
+  ------
+  Pins and Connectors:
+
+    RXD: PA1  To be provided
+         PC11
+    TXD: PA0
+         PC10
+
+  Virtual COM Port
+  ----------------
+  Yet another option is to use UART2 and the USB virtual COM port.  This
+  option may be more convenient for long term development, but is painful
+  to use during board bring-up.
+
+  Solder Bridges.  This configuration requires:
+
+  - SB62 and SB63 Open: PA2 and PA3 on STM32 MCU are disconnected to D1
+    and D0 (pin 7 and pin 8) on Arduino connector CN9 and ST Morpho
+    connector CN10.
+
+  - SB13 and SB14 Closed:  PA2 and PA3 on STM32F103C8T6 (ST-LINK MCU) are
+    connected to PA3 and PA2 on STM32 MCU to have USART communication
+    between them. Thus SB61, SB62 and SB63 should be OFF.
+
+  Configuring USART2 is the same as given above.
+
+  Question:  What BAUD should be configure to interface with the Virtual
+  COM port?  115200 8N1?
+
+  Default
+  -------
+  As shipped, SB62 and SB63 are open and SB13 and SB14 closed, so the
+  virtual COM port is enabled.
+
+  RS-232 Shield
+  -------------
+  Supports a single RS-232 connected via
+
+    Nucleo    STM32F4x1RE     Shield
+    --------- --------------- --------
+    CN9 Pin 1 PA3  USART2_RXD RXD
+    CN9 Pin 2 PA2  USART2_TXD TXD
+
+  Support for this shield is enabled by selecting USART2 and configuring
+  SB13, 14, 62, and 63 as described above under "Virtual COM Port"
+
+Configurations
+==============
+
+  Information Common to All Configurations
+  ----------------------------------------
+  Each configuration is maintained in a sub-directory and can be
+  selected as follow:
+
+    cd tools
+    ./configure.sh nucleo-f091rc/<subdir>
+    cd -
+
+  Before building, make sure the PATH environment variable includes the
+  correct path to the directory than holds your toolchain binaries.
+
+  And then build NuttX by simply typing the following.  At the conclusion of
+  the make, the nuttx binary will reside in an ELF file called, simply, nuttx.
+
+    make oldconfig
+    make
+
+  The <subdir> that is provided above as an argument to the tools/configure.sh
+  must be is one of the following.
+
+  NOTES:
+
+    1. These configurations use the mconf-based configuration tool.  To
+      change any of these configurations using that tool, you should:
+
+      a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+         see additional README.txt files in the NuttX tools repository.
+
+      b. Execute 'make menuconfig' in nuttx/ in order to start the
+         reconfiguration process.
+
+    2. Unless stated otherwise, all configurations generate console
+       output on USART2, as described above under "Serial Console".  The 
+       elevant configuration settings are listed below:
+
+         CONFIG_STM32_USART2=y
+         CONFIG_STM32_USART2_SERIALDRIVER=y
+         CONFIG_STM32_USART=y
+
+         CONFIG_USART2_SERIALDRIVER=y
+         CONFIG_USART2_SERIAL_CONSOLE=y
+
+         CONFIG_USART2_RXBUFSIZE=256
+         CONFIG_USART2_TXBUFSIZE=256
+         CONFIG_USART2_BAUD=115200
+         CONFIG_USART2_BITS=8
+         CONFIG_USART2_PARITY=0
+         CONFIG_USART2_2STOP=0
+
+  3. All of these configurations are set up to build under Linux using the
+     "GNU Tools for ARM Embedded Processors" that is maintained by ARM
+     (unless stated otherwise in the description of the configuration).
+
+       https://launchpad.net/gcc-arm-embedded
+
+     That toolchain selection can easily be reconfigured using
+     'make menuconfig'.  Here are the relevant current settings:
+
+     Build Setup:
+       CONFIG_HOST_LINUX=y                 : Linux environment
+
+     System Type -> Toolchain:
+       CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y : GNU ARM EABI toolchain
+
+  Configuration sub-directories
+  -----------------------------
+
+  nsh:
+
+    Configures the NuttShell (nsh) located at examples/nsh.  This
+    configuration is focused on low level, command-line driver testing.
+
+    NOTES:
+
+    1. This initial release of this configuration was very minimal, but
+       also very small:
+
+       $ size nuttx
+          text    data     bss     dec     hex filename
+         32000      92    1172   33264    81f0 nuttx
+
+       The current version, additional features have been enabled:  board
+       bring-up initialization, button support, the procfs file system,
+       and NSH built-in application support.  The size increased as follows:
+
+       $ size nuttx
+          text    data     bss     dec     hex filename
+         40231      92    1208   41531    a23b nuttx
+
+       Those additional features cost about 8KiB FLASH.  I believe that is a
+       good use of the STM32F072RB's FLASH, but if you interested in the
+       more minimal configuration, here is what was changed:
+
+       Removed
+
+         CONFIG_BINFMT_DISABLE=y
+         CONFIG_DISABLE_MOUNTPOINT=y
+         CONFIG_NSH_DISABLE_CD=y
+
+       Added:
+
+         CONFIG_ARCH_BUTTONS=y
+         CONFIG_ARCH_IRQBUTTONS=y
+
+         CONFIG_BUILTIN=y
+         CONFIG_BUILTIN_PROXY_STACKSIZE=1024
+
+         CONFIG_FS_PROCFS=y
+         CONFIG_NSH_PROC_MOUNTPOINT="/proc"
+
+         CONFIG_LIB_BOARDCTL=y
+         CONFIG_NSH_ARCHINIT=y
+         CONFIG_NSH_BUILTIN_APPS=y
+
+       Support for NSH built-in applications is enabled for future use. 
+       However, no built applications are enabled in this base configuration.
+
+    2. C++ support for applications is NOT enabled.  That could be enabled
+       with the following configuration changes:
+
+         CONFIG_HAVE_CXX=y
+         CONFIG_HAVE_CXXINITIALIZE=y
+         CONFIG_EXAMPLES_NSH_CXXINITIALIZE=y
+
+       And also support fo C++ constructors under
+       apps/platform/nucleo-stm32f072rb.

configs/nucleo-f091rc/include/board.h

@@ -0,0 +1,241 @@
+/************************************************************************************
+ * configs/nucleo-f091rc/include/board.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Alan Carvalho de Assis <acassis@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __CONFIG_NUCLEO_F091RC_INCLUDE_BOARD_H
+#define __CONFIG_NUCLEO_F091RC_INCLUDE_BOARD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Clocking *************************************************************************/
+/* Four different clock sources can be used to drive the system clock (SYSCLK):
+ *
+ * - HSI high-speed internal oscillator clock
+ *   Generated from an internal 8 MHz RC oscillator
+ * - HSE high-speed external oscillator clock
+ *   Normally driven by an external crystal (X3).  However, this crystal is not
+ *   fitted on the Nucleo-F091RC board.
+ * - PLL clock
+ * - MSI multispeed internal oscillator clock
+ *   The MSI clock signal is generated from an internal RC oscillator. Seven frequency
+ *   ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz,
+ *   2.097 MHz (default value) and 4.194 MHz.
+ *
+ * The devices have the following two secondary clock sources
+ * - LSI low-speed internal RC clock
+ *   Drives the watchdog and RTC.  Approximately 37KHz
+ * - LSE low-speed external oscillator clock
+ *   Driven by 32.768KHz crystal (X2) on the OSC32_IN and OSC32_OUT pins.
+ */
+
+#define STM32F0_BOARD_XTAL         8000000ul        /* X3 on board (not fitted)*/
+
+#define STM32F0_HSI_FREQUENCY      8000000ul        /* Approximately 8MHz */
+#define STM32F0_HSI14_FREQUENCY    14000000ul       /* HSI14 for ADC */
+#define STM32F0_HSI48_FREQUENCY    48000000ul       /* HSI48 for USB, only some STM32F0xx */
+#define STM32F0_HSE_FREQUENCY      STM32F0_BOARD_XTAL
+#define STM32F0_LSI_FREQUENCY      40000            /* Approximately 40KHz */
+#define STM32F0_LSE_FREQUENCY      32768            /* X2 on board */
+
+/* PLL Configuration
+ *
+ *   - PLL source is HSI       -> 8MHz input (nominal)
+ *   - PLL source predivider 2 -> 4MHz divided down PLL VCO clock output
+ *   - PLL multipler is 12     -> 48MHz PLL VCO clock output (for USB)
+ *
+ * Resulting SYSCLK frequency is 8MHz x 12 / 2 = 48MHz
+ *
+ * USB:
+ *   If the USB interface is used in the application, it requires a precise
+ *   48MHz clock which can be generated from either the (1) the internal
+ *   main PLL with the HSE clock source using an HSE crystal oscillator.  In
+ *   this case,  the PLL VCO clock (defined by STM32F0_CFGR_PLLMUL) must be
+ *   programmed to output a 96 MHz frequency. This is required to provide a
+ *   48MHz clock to the (USBCLK = PLLVCO/2).  Or (2) by using the internal
+ *   48MHz oscillator in automatic trimming mode. The synchronization for
+ *   this oscillator can be taken from the USB data stream itself (SOF
+ *   signalization) which allows crystal-less operation.
+ * SYSCLK
+ *   The system clock is derived from the PLL VCO divided by the output
+ *   division factor.
+ * Limitations:
+ *   - 96 MHz as PLLVCO when the product is in range 1 (1.8V),
+ *   - 48 MHz as PLLVCO when the product is in range 2 (1.5V),
+ *   - 24 MHz when the product is in range 3 (1.2V).
+ *   - Output division to avoid exceeding 32 MHz as SYSCLK.
+ *   - The minimum input clock frequency for PLL is 2 MHz (when using HSE as
+ *     PLL source).
+ */
+
+#define STM32F0_CFGR_PLLSRC        RCC_CFGR_PLLSRC_HSId2         /* Source is HSI/2 */
+#define STM32F0_PLLSRC_FREQUENCY   (STM32F0_HSI_FREQUENCY/2)     /* 8MHz / 2 = 4MHz */
+#ifdef CONFIG_STM32F0_USB
+#  undef  STM32F0_CFGR2_PREDIV                                   /* Not used with source HSI/2 */
+#  define STM32F0_CFGR_PLLMUL      RCC_CFGR_PLLMUL_CLKx12        /* PLLMUL = 12 */
+#  define STM32F0_PLL_FREQUENCY    (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
+#else
+#  undef  STM32F0_CFGR2_PREDIV                                   /* Not used with source HSI/2 */
+#  define STM32F0_CFGR_PLLMUL      RCC_CFGR_PLLMUL_CLKx12        /* PLLMUL = 12 */
+#  define STM32F0_PLL_FREQUENCY    (12*STM32F0_PLLSRC_FREQUENCY) /* PLL VCO Frequency is 48MHz */
+#endif
+
+/* Use the PLL and set the SYSCLK source to be the divided down PLL VCO output
+ * frequency (STM32F0_PLL_FREQUENCY divided by the PLLDIV value).
+ */
+
+#define STM32F0_SYSCLK_SW          RCC_CFGR_SW_PLL       /* Use the PLL as the SYSCLK */
+#define STM32F0_SYSCLK_SWS         RCC_CFGR_SWS_PLL
+#ifdef CONFIG_STM32F0_USB
+#  define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
+#else
+#  define STM32F0_SYSCLK_FREQUENCY STM32F0_PLL_FREQUENCY /* SYSCLK frequency is PLL VCO = 48MHz */
+#endif
+
+#define STM32F0_RCC_CFGR_HPRE      RCC_CFGR_HPRE_SYSCLK
+#define STM32F0_HCLK_FREQUENCY     STM32F0_SYSCLK_FREQUENCY
+#define STM32F0_BOARD_HCLK         STM32F0_HCLK_FREQUENCY    /* Same as above, to satisfy compiler */
+
+/* APB1 clock (PCLK1) is HCLK (48MHz) */
+
+#define STM32F0_RCC_CFGR_PPRE1     RCC_CFGR_PPRE1_HCLK
+#define STM32F0_PCLK1_FREQUENCY    (STM32F0_HCLK_FREQUENCY)
+
+/* APB2 clock (PCLK2) is HCLK (48MHz) */
+
+#define STM32F0_RCC_CFGR_PPRE2     RCC_CFGR_PPRE2_HCLK
+#define STM32F0_PCLK2_FREQUENCY    STM32F0_HCLK_FREQUENCY
+#define STM32F0_APB2_CLKIN         (STM32F0_PCLK2_FREQUENCY)
+
+/* APB1 timers 1-3, 6-7, and 14-17 will receive PCLK1 */
+
+#define STM32F0_APB1_TIM1_CLKIN    (STM32F0_PCLK1_FREQUENCY)
+#define STM32F0_APB1_TIM2_CLKIN    (STM32F0_PCLK1_FREQUENCY)
+#define STM32F0_APB1_TIM3_CLKIN    (STM32F0_PCLK1_FREQUENCY)
+
+#define STM32F0_APB1_TIM6_CLKIN    (STM32F0_PCLK1_FREQUENCY)
+#define STM32F0_APB1_TIM7_CLKIN    (STM32F0_PCLK1_FREQUENCY)
+
+#define STM32F0_APB1_TIM14_CLKIN   (STM32F0_PCLK1_FREQUENCY)
+#define STM32F0_APB1_TIM15_CLKIN   (STM32F0_PCLK1_FREQUENCY)
+#define STM32F0_APB1_TIM16_CLKIN   (STM32F0_PCLK1_FREQUENCY)
+#define STM32F0_APB1_TIM17_CLKIN   (STM32F0_PCLK1_FREQUENCY)
+
+/* LED definitions ******************************************************************/
+/* LEDs
+ *
+ * The Nucleo-64 board has one user controlable LED, User LD2.  This green
+ * LED is a user LED connected to Arduino signal D13 corresponding to STM32
+ * I/O PA5 (PB13 on other some other Nucleo-64 boards).
+ *
+ *   - When the I/O is HIGH value, the LED is on
+ *   - When the I/O is LOW, the LED is off
+ */
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_LD2         0
+#define BOARD_NLEDS       1
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LD2_BIT     (1 << BOARD_LD2)
+
+/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+ * defined.  In that case, the usage by the board port is defined in
+ * include/board.h and src/sam_leds.c. The LEDs are used to encode OS-related
+ * events as follows when the red LED (PE24) is available:
+ *
+ *   SYMBOL                Meaning                   LD2
+ *   -------------------  -----------------------  -----------
+ *   LED_STARTED          NuttX has been started     OFF
+ *   LED_HEAPALLOCATE     Heap has been allocated    OFF
+ *   LED_IRQSENABLED      Interrupts enabled         OFF
+ *   LED_STACKCREATED     Idle stack created         ON
+ *   LED_INIRQ            In an interrupt            No change
+ *   LED_SIGNAL           In a signal handler        No change
+ *   LED_ASSERTION        An assertion failed        No change
+ *   LED_PANIC            The system has crashed     Blinking
+ *   LED_IDLE             MCU is is sleep mode       Not used
+ *
+ * Thus if LD2, NuttX has successfully booted and is, apparently, running
+ * normally.  If LD2 is flashing at approximately 2Hz, then a fatal error
+ * has been detected and the system has halted.
+ */
+
+#define LED_STARTED      0
+#define LED_HEAPALLOCATE 0
+#define LED_IRQSENABLED  0
+#define LED_STACKCREATED 1
+#define LED_INIRQ        2
+#define LED_SIGNAL       2
+#define LED_ASSERTION    2
+#define LED_PANIC        1
+
+/* Button definitions ***************************************************************/
+/* Buttons
+ *
+ * B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
+ * microcontroller.
+ */
+
+#define BUTTON_USER        0
+#define NUM_BUTTONS        1
+
+#define BUTTON_USER_BIT    (1 << BUTTON_USER)
+
+/* Alternate Pin Functions **********************************************************/
+/* USART 1 */
+
+#define GPIO_USART1_TX           GPIO_USART1_TX_2
+#define GPIO_USART1_RX           GPIO_USART1_RX_2
+
+/* USART 2 */
+
+#define GPIO_USART2_TX           GPIO_USART2_TX_3
+#define GPIO_USART2_RX           GPIO_USART2_RX_3
+
+#endif  /* __CONFIG_NUCLEO_F091RC_INCLUDE_BOARD_H */

configs/nucleo-f091rc/nsh/Make.defs

@@ -0,0 +1,113 @@
+############################################################################
+# configs/nucleo-f091rc/nsh/Make.defs
+#
+#   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#           Alan Carvalho de Assis <acassis@gmail.com>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv6-m/Toolchain.defs
+
+LDSCRIPT = flash.ld
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK = $(TOPDIR)/tools/copydir.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mkwindeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+  # Linux/Cygwin-native toolchain
+  MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+  ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDFLAGS += -g
+endif
+
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =

configs/nucleo-f091rc/scripts/flash.ld

@@ -0,0 +1,127 @@
+/****************************************************************************
+ * configs/nucleo-f091rc/scripts/flash.ld
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Alan Carvalho de Assis <acassis@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32F091RCT6 has 256Kb of FLASH beginning at address 0x0800:0000 and
+ * 32Kb of SRAM at address 0x20000000.
+ *
+ * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
+ * where the code expects to begin execution by jumping to the entry point in
+ * the 0x0800:0000 address range.
+ */
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x08000000, LENGTH = 256K
+    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
+}
+
+OUTPUT_ARCH(arm)
+EXTERN(_vectors)
+ENTRY(_stext)
+
+SECTIONS
+{
+	.text :
+	{
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+	} > flash
+
+	.init_section :
+	{
+		_sinit = ABSOLUTE(.);
+		*(.init_array .init_array.*)
+		_einit = ABSOLUTE(.);
+	} > flash
+
+	.ARM.extab :
+	{
+		*(.ARM.extab*)
+	} > flash
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx :
+	{
+		*(.ARM.exidx*)
+	} > flash
+	__exidx_end = ABSOLUTE(.);
+
+	_eronly = ABSOLUTE(.);
+
+	.data :
+	{
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.bss :
+	{
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sram
+
+	/* Stabs debugging sections. */
+
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}

configs/nucleo-f091rc/src/.gitignore

@@ -0,0 +1,2 @@
+/.depend
+/Make.dep

configs/nucleo-f091rc/src/Makefile

@@ -0,0 +1,56 @@
+############################################################################
+# configs/nucleo-f091rc/src/Makefile
+#
+#   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#           Alan Carvalho de Assis <acassis@gmail.com>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+-include $(TOPDIR)/Make.defs
+
+ASRCS =
+CSRCS = stm32_boot.c stm32_bringup.c
+
+ifeq ($(CONFIG_ARCH_LEDS),y)
+CSRCS += stm32_autoleds.c
+else
+CSRCS += stm32_userleds.c
+endif
+
+ifeq ($(CONFIG_ARCH_BUTTONS),y)
+CSRCS += stm32_buttons.c
+endif
+
+ifeq ($(CONFIG_LIB_BOARDCTL),y)
+CSRCS += stm32_appinit.c
+endif
+
+include $(TOPDIR)/configs/Board.mk

configs/nucleo-f091rc/src/nucleo-f091rc.h

@@ -0,0 +1,123 @@
+/****************************************************************************
+ * configs/nucleo-f091rc/src/nucleo-f091rc.h
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Alan Carvalho de Assis <acassis@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __CONFIGS_NUCLEO_F091RC_SRC_NUCLEO_F091RC_H
+#define __CONFIGS_NUCLEO_F091RC_SRC_NUCLEO_F091RC_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/compiler.h>
+#include <stdint.h>
+
+#include "stm32f0_gpio.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+/* How many SPI modules does this chip support? */
+
+#if STM32F0_NSPI < 1
+#  undef CONFIG_STM32F0_SPI1
+#  undef CONFIG_STM32F0_SPI2
+#  undef CONFIG_STM32F0_SPI3
+#elif STM32F0_NSPI < 2
+#  undef CONFIG_STM32F0_SPI2
+#  undef CONFIG_STM32F0_SPI3
+#elif STM32F0_NSPI < 3
+#  undef CONFIG_STM32F0_SPI3
+#endif
+
+/* Nucleo-F091RC GPIOs ******************************************************/
+/* LED.  User LD2: the green LED is a user LED connected to Arduino signal
+ * D13 corresponding to MCU I/O PA5 (pin 21) or PB13 (pin 34) depending on
+ * the STM32 target.
+ *
+ * - When the I/O is HIGH value, the LED is on.
+ * - When the I/O is LOW, the LED is off.
+ */
+
+#define GPIO_LD2        (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_10MHz | \
+                         GPIO_OUTPUT_CLEAR | GPIO_PORTA | GPIO_PIN5)
+
+/* Button definitions *******************************************************/
+/*   B1 USER: the user button is connected to the I/O PC13 (pin 2) of the STM32
+ *   microcontroller.
+ */
+
+#define MIN_IRQBUTTON   BUTTON_USER
+#define MAX_IRQBUTTON   BUTTON_USER
+#define NUM_IRQBUTTONS  1
+
+#define GPIO_BTN_USER   (GPIO_INPUT | GPIO_FLOAT | GPIO_EXTI | \
+                         GPIO_PORTC | GPIO_PIN13)
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public data
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_INITIALIZE=y :
+ *     Called from board_initialize().
+ *
+ *   CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
+ ****************************************************************************/
+
+int stm32_bringup(void);
+
+#endif /* __ASSEMBLY__ */
+#endif /* __CONFIGS_NUCLEO_F091RC_SRC_NUCLEO_F091RC_H */

configs/nucleo-f091rc/src/stm32_appinit.c

@@ -0,0 +1,87 @@
+/****************************************************************************
+ * config/nucleo-f091rc/src/stm32_appinit.c
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Alan Carvalho de Assis <acassis@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+
+#include <nuttx/board.h>
+
+#include "nucleo-f091rc.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_app_initialize
+ *
+ * Description:
+ *   Perform application specific initialization.  This function is never
+ *   called directly from application code, but only indirectly via the
+ *   (non-standard) boardctl() interface using the command BOARDIOC_INIT.
+ *
+ * Input Parameters:
+ *   arg - The boardctl() argument is passed to the board_app_initialize()
+ *         implementation without modification.  The argument has no
+ *         meaning to NuttX; the meaning of the argument is a contract
+ *         between the board-specific initalization logic and the the
+ *         matching application logic.  The value cold be such things as a
+ *         mode enumeration value, a set of DIP switch switch settings, a
+ *         pointer to configuration data read from a file or serial FLASH,
+ *         or whatever you would like to do with it.  Every implementation
+ *         should accept zero/NULL as a default configuration.
+ *
+ * Returned Value:
+ *   Zero (OK) is returned on success; a negated errno value is returned on
+ *   any failure to indicate the nature of the failure.
+ *
+ ****************************************************************************/
+
+int board_app_initialize(uintptr_t arg)
+{
+  /* Did we already initialize via board_initialize()? */
+
+#ifndef CONFIG_BOARD_INITIALIZE
+  return stm32_bringup();
+#else
+  return OK;
+#endif
+}

configs/nucleo-f091rc/src/stm32_autoleds.c

@@ -0,0 +1,96 @@
+/****************************************************************************
+ * configs/nucleo-f091rc/src/stm32_autoleds.c
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+#include "stm32f0_gpio.h"
+#include "nucleo-f091rc.h"
+
+#ifdef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_autoled_initialize
+ ****************************************************************************/
+
+void board_autoled_initialize(void)
+{
+  /* Configure LD2 GPIO for output */
+
+  stm32f0_configgpio(GPIO_LD2);
+}
+
+/****************************************************************************
+ * Name: board_autoled_on
+ ****************************************************************************/
+
+void board_autoled_on(int led)
+{
+  if (led == 1)
+    {
+      stm32f0_gpiowrite(GPIO_LD2, true);
+    }
+}
+
+/****************************************************************************
+ * Name: board_autoled_off
+ ****************************************************************************/
+
+void board_autoled_off(int led)
+{
+  if (led == 1)
+    {
+      stm32f0_gpiowrite(GPIO_LD2, false);
+    }
+}
+
+#endif /* CONFIG_ARCH_LEDS */

configs/nucleo-f091rc/src/stm32_boot.c

@@ -0,0 +1,94 @@
+/************************************************************************************
+ * configs/nucleo-f091rc/src/stm32f0_boot.c
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Alan Carvalho de Assis <acassis@gmail.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "up_arch.h"
+#include "nucleo-f091rc.h"
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32f0_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This entry point
+ *   is called early in the intitialization -- after all memory has been configured
+ *   and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+void stm32f0_boardinitialize(void)
+{
+#ifdef CONFIG_ARCH_LEDS
+  /* Configure on-board LEDs if LED support has been selected. */
+
+  board_autoled_initialize();
+#endif
+}
+
+/****************************************************************************
+ * Name: board_initialize
+ *
+ * Description:
+ *   If CONFIG_BOARD_INITIALIZE is selected, then an additional
+ *   initialization call will be performed in the boot-up sequence to a
+ *   function called board_initialize().  board_initialize() will be
+ *   called immediately after up_initialize() is called and just before the
+ *   initial application is started.  This additional initialization phase
+ *   may be used, for example, to initialize board-specific device drivers.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_BOARD_INITIALIZE
+void board_initialize(void)
+{
+  /* Perform board-specific initialization here if so configured */
+
+  (void)stm32_bringup();
+}
+#endif

configs/nucleo-f091rc/src/stm32_bringup.c

@@ -0,0 +1,82 @@
+/****************************************************************************
+ * config/nucleo-f091rc/src/stm32_bringup.c
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <sys/mount.h>
+#include <sys/types.h>
+#include <debug.h>
+
+#include "nucleo-f091rc.h"
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_bringup
+ *
+ * Description:
+ *   Perform architecture-specific initialization
+ *
+ *   CONFIG_BOARD_INITIALIZE=y :
+ *     Called from board_initialize().
+ *
+ *   CONFIG_BOARD_INITIALIZE=n && CONFIG_LIB_BOARDCTL=y :
+ *     Called from the NSH library
+ *
+ ****************************************************************************/
+
+int stm32_bringup(void)
+{
+  int ret;
+
+#ifdef CONFIG_FS_PROCFS
+  /* Mount the procfs file system */
+
+  ret = mount(NULL, "/proc", "procfs", 0, NULL);
+  if (ret < 0)
+    {
+      ferr("ERROR: Failed to mount procfs at /proc: %d\n", ret);
+    }
+#endif
+
+  UNUSED(ret);
+  return OK;
+}

configs/nucleo-f091rc/src/stm32_buttons.c

@@ -0,0 +1,128 @@
+/****************************************************************************
+ * configs/nucleo-f091rc/src/stm32_buttons.c
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <errno.h>
+
+#include <nuttx/arch.h>
+#include <nuttx/board.h>
+#include <arch/board/board.h>
+
+#include "stm32f0_gpio.h"
+#include "nucleo-f091rc.h"
+
+#ifdef CONFIG_ARCH_BUTTONS
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_button_initialize
+ *
+ * Description:
+ *   board_button_initialize() must be called to initialize button resources.
+ *   After that, board_buttons() may be called to collect the current state
+ *   of all buttons or board_button_irq() may be called to register button
+ *   interrupt handlers.
+ *
+ ****************************************************************************/
+
+void board_button_initialize(void)
+{
+  /* Configure the single button as an input.  NOTE that EXTI interrupts are
+   * also configured for the pin.
+   */
+
+  stm32f0_configgpio(GPIO_BTN_USER);
+}
+
+/****************************************************************************
+ * Name: board_buttons
+ ****************************************************************************/
+
+uint32_t board_buttons(void)
+{
+  /* Check that state of each USER button. A LOW value means that the key is
+   * pressed.
+   */
+
+  bool released = stm32f0_gpioread(GPIO_BTN_USER);
+  return !released;
+}
+
+/************************************************************************************
+ * Button support.
+ *
+ * Description:
+ *   board_button_initialize() must be called to initialize button resources.  After
+ *   that, board_buttons() may be called to collect the current state of all
+ *   buttons or board_button_irq() may be called to register button interrupt
+ *   handlers.
+ *
+ *   After board_button_initialize() has been called, board_buttons() may be called to
+ *   collect the state of all buttons.  board_buttons() returns an 32-bit bit set
+ *   with each bit associated with a button.  See the BUTTON_*_BIT
+ *   definitions in board.h for the meaning of each bit.
+ *
+ *   board_button_irq() may be called to register an interrupt handler that will
+ *   be called when a button is depressed or released.  The ID value is a
+ *   button enumeration value that uniquely identifies a button resource. See the
+ *   BUTTON_* definitions in board.h for the meaning of enumeration
+ *   value.
+ *
+ ************************************************************************************/
+
+#ifdef CONFIG_ARCH_IRQBUTTONS
+int board_button_irq(int id, xcpt_t irqhandler, FAR void *arg)
+{
+  int ret = -EINVAL;
+
+  if (id == BUTTON_USER)
+    {
+      ret = stm32f0_gpiosetevent(GPIO_BTN_USER, true, true, true, irqhandler, arg);
+    }
+
+  return ret;
+}
+#endif
+#endif /* CONFIG_ARCH_BUTTONS */

configs/nucleo-f091rc/src/stm32_userleds.c

@@ -0,0 +1,217 @@
+/****************************************************************************
+ * configs/nucleo-f091rc/src/stm32_userleds.c
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <debug.h>
+
+#include <arch/board/board.h>
+#include <nuttx/power/pm.h>
+
+#include "chip.h"
+#include "up_arch.h"
+#include "up_internal.h"
+#include "stm32f0_gpio.h"
+#include "nucleo-f091rc.h"
+
+#ifndef CONFIG_ARCH_LEDS
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/* LED Power Management */
+
+#ifdef CONFIG_PM
+static void led_pm_notify(struct pm_callback_s *cb, int domain,
+                          enum pm_state_e pmstate);
+static int led_pm_prepare(struct pm_callback_s *cb, int domain,
+                          enum pm_state_e pmstate);
+#endif
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static struct pm_callback_s g_ledscb =
+{
+  .notify  = led_pm_notify,
+  .prepare = led_pm_prepare,
+};
+#endif
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: led_pm_notify
+ *
+ * Description:
+ *   Notify the driver of new power state. This callback is called after
+ *   all drivers have had the opportunity to prepare for the new power state.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static void led_pm_notify(struct pm_callback_s *cb, int domain,
+                          enum pm_state_e pmstate)
+{
+  switch (pmstate)
+    {
+      case(PM_NORMAL):
+        {
+          /* Restore normal LEDs operation */
+
+        }
+        break;
+
+      case(PM_IDLE):
+        {
+          /* Entering IDLE mode - Turn leds off */
+
+        }
+        break;
+
+      case(PM_STANDBY):
+        {
+          /* Entering STANDBY mode - Logic for PM_STANDBY goes here */
+
+        }
+        break;
+
+      case(PM_SLEEP):
+        {
+          /* Entering SLEEP mode - Logic for PM_SLEEP goes here */
+
+        }
+        break;
+
+      default:
+        {
+          /* Should not get here */
+
+        }
+        break;
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: led_pm_prepare
+ *
+ * Description:
+ *   Request the driver to prepare for a new power state. This is a warning
+ *   that the system is about to enter into a new power state. The driver
+ *   should begin whatever operations that may be required to enter power
+ *   state. The driver may abort the state change mode by returning a
+ *   non-zero value from the callback function.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+static int led_pm_prepare(struct pm_callback_s *cb, int domain,
+                          enum pm_state_e pmstate)
+{
+  /* No preparation to change power modes is required by the LEDs driver.
+   * We always accept the state change by returning OK.
+   */
+
+  return OK;
+}
+#endif
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: board_userled_initialize
+ ****************************************************************************/
+
+void board_userled_initialize(void)
+{
+  /* Configure LD2 GPIO for output */
+
+  stm32f0_configgpio(GPIO_LD2);
+}
+
+/****************************************************************************
+ * Name: board_userled
+ ****************************************************************************/
+
+void board_userled(int led, bool ledon)
+{
+  if (led == 1)
+    {
+      stm32f0_gpiowrite(GPIO_LD2, ldeon);
+    }
+}
+
+/****************************************************************************
+ * Name: board_userled_all
+ ****************************************************************************/
+
+void board_userled_all(uint8_t ledset)
+{
+  if (led == 1)
+    {
+      stm32f0_gpiowrite(GPIO_LD2, (ledset & BOARD_LD2_BIT) != 0);
+    }
+}
+
+/****************************************************************************
+ * Name: stm32f0_led_pminitialize
+ ****************************************************************************/
+
+#ifdef CONFIG_PM
+void stm32f0_led_pminitialize(void)
+{
+  /* Register to receive power management callbacks */
+
+  int ret = pm_register(&g_ledscb);
+  DEBUGASSERT(ret == OK);
+  UNUSED(ret);
+}
+#endif /* CONFIG_PM */
+
+#endif /* !CONFIG_ARCH_LEDS */

configs/nucleo-f334r8/include/board.h

@@ -237,8 +237,14 @@
 #define GPIO_USART1_RX GPIO_USART1_RX_1 /* PA10 */
 #define GPIO_USART1_TX GPIO_USART1_TX_1 /* PA9 */
 
-/* HRTIM */
+/* COMP */
 
+/* OPAMP */
+
+#define OPAMP2_VMSEL OPAMP2_VMSEL_PC5
+#define OPAMP2_VPSEL OPAMP2_VPSEL_PB14
+
+/* HRTIM */
 
 /* DMA channels *************************************************************/
 /* ADC */

configs/nucleo-f334r8/src/nucleo-f334r8.h

@@ -202,4 +202,16 @@ int stm32_can_setup(void);
 int stm32_comp_setup(void);
 #endif
 
+/****************************************************************************
+ * Name: stm32_opamp_setup
+ *
+ * Description:
+ *  Initialize OPAMP peripheral for the board.
+ *
+ ****************************************************************************/
+
+#ifdef CONFIG_OPAMP
+int stm32_opamp_setup(void);
+#endif
+
 #endif /* __CONFIGS_NUCLEO_F334R8_SRC_NUCLEO_F334R8_H */

configs/nucleo-f334r8/src/stm32_appinit.c

@@ -137,6 +137,16 @@ int board_app_initialize(uintptr_t arg)
     }
 #endif
 
+#ifdef CONFIG_OPAMP
+  /* Initialize OPAMP and register the OPAMP driver. */
+
+  ret = stm32_opamp_setup();
+  if (ret < 0)
+    {
+      syslog(LOG_ERR, "ERROR: stm32_opamp_setup failed: %d\n", ret);
+    }
+#endif
+
   UNUSED(ret);
   return OK;
 }

configs/nucleo-f334r8/src/stm32_opamp.c

@@ -0,0 +1,99 @@
+/****************************************************************************
+ * configs/nucleo-f334r8/src/stm32_opamp.c
+ *
+ *   Copyright (C) 2017 Gregory Nutt. All rights reserved.
+ *   Author: Mateusz Szafoni <raiden00@railab.me>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include <stdbool.h>
+#include <errno.h>
+#include <debug.h>
+
+#include <nuttx/board.h>
+#include <nuttx/analog/opamp.h>
+
+#include "stm32.h"
+
+#if defined(CONFIG_OPAMP) && defined(CONFIG_STM32_OPAMP2)
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: stm32_opamp_setup
+ *
+ * Description:
+ *   Initialize OPAMP
+ *
+ ****************************************************************************/
+
+int stm32_opamp_setup(void)
+{
+  static bool initialized = false;
+  struct opamp_dev_s* opamp = NULL;
+  int ret;
+
+  if (!initialized)
+    {
+      /* Get the OPAMP interface */
+
+#ifdef CONFIG_STM32_OPAMP2
+      opamp = stm32_opampinitialize(2);
+      if (opamp == NULL)
+        {
+          aerr("ERROR: Failed to get OPAMP%d interface\n", 2);
+          return -ENODEV;
+        }
+#endif
+
+      /* Register the OPAMP character driver at /dev/opamp0 */
+
+      ret = opamp_register("/dev/opamp0", opamp);
+      if (ret < 0)
+        {
+          aerr("ERROR: opamp_register failed: %d\n", ret);
+          return ret;
+        }
+
+      initialized = true;
+    }
+
+  return OK;
+}
+
+#endif /* CONFIG_OPAMP && CONFIG_STM32_OPAMP2 */

configs/nucleo-l476rg/README.txt

@@ -6,9 +6,9 @@ NucleoL476RG board from ST Micro.  See
 
   http://www.st.com/nucleo-l476rg
 
-NucleoF476RG:
+NucleoL476RG:
 
-  Microprocessor: 32-bit ARM Cortex M4 at 80MHz STM32F476RGT6
+  Microprocessor: 32-bit ARM Cortex M4 at 80MHz STM32L476RGT6
   Memory:         1024 KB Flash and 96+32 KB SRAM
   ADC:            2×12-bit, 2.4 MSPS A/D converter: up to 24 channels
   DMA:            16-stream DMA controllers with FIFOs and burst support

configs/nucleo-l476rg/scripts/l476rg.ld

@@ -34,7 +34,7 @@
  *
  ****************************************************************************/
 
-/* The STM32F411RE has 512Kb of FLASH beginning at address 0x0800:0000 and
+/* The STM32L476RG has 512Kb of FLASH beginning at address 0x0800:0000 and
  * 128Kb of SRAM beginning at address 0x2000:0000.  When booting from FLASH,
  * FLASH memory is aliased to address 0x0000:0000 where the code expects to
  * begin execution by jumping to the entry point in the 0x0800:0000 address

configs/nucleo-l496zg/Kconfig

@@ -0,0 +1,223 @@
+#
+# For a description of the syntax of this configuration file,
+# see the file kconfig-language.txt in the NuttX tools repository.
+#
+
+if ARCH_BOARD_NUCLEO_144
+
+choice
+	prompt "Select Console wiring."
+	default NUCLEO_ARDUINO
+	---help---
+		Select where you will connect the console.
+
+		Virtual COM Port:
+
+		Advantage: Use the ST-Link as a console. No Extra wiring
+		neded.
+
+		Disdvantage: Not the best choice for initial bring up.
+
+		ARDUINO Connector:
+
+		Advantage: You have a shield so it is
+		easy.
+
+		Disdvantage: You loose the use of the
+		other functions on PC6, PC7
+
+				STM32F7
+			ARDUIONO FUNCTION  GPIO
+			-- ----- --------- ----
+			DO RX    USART6_RX PG9
+			D1 TX    USART6_TX PG14
+			-- ----- --------- ---
+
+					OR
+
+		Morpho Connector:
+
+				STM32F7
+			MORPHO   FUNCTION  GPIO
+			-------- --------- -----
+			CN12-64  USART8_RX PE0
+			CN11-61  USART8_TX PE1
+			-------- --------- -----
+
+config NUCLEO_CONSOLE_ARDUINO
+	bool "ARDUINO Connector"
+	select STM32F7_USART6
+	select USART6_SERIALDRIVER
+	select USART6_SERIAL_CONSOLE
+
+config NUCLEO_CONSOLE_VIRTUAL
+	bool "Virtual Comport"
+	select STM32F7_USART3
+	select USART3_SERIALDRIVER
+	select USART3_SERIAL_CONSOLE
+
+config NUCLEO_CONSOLE_MORPHO
+	bool "Morpho Connector"
+	select STM32F7_UART8
+	select UART8_SERIALDRIVER
+	select UART8_SERIAL_CONSOLE
+
+config NUCLEO_CONSOLE_NONE
+	bool "No Console"
+
+endchoice # "Select Console wiring"
+
+config NUCLEO_SPI_TEST
+	bool "Enable SPI test"
+	default n
+	---help---
+		Enable Spi test - initalize and configure SPI to send
+		NUCLEO_SPI_TEST_MESSAGE text. The text is sent on the
+		selected SPI Buses with the configured parameters.
+		Note the CS lines will not be asserted.
+
+if NUCLEO_SPI_TEST
+
+config NUCLEO_SPI_TEST_MESSAGE
+	string "Text to Send on SPI Bus(es)"
+	default "Hello World"
+	depends on NUCLEO_SPI_TEST
+	---help---
+		Text to sent on SPI bus(es)
+
+config NUCLEO_SPI1_TEST
+	bool "Test SPI bus 1"
+	default n
+	depends on NUCLEO_SPI_TEST
+	---help---
+		Enable Spi test - on SPI BUS 1
+
+if NUCLEO_SPI1_TEST
+
+config NUCLEO_SPI1_TEST_FREQ
+	int "SPI 1 Clock Freq in Hz"
+	default 1000000
+	depends on NUCLEO_SPI1_TEST
+	---help---
+		Sets SPI 1 Clock Freq
+
+config NUCLEO_SPI1_TEST_BITS
+	int "SPI 1 number of bits"
+	default 8
+	depends on NUCLEO_SPI1_TEST
+	---help---
+		Sets SPI 1 bit length
+
+choice
+	prompt "SPI BUS 1 Clock Mode"
+	default NUCLEO_SPI1_TEST_MODE3
+	---help---
+		Sets SPI 1 clock mode
+
+config NUCLEO_SPI1_TEST_MODE0
+	bool "CPOL=0 CHPHA=0"
+
+config NUCLEO_SPI1_TEST_MODE1
+	bool "CPOL=0 CHPHA=1"
+
+config NUCLEO_SPI1_TEST_MODE2
+	bool "CPOL=1 CHPHA=0"
+
+config NUCLEO_SPI1_TEST_MODE3
+	bool "CPOL=1 CHPHA=1"
+
+endchoice # "SPI BUS 1 Clock Mode"
+
+endif # NUCLEO_SPI1_TEST
+
+config NUCLEO_SPI2_TEST
+	bool "Test SPI bus 2"
+	default n
+	depends on NUCLEO_SPI_TEST
+	---help---
+		Enable Spi test - on SPI BUS 2
+
+if NUCLEO_SPI2_TEST
+
+config NUCLEO_SPI2_TEST_FREQ
+	int "SPI 2 Clock Freq in Hz"
+	default 12000000
+	depends on NUCLEO_SPI2_TEST
+	---help---
+		Sets SPI 2 Clock Freq
+
+config NUCLEO_SPI2_TEST_BITS
+	int "SPI 2 number of bits"
+	default 8
+	depends on NUCLEO_SPI2_TEST
+	---help---
+		Sets SPI 2 bit length
+
+choice
+	prompt "SPI BUS 2 Clock Mode"
+	default NUCLEO_SPI2_TEST_MODE3
+	---help---
+		Sets SPI 2 clock mode
+
+config NUCLEO_SPI2_TEST_MODE0
+	bool "CPOL=0 CHPHA=0"
+
+config NUCLEO_SPI2_TEST_MODE1
+	bool "CPOL=0 CHPHA=1"
+
+config NUCLEO_SPI2_TEST_MODE2
+	bool "CPOL=1 CHPHA=0"
+
+config NUCLEO_SPI2_TEST_MODE3
+	bool "CPOL=1 CHPHA=1"
+
+endchoice # "SPI BUS 2 Clock Mode"
+
+endif # NUCLEO_SPI2_TEST
+
+config NUCLEO_SPI3_TEST
+	bool "Test SPI bus 3"
+	default n
+	depends on NUCLEO_SPI_TEST
+	---help---
+		Enable Spi test - on SPI BUS 3
+
+if NUCLEO_SPI3_TEST
+
+config NUCLEO_SPI3_TEST_FREQ
+	int "SPI 3 Clock Freq in Hz"
+	default 40000000
+	depends on NUCLEO_SPI3_TEST
+	---help---
+		Sets SPI 3 Clock Freq
+
+config NUCLEO_SPI3_TEST_BITS
+	int "SPI 3 number of bits"
+	default 8
+	depends on NUCLEO_SPI3_TEST
+	---help---
+		Sets SPI 3 bit length
+
+choice
+	prompt "SPI BUS 3 Clock Mode"
+	default NUCLEO_SPI3_TEST_MODE3
+	---help---
+		Sets SPI 3 clock mode
+
+config NUCLEO_SPI3_TEST_MODE0
+	bool "CPOL=0 CHPHA=0"
+
+config NUCLEO_SPI3_TEST_MODE1
+	bool "CPOL=0 CHPHA=1"
+
+config NUCLEO_SPI3_TEST_MODE2
+	bool "CPOL=1 CHPHA=0"
+
+config NUCLEO_SPI3_TEST_MODE3
+	bool "CPOL=1 CHPHA=1"
+
+endchoice # "SPI BUS 3 Clock Mode"
+
+endif # NUCLEO_SPI3_TEST
+endif # NUCLEO_SPI_TEST
+endif # ARCH_BOARD_NUCLEO_144

configs/nucleo-l496zg/README.txt

@@ -0,0 +1,378 @@
+README
+======
+
+This README discusses issues unique to NuttX configurations for the STMicro
+Nucleo-144 board.  See
+
+http://www.st.com/content/ccc/resource/technical/document/data_brief/group0/7b/df/1d/e9/64/55/43/8d/DM00247910/files/DM00247910.pdf/jcr:content/translations/en.DM00247910.pdf
+
+Contents
+========
+
+  - Nucleo-144 Boards
+  - Nucleo L496ZG
+  - Hardware
+    - Button
+    - LED
+    - U[S]ARTs and Serial Consoles
+    - SPI
+    - SDIO - MMC
+  - SPI Test
+  - Configurations
+     nsh
+
+Nucleo-144 Boards:
+=================
+
+The Nucleo-144 is a standard board for use with several STM32 parts in the
+LQFP144 package.  Variants include
+
+  STM32 Part     Board Variant Name
+  -------------  ------------------
+  STM32F207ZGT6  NUCLEO-F207ZG
+  STM32F303ZET6  NUCLEO-F303ZE
+  STM32F429ZIT6  NUCLEO-F429ZI
+  STM32F446ZET6  NUCLEO-F446ZE
+  STM32F746ZGT6  NUCLEO-F746ZG
+  STM32F767ZIT6  NUCLEO-F767ZI
+  STM32L496ZGT6  NUCLEO-L496ZG
+  STM32L496ZGT6P NUCLEO-L496ZG-P
+
+  ------------- ------------------
+
+This directory supports the L4 variants of Nucleo-144
+
+Please read the User Manual UM2179: Getting started with STM32 Nucleo board
+software development tools and take note of the Powering options for the
+board (6.3 Power supply and power selection) and the Solder bridges based
+hardware configuration changes that are configurable (6.11 Solder bridges).
+
+Also note that UM1727 is not valid for L4 Nucleo-144 boards!
+
+Common Board Features:
+---------------------
+
+  Peripherals:    8 leds, 2 push button (3 LEDs, 1 button) under software
+                  control
+  Debug:          STLINK/V2-1 debugger/programmer Uses a STM32F103CB to
+                  provide a ST-Link for programming, debug similar to the
+                  OpenOcd FTDI function - USB to JTAG front-end.
+
+  Expansion I/F:  ST Zio and Extended Ardino and Morpho Headers
+
+Nucleo L496ZG
+=============
+
+ST Nucleo L496ZG board from ST Micro is supported.  See
+
+http://www.st.com/content/st_com/en/products/evaluation-tools/product-evaluation-tools/mcu-eval-tools/stm32-mcu-eval-tools/stm32-mcu-nucleo/nucleo-l496zg.html
+
+The Nucleo L496ZG order part number is NUCLEO-L496ZG. It is one member of
+the STM32 Nucleo-144 board family.
+
+NUCLEO-L496ZG Features:
+----------------------
+
+  Microprocessor: STM32L496ZGT6 Core: ARM 32-bit Cortex®-M4 CPU with FPU,
+                  80 MHz, MPU, and DSP instructions.
+  Memory:         1024 KB Flash 320KB of SRAM (including 64KB of SRAM2)
+  ADC:            3×12-bit: up to 24 channels 
+  DMA:            2 X 7-stream DMA controllers with FIFOs and burst support
+  Timers:         Up to 13 timers: (2x 16-bit lowpower), two 32-bit timers,
+                  2x watchdogs, SysTick
+  GPIO:           114 I/O ports with interrupt capability
+  LCD:            LCD-TFT Controller, Parallel interface
+  I2C:            4 × I2C interfaces (SMBus/PMBus)
+  U[S]ARTs:       3 USARTs, 2 UARTs (27 Mbit/s, ISO7816 interface, LIN, IrDA,
+                  modem control)
+  SPI/12Ss:       6/3 (simplex) (up to 50 Mbit/s), 3 with muxed simplex I2S
+                  for audio class accuracy via internal audio PLL or external
+                  clock
+  QSPI:           Dual mode Quad-SPI
+  SAIs:           2 Serial Audio Interfaces
+  CAN:            2 X CAN interface
+  SDMMC interface
+  USB:            USB 2.0 full-speed device/host/OTG controller with on-chip
+                  PHY
+  Camera Interface: 8/14 Bit
+  CRC calculation unit
+  TRG:            True random number generator
+  RTC
+
+See https://developer.mbed.org/platforms/ST-Nucleo-L496ZG  for additional
+information about this board.
+
+Hardware
+========
+< Section needs updating >
+
+  GPIO - there are 144 I/O lines on the STM32L4xxZx with various pins pined out
+  on the Nucleo 144.
+
+  Keep in mind that:
+   1) The I/O is 3.3 Volt not 5 Volt like on the Arduino products.
+   2) The Nucleo-144 board family has 3 pages of Solder Bridges AKA Solder
+      Blobs (SB) that can alter the factory configuration. We will note SB
+      in effect but will assume the facitory defualt settings.
+
+  Our main concern is establishing a console and LED utilization for
+  debugging. Because so many pins can be multiplexed with so many functions,
+  the above mentioned graphic may be helpful in indentifying a serial port.
+
+  There are 4 choices that can be made from the menuconfig:
+
+  CONFIG_NUCLEO_CONSOLE_ARDUINO or CONFIG_NUCLEO_CONSOLE_MORPHO or
+  CONFIG_NUCLEO_CONSOLE_VIRTUAL or CONFIG_NUCLEO_CONSOLE_NONE
+
+  The CONFIG_NUCLEO_CONSOLE_NONE makes no preset for the console. You should still visit
+  the U[S]ART selection and Device Drivers to disable any U[S]ART reamaing.
+
+  The CONFIG_NUCLEO_CONSOLE_ARDUINO configurations assume that you are using a
+  standard Arduio RS-232 shield with the serial interface with RX on pin D0 and
+  TX on pin D1 from USART6:
+
+            -------- ---------------
+                        STM32F7
+            ARDUIONO FUNCTION  GPIO
+            -- ----- --------- -----
+            DO RX    USART6_RX PG9
+            D1 TX    USART6_TX PG14
+            -- ----- --------- -----
+
+  The CONFIG_NUCLEO_CONSOLE_MORPHO configurations uses Serial Port 8 (USART8)
+  with TX on PE1 and RX on PE0.
+          Serial
+            ------
+            SERIAL_RX         PE_0
+            SERIAL_TX         PE_1
+
+  The CONFIG_NUCLEO_CONSOLE_VIRTUAL configurations uses Serial Port 3 (USART3)
+  with TX on PD8 and RX on PD9.
+          Serial
+            ------
+            SERIAL_RX         PD9
+            SERIAL_TX         PD8
+
+  These signals are internally connected to the on board ST-Link
+
+  Of course if your design  has used those pins you can choose a completely
+  different U[S]ART to use as the console. In that Case, you will need to edit
+  the include/board.h to select different U[S]ART and / or pin selections.
+
+  Buttons
+  -------
+  B1 USER: the user button is connected to the I/O PC13 (Tamper support, SB173
+           ON and SB180 OFF)
+
+  LEDs
+  ----
+  The Board provides a 3 user LEDs, LD1-LD3
+  LED1 (Green)      PB_0  (SB120 ON and SB119 OFF)
+  LED2 (Blue)       PB_7  (SB139 ON)
+  LED3 (Red)        PB_14 (SP118 ON)
+
+    - When the I/O is HIGH value, the LEDs are on.
+    - When the I/O is LOW, the LEDs are off.
+
+  These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is
+  defined.  In that case, the usage by the board port is defined in
+  include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS
+  related events as follows when the LEDs are available:
+
+  SYMBOL                Meaning                  RED  GREEN BLUE
+  -------------------  -----------------------   ---  ----- ----
+
+  LED_STARTED          NuttX has been started    OFF  OFF   OFF
+  LED_HEAPALLOCATE     Heap has been allocated   OFF  OFF   ON
+  LED_IRQSENABLED      Interrupts enabled        OFF  ON    OFF
+  LED_STACKCREATED     Idle stack created        OFF  ON    ON
+  LED_INIRQ            In an interrupt           NC   NC    ON  (momentary)
+  LED_SIGNAL           In a signal handler       NC   ON    OFF (momentary)
+  LED_ASSERTION        An assertion failed       ON   NC    ON  (momentary)
+  LED_PANIC            The system has crashed    ON   OFF   OFF (flashing 2Hz)
+  LED_IDLE             MCU is is sleep mode      ON   OFF   OFF
+
+
+OFF -    means that the OS is still initializing. Initialization is very fast
+         so if you see this at all, it probably means that the system is
+         hanging up somewhere in the initialization phases.
+
+GREEN -  This means that the OS completed initialization.
+
+BLUE  -  Whenever and interrupt or signal handler is entered, the BLUE LED is
+         illuminated and extinguished when the interrupt or signal handler
+         exits.
+
+VIOLET - If a recovered assertion occurs, the RED and blue LED will be
+         illuminated briefly while the assertion is handled.  You will
+         probably never see this.
+
+Flashing RED - In the event of a fatal crash, all other LEDs will be
+          extinguished and RED LED will FLASH at a 2Hz rate.
+
+
+  Thus if the GREEN LED is lit, NuttX has successfully booted and is,
+  apparently, running normally.  If the RED LED is flashing at
+  approximately 2Hz, then a fatal error has been detected and the system has
+  halted.
+
+Serial Consoles
+===============
+< Section needs updating >
+
+  USART6 (CONFIG_NUCLEO_CONSOLE_ARDUINO)
+  ------
+                STM32F7
+    ARDUIONO FUNCTION  GPIO
+    -- ----- --------- -----
+    DO RX    USART6_RX PG9
+    D1 TX    USART6_TX PG14
+    -- ----- --------- -----
+
+  You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL
+
+    Nucleo 144           FTDI TTL-232R-3V3
+    -------------       -------------------
+    TXD - D1-TXD   -    RXD - Pin 5 (Yellow)
+    RXD - D0-RXD   -    TXD - Pin 4 (Orange)
+    GND   GND      -    GND   Pin 1  (Black)
+    -------------       -------------------
+
+    *Note you will be reverse RX/TX
+
+  Use make menuconfig to configure USART6 as the console:
+
+    CONFIG_STM32F7_USART6=y
+    CONFIG_USARTs_SERIALDRIVER=y
+    CONFIG_USARTS_SERIAL_CONSOLE=y
+    CONFIG_USART6_RXBUFSIZE=256
+    CONFIG_USART6_TXBUFSIZE=256
+    CONFIG_USART6_BAUD=115200
+    CONFIG_USART6_BITS=8
+    CONFIG_USART6_PARITY=0
+    CONFIG_USART6_2STOP=0
+
+  USART8 (CONFIG_NUCLEO_CONSOLE_MORPHO)
+  ------
+
+  Pins and Connectors:
+    FUNC GPIO  Connector
+                   Pin NAME
+    ---- ---   ------- ----
+    TXD: PE1   CN11-61, PE1
+    RXD: PE0   CN12-64, PE0
+               CN10-33, D34
+    ---- ---   ------- ----
+
+
+  You must use a 3.3 TTL to RS-232 converter or a USB to 3.3V TTL
+
+    Nucleo 144           FTDI TTL-232R-3V3
+    -------------       -------------------
+    TXD - CN11-61   -   RXD - Pin 5 (Yellow)
+    RXD - CN12-64   -   TXD - Pin 4 (Orange)
+    GND   CN12-63   -   GND   Pin 1  (Black)
+    -------------       -------------------
+
+    *Note you will be reverse RX/TX
+
+  Use make menuconfig to configure USART8 as the console:
+
+    CONFIG_STM32L4_UART8=y
+    CONFIG_UART8_SERIALDRIVER=y
+    CONFIG_UART8_SERIAL_CONSOLE=y
+    CONFIG_UART8_RXBUFSIZE=256
+    CONFIG_UART8_TXBUFSIZE=256
+    CONFIG_UART8_BAUD=115200
+    CONFIG_UART8_BITS=8
+    CONFIG_UART8_PARITY=0
+    CONFIG_UART8_2STOP=0
+
+  Virtual COM Port (CONFIG_NUCLEO_CONSOLE_VIRTUAL)
+  ----------------
+  Yet another option is to use USART3 and the USB virtual COM port.  This
+  option may be more convenient for long term development, but is painful
+  to use during board bring-up.
+
+  Solder Bridges.  This configuration requires:
+
+    PD8 USART3 TX SB5 ON and SB7 OFF (Default)
+    PD9 USART3 RX SB6 ON and SB4 OFF (Default)
+
+  Configuring USART3 is the same as given above but add the S and #3.
+
+  Question:  What BAUD should be configure to interface with the Virtual
+  COM port?  115200 8N1?
+
+  Default
+  -------
+  As shipped, SB4 and SB7 are open and SB5 and SB6 closed, so the
+  virtual COM port is enabled.
+
+
+SPI
+---
+  Since this board is so generic, having a quick way to vet the SPI
+  configuration seams in order. So the board provides a quick test
+  that can be selected vi CONFIG_NUCLEO_SPI_TEST that will initalise
+  the selected buses (SPI1-SPI3) and send some text on the bus at
+  application initalization time board_app_initialize.
+
+SDIO
+----
+  To test the SD performace one can use a SparkFun microSD Sniffer
+  from https://www.sparkfun.com/products/9419 or similar board
+  and connect it as follows:
+
+          VCC    V3.3 CN11  16
+          GND    GND  CN11-8
+          CMD    PD2  CN11-4
+          CLK    PC12 CN11-3
+          DAT0 - PC8  CN12-2
+          DAT1 - PC9  CN12-1
+          DAT2   PC10 CN11-1
+          CD     PC11 CN11-2
+
+Configurations
+==============
+
+nsh:
+----
+  Configures the NuttShell (nsh) located at apps/examples/nsh for the
+  Nucleo-144 boards.  The Configuration enables the serial interfaces
+  on USART6.  Support for builtin applications is enabled, but in the base
+  configuration no builtin applications are selected (see NOTES below).
+
+  NOTES:
+
+  1. This configuration uses the mconf-based configuration tool.  To
+     change this configuration using that tool, you should:
+
+     a. Build and install the kconfig-mconf tool.  See nuttx/README.txt
+        see additional README.txt files in the NuttX tools repository.
+
+     b. If this is the intall configuration then Execute
+           'cd tools && ./configure.sh nucleo-144/nsh && cd ..'
+        in nuttx/ in order to start configuration process.
+        Caution: Doing this step more than once will overwrite .config with
+        the contents of the nucleo-144/nsh/defconfig file.
+
+     c. Execute 'make oldconfig' in nuttx/ in order to refresh the
+        configuration.
+
+     d. Execute 'make menuconfig' in nuttx/ in order to start the
+        reconfiguration process.
+
+     e. Save the .config file to reuse it in the future starting at step d.
+
+  2. By default, this configuration uses the ARM GNU toolchain
+     for Linux.  That can easily be reconfigured, of course.
+
+     CONFIG_HOST_LINUX=y                     : Builds under Linux
+     CONFIG_ARMV7M_TOOLCHAIN_GNU_EABIL=y     : ARM GNU for Linux
+
+  3. Although the default console is USART3 (which would correspond to
+     the Virtual COM port) I have done all testing with the console
+     device configured for UART8 (see instruction above under "Serial
+     Consoles).
+

configs/nucleo-l496zg/include/board.h

@@ -0,0 +1,458 @@
+/************************************************************************************
+ * configs/nucleo-l496zg/include/board.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *           Mark Olsson <post@markolsson.se>
+ *           David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __CONFIG_NUCLEO_L496ZG_INCLUDE_BOARD_H
+#define __CONFIG_NUCLEO_L496ZG_INCLUDE_BOARD_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+#ifndef __ASSEMBLY__
+# include <stdint.h>
+#endif
+
+#ifdef __KERNEL__
+#include "stm32l4_rcc.h"
+#ifdef CONFIG_STM32L4_SDMMC1
+#  include "stm32l4_sdmmc.h"
+#endif
+#endif
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/* Clocking *************************************************************************/
+/* The Nucleo-144  board provides the following clock sources:
+ *
+ *   MCO: 8 MHz from MCO output of ST-LINK is used as input clock
+ *   X2:  32.768 KHz crystal for LSE
+ *   X3:  HSE crystal oscillator (not provided)
+ *
+ * So we have these clock source available within the STM32
+ *
+ *   HSI: 16 MHz RC factory-trimmed
+ *   LSI: 32 KHz RC
+ *   HSE: 8 MHz from MCO output of ST-LINK
+ *   LSE: 32.768 kHz
+ */
+
+
+#define STM32_BOARD_XTAL        8000000ul
+
+#define STM32_HSI_FREQUENCY     16000000ul
+#define STM32_LSI_FREQUENCY     32000
+#define STM32_HSE_FREQUENCY     STM32_BOARD_XTAL
+#define STM32_LSE_FREQUENCY     32768
+
+#define HSI_CLOCK_CONFIG
+
+#if defined(HSI_CLOCK_CONFIG)
+
+#define STM32L4_BOARD_USEHSI
+
+/* Prescaler common to all PLL inputs; will be 1 */
+
+#define STM32L4_PLLCFG_PLLM             RCC_PLLCFG_PLLM(1)
+
+/* 'main' PLL config; we use this to generate our system clock via the R
+ *  output.  We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz
+ *
+ * XXX NOTE:  currently the main PLL is implicitly turned on and is implicitly
+ * the system clock; this should be configurable since not all applications may
+ * want things done this way.
+ */
+
+#define STM32L4_PLLCFG_PLLN             RCC_PLLCFG_PLLN(10)
+#define STM32L4_PLLCFG_PLLP             0
+#undef  STM32L4_PLLCFG_PLLP_ENABLED
+#define STM32L4_PLLCFG_PLLQ             RCC_PLLCFG_PLLQ_2
+#define STM32L4_PLLCFG_PLLQ_ENABLED
+#define STM32L4_PLLCFG_PLLR             RCC_PLLCFG_PLLR_2
+#define STM32L4_PLLCFG_PLLR_ENABLED
+
+/* 'SAIPLL1' is used to generate the 48 MHz clock, since we can't
+ * do that with the main PLL's N value.  We set N = 13, and enable
+ * the Q output (ultimately for CLK48) with /4.  So,
+ * 16 MHz / 1 * 12 / 4 = 48 MHz
+ *
+ * XXX NOTE:  currently the SAIPLL /must/ be explicitly selected in the
+ * menuconfig, or else all this is a moot point, and the various 48 MHz
+ * peripherals will not work (RNG at present).  I would suggest removing
+ * that option from Kconfig altogether, and simply making it an option
+ * that is selected via a #define here, like all these other params.
+ */
+
+#define STM32L4_PLLSAI1CFG_PLLN         RCC_PLLSAI1CFG_PLLN(12)
+#define STM32L4_PLLSAI1CFG_PLLP         0
+#undef  STM32L4_PLLSAI1CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLQ         RCC_PLLSAI1CFG_PLLQ_4
+#define STM32L4_PLLSAI1CFG_PLLQ_ENABLED
+#define STM32L4_PLLSAI1CFG_PLLR         0
+#undef  STM32L4_PLLSAI1CFG_PLLR_ENABLED
+
+/* 'SAIPLL2' is not used in this application */
+
+#define STM32L4_PLLSAI2CFG_PLLN         RCC_PLLSAI2CFG_PLLN(8)
+#define STM32L4_PLLSAI2CFG_PLLP         0
+#undef  STM32L4_PLLSAI2CFG_PLLP_ENABLED
+#define STM32L4_PLLSAI2CFG_PLLR         0
+#undef  STM32L4_PLLSAI2CFG_PLLR_ENABLED
+
+#define STM32L4_SYSCLK_FREQUENCY  80000000ul
+
+/* CLK48 will come from PLLSAI1 (implicitly Q) */
+
+#define STM32L4_USE_CLK48         1
+#define STM32L4_CLK48_SEL         RCC_CCIPR_CLK48SEL_PLLSAI1
+
+/* Enable the LSE oscillator, used automatically trim the MSI, and for RTC */
+
+#define STM32L4_USE_LSE           1
+
+/* AHB clock (HCLK) is SYSCLK (80MHz) */
+
+#define STM32L4_RCC_CFGR_HPRE     RCC_CFGR_HPRE_SYSCLK      /* HCLK  = SYSCLK / 1 */
+#define STM32L4_HCLK_FREQUENCY    STM32L4_SYSCLK_FREQUENCY
+#define STM32L4_BOARD_HCLK        STM32L4_HCLK_FREQUENCY    /* Same as above, to satisfy compiler */
+
+/* APB1 clock (PCLK1) is HCLK/1 (80MHz) */
+
+#define STM32L4_RCC_CFGR_PPRE1    RCC_CFGR_PPRE1_HCLK       /* PCLK1 = HCLK / 1 */
+#define STM32L4_PCLK1_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+/* Timers driven from APB1 will be twice PCLK1 */
+/* REVISIT : this can be configured */
+
+#define STM32L4_APB1_TIM2_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM3_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM4_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM5_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM6_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+#define STM32L4_APB1_TIM7_CLKIN   (2*STM32L4_PCLK1_FREQUENCY)
+
+/* APB2 clock (PCLK2) is HCLK (80MHz) */
+
+#define STM32L4_RCC_CFGR_PPRE2    RCC_CFGR_PPRE2_HCLK       /* PCLK2 = HCLK / 1 */
+#define STM32L4_PCLK2_FREQUENCY   (STM32L4_HCLK_FREQUENCY/1)
+
+/* Timers driven from APB2 will be twice PCLK2 */
+/* REVISIT : this can be configured */
+
+#define STM32L4_APB2_TIM1_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+#define STM32L4_APB2_TIM8_CLKIN   (2*STM32L4_PCLK2_FREQUENCY)
+
+/* Timer Frequencies, if APBx is set to 1, frequency is same to APBx
+ * otherwise frequency is 2xAPBx.
+ * Note: TIM1,8 are on APB2, others on APB1
+ */
+/* REVISIT : this can be configured */
+
+#elif defined(HSE_CLOCK_CONFIG)
+
+#  error "Not implemented"
+
+#endif
+
+/* SDMMC dividers.  Note that slower clocking is required when DMA is disabled
+ * in order to avoid RX overrun/TX underrun errors due to delayed responses
+ * to service FIFOs in interrupt driven mode.  These values have not been
+ * tuned!!!
+ *
+ * SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(118+2)=400 KHz
+ */
+
+#define STM32_SDMMC_INIT_CLKDIV         (118 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+
+/* DMA ON:  SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
+ * DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
+ */
+
+#ifdef CONFIG_SDIO_DMA
+#  define STM32_SDMMC_MMCXFR_CLKDIV     (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#else
+#  define STM32_SDMMC_MMCXFR_CLKDIV     (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#endif
+
+/* DMA ON:  SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(1+2)=16 MHz
+ * DMA OFF: SDMMCCLK=48MHz, SDMMC_CK=SDMMCCLK/(2+2)=12 MHz
+ */
+
+#ifdef CONFIG_SDIO_DMA
+#  define STM32_SDMMC_SDXFR_CLKDIV      (1 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#else
+#  define STM32_SDMMC_SDXFR_CLKDIV      (2 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
+#endif
+
+#if defined(CONFIG_STM32L4_SDMMC2)
+#  define GPIO_SDMMC2_D0 GPIO_SDMMC2_D0_1
+#  define GPIO_SDMMC2_D1 GPIO_SDMMC2_D1_1
+#  define GPIO_SDMMC2_D2 GPIO_SDMMC2_D2_1
+#  define GPIO_SDMMC2_D3 GPIO_SDMMC2_D3_1
+#endif
+
+/* DMA Channel/Stream Selections *****************************************************/
+/* Stream selections are arbitrary for now but might become important in the future
+ * if we set aside more DMA channels/streams.
+ *
+ * SDMMC DMA is on DMA2
+ *
+ * SDMMC1 DMA
+ *   DMAMAP_SDMMC1_1 = Channel 4, Stream 3
+ *   DMAMAP_SDMMC1_2 = Channel 4, Stream 6
+ *
+ * SDMMC2 DMA
+ *   DMAMAP_SDMMC2_1 = Channel 11, Stream 0
+ *   DMAMAP_SDMMC3_2 = Channel 11, Stream 5
+ */
+
+#define DMAMAP_SDMMC1  DMAMAP_SDMMC1_1
+#define DMAMAP_SDMMC2  DMAMAP_SDMMC2_1
+
+
+/* FLASH wait states
+ *
+ *  --------- ---------- -----------
+ *  VDD       MAX SYSCLK WAIT STATES
+ *  --------- ---------- -----------
+ *  1.7-2.1 V   180 MHz    8
+ *  2.1-2.4 V   216 MHz    9
+ *  2.4-2.7 V   216 MHz    8
+ *  2.7-3.6 V   216 MHz    7
+ *  --------- ---------- -----------
+ */
+
+#define BOARD_FLASH_WAITSTATES 7
+
+/* LED definitions ******************************************************************/
+/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue
+ * LED and LD3 a Red LED, that can be controlled by software. The following
+ * definitions assume the default Solder Bridges are installed.
+ *
+ * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way.
+ * The following definitions are used to access individual LEDs.
+ */
+
+/* LED index values for use with board_userled() */
+
+#define BOARD_LED1        0
+#define BOARD_LED2        1
+#define BOARD_LED3        2
+#define BOARD_NLEDS       3
+
+#define BOARD_LED_GREEN   BOARD_LED1
+#define BOARD_LED_BLUE    BOARD_LED2
+#define BOARD_LED_RED     BOARD_LED3
+
+/* LED bits for use with board_userled_all() */
+
+#define BOARD_LED1_BIT    (1 << BOARD_LED1)
+#define BOARD_LED2_BIT    (1 << BOARD_LED2)
+#define BOARD_LED3_BIT    (1 << BOARD_LED3)
+
+/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
+ * include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS-related
+ * events as follows:
+ *
+ *
+ *   SYMBOL                     Meaning                      LED state
+ *                                                        Red   Green Blue
+ *   ----------------------  --------------------------  ------ ------ ----*/
+
+#define LED_STARTED        0 /* NuttX has been started   OFF    OFF   OFF  */
+#define LED_HEAPALLOCATE   1 /* Heap has been allocated  OFF    OFF   ON   */
+#define LED_IRQSENABLED    2 /* Interrupts enabled       OFF    ON    OFF  */
+#define LED_STACKCREATED   3 /* Idle stack created       OFF    ON    ON   */
+#define LED_INIRQ          4 /* In an interrupt          N/C    N/C   GLOW */
+#define LED_SIGNAL         5 /* In a signal handler      N/C    GLOW  N/C  */
+#define LED_ASSERTION      6 /* An assertion failed      GLOW   N/C   GLOW */
+#define LED_PANIC          7 /* The system has crashed   Blink  OFF   N/C  */
+#define LED_IDLE           8 /* MCU is is sleep mode     ON     OFF   OFF  */
+
+/* Thus if the Green LED is statically on, NuttX has successfully booted and
+ * is, apparently, running normally.  If the Red LED is flashing at
+ * approximately 2Hz, then a fatal error has been detected and the system
+ * has halted.
+ */
+
+/* Button definitions ***************************************************************/
+/* The Nucleo-L496ZG supports one button:  Pushbutton B1, labeled "User", is
+ * connected to GPIO PC13.  A high value will be sensed when the button is depressed.
+ */
+
+#define BUTTON_USER        0
+#define NUM_BUTTONS        1
+#define BUTTON_USER_BIT    (1 << BUTTON_USER)
+
+/* Alternate function pin selections ************************************************/
+
+#define GPIO_USART2_TX        GPIO_USART2_TX_2
+#define GPIO_USART2_RX        GPIO_USART2_RX_2
+#define GPIO_USART3_TX        GPIO_USART3_TX_2
+#define GPIO_USART3_RX        GPIO_USART3_RX_2
+
+#if defined(CONFIG_NUCLEO_CONSOLE_ARDUINO)
+/* USART6:
+ *
+ * These configurations assume that you are using a standard Arduio RS-232 shield
+ * with the serial interface with RX on pin D0 and TX on pin D1:
+ *
+ *   -------- ---------------
+ *               STM32F7
+ *   ARDUIONO FUNCTION  GPIO
+ *   -- ----- --------- -----
+ *   DO RX    USART6_RX PG9
+ *   D1 TX    USART6_TX PG14
+ *   -- ----- --------- -----
+ */
+
+ # define GPIO_USART6_RX GPIO_USART6_RX_2
+ # define GPIO_USART6_TX GPIO_USART6_TX_2
+#endif
+
+/* USART3:
+ * Use  USART3 and the USB virtual COM port
+*/
+
+#if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL)
+/* LPUART1 is connector to Virtual COM port PG6 and PG7, but there is no lpserial. */
+//#define GPIO_USART2_TX        GPIO_LPUART1_TX_3
+//#define GPIO_USART2_RX        GPIO_LPUART1_RX_3
+#  error "No Nucleo virtual console before lpserial is unimplemented"
+#endif
+
+/* DMA channels *************************************************************/
+/* ADC */
+
+#define ADC1_DMA_CHAN DMAMAP_ADC1_1
+#define ADC2_DMA_CHAN DMAMAP_ADC2_1
+#define ADC3_DMA_CHAN DMAMAP_ADC3_1
+
+/* SPI
+ *
+ *
+ *  PA6   SPI1_MISO CN12-13
+ *  PA7   SPI1_MOSI CN12-15
+ *  PA5   SPI1_SCK  CN12-11
+ *
+ *  PB14  SPI2_MISO CN12-28
+ *  PB15  SPI2_MOSI CN12-26
+ *  PB13  SPI2_SCK  CN12-30
+ *
+ *  PB4   SPI3_MISO CN12-27
+ *  PB5   SPI3_MOSI CN12-29
+ *  PB3   SPI3_SCK  CN12-31
+ */
+
+#define GPIO_SPI1_MISO   GPIO_SPI1_MISO_1
+#define GPIO_SPI1_MOSI   GPIO_SPI1_MOSI_1
+#define GPIO_SPI1_SCK    GPIO_SPI1_SCK_1
+
+#define GPIO_SPI2_MISO   GPIO_SPI2_MISO_1
+#define GPIO_SPI2_MOSI   GPIO_SPI2_MOSI_1
+#define GPIO_SPI2_SCK    GPIO_SPI2_SCK_3
+
+#define GPIO_SPI3_MISO   GPIO_SPI3_MISO_1
+#define GPIO_SPI3_MOSI   GPIO_SPI3_MOSI_2
+#define GPIO_SPI3_SCK    GPIO_SPI3_SCK_1
+
+/* I2C
+ *
+ *
+ *  PB8   I2C1_SCL CN12-3
+ *  PB9   I2C1_SDA CN12-5
+
+ *  PB10   I2C2_SCL CN11-51
+ *  PB11 I2C2_SDA CN12-18
+ *
+ *  PA8   I2C3_SCL CN12-23
+ *  PC9   I2C3_SDA CN12-1
+ *
+ */
+
+#define GPIO_I2C1_SCL GPIO_I2C1_SCL_2
+#define GPIO_I2C1_SDA GPIO_I2C1_SDA_2
+
+#define GPIO_I2C2_SCL GPIO_I2C2_SCL_1
+#define GPIO_I2C2_SDA GPIO_I2C2_SDA_1
+
+#define GPIO_I2C3_SCL GPIO_I2C3_SCL_1
+#define GPIO_I2C3_SDA GPIO_I2C3_SDA_1
+
+#define GPIO_I2C4_SCL GPIO_I2C4_SCL_1
+#define GPIO_I2C4_SDA GPIO_I2C4_SDA_1
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: stm32l4_boardinitialize
+ *
+ * Description:
+ *   All STM32 architectures must provide the following entry point.  This entry point
+ *   is called early in the initialization -- after all memory has been configured
+ *   and mapped but before any devices have been initialized.
+ *
+ ************************************************************************************/
+
+void stm32l4_boardinitialize(void);
+
+#undef EXTERN
+#if defined(__cplusplus)
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif  /* __CONFIG_NUCLEO_L496ZG_INCLUDE_BOARD_H */

configs/nucleo-l496zg/nsh/Make.defs

@@ -0,0 +1,112 @@
+############################################################################
+# configs/nucleo-144/l496-nsh/Make.defs
+#
+#   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <gnutt@nuttx.org>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name NuttX nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+include ${TOPDIR}/.config
+include ${TOPDIR}/tools/Config.mk
+include ${TOPDIR}/arch/arm/src/armv7-m/Toolchain.defs
+
+LDSCRIPT = l496zg-flash.ld
+
+ifeq ($(WINTOOL),y)
+  # Windows-native toolchains
+  DIRLINK = $(TOPDIR)/tools/copydir.sh
+  DIRUNLINK = $(TOPDIR)/tools/unlink.sh
+  MKDEP = $(TOPDIR)/tools/mknulldeps.sh
+  ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}"
+  ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}"
+  ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)}"
+else
+  # Linux/Cygwin-native toolchain
+  MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT)
+  ARCHINCLUDES = -I. -isystem $(TOPDIR)/include
+  ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx
+  ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/$(LDSCRIPT)
+endif
+
+CC = $(CROSSDEV)gcc
+CXX = $(CROSSDEV)g++
+CPP = $(CROSSDEV)gcc -E
+LD = $(CROSSDEV)ld
+AR = $(ARCROSSDEV)ar rcs
+NM = $(ARCROSSDEV)nm
+OBJCOPY = $(CROSSDEV)objcopy
+OBJDUMP = $(CROSSDEV)objdump
+
+ARCHCCVERSION = ${shell $(CC) -v 2>&1 | sed -n '/^gcc version/p' | sed -e 's/^gcc version \([0-9\.]\)/\1/g' -e 's/[-\ ].*//g' -e '1q'}
+ARCHCCMAJOR = ${shell echo $(ARCHCCVERSION) | cut -d'.' -f1}
+
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  ARCHOPTIMIZATION = -g
+endif
+
+ifneq ($(CONFIG_DEBUG_NOOPT),y)
+  ARCHOPTIMIZATION += $(MAXOPTIMIZATION) -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer
+endif
+
+ARCHCFLAGS = -fno-builtin
+ARCHCXXFLAGS = -fno-builtin -fno-exceptions -fcheck-new -fno-rtti
+ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef
+ARCHWARNINGSXX = -Wall -Wshadow -Wundef
+ARCHDEFINES =
+ARCHPICFLAGS = -fpic -msingle-pic-base -mpic-register=r10
+
+CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CPICFLAGS = $(ARCHPICFLAGS) $(CFLAGS)
+CXXFLAGS = $(ARCHCXXFLAGS) $(ARCHWARNINGSXX) $(ARCHOPTIMIZATION) $(ARCHCPUFLAGS) $(ARCHXXINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe
+CXXPICFLAGS = $(ARCHPICFLAGS) $(CXXFLAGS)
+CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES)
+AFLAGS = $(CFLAGS) -D__ASSEMBLY__
+
+NXFLATLDFLAGS1 = -r -d -warn-common
+NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections
+LDNXFLATFLAGS = -e main -s 2048
+
+ASMEXT = .S
+OBJEXT = .o
+LIBEXT = .a
+EXEEXT =
+
+ifneq ($(CROSSDEV),arm-nuttx-elf-)
+  LDFLAGS += -nostartfiles -nodefaultlibs
+endif
+ifeq ($(CONFIG_DEBUG_SYMBOLS),y)
+  LDFLAGS += -g
+endif
+
+HOSTCC = gcc
+HOSTINCLUDES = -I.
+HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe
+HOSTLDFLAGS =
+

configs/nucleo-l496zg/scripts/kernel-space.ld

@@ -0,0 +1,109 @@
+/****************************************************************************
+ * configs/nucleo-144/scripts/kernel-space.ld
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* NOTE:  This depends on the memory.ld script having been included prior to
+ * this script.
+ */
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+SECTIONS
+{
+    .text : {
+        _stext = ABSOLUTE(.);
+        *(.vectors)
+        *(.text .text.*)
+        *(.fixup)
+        *(.gnu.warning)
+        *(.rodata .rodata.*)
+        *(.gnu.linkonce.t.*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.got)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.r.*)
+        _etext = ABSOLUTE(.);
+    } > kflash
+
+    .init_section : {
+        _sinit = ABSOLUTE(.);
+        *(.init_array .init_array.*)
+        _einit = ABSOLUTE(.);
+    } > kflash
+
+    .ARM.extab : {
+        *(.ARM.extab*)
+    } > kflash
+
+    __exidx_start = ABSOLUTE(.);
+    .ARM.exidx : {
+        *(.ARM.exidx*)
+    } > kflash
+
+    __exidx_end = ABSOLUTE(.);
+
+    _eronly = ABSOLUTE(.);
+
+    .data : {
+        _sdata = ABSOLUTE(.);
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        CONSTRUCTORS
+        _edata = ABSOLUTE(.);
+    } > ksram AT > kflash
+
+    .bss : {
+        _sbss = ABSOLUTE(.);
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        _ebss = ABSOLUTE(.);
+    } > ksram
+
+    /* Stabs debugging sections */
+
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+    .debug_abbrev 0 : { *(.debug_abbrev) }
+    .debug_info 0 : { *(.debug_info) }
+    .debug_line 0 : { *(.debug_line) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    .debug_aranges 0 : { *(.debug_aranges) }
+}

configs/nucleo-l496zg/scripts/l496zg-flash.ld

@@ -0,0 +1,119 @@
+/****************************************************************************
+ * configs/nucleo-l496zg/scripts/l496zg-flash.ld
+ *
+ *   Copyright (C) 2014 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *           Sebastien Lorquet <sebastien@lorquet.fr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32L496ZG has 1024Kb of FLASH beginning at address 0x0800:0000 and
+ * 256Kb of SRAM beginning at address 0x2000:0000.  When booting from FLASH,
+ * FLASH memory is aliased to address 0x0000:0000 where the code expects to
+ * begin execution by jumping to the entry point in the 0x0800:0000 address
+ * range.
+ */
+
+MEMORY
+{
+    flash (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
+    sram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
+}
+
+OUTPUT_ARCH(arm)
+ENTRY(_stext)
+SECTIONS
+{
+	.text : {
+		_stext = ABSOLUTE(.);
+		*(.vectors)
+		*(.text .text.*)
+		*(.fixup)
+		*(.gnu.warning)
+		*(.rodata .rodata.*)
+		*(.gnu.linkonce.t.*)
+		*(.glue_7)
+		*(.glue_7t)
+		*(.got)
+		*(.gcc_except_table)
+		*(.gnu.linkonce.r.*)
+		_etext = ABSOLUTE(.);
+	} > flash
+
+	.init_section : {
+		_sinit = ABSOLUTE(.);
+		*(.init_array .init_array.*)
+		_einit = ABSOLUTE(.);
+	} > flash
+
+	.ARM.extab : {
+		*(.ARM.extab*)
+	} > flash
+
+	__exidx_start = ABSOLUTE(.);
+	.ARM.exidx : {
+		*(.ARM.exidx*)
+	} > flash
+	__exidx_end = ABSOLUTE(.);
+
+	_eronly = ABSOLUTE(.);
+
+	/* The STM32L496ZG has 256Kb of SRAM beginning at the following address */
+
+	.data : {
+		_sdata = ABSOLUTE(.);
+		*(.data .data.*)
+		*(.gnu.linkonce.d.*)
+		CONSTRUCTORS
+		_edata = ABSOLUTE(.);
+	} > sram AT > flash
+
+	.bss : {
+		_sbss = ABSOLUTE(.);
+		*(.bss .bss.*)
+		*(.gnu.linkonce.b.*)
+		*(COMMON)
+		_ebss = ABSOLUTE(.);
+	} > sram
+
+	/* Stabs debugging sections. */
+	.stab 0 : { *(.stab) }
+	.stabstr 0 : { *(.stabstr) }
+	.stab.excl 0 : { *(.stab.excl) }
+	.stab.exclstr 0 : { *(.stab.exclstr) }
+	.stab.index 0 : { *(.stab.index) }
+	.stab.indexstr 0 : { *(.stab.indexstr) }
+	.comment 0 : { *(.comment) }
+	.debug_abbrev 0 : { *(.debug_abbrev) }
+	.debug_info 0 : { *(.debug_info) }
+	.debug_line 0 : { *(.debug_line) }
+	.debug_pubnames 0 : { *(.debug_pubnames) }
+	.debug_aranges 0 : { *(.debug_aranges) }
+}

configs/nucleo-l496zg/scripts/memory.ld

@@ -0,0 +1,129 @@
+/****************************************************************************
+ * configs/nucleo-144/scripts/memory.ld
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* The STM32F746NGH6 has 1024Kb of main FLASH memory.  This FLASH memory can
+ * be accessed from either the AXIM interface at address 0x0800:0000 or from
+ * the ITCM interface at address 0x0020:0000.
+ *
+ * Additional information, including the option bytes, is available at at
+ * FLASH at address 0x1ff0:0000 (AXIM) or 0x0010:0000 (ITCM).
+ *
+ * In the STM32F746NGH6, two different boot spaces can be selected through
+ * the BOOT pin and the boot base address programmed in the BOOT_ADD0 and
+ * BOOT_ADD1 option bytes:
+ *
+ *   1) BOOT=0: Boot address defined by user option byte BOOT_ADD0[15:0].
+ *      ST programmed value: Flash on ITCM at 0x0020:0000
+ *   2) BOOT=1: Boot address defined by user option byte BOOT_ADD1[15:0].
+ *      ST programmed value: System bootloader at 0x0010:0000
+ *
+ * NuttX does not modify these option byes.  On the unmodified STM32F746G
+ * DISCO board, the BOOT0 pin is at ground so by default, the STM32 will boot
+ * to address 0x0020:0000 in ITCM FLASH.
+ *
+ * The STM32F746NGH6 also has 320Kb of data SRAM (in addition to ITCM SRAM).
+ * SRAM is split up into three blocks:
+ *
+ *   1)  64Kb of DTCM SRM beginning at address 0x2000:0000
+ *   2) 240Kb of SRAM1 beginning at address 0x2001:0000
+ *   3)  16Kb of SRAM2 beginning at address 0x2004:c000
+ *
+ * When booting from FLASH, FLASH memory is aliased to address 0x0000:0000
+ * where the code expects to begin execution by jumping to the entry point in
+ * the 0x0800:0000 address range.
+ *
+ * For MPU support, the kernel-mode NuttX section is assumed to be 128Kb of
+ * FLASH and 4Kb of SRAM.  That is an excessive amount for the kernel which
+ * should fit into 64KB and, of course, can be optimized as needed (See
+ * also configs/stm32f746g-disco/scripts/kernel-space.ld).  Allowing the
+ * additional does permit addition debug instrumentation to be added to the
+ * kernel space without overflowing the partition.
+ *
+ * Alignment of the user space FLASH partition is also a critical factor:
+ * The user space FLASH partition will be spanned with a single region of
+ * size 2**n bytes.  The alignment of the user-space region must be the same.
+ * As a consequence, as the user-space increases in size, the alignment
+ * requirement also increases.
+ *
+ * This alignment requirement means that the largest user space FLASH region
+ * you can have will be 512KB at it would have to be positioned at
+ * 0x08800000.  If you change this address, don't forget to change the
+ * CONFIG_NUTTX_USERSPACE configuration setting to match and to modify
+ * the check in kernel/userspace.c.
+ *
+ * For the same reasons, the maximum size of the SRAM mapping is limited to
+ * 4KB.  Both of these alignment limitations could be reduced by using
+ * multiple regions to map the FLASH/SDRAM range or perhaps with some
+ * clever use of subregions.
+ *
+ * A detailed memory map for the 112KB SRAM region is as follows:
+ *
+ *   0x20001 0000:  Kernel .data region.  Typical size: 0.1KB
+ *   ------- ----   Kernel .bss  region.  Typical size: 1.8KB
+ *   0x20001 0800:  Kernel IDLE thread stack (approximate).  Size is
+ *                  determined by CONFIG_IDLETHREAD_STACKSIZE and
+ *                  adjustments for alignment.  Typical is 1KB.
+ *   ------- ----   Padded to 4KB
+ *   0x20001 1000:  User .data region.  Size is variable.
+ *   ------- ----   User .bss region  Size is variable.
+ *   0x20001 2000:  Beginning of kernel heap.  Size determined by
+ *                  CONFIG_MM_KERNEL_HEAPSIZE.
+ *   ------- ----   Beginning of user heap.  Can vary with other settings.
+ *   0x20004 c000:  End+1 of SRAM1
+ */
+
+MEMORY
+{
+	/* ITCM boot address */
+
+	itcm  (rwx) : ORIGIN = 0x00200000, LENGTH = 1024K
+
+	/* 1024KB FLASH */
+
+	kflash (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+	uflash (rx) : ORIGIN = 0x08020000, LENGTH = 128K
+	xflash (rx) : ORIGIN = 0x08040000, LENGTH = 768K
+
+	/* 240KB of contiguous SRAM1 */
+
+	ksram (rwx) : ORIGIN = 0x20010000, LENGTH = 4K
+	usram (rwx) : ORIGIN = 0x20011000, LENGTH = 4K
+	xsram (rwx) : ORIGIN = 0x20012000, LENGTH = 240K - 8K
+
+    /* DTCM SRAM */
+
+	dtcm  (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+	sram2 (rwx) : ORIGIN = 0x2004c000, LENGTH = 16K
+}

configs/nucleo-l496zg/scripts/user-space.ld

@@ -0,0 +1,111 @@
+/****************************************************************************
+ * configs/nucleo-144/scripts/user-space.ld
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* NOTE:  This depends on the memory.ld script having been included prior to
+ * this script.
+ */
+
+OUTPUT_ARCH(arm)
+SECTIONS
+{
+    .userspace : {
+        *(.userspace)
+    } > uflash
+
+    .text : {
+        _stext = ABSOLUTE(.);
+        *(.text .text.*)
+        *(.fixup)
+        *(.gnu.warning)
+        *(.rodata .rodata.*)
+        *(.gnu.linkonce.t.*)
+        *(.glue_7)
+        *(.glue_7t)
+        *(.got)
+        *(.gcc_except_table)
+        *(.gnu.linkonce.r.*)
+        _etext = ABSOLUTE(.);
+    } > uflash
+
+    .init_section : {
+        _sinit = ABSOLUTE(.);
+        *(.init_array .init_array.*)
+        _einit = ABSOLUTE(.);
+    } > uflash
+
+    .ARM.extab : {
+        *(.ARM.extab*)
+    } > uflash
+
+    __exidx_start = ABSOLUTE(.);
+    .ARM.exidx : {
+        *(.ARM.exidx*)
+    } > uflash
+
+    __exidx_end = ABSOLUTE(.);
+
+    _eronly = ABSOLUTE(.);
+
+    .data : {
+        _sdata = ABSOLUTE(.);
+        *(.data .data.*)
+        *(.gnu.linkonce.d.*)
+        CONSTRUCTORS
+        _edata = ABSOLUTE(.);
+    } > usram AT > uflash
+
+    .bss : {
+        _sbss = ABSOLUTE(.);
+        *(.bss .bss.*)
+        *(.gnu.linkonce.b.*)
+        *(COMMON)
+        _ebss = ABSOLUTE(.);
+    } > usram
+
+    /* Stabs debugging sections */
+
+    .stab 0 : { *(.stab) }
+    .stabstr 0 : { *(.stabstr) }
+    .stab.excl 0 : { *(.stab.excl) }
+    .stab.exclstr 0 : { *(.stab.exclstr) }
+    .stab.index 0 : { *(.stab.index) }
+    .stab.indexstr 0 : { *(.stab.indexstr) }
+    .comment 0 : { *(.comment) }
+    .debug_abbrev 0 : { *(.debug_abbrev) }
+    .debug_info 0 : { *(.debug_info) }
+    .debug_line 0 : { *(.debug_line) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    .debug_aranges 0 : { *(.debug_aranges) }
+}

configs/nucleo-l496zg/src/.gitignore

@@ -0,0 +1,2 @@
+/.depend
+/Make.dep