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PIC32MZ: Most related to start up file a FLASH device configuration setup

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This commit is contained in:
Gregory Nutt
2015-02-23 16:36:35 -06:00
parent 9432a01645
commit 87f893887d
8 changed files with 374 additions and 1182 deletions
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arch/mips/src/pic32mz/Kconfig
+67 -399
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File diff suppressed because it is too large Load Diff
arch/mips/src/pic32mz/chip/pic32mzec-features.h
+26 -20
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@@ -203,20 +203,20 @@
# define CFGEBIA_EBIA7EN (1 << 7) /* Bit 7: EBI address pin 7 enable */
# define CFGEBIA_EBIA8EN (1 << 8) /* Bit 8: EBI address pin 8 enable */
# define CFGEBIA_EBIA9EN (1 << 9) /* Bit 9: EBI address pin 9 enable */
# define CFGEBIA_EBIA0EN (1 << 10) /* Bit 10: EBI address pin 10 enable */
# define CFGEBIA_EBIA1EN (1 << 11) /* Bit 11: EBI address pin 11 enable */
# define CFGEBIA_EBIA2EN (1 << 12) /* Bit 12: EBI address pin 12 enable */
# define CFGEBIA_EBIA3EN (1 << 13) /* Bit 13: EBI address pin 13 enable */
# define CFGEBIA_EBIA4EN (1 << 14) /* Bit 14: EBI address pin 14 enable */
# define CFGEBIA_EBIA5EN (1 << 15) /* Bit 15: EBI address pin 15 enable */
# define CFGEBIA_EBIA6EN (1 << 16) /* Bit 16: EBI address pin 16 enable */
# define CFGEBIA_EBIA7EN (1 << 17) /* Bit 17: EBI address pin 17 enable */
# define CFGEBIA_EBIA8EN (1 << 18) /* Bit 18: EBI address pin 18 enable */
# define CFGEBIA_EBIA9EN (1 << 19) /* Bit 19: EBI address pin 19 enable */
# define CFGEBIA_EBIA0EN (1 << 20) /* Bit 20: EBI address pin 20 enable */
# define CFGEBIA_EBIA1EN (1 << 21) /* Bit 21: EBI address pin 21 enable */
# define CFGEBIA_EBIA2EN (1 << 22) /* Bit 22: EBI address pin 22 enable */
# define CFGEBIA_EBIA3EN (1 << 23) /* Bit 23: EBI address pin 23 enable */
# define CFGEBIA_EBIA10EN (1 << 10) /* Bit 10: EBI address pin 10 enable */
# define CFGEBIA_EBIA11EN (1 << 11) /* Bit 11: EBI address pin 11 enable */
# define CFGEBIA_EBIA12EN (1 << 12) /* Bit 12: EBI address pin 12 enable */
# define CFGEBIA_EBIA13EN (1 << 13) /* Bit 13: EBI address pin 13 enable */
# define CFGEBIA_EBIA14EN (1 << 14) /* Bit 14: EBI address pin 14 enable */
# define CFGEBIA_EBIA15EN (1 << 15) /* Bit 15: EBI address pin 15 enable */
# define CFGEBIA_EBIA16EN (1 << 16) /* Bit 16: EBI address pin 16 enable */
# define CFGEBIA_EBIA17EN (1 << 17) /* Bit 17: EBI address pin 17 enable */
# define CFGEBIA_EBIA18EN (1 << 18) /* Bit 18: EBI address pin 18 enable */
# define CFGEBIA_EBIA19EN (1 << 19) /* Bit 19: EBI address pin 19 enable */
# define CFGEBIA_EBIA20EN (1 << 20) /* Bit 20: EBI address pin 20 enable */
# define CFGEBIA_EBIA21EN (1 << 21) /* Bit 21: EBI address pin 21 enable */
# define CFGEBIA_EBIA22EN (1 << 22) /* Bit 22: EBI address pin 22 enable */
# define CFGEBIA_EBIA23EN (1 << 23) /* Bit 23: EBI address pin 23 enable */
#define CFGEBIA_EBIPINEN (1 << 31) /* Bit 31: EBI Pin Enable bit */
/* External bus interface address pin control register */
@@ -308,11 +308,17 @@
#define DEVCFG3_USERID_SHIFT (0) /* Bit 0-15: 16-bit user defined value */
#define DEVCFG3_USERID_MASK (0xffff << DEVCFG3_USERID_SHIFT)
# define DEVCFG3_USERID(n) ((uint32_t)(n) << DEVCFG3_USERID_SHIFT)
#define DEVCFG3_FMIIEN_SHIFT (24) /* Bit 24: Ethernet MII Enable Configuration bit */
#define DEVCFG3_FMIIEN (1 << 24) /* Bit 24: Ethernet MII Enable Configuration bit */
#define DEVCFG3_FETHIO_SHIFT (25) /* Bit 25: Ethernet I/O Pin Selection Configuration bit */
#define DEVCFG3_FETHIO (1 << 25) /* Bit 25: Ethernet I/O Pin Selection Configuration bit */
#define DEVCFG3_PGL1WAY_SHIFT (27) /* Bit 27: Permission Group Lock One Way Configuration bit */
#define DEVCFG3_PGL1WAY (1 << 27) /* Bit 27: Permission Group Lock One Way Configuration bit */
#define DEVCFG3_PMDL1WAY_SHIFT (28) /* Bit 28: Peripheral Module Disable Configuration bit */
#define DEVCFG3_PMDL1WAY (1 << 28) /* Bit 28: Peripheral Module Disable Configuration bit */
#define DEVCFG3_IOL1WAY_SHIFT (29) /* Bit 29: Peripheral Pin Select Configuration bit */
#define DEVCFG3_IOL1WAY (1 << 29) /* Bit 29: Peripheral Pin Select Configuration bit */
#define DEVCFG3_FUSBIDIO_SHIFT (30) /* Bit 30: USB USBID Selection bit */
#define DEVCFG3_FUSBIDIO (1 << 30) /* Bit 30: USB USBID Selection bit */
#define DEVCFG3_RWO 0x84ff0000 /* Bits 16-23, 31: Reserved, write as one */
@@ -357,12 +363,12 @@
#define DEVCFG1_FNOSC_SHIFT (0) /* Bits 0-2: Oscillator Selection bits */
#define DEVCFG1_FNOSC_MASK (7 << DEVCFG1_FNOSC_SHIFT)
# define DEVCFG1_FNOSC_FRCDIV (0 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV */
# define DEVCFG1_FNOSC_FRC (0 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV */
# define DEVCFG1_FNOSC_SPLL (1 << DEVCFG1_FNOSC_SHIFT) /* SPLL */
# define DEVCFG1_FNOSC_POSC (2 << DEVCFG1_FNOSC_SHIFT) /* POSC (HS, EC) */
# define DEVCFG1_FNOSC_SOSC (4 << DEVCFG1_FNOSC_SHIFT) /* SOSC */
# define DEVCFG1_FNOSC_LPRC (5 << DEVCFG1_FNOSC_SHIFT) /* LPRC */
# define DEVCFG1_FNOSC_FRCDIV20 (7 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV<2:0> */
# define DEVCFG1_FNOSC_FRCDIV (7 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV<2:0> */
#define DEVCFG1_DMTINV_SHIFT (3) /* Bits 3-5: Deadman Timer Count Window Interval bits */
#define DEVCFG1_DMTINV_MASK (7 << DEVCFG1_DMTINV_SHIFT)
# define DEVCFG1_DMTINV_0 (0 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value zero */
@@ -410,9 +416,9 @@
# define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */
# define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */
# define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */
#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: Watchdog Timer Stop During Flash Programming bit */
#define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Watchdog Timer Window Enable bit */
#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: Watchdog Timer Enable bit */
#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: Watchdog Timer Stop During Flash Programming bit */
#define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Watchdog Timer Window Enable bit */
#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: Watchdog Timer Enable bit */
#define DEVCFG1_FWDTWINSZ_SHIFT (24) /* Bits 24-25: Watchdog Timer Window Size bits */
#define DEVCFG1_FWDTWINSZ_MASK (3 << DEVCFG1_FWDTWINSZ_SHIFT)
# define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */
@@ -422,7 +428,7 @@
#define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */
#define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT)
# define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */
#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */
#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */
#define DEVCFG1_RWO 0x00003800 /* Bits 11-13: Reserved, write as one */
arch/mips/src/pic32mz/pic32mz-config.h
+167 -636
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File diff suppressed because it is too large Load Diff
arch/mips/src/pic32mz/pic32mz-head.S
+75 -66
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@@ -43,8 +43,7 @@
#include <arch/pic32mz/cp0.h>
#include "pic32mz-config.h"
// REVISIT
//#include "pic32mz-bmx.h"
#include "chip/pic32mz-features.h"
#include "pic32mz-excptmacros.h"
/****************************************************************************
@@ -116,7 +115,7 @@
.globl __reset
.global __start
.global halt
.global devconfig
.global devcfg
#if CONFIG_ARCH_INTERRUPTSTACK > 3
.global g_intstackbase
#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
@@ -157,6 +156,7 @@
.section .reset, "ax", @progbits
.align 2
.set noreorder
.set nomips16
.set micromips
.ent __reset
@@ -643,79 +643,88 @@ halt:
****************************************************************************/
.section .devcfg, "a"
.type devconfig, object
devconfig:
devconfig3:
#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2)
.type devcfg, object
devcfg:
devcfg3:
.long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \
CONFIG_PIC32MZ_FMIIEN << DEVCFG3_FMIIEN_SHIFT | \
CONFIG_PIC32MZ_FETHIO << DEVCFG3_FETHIO_SHIFT | \
CONFIG_PIC32MZ_PGL1WAY << DEVCFG3_PGL1WAY_SHIFT | \
CONFIG_PIC32MZ_PMDL1WAY << DEVCFG3_PMDL1WAY_SHIFT | \
CONFIG_PIC32MZ_IOL1WAY << DEVCFG3_IOL1WAY_SHIFT | \
CONFIG_PIC32MZ_FUSBIDIO << DEVCFG3_FUSBIDIO_SHIFT | \
DEVCFG3_RWO
.long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \
CONFIG_PIC32MZ_PMDL1WAY << 28 | CONFIG_PIC32MZ_IOL1WAY << 29 | \
CONFIG_PIC32MZ_USBIDO << 30 | CONFIG_PIC32MZ_VBUSIO << 31 | \
DEVCFG3_UNUSED
devcfg2:
.long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \
CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \
CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \
DEVCFG2_RWO
#elif defined(CHIP_PIC32MZ3) || defined(CHIP_PIC32MZ4)
devcfg1:
.long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \
CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \
CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \
CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \
CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \
CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \
DEVCFG1_RWO
.long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \
DEVCFG3_UNUSED
devcfg0:
.long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \
CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \
CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \
CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \
CONFIG_PIC32MZ_EJTAGBEN | DEVCFG0_RW0
#elif defined(CHIP_PIC32MZ5) || defined(CHIP_PIC32MZ6) || defined(CHIP_PIC32MZ7)
.size devcfg, .-devcfg
.long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \
CONFIG_PIC32MZ_SRSSEL << DEVCFG3_FSRSSEL_SHIFT | \
CONFIG_PIC32MZ_FMIIEN << 24 | CONFIG_PIC32MZ_FETHIO << 25 | \
CONFIG_PIC32MZ_FCANIO << 26 | CONFIG_PIC32MZ_FSCM1IO << 29 | \
CONFIG_PIC32MZ_USBIDO << 30 | CONFIG_PIC32MZ_VBUSIO << 31 | \
DEVCFG3_UNUSED
/* Every word in the configuration space and sequence space has an
* associated alternate word. During device start-up, primary words are
* read and if uncorrectable ECC errors are found, the BCFGERR flag is set
* and alternate words are used.
*/
#endif
.section .adevcfg, "a"
.type adevcfg, object
adevcfg:
adevcfg3:
.long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \
CONFIG_PIC32MZ_FMIIEN << DEVCFG3_FMIIEN_SHIFT | \
CONFIG_PIC32MZ_FETHIO << DEVCFG3_FETHIO_SHIFT | \
CONFIG_PIC32MZ_PGL1WAY << DEVCFG3_PGL1WAY_SHIFT | \
CONFIG_PIC32MZ_PMDL1WAY << DEVCFG3_PMDL1WAY_SHIFT | \
CONFIG_PIC32MZ_IOL1WAY << DEVCFG3_IOL1WAY_SHIFT | \
CONFIG_PIC32MZ_FUSBIDIO << DEVCFG3_FUSBIDIO_SHIFT | \
DEVCFG3_RWO
devconfig2:
.long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_PLLMULT | \
CONFIG_PIC32MZ_UPLLIDIV | CONFIG_PIC32MZ_PLLODIV | \
CONFIG_PIC32MZ_FUPLLEN << 15 | DEVCFG2_UNUSED
adevcfg2:
.long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \
CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \
CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \
DEVCFG2_RWO
devconfig1:
#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2)
adevcfg1:
.long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \
CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \
CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \
CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \
CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \
CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \
DEVCFG1_RWO
.long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_FSOSCEN | \
CONFIG_PIC32MZ_IESO | CONFIG_PIC32MZ_POSCMOD | \
CONFIG_PIC32MZ_OSCOUT << 10 | \
CONFIG_PIC32MZ_PBDIV | CONFIG_PIC32MZ_FCKSM | \
DEVCFG1_WINDIS | CONFIG_PIC32MZ_WDENABLE | \
DEVCFG1_FWDTWINSZ_75 | DEVCFG1_UNUSED
adevcfg0:
.long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \
CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \
CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \
CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \
CONFIG_PIC32MZ_EJTAGBEN | DEVCFG0_RW0
#else
.long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_FSOSCEN | \
CONFIG_PIC32MZ_IESO | CONFIG_PIC32MZ_POSCMOD | \
CONFIG_PIC32MZ_OSCOUT << 10 | \
CONFIG_PIC32MZ_PBDIV | CONFIG_PIC32MZ_FCKSM | \
CONFIG_PIC32MZ_WDENABLE | DEVCFG1_UNUSED
#endif
devconfig0:
#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2)
.long CONFIG_PIC32MZ_DEBUGGER << DEVCFG0_DEBUG_SHIFT | \
DEVCFG0_JTAGEN | \
CONFIG_PIC32MZ_ICESEL << DEVCFG0_ICESEL_SHIFT | \
CONFIG_PIC32MZ_PROGFLASHWP << DEVCFG0_PWP_SHIFT | \
CONFIG_PIC32MZ_BOOTFLASHWP << 24 | \
CONFIG_PIC32MZ_CODEWP << 28 | \
DEVCFG0_UNUSED
#else
.long CONFIG_PIC32MZ_DEBUGGER << DEVCFG0_DEBUG_SHIFT | \
CONFIG_PIC32MZ_ICESEL << 3 | \
CONFIG_PIC32MZ_PROGFLASHWP << DEVCFG0_PWP_SHIFT | \
CONFIG_PIC32MZ_BOOTFLASHWP << 24 | \
CONFIG_PIC32MZ_CODEWP << 28 | \
DEVCFG0_UNUSED
#endif
.size devconfig, .-devconfig
.size adevcfg, .-adevcfg
/****************************************************************************
* Global Data