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PIC32MZ: Most related to start up file a FLASH device configuration setup

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This commit is contained in:
Gregory Nutt
2015-02-23 16:36:35 -06:00
parent 9432a01645
commit 87f893887d
8 changed files with 374 additions and 1182 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/mips/src/pic32mz/Kconfig
+67 -399
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File diff suppressed because it is too large Load Diff
arch/mips/src/pic32mz/chip/pic32mzec-features.h
+26 -20
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@@ -203,20 +203,20 @@
# define CFGEBIA_EBIA7EN (1 << 7) /* Bit 7: EBI address pin 7 enable */
# define CFGEBIA_EBIA8EN (1 << 8) /* Bit 8: EBI address pin 8 enable */
# define CFGEBIA_EBIA9EN (1 << 9) /* Bit 9: EBI address pin 9 enable */
# define CFGEBIA_EBIA0EN (1 << 10) /* Bit 10: EBI address pin 10 enable */
# define CFGEBIA_EBIA1EN (1 << 11) /* Bit 11: EBI address pin 11 enable */
# define CFGEBIA_EBIA2EN (1 << 12) /* Bit 12: EBI address pin 12 enable */
# define CFGEBIA_EBIA3EN (1 << 13) /* Bit 13: EBI address pin 13 enable */
# define CFGEBIA_EBIA4EN (1 << 14) /* Bit 14: EBI address pin 14 enable */
# define CFGEBIA_EBIA5EN (1 << 15) /* Bit 15: EBI address pin 15 enable */
# define CFGEBIA_EBIA6EN (1 << 16) /* Bit 16: EBI address pin 16 enable */
# define CFGEBIA_EBIA7EN (1 << 17) /* Bit 17: EBI address pin 17 enable */
# define CFGEBIA_EBIA8EN (1 << 18) /* Bit 18: EBI address pin 18 enable */
# define CFGEBIA_EBIA9EN (1 << 19) /* Bit 19: EBI address pin 19 enable */
# define CFGEBIA_EBIA0EN (1 << 20) /* Bit 20: EBI address pin 20 enable */
# define CFGEBIA_EBIA1EN (1 << 21) /* Bit 21: EBI address pin 21 enable */
# define CFGEBIA_EBIA2EN (1 << 22) /* Bit 22: EBI address pin 22 enable */
# define CFGEBIA_EBIA3EN (1 << 23) /* Bit 23: EBI address pin 23 enable */
# define CFGEBIA_EBIA10EN (1 << 10) /* Bit 10: EBI address pin 10 enable */
# define CFGEBIA_EBIA11EN (1 << 11) /* Bit 11: EBI address pin 11 enable */
# define CFGEBIA_EBIA12EN (1 << 12) /* Bit 12: EBI address pin 12 enable */
# define CFGEBIA_EBIA13EN (1 << 13) /* Bit 13: EBI address pin 13 enable */
# define CFGEBIA_EBIA14EN (1 << 14) /* Bit 14: EBI address pin 14 enable */
# define CFGEBIA_EBIA15EN (1 << 15) /* Bit 15: EBI address pin 15 enable */
# define CFGEBIA_EBIA16EN (1 << 16) /* Bit 16: EBI address pin 16 enable */
# define CFGEBIA_EBIA17EN (1 << 17) /* Bit 17: EBI address pin 17 enable */
# define CFGEBIA_EBIA18EN (1 << 18) /* Bit 18: EBI address pin 18 enable */
# define CFGEBIA_EBIA19EN (1 << 19) /* Bit 19: EBI address pin 19 enable */
# define CFGEBIA_EBIA20EN (1 << 20) /* Bit 20: EBI address pin 20 enable */
# define CFGEBIA_EBIA21EN (1 << 21) /* Bit 21: EBI address pin 21 enable */
# define CFGEBIA_EBIA22EN (1 << 22) /* Bit 22: EBI address pin 22 enable */
# define CFGEBIA_EBIA23EN (1 << 23) /* Bit 23: EBI address pin 23 enable */
#define CFGEBIA_EBIPINEN (1 << 31) /* Bit 31: EBI Pin Enable bit */
/* External bus interface address pin control register */
@@ -308,11 +308,17 @@
#define DEVCFG3_USERID_SHIFT (0) /* Bit 0-15: 16-bit user defined value */
#define DEVCFG3_USERID_MASK (0xffff << DEVCFG3_USERID_SHIFT)
# define DEVCFG3_USERID(n) ((uint32_t)(n) << DEVCFG3_USERID_SHIFT)
#define DEVCFG3_FMIIEN_SHIFT (24) /* Bit 24: Ethernet MII Enable Configuration bit */
#define DEVCFG3_FMIIEN (1 << 24) /* Bit 24: Ethernet MII Enable Configuration bit */
#define DEVCFG3_FETHIO_SHIFT (25) /* Bit 25: Ethernet I/O Pin Selection Configuration bit */
#define DEVCFG3_FETHIO (1 << 25) /* Bit 25: Ethernet I/O Pin Selection Configuration bit */
#define DEVCFG3_PGL1WAY_SHIFT (27) /* Bit 27: Permission Group Lock One Way Configuration bit */
#define DEVCFG3_PGL1WAY (1 << 27) /* Bit 27: Permission Group Lock One Way Configuration bit */
#define DEVCFG3_PMDL1WAY_SHIFT (28) /* Bit 28: Peripheral Module Disable Configuration bit */
#define DEVCFG3_PMDL1WAY (1 << 28) /* Bit 28: Peripheral Module Disable Configuration bit */
#define DEVCFG3_IOL1WAY_SHIFT (29) /* Bit 29: Peripheral Pin Select Configuration bit */
#define DEVCFG3_IOL1WAY (1 << 29) /* Bit 29: Peripheral Pin Select Configuration bit */
#define DEVCFG3_FUSBIDIO_SHIFT (30) /* Bit 30: USB USBID Selection bit */
#define DEVCFG3_FUSBIDIO (1 << 30) /* Bit 30: USB USBID Selection bit */
#define DEVCFG3_RWO 0x84ff0000 /* Bits 16-23, 31: Reserved, write as one */
@@ -357,12 +363,12 @@
#define DEVCFG1_FNOSC_SHIFT (0) /* Bits 0-2: Oscillator Selection bits */
#define DEVCFG1_FNOSC_MASK (7 << DEVCFG1_FNOSC_SHIFT)
# define DEVCFG1_FNOSC_FRCDIV (0 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV */
# define DEVCFG1_FNOSC_FRC (0 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV */
# define DEVCFG1_FNOSC_SPLL (1 << DEVCFG1_FNOSC_SHIFT) /* SPLL */
# define DEVCFG1_FNOSC_POSC (2 << DEVCFG1_FNOSC_SHIFT) /* POSC (HS, EC) */
# define DEVCFG1_FNOSC_SOSC (4 << DEVCFG1_FNOSC_SHIFT) /* SOSC */
# define DEVCFG1_FNOSC_LPRC (5 << DEVCFG1_FNOSC_SHIFT) /* LPRC */
# define DEVCFG1_FNOSC_FRCDIV20 (7 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV<2:0> */
# define DEVCFG1_FNOSC_FRCDIV (7 << DEVCFG1_FNOSC_SHIFT) /* FRC divided by FRCDIV<2:0> */
#define DEVCFG1_DMTINV_SHIFT (3) /* Bits 3-5: Deadman Timer Count Window Interval bits */
#define DEVCFG1_DMTINV_MASK (7 << DEVCFG1_DMTINV_SHIFT)
# define DEVCFG1_DMTINV_0 (0 << DEVCFG1_DMTINV_SHIFT) /* Window/Interval value zero */
@@ -410,9 +416,9 @@
# define DEVCFG1_WDTPS_262144 (18 << DEVCFG1_WDTPS_SHIFT) /* 1:262144 */
# define DEVCFG1_WDTPS_524288 (19 << DEVCFG1_WDTPS_SHIFT) /* 1:524288 */
# define DEVCFG1_WDTPS_1048576 (20 << DEVCFG1_WDTPS_SHIFT) /* 1:1048576 */
#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: Watchdog Timer Stop During Flash Programming bit */
#define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Watchdog Timer Window Enable bit */
#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: Watchdog Timer Enable bit */
#define DEVCFG1_WDTSPGM (1 << 21) /* Bit 21: Watchdog Timer Stop During Flash Programming bit */
#define DEVCFG1_WINDIS (1 << 22) /* Bit 22: Watchdog Timer Window Enable bit */
#define DEVCFG1_FWDTEN (1 << 23) /* Bit 23: Watchdog Timer Enable bit */
#define DEVCFG1_FWDTWINSZ_SHIFT (24) /* Bits 24-25: Watchdog Timer Window Size bits */
#define DEVCFG1_FWDTWINSZ_MASK (3 << DEVCFG1_FWDTWINSZ_SHIFT)
# define DEVCFG1_FWDTWINSZ_75 (0 << DEVCFG1_FWDTWINSZ_SHIFT) /* Window size is 75% */
@@ -422,7 +428,7 @@
#define DEVCFG1_DMTCNT_SHIFT (26) /* Bits 26-30: Deadman Timer Count Select bits */
#define DEVCFG1_DMTCNT_MASK (31 << DEVCFG1_DMTCNT_SHIFT)
# define DEVCFG1_DMTCNT(n) ((uint32_t)((n)-8) << DEVCFG1_DMTCNT_SHIFT) /* 2**n, n=8..31 */
#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */
#define DEVCFG1_FDMTEN (1 << 31) /* Bit 31: Deadman Timer enable bit */
#define DEVCFG1_RWO 0x00003800 /* Bits 11-13: Reserved, write as one */
arch/mips/src/pic32mz/pic32mz-config.h
+167 -636
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File diff suppressed because it is too large Load Diff
arch/mips/src/pic32mz/pic32mz-head.S
+75 -66
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@@ -43,8 +43,7 @@
#include <arch/pic32mz/cp0.h>
#include "pic32mz-config.h"
// REVISIT
//#include "pic32mz-bmx.h"
#include "chip/pic32mz-features.h"
#include "pic32mz-excptmacros.h"
/****************************************************************************
@@ -116,7 +115,7 @@
.globl __reset
.global __start
.global halt
.global devconfig
.global devcfg
#if CONFIG_ARCH_INTERRUPTSTACK > 3
.global g_intstackbase
#ifdef CONFIG_PIC32MZ_NESTED_INTERRUPTS
@@ -157,6 +156,7 @@
.section .reset, "ax", @progbits
.align 2
.set noreorder
.set nomips16
.set micromips
.ent __reset
@@ -643,79 +643,88 @@ halt:
****************************************************************************/
.section .devcfg, "a"
.type devconfig, object
devconfig:
devconfig3:
#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2)
.type devcfg, object
devcfg:
devcfg3:
.long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \
CONFIG_PIC32MZ_FMIIEN << DEVCFG3_FMIIEN_SHIFT | \
CONFIG_PIC32MZ_FETHIO << DEVCFG3_FETHIO_SHIFT | \
CONFIG_PIC32MZ_PGL1WAY << DEVCFG3_PGL1WAY_SHIFT | \
CONFIG_PIC32MZ_PMDL1WAY << DEVCFG3_PMDL1WAY_SHIFT | \
CONFIG_PIC32MZ_IOL1WAY << DEVCFG3_IOL1WAY_SHIFT | \
CONFIG_PIC32MZ_FUSBIDIO << DEVCFG3_FUSBIDIO_SHIFT | \
DEVCFG3_RWO
.long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \
CONFIG_PIC32MZ_PMDL1WAY << 28 | CONFIG_PIC32MZ_IOL1WAY << 29 | \
CONFIG_PIC32MZ_USBIDO << 30 | CONFIG_PIC32MZ_VBUSIO << 31 | \
DEVCFG3_UNUSED
devcfg2:
.long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \
CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \
CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \
DEVCFG2_RWO
#elif defined(CHIP_PIC32MZ3) || defined(CHIP_PIC32MZ4)
devcfg1:
.long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \
CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \
CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \
CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \
CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \
CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \
DEVCFG1_RWO
.long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \
DEVCFG3_UNUSED
devcfg0:
.long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \
CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \
CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \
CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \
CONFIG_PIC32MZ_EJTAGBEN | DEVCFG0_RW0
#elif defined(CHIP_PIC32MZ5) || defined(CHIP_PIC32MZ6) || defined(CHIP_PIC32MZ7)
.size devcfg, .-devcfg
.long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \
CONFIG_PIC32MZ_SRSSEL << DEVCFG3_FSRSSEL_SHIFT | \
CONFIG_PIC32MZ_FMIIEN << 24 | CONFIG_PIC32MZ_FETHIO << 25 | \
CONFIG_PIC32MZ_FCANIO << 26 | CONFIG_PIC32MZ_FSCM1IO << 29 | \
CONFIG_PIC32MZ_USBIDO << 30 | CONFIG_PIC32MZ_VBUSIO << 31 | \
DEVCFG3_UNUSED
/* Every word in the configuration space and sequence space has an
* associated alternate word. During device start-up, primary words are
* read and if uncorrectable ECC errors are found, the BCFGERR flag is set
* and alternate words are used.
*/
#endif
.section .adevcfg, "a"
.type adevcfg, object
adevcfg:
adevcfg3:
.long CONFIG_PIC32MZ_USERID << DEVCFG3_USERID_SHIFT | \
CONFIG_PIC32MZ_FMIIEN << DEVCFG3_FMIIEN_SHIFT | \
CONFIG_PIC32MZ_FETHIO << DEVCFG3_FETHIO_SHIFT | \
CONFIG_PIC32MZ_PGL1WAY << DEVCFG3_PGL1WAY_SHIFT | \
CONFIG_PIC32MZ_PMDL1WAY << DEVCFG3_PMDL1WAY_SHIFT | \
CONFIG_PIC32MZ_IOL1WAY << DEVCFG3_IOL1WAY_SHIFT | \
CONFIG_PIC32MZ_FUSBIDIO << DEVCFG3_FUSBIDIO_SHIFT | \
DEVCFG3_RWO
devconfig2:
.long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_PLLMULT | \
CONFIG_PIC32MZ_UPLLIDIV | CONFIG_PIC32MZ_PLLODIV | \
CONFIG_PIC32MZ_FUPLLEN << 15 | DEVCFG2_UNUSED
adevcfg2:
.long CONFIG_PIC32MZ_PLLIDIV | CONFIG_PIC32MZ_FPLLRNG | \
CONFIG_PIC32MZ_FPLLICLK | CONFIG_PIC32MZ_PLLMULT | \
CONFIG_PIC32MZ_PLLODIV | CONFIG_PIC32MZ_UPLLFSEL | \
DEVCFG2_RWO
devconfig1:
#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2)
adevcfg1:
.long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_DMTINV |\
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_IESO | \
CONFIG_PIC32MZ_POSCMOD | CONFIG_PIC32MZ_OSCIOFNC | \
CONFIG_PIC32MZ_FCKSM | CONFIG_PIC32MZ_WDTPS | \
CONFIG_PIC32MZ_WDTSPGM | CONFIG_PIC32MZ_WINDIS | \
CONFIG_PIC32MZ_FWDTEN | CONFIG_PIC32MZ_FWDTWINSZ | \
CONFIG_PIC32MZ_DMTCNT | CONFIG_PIC32MZ_FSOSCEN | \
CONFIG_PIC32MZ_FSOSCEN | CONFIG_PIC32MZ_FDMTEN | \
DEVCFG1_RWO
.long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_FSOSCEN | \
CONFIG_PIC32MZ_IESO | CONFIG_PIC32MZ_POSCMOD | \
CONFIG_PIC32MZ_OSCOUT << 10 | \
CONFIG_PIC32MZ_PBDIV | CONFIG_PIC32MZ_FCKSM | \
DEVCFG1_WINDIS | CONFIG_PIC32MZ_WDENABLE | \
DEVCFG1_FWDTWINSZ_75 | DEVCFG1_UNUSED
adevcfg0:
.long CONFIG_PIC32MZ_DEBUGGER | CONFIG_PIC32MZ_JTAGEN | \
CONFIG_PIC32MZ_ICESEL | CONFIG_PIC32MZ_TRCEN | \
CONFIG_PIC32MZ_BOOTISA | CONFIG_PIC32MZ_FECCCON | \
CONFIG_PIC32MZ_FSLEEP | CONFIG_PIC32MZ_DBGPER | \
CONFIG_PIC32MZ_EJTAGBEN | DEVCFG0_RW0
#else
.long CONFIG_PIC32MZ_FNOSC | CONFIG_PIC32MZ_FSOSCEN | \
CONFIG_PIC32MZ_IESO | CONFIG_PIC32MZ_POSCMOD | \
CONFIG_PIC32MZ_OSCOUT << 10 | \
CONFIG_PIC32MZ_PBDIV | CONFIG_PIC32MZ_FCKSM | \
CONFIG_PIC32MZ_WDENABLE | DEVCFG1_UNUSED
#endif
devconfig0:
#if defined(CHIP_PIC32MZ1) || defined(CHIP_PIC32MZ2)
.long CONFIG_PIC32MZ_DEBUGGER << DEVCFG0_DEBUG_SHIFT | \
DEVCFG0_JTAGEN | \
CONFIG_PIC32MZ_ICESEL << DEVCFG0_ICESEL_SHIFT | \
CONFIG_PIC32MZ_PROGFLASHWP << DEVCFG0_PWP_SHIFT | \
CONFIG_PIC32MZ_BOOTFLASHWP << 24 | \
CONFIG_PIC32MZ_CODEWP << 28 | \
DEVCFG0_UNUSED
#else
.long CONFIG_PIC32MZ_DEBUGGER << DEVCFG0_DEBUG_SHIFT | \
CONFIG_PIC32MZ_ICESEL << 3 | \
CONFIG_PIC32MZ_PROGFLASHWP << DEVCFG0_PWP_SHIFT | \
CONFIG_PIC32MZ_BOOTFLASHWP << 24 | \
CONFIG_PIC32MZ_CODEWP << 28 | \
DEVCFG0_UNUSED
#endif
.size devconfig, .-devconfig
.size adevcfg, .-adevcfg
/****************************************************************************
* Global Data
configs/pic32mz-starterkit/include/board.h
+9 -34
View File
@@ -54,53 +54,28 @@
/* Clocking *****************************************************************/
/* Crystal frequencies */
#define BOARD_POSC_FREQ 8000000 /* Primary OSC XTAL frequency (8MHz) */
#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
#define BOARD_POSC_FREQ 24000000 /* Primary OSC XTAL frequency (24MHz) */
#define BOARD_SOSC_FREQ 32768 /* Secondary OSC XTAL frequency (32.768KHz) */
/* Oscillator modes */
#define BOARD_FNOSC_POSCPLL 1 /* Use primary oscillator w/PLL */
#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */
#define BOARD_FNOSC_POSC 1 /* Use primary oscillator */
#define BOARD_POSC_HSMODE 1 /* High-speed crystal (HS) mode */
/* PLL configuration and resulting CPU clock.
* CPU_CLOCK = ((POSC_FREQ / IDIV) * MULT) / ODIV
*/
#define BOARD_PLL_INPUT BOARD_POSC_FREQ
#define BOARD_PLL_IDIV 2 /* PLL input divider */
#define BOARD_PLL_MULT 20 /* PLL multiplier */
#define BOARD_PLL_ODIV 1 /* PLL output divider */
#define BOARD_PLL_IDIV 3 /* PLL input divider */
#define BOARD_PLL_MULT 50 /* PLL multiplier */
#define BOARD_PLL_ODIV 2 /* PLL output divider */
#define BOARD_CPU_CLOCK 80000000 /* CPU clock (80MHz = 8MHz * 20 / 2) */
/* USB PLL configuration.
* USB_CLOCK = ((POSC_XTAL / IDIV) * 24) / 2
*/
#define BOARD_UPLL_IDIV 2 /* USB PLL divider (revisit) */
#define BOARD_USB_CLOCK 48000000 /* USB clock (8MHz / 2) * 24 / 2) */
/* Peripheral clock is divided down from CPU clock.
* PBCLOCK = CPU_CLOCK / PBDIV
*/
#define BOARD_PBDIV 2 /* Peripheral clock divisor (PBDIV) */
#define BOARD_PBCLOCK 40000000 /* Peripheral clock (PBCLK = 80MHz/2) */
#define BOARD_CPU_CLOCK 200000000 /* CPU clock: 200MHz = (24MHz / 3) * 50 / 2) */
/* Watchdog pre-scaler (re-visit) */
#define BOARD_WD_ENABLE 0 /* Watchdog is disabled */
#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */
/* Ethernet MII clocking.
*
* The clock divider used to create the MII Management Clock (MDC). The MIIM
* module uses the SYSCLK as an input clock. According to the IEEE 802.3
* Specification this should be no faster than 2.5 MHz. However, some PHYs
* support clock rates up to 12.5 MHz.
*/
#define BOARD_EMAC_MIIM_DIV 32 /* Ideal: 80MHz/32 = 2.5MHz */
#define BOARD_WD_PRESCALER 8 /* Watchdog pre-scaler */
/* LED definitions **********************************************************/
/* LED Configuration ********************************************************/
configs/pic32mz-starterkit/nsh/defconfig
+12 -23
View File
@@ -143,41 +143,30 @@ CONFIG_PIC32MZ_UART1=y
# CONFIG_PIC32MZ_ETHERNET is not set
# CONFIG_PIC32MZ_CTMU is not set
#
# PIC32MZ Peripheral Interrupt Priorities
#
CONFIG_PIC32MZ_CTPRIO=16
CONFIG_PIC32MZ_CS0PRIO=16
CONFIG_PIC32MZ_CS1PRIO=16
CONFIG_PIC32MZ_INT0PRIO=16
CONFIG_PIC32MZ_INT1PRIO=16
CONFIG_PIC32MZ_INT2PRIO=16
CONFIG_PIC32MZ_INT3PRIO=16
CONFIG_PIC32MZ_INT4PRIO=16
CONFIG_PIC32MZ_T1PRIO=16
CONFIG_PIC32MZ_UART1PRIO=16
#
# Device Configuration 0 (DEVCFG0)
#
CONFIG_PIC32MZ_DEBUGGER=2
CONFIG_PIC32MZ_ICESEL=1
CONFIG_PIC32MZ_PROGFLASHWP=0xff
CONFIG_PIC32MZ_BOOTFLASHWP=1
CONFIG_PIC32MZ_CODEWP=1
# CONFIG_PIC32MZ_DEBUGGER_ENABLE is not set
CONFIG_PIC32MZ_JTAG_ENABLE=y
# CONFIG_PIC32MZ_ICESEL_CH2 is not set
# CONFIG_PIC32MZ_TRACE_ENABLE is not set
#
# Device Configuration 1 (DEVCFG1)
#
CONFIG_CONFIG_PIC32MZ_OSCIOFNC=0
# CONFIG_PIC32MZ_WDTENABLE is not set
#
# Device Configuration 3 (DEVCFG3)
#
CONFIG_PIC32MZ_USBIDO=0
CONFIG_PIC32MZ_VBUSIO=0
# CONFIG_PIC32MZ_WDENABLE is not set
CONFIG_PIC32MZ_FETHIO=0
CONFIG_PIC32MZ_USERID=0x584e
CONFIG_PIC32MZ_FMIIEN=0
CONFIG_PIC32MZ_PGL1WAY=0
CONFIG_PIC32MZ_PMDL1WAY=0
CONFIG_PIC32MZ_IOL1WAY=0
CONFIG_PIC32MZ_FETHIO=0
CONFIG_PIC32MZ_FUSBIDIO=1
#
# Architecture Options
configs/pic32mz-starterkit/scripts/c32-release.ld
+9 -2
View File
@@ -59,7 +59,8 @@ MEMORY
* JTAG 0x1fc00480 KSEG1 16 1168
* Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb)
* Debug code 0x1fc02000 KSEG1 4096-16 12272
* DEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
* ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
* DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb)
*
* Exceptions assume:
*
@@ -77,7 +78,8 @@ MEMORY
kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168
kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
kseg1_devcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 192
kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128
kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128
/* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb
* of data memory at physical address 0x00000000. Since the PIC32MZ
@@ -159,6 +161,11 @@ SECTIONS
.dbg_code = ORIGIN(kseg1_dbgcode);
.adevcfg :
{
KEEP (*(.adevcfg))
} > kseg1_adevcfg
.devcfg :
{
KEEP (*(.devcfg))
configs/pic32mz-starterkit/scripts/mips-release.ld
+9 -2
View File
@@ -59,7 +59,8 @@ MEMORY
* JTAG 0x1fc00480 KSEG1 16 1168
* Exceptions 0x1fc00490 KSEG0 8192-1168 8192 (4Kb)
* Debug code 0x1fc02000 KSEG1 4096-16 12272
* DEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
* ADEVCFG3-0 0x1fc0ff40 KSEG1 16 12288 (12Kb)
* DEVCFG3-0 0x1fc0ffc0 KSEG1 16 12288 (12Kb)
*
* Exceptions assume:
*
@@ -77,7 +78,8 @@ MEMORY
kseg1_dbgexcpt (rx) : ORIGIN = 0xbfc00480, LENGTH = 16
kseg0_bootmem (rx) : ORIGIN = 0x9fc00490, LENGTH = 8192-1168
kseg1_dbgcode (rx) : ORIGIN = 0xbfc02000, LENGTH = 4096-16
kseg1_devcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 192
kseg1_adevcfg (r) : ORIGIN = 0x1fc0ff40, LENGTH = 128
kseg1_devcfg (r) : ORIGIN = 0x1fc0ffc0, LENGTH = 128
/* The The PIC32MZ2048ECH144 and PIC32MZ2048ECM144 chips have has 512Kb
* of data memory at physical address 0x00000000. Since the PIC32MZ
@@ -159,6 +161,11 @@ SECTIONS
.dbg_code = ORIGIN(kseg1_dbgcode);
.adevcfg :
{
KEEP (*(.adevcfg))
} > kseg1_adevcfg
.devcfg :
{
KEEP (*(.devcfg))