mirror of
https://github.com/apache/nuttx.git
synced 2026-06-07 09:18:00 +08:00
Add framework for lower half STM32 PWM driver; updates to the STM32 ADC driver
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@4192 42af7a65-404d-4744-a932-0658087f49c3
This commit is contained in:
patacongo
@@ -83,6 +83,10 @@ ifeq ($(CONFIG_DAC),y)
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CHIP_CSRCS += stm32_dac.c
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endif
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ifeq ($(CONFIG_PWM),y)
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CHIP_CSRCS += stm32_pwm.c
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endif
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ifeq ($(CONFIG_DEBUG),y)
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CHIP_CSRCS += stm32_dumpgpio.c
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endif
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+339
-39
File diff suppressed because it is too large
Load Diff
@@ -47,6 +47,104 @@
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#include <nuttx/analog/adc.h>
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/************************************************************************************
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* Pre-processor Definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* Timer devices may be used for different purposes. One special purpose is to
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* control periodic ADC sampling. If CONFIG_STM32_TIMn is defined then
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* CONFIG_STM32_TIMn_ADC must also be defined to indicate that timer "n" is intended
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* to be used for that purpose.
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*/
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/* For the STM32 F1 line, timers 1-4 may be used. For STM32 F4 line, timers 1-5 and
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* 8 may be used.
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*/
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#ifndef CONFIG_STM32_TIM1
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# undef CONFIG_STM32_TIM1_ADC
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# undef CONFIG_STM32_TIM1_ADC1
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# undef CONFIG_STM32_TIM1_ADC2
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# undef CONFIG_STM32_TIM1_ADC3
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#endif
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#ifndef CONFIG_STM32_TIM2
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# undef CONFIG_STM32_TIM2_ADC
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# undef CONFIG_STM32_TIM2_ADC1
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# undef CONFIG_STM32_TIM2_ADC2
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# undef CONFIG_STM32_TIM2_ADC3
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#endif
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#ifndef CONFIG_STM32_TIM3
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# undef CONFIG_STM32_TIM3_ADC
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# undef CONFIG_STM32_TIM3_ADC1
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# undef CONFIG_STM32_TIM3_ADC2
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# undef CONFIG_STM32_TIM3_ADC3
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#endif
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#ifndef CONFIG_STM32_TIM4
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# undef CONFIG_STM32_TIM4_ADC
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# undef CONFIG_STM32_TIM4_ADC1
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# undef CONFIG_STM32_TIM4_ADC2
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# undef CONFIG_STM32_TIM4_ADC3
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#endif
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#if defined(CONFIG_STM32_STM32F40XX)
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# ifndef CONFIG_STM32_TIM5
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# undef CONFIG_STM32_TIM5_ADC
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# undef CONFIG_STM32_TIM5_ADC1
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# undef CONFIG_STM32_TIM5_ADC2
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# undef CONFIG_STM32_TIM5_ADC3
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# endif
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# ifndef CONFIG_STM32_TIM8
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# undef CONFIG_STM32_TIM8_ADC
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# undef CONFIG_STM32_TIM8_ADC1
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# undef CONFIG_STM32_TIM8_ADC2
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# undef CONFIG_STM32_TIM8_ADC3
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# endif
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#else
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# undef CONFIG_STM32_TIM5_ADC
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# undef CONFIG_STM32_TIM5_ADC1
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# undef CONFIG_STM32_TIM5_ADC2
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# undef CONFIG_STM32_TIM5_ADC3
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# undef CONFIG_STM32_TIM8_ADC
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# undef CONFIG_STM32_TIM8_ADC1
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# undef CONFIG_STM32_TIM8_ADC2
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# undef CONFIG_STM32_TIM8_ADC3
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#endif
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/* Timers 6, 7, and 10-14 are not used with the ADC by any supported family */
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#undef CONFIG_STM32_TIM6_ADC
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#undef CONFIG_STM32_TIM6_ADC1
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#undef CONFIG_STM32_TIM6_ADC2
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#undef CONFIG_STM32_TIM6_ADC3
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#undef CONFIG_STM32_TIM7_ADC
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#undef CONFIG_STM32_TIM7_ADC1
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#undef CONFIG_STM32_TIM7_ADC2
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#undef CONFIG_STM32_TIM7_ADC3
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#undef CONFIG_STM32_TIM9_ADC
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#undef CONFIG_STM32_TIM9_ADC1
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#undef CONFIG_STM32_TIM9_ADC2
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#undef CONFIG_STM32_TIM9_ADC3
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#undef CONFIG_STM32_TIM10_ADC
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#undef CONFIG_STM32_TIM10_ADC1
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#undef CONFIG_STM32_TIM10_ADC2
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#undef CONFIG_STM32_TIM10_ADC3
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#undef CONFIG_STM32_TIM11_ADC
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#undef CONFIG_STM32_TIM11_ADC1
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#undef CONFIG_STM32_TIM11_ADC2
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#undef CONFIG_STM32_TIM11_ADC3
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#undef CONFIG_STM32_TIM12_ADC
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#undef CONFIG_STM32_TIM12_ADC1
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#undef CONFIG_STM32_TIM12_ADC2
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#undef CONFIG_STM32_TIM12_ADC3
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#undef CONFIG_STM32_TIM13_ADC
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#undef CONFIG_STM32_TIM13_ADC1
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#undef CONFIG_STM32_TIM13_ADC2
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#undef CONFIG_STM32_TIM13_ADC3
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#undef CONFIG_STM32_TIM14_ADC
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#undef CONFIG_STM32_TIM14_ADC1
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#undef CONFIG_STM32_TIM14_ADC2
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#undef CONFIG_STM32_TIM14_ADC3
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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@@ -172,49 +172,49 @@
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#ifdef CONFIG_STM32_DAC1_DMA
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# if CONFIG_STM32_DAC1_TIMER == 6
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# ifndef CONFIG_STM32_TIM6
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# error "CONFIG_STM32_TIM6 required for DAC1"
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# ifndef CONFIG_STM32_TIM6_DAC
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# error "CONFIG_STM32_TIM6_DAC required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM6
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# define DAC1_TIMER_BASE STM32_TIM6_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC1_TIMER == 3 && defined(CONFIG_STM32_CONNECTIVITYLINE)
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# ifndef CONFIG_STM32_TIM3
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# error "CONFIG_STM32_TIM3 required for DAC1"
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# ifndef CONFIG_STM32_TIM3_DAC
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# error "CONFIG_STM32_TIM3_DAC required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM3
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# define DAC1_TIMER_BASE STM32_TIM3_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC1_TIMER == 8 && !defined(CONFIG_STM32_CONNECTIVITYLINE)
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# ifndef CONFIG_STM32_TIM8
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# error "CONFIG_STM32_TIM8 required for DAC1"
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# ifndef CONFIG_STM32_TIM8_DAC
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# error "CONFIG_STM32_TIM8_DAC required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM8
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# define DAC1_TIMER_BASE STM32_TIM8_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
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# elif CONFIG_STM32_DAC1_TIMER == 7
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# ifndef CONFIG_STM32_TIM7
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# error "CONFIG_STM32_TIM7 required for DAC1"
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# ifndef CONFIG_STM32_TIM7_DAC
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# error "CONFIG_STM32_TIM7_DAC required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM7
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# define DAC1_TIMER_BASE STM32_TIM7_BASE
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# elif CONFIG_STM32_DAC1_TIMER == 5
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# ifndef CONFIG_STM32_TIM5
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# error "CONFIG_STM32_TIM5 required for DAC1"
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# ifndef CONFIG_STM32_TIM5_DAC
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# error "CONFIG_STM32_TIM5_DAC required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM5
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# define DAC1_TIMER_BASE STM32_TIM5_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC1_TIMER == 2
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# ifndef CONFIG_STM32_TIM2
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# error "CONFIG_STM32_TIM2 required for DAC1"
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# ifndef CONFIG_STM32_TIM2_DAC
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# error "CONFIG_STM32_TIM2_DAC required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM2
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# define DAC1_TIMER_BASE STM32_TIM2_BASE
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# define DAC1_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC1_TIMER == 4
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# ifndef CONFIG_STM32_TIM4
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# error "CONFIG_STM32_TIM4 required for DAC1"
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# ifndef CONFIG_STM32_TIM4_DAC
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# error "CONFIG_STM32_TIM4_DAC required for DAC1"
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# endif
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# define DAC1_TSEL_VALUE DAC_CR_TSEL_TIM4
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# define DAC1_TIMER_BASE STM32_TIM4_BASE
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@@ -228,50 +228,50 @@
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#ifdef CONFIG_STM32_DAC2_DMA
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# if CONFIG_STM32_DAC2_TIMER == 6
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# ifndef CONFIG_STM32_TIM6
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# error "CONFIG_STM32_TIM6 required for DAC2"
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# ifndef CONFIG_STM32_TIM6_DAC
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# error "CONFIG_STM32_TIM6_DAC required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM6
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# define DAC2_TIMER_BASE STM32_TIM6_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 3 && defined(CONFIG_STM32_CONNECTIVITYLINE)
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# ifndef CONFIG_STM32_TIM3
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# error "CONFIG_STM32_TIM3 required for DAC2"
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# ifndef CONFIG_STM32_TIM3_DAC
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# error "CONFIG_STM32_TIM3_DAC required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM3
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# define DAC2_TIMER_BASE STM32_TIM3_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 8 && !defined(CONFIG_STM32_CONNECTIVITYLINE)
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# ifndef CONFIG_STM32_TIM8
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# error "CONFIG_STM32_TIM8 required for DAC2"
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# ifndef CONFIG_STM32_TIM8_DAC
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# error "CONFIG_STM32_TIM8_DAC required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM8
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# define DAC2_TIMER_BASE STM32_TIM8_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK2_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 7
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# ifndef CONFIG_STM32_TIM7
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# error "CONFIG_STM32_TIM7 required for DAC2"
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# ifndef CONFIG_STM32_TIM7_DAC
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# error "CONFIG_STM32_TIM7_DAC required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM7
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# define DAC2_TIMER_BASE STM32_TIM7_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 5
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# ifndef CONFIG_STM32_TIM5
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# error "CONFIG_STM32_TIM5 required for DAC2"
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# ifndef CONFIG_STM32_TIM5_DAC
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# error "CONFIG_STM32_TIM5_DAC required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM5
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# define DAC2_TIMER_BASE STM32_TIM5_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 2
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# ifndef CONFIG_STM32_TIM2
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# error "CONFIG_STM32_TIM2 required for DAC2"
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# ifndef CONFIG_STM32_TIM2_DAC
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# error "CONFIG_STM32_TIM2_DAC required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM2
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# define DAC2_TIMER_BASE STM32_TIM2_BASE
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# define DAC2_TIMER_PCLK_FREQUENCY STM32_PCLK1_FREQUENCY
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# elif CONFIG_STM32_DAC2_TIMER == 4
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# ifndef CONFIG_STM32_TIM4
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# error "CONFIG_STM32_TIM4 required for DAC2"
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# ifndef CONFIG_STM32_TIM4_DAC
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# error "CONFIG_STM32_TIM4_DAC required for DAC2"
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# endif
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# define DAC2_TSEL_VALUE DAC_CR_TSEL_TIM4
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# define DAC2_TIMER_BASE STM32_TIM4_BASE
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@@ -47,6 +47,59 @@
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#include <nuttx/analog/dac.h>
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/************************************************************************************
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* Pre-processor definitions
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************************************************************************************/
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/* Configuration ********************************************************************/
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/* Timer devices may be used for different purposes. One special purpose is to
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* control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then
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* CONFIG_STM32_TIMn_DAC must also be defined to indicate that timer "n" is intended
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* to be used for that purpose.
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*/
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#ifndef CONFIG_STM32_TIM1
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# undef CONFIG_STM32_TIM1_DAC
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#endif
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#ifndef CONFIG_STM32_TIM2
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# undef CONFIG_STM32_TIM2_DAC
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#endif
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#ifndef CONFIG_STM32_TIM3
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# undef CONFIG_STM32_TIM3_DAC
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#endif
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#ifndef CONFIG_STM32_TIM4
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# undef CONFIG_STM32_TIM4_DAC
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#endif
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#ifndef CONFIG_STM32_TIM5
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# undef CONFIG_STM32_TIM5_DAC
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#endif
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#ifndef CONFIG_STM32_TIM6
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# undef CONFIG_STM32_TIM6_DAC
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#endif
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#ifndef CONFIG_STM32_TIM7
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# undef CONFIG_STM32_TIM7_DAC
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#endif
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#ifndef CONFIG_STM32_TIM8
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# undef CONFIG_STM32_TIM8_DAC
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#endif
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#ifndef CONFIG_STM32_TIM9
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# undef CONFIG_STM32_TIM9_DAC
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#endif
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#ifndef CONFIG_STM32_TIM10
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# undef CONFIG_STM32_TIM10_DAC
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#endif
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#ifndef CONFIG_STM32_TIM11
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# undef CONFIG_STM32_TIM11_DAC
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#endif
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#ifndef CONFIG_STM32_TIM12
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# undef CONFIG_STM32_TIM12_DAC
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#endif
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#ifndef CONFIG_STM32_TIM13
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# undef CONFIG_STM32_TIM13_DAC
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#endif
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#ifndef CONFIG_STM32_TIM14
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# undef CONFIG_STM32_TIM14_DAC
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#endif
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/************************************************************************************
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* Public Function Prototypes
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************************************************************************************/
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@@ -0,0 +1,459 @@
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/****************************************************************************
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* arch/arm/src/stm32/stm32_pwm.c
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*
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* Copyright (C) 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <spudmonkey@racsa.co.cr>
|
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*
|
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* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/pwm.h>
|
||||
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
#include "chip.h"
|
||||
#include "stm32_pwm.h"
|
||||
#include "stm32_internal.h"
|
||||
|
||||
/* This module then only compiles if there is at least one enabled timer
|
||||
* intended for use with the PWM upper half driver.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_PWM) || defined(CONFIG_STM32_TIM2_PWM) || \
|
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defined(CONFIG_STM32_TIM3_PWM) || defined(CONFIG_STM32_TIM4_PWM) || \
|
||||
defined(CONFIG_STM32_TIM5_PWM) || defined(CONFIG_STM32_TIM6_PWM) || \
|
||||
defined(CONFIG_STM32_TIM7_PWM) || defined(CONFIG_STM32_TIM8_PWM) || \
|
||||
defined(CONFIG_STM32_TIM9_PWM) || defined(CONFIG_STM32_TIM10_PWM) || \
|
||||
defined(CONFIG_STM32_TIM11_PWM) || defined(CONFIG_STM32_TIM12_PWM) || \
|
||||
defined(CONFIG_STM32_TIM13_PWM) || defined(CONFIG_STM32_TIM14_PWM)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Types
|
||||
****************************************************************************/
|
||||
/* This structure representst the state of one PWM timer */
|
||||
|
||||
struct stm32_pwmtimer_s
|
||||
{
|
||||
uint32_t base; /* The base address of the timer */
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Static Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_setup(FAR struct pwm_lowerhalf_s *dev);
|
||||
static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev);
|
||||
static int pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info);
|
||||
static int pwm_stop(FAR struct pwm_lowerhalf_s *dev);
|
||||
static int pwm_pulsecount(FAR struct pwm_lowerhalf_s *dev, FAR pwm_count_t *count);
|
||||
static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg);
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
/* This is the list of lower half PWM driver methods used by the upper half driver */
|
||||
|
||||
static const struct pwm_ops_s g_pwmops =
|
||||
{
|
||||
.setup = pwm_setup(FAR struct pwm_lowerhalf_s *dev);
|
||||
.shutdown = pwm_shutdown(FAR struct pwm_lowerhalf_s *dev);
|
||||
.start = pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info);
|
||||
.stop = pwm_stop(FAR struct pwm_lowerhalf_s *dev);
|
||||
.pulsecount = pwm_pulsecount(FAR struct pwm_lowerhalf_s *dev, FAR pwm_count_t *count);
|
||||
.ioctl = pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg);
|
||||
};
|
||||
|
||||
/* The following represent the state of each possible PWM driver */
|
||||
|
||||
#ifdef CONFIG_STM32_TIM1_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm1dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM1_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM2_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm2dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM2_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM3_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm3dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM3_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM4_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm4dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM4_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM5_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm5dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM5_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM6_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm6dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM6_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM7_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm7dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM7_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM8_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm8dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM8_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM9_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm9dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM9_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM10_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm10dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM10_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM11_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm11dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM11_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM12_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm12dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM12_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM13_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm13dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM13_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_STM32_TIM14_PWM
|
||||
static struct stm32_pwmtimer_s g_pwm14dev =
|
||||
{
|
||||
.ops = *g_pwmops;
|
||||
.base = STM32_TIM14_BASE;
|
||||
};
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pwm_setup
|
||||
*
|
||||
* Description:
|
||||
* This method is called when the driver is opened. The lower half driver
|
||||
* should configure and initialize the device so that it is ready for use.
|
||||
* It should not, however, output pulses until the start method is called.
|
||||
*
|
||||
* Input parameters:
|
||||
* dev - A reference to the lower half PWM driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_setup(FAR struct pwm_lowerhalf_s *dev)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pwm_shutdown
|
||||
*
|
||||
* Description:
|
||||
* This method is called when the driver is closed. The lower half driver
|
||||
* stop pulsed output, free any resources, disable the timer hardware, and
|
||||
* put the system into the lowest possible power usage state
|
||||
*
|
||||
* Input parameters:
|
||||
* dev - A reference to the lower half PWM driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_shutdown(FAR struct pwm_lowerhalf_s *dev)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pwm_start
|
||||
*
|
||||
* Description:
|
||||
* (Re-)initialize the timer resources and start the pulsed output
|
||||
*
|
||||
* Input parameters:
|
||||
* dev - A reference to the lower half PWM driver state structure
|
||||
* info - A reference to the characteristics of the pulsed output
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_start(FAR struct pwm_lowerhalf_s *dev, FAR const struct pwm_info_s *info)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pwm_stop
|
||||
*
|
||||
* Description:
|
||||
* Stop the pulsed output and reset the timer resources
|
||||
*
|
||||
* Input parameters:
|
||||
* dev - A reference to the lower half PWM driver state structure
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_stop(FAR struct pwm_lowerhalf_s *dev)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: pwm_pulsecount
|
||||
*
|
||||
* Description:
|
||||
* Get the number of pulses generated
|
||||
*
|
||||
* Input parameters:
|
||||
* dev - A reference to the lower half PWM driver state structure
|
||||
* count - A pointer to the location to return the pulse count
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_pulsecount(FAR struct pwm_lowerhalf_s *dev, FAR pwm_count_t *count)
|
||||
{
|
||||
#warning "Missing logic"
|
||||
return -ENOSYS;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name:
|
||||
*
|
||||
* Description:
|
||||
* Lower-half logic may support platform-specific ioctl commands
|
||||
*
|
||||
* Input parameters:
|
||||
* dev - A reference to the lower half PWM driver state structure
|
||||
* cmd - The ioctl command
|
||||
* arg - The argument accompanying the ioctl command
|
||||
*
|
||||
* Returned Value:
|
||||
* Zero on success; a negated errno value on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
static int pwm_ioctl(FAR struct pwm_lowerhalf_s *dev, int cmd, unsigned long arg)
|
||||
{
|
||||
/* There are no platform-specific ioctl commands */
|
||||
|
||||
return -ENOTTY;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: stm32_pwminitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize one timer for use with the upper_level PWM driver.
|
||||
*
|
||||
* Input Parameters:
|
||||
* timer - A number identifying the timer use. The number of valid timer
|
||||
* IDs varies with the STM32 MCU and MCU family but is somewhere in
|
||||
* the range of {1,..,14}.
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, a pointer to the STM32 lower half PWM driver is returned.
|
||||
* NULL is returned on any failure.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer)
|
||||
{
|
||||
FAR struct stm32_pwmtimer_s *lower;
|
||||
|
||||
switch (timer)
|
||||
{
|
||||
#ifdef CONFIG_STM32_TIM1_PWM
|
||||
case 1:
|
||||
lower = &g_pwm1dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM2_PWM
|
||||
case 2:
|
||||
lower = &g_pwm2dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM3_PWM
|
||||
case 3:
|
||||
lower = &g_pwm3dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM4_PWM
|
||||
case 4:
|
||||
lower = &g_pwm4dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM5_PWM
|
||||
case 5:
|
||||
lower = &g_pwm5dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM6_PWM
|
||||
case 6:
|
||||
lower = &g_pwm6dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM7_PWM
|
||||
case 7:
|
||||
lower = &g_pwm7dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM8_PWM
|
||||
case 8:
|
||||
lower = &g_pwm8dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM9_PWM
|
||||
case 9:
|
||||
lower = &g_pwm9dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM10_PWM
|
||||
case 10:
|
||||
lower = &g_pwm10dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM11_PWM
|
||||
case 11:
|
||||
lower = &g_pwm11dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM12_PWM
|
||||
case 12:
|
||||
lower = &g_pwm12dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM13_PWM
|
||||
case 13:
|
||||
lower = &g_pwm13dev;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_STM32_TIM14_PWM
|
||||
case 14:
|
||||
lower = &g_pwm14dev;
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
return (FAR struct pwm_lowerhalf_s *)lower;
|
||||
}
|
||||
|
||||
#endif /* CONFIG_STM32_TIMn_PWM, n = 1,...,14 */
|
||||
@@ -0,0 +1,154 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/stm32/stm32_pwm.h
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_TIM_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_TIM_H
|
||||
|
||||
/* The STM32 does not have dedicated PWM hardware. Rather, pulsed output control
|
||||
* is a capabilitiy of the STM32 timers. The logic in this file implements the
|
||||
* lower half of the standard, NuttX PWM interface using the STM32 timers. That
|
||||
* interface is described in include/nuttx/pwm.h.
|
||||
*/
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
#include "chip/stm32_tim.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
/* Configuration ********************************************************************/
|
||||
/* Timer devices may be used for different purposes. One special purpose is
|
||||
* to generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
|
||||
* is defined then the CONFIG_STM32_TIMn_PWM must also be defined to indicate that
|
||||
* timer "n" is intended to be used for pulsed output signal generation.
|
||||
*/
|
||||
|
||||
#ifndef CONFIG_STM32_TIM1
|
||||
# undef CONFIG_STM32_TIM1_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM2
|
||||
# undef CONFIG_STM32_TIM2_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM3
|
||||
# undef CONFIG_STM32_TIM3_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM4
|
||||
# undef CONFIG_STM32_TIM4_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM5
|
||||
# undef CONFIG_STM32_TIM5_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM6
|
||||
# undef CONFIG_STM32_TIM6_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM7
|
||||
# undef CONFIG_STM32_TIM7_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM8
|
||||
# undef CONFIG_STM32_TIM8_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM9
|
||||
# undef CONFIG_STM32_TIM9_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM10
|
||||
# undef CONFIG_STM32_TIM10_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM11
|
||||
# undef CONFIG_STM32_TIM11_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM12
|
||||
# undef CONFIG_STM32_TIM12_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM13
|
||||
# undef CONFIG_STM32_TIM13_PWM
|
||||
#endif
|
||||
#ifndef CONFIG_STM32_TIM14
|
||||
# undef CONFIG_STM32_TIM14_PWM
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Public Data
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/************************************************************************************
|
||||
* Name: stm32_pwminitialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize one timer for use with the upper_level PWM driver.
|
||||
*
|
||||
* Input Parameters:
|
||||
* timer - A number identifying the timer use. The number of valid timer
|
||||
* IDs varies with the STM32 MCU and MCU family but is somewhere in
|
||||
* the range of {1,..,14}.
|
||||
*
|
||||
* Returned Value:
|
||||
* On success, a pointer to the STM32 lower half PWM driver is returned.
|
||||
* NULL is returned on any failure.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
EXTERN FAR struct pwm_lowerhalf_s *stm32_pwminitialize(int timer);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM_SRC_STM32_STM32_TIM_H */
|
||||
@@ -4,6 +4,11 @@
|
||||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Author: Uros Platise <uros.platise@isotel.eu>
|
||||
*
|
||||
* With modifications and updates by:
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
@@ -33,10 +38,9 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/** \file
|
||||
* \author Uros Platise
|
||||
* \brief STM32 Basic, General and Advanced Timers
|
||||
*/
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/arch.h>
|
||||
@@ -59,6 +63,74 @@
|
||||
#include "stm32_gpio.h"
|
||||
#include "stm32_tim.h"
|
||||
|
||||
/************************************************************************************
|
||||
* Private Types
|
||||
************************************************************************************/
|
||||
/* Configuration ********************************************************************/
|
||||
/* Timer devices may be used for different purposes. Such special purposes include:
|
||||
*
|
||||
* - To generate modulated outputs for such things as motor control. If CONFIG_STM32_TIMn
|
||||
* is defined then the CONFIG_STM32_TIMn_PWM may also be defined to indicate that
|
||||
* the timer is intended to be used for pulsed output modulation.
|
||||
*
|
||||
* - To control periodic ADC input sampling. If CONFIG_STM32_TIMn is defined then
|
||||
* CONFIG_STM32_TIMn_ADC may also be defined to indicate that timer "n" is intended
|
||||
* to be used for that purpose.
|
||||
*
|
||||
* - To control periodic DAC outputs. If CONFIG_STM32_TIMn is defined then
|
||||
* CONFIG_STM32_TIMn_DAC may also be defined to indicate that timer "n" is intended
|
||||
* to be used for that purpose.
|
||||
*
|
||||
* In any of these cases, the timer will not be used by this timer module.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1_PWM) || defined (CONFIG_STM32_TIM1_ADC) || defined(CONFIG_STM32_TIM1_DAC)
|
||||
# undef CONFIG_STM32_TIM1
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM2_PWM || defined (CONFIG_STM32_TIM2_ADC) || defined(CONFIG_STM32_TIM2_DAC)
|
||||
# undef CONFIG_STM32_TIM2
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM3_PWM || defined (CONFIG_STM32_TIM3_ADC) || defined(CONFIG_STM32_TIM3_DAC)
|
||||
# undef CONFIG_STM32_TIM3
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM4_PWM || defined (CONFIG_STM32_TIM4_ADC) || defined(CONFIG_STM32_TIM4_DAC)
|
||||
# undef CONFIG_STM32_TIM4
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM5_PWM || defined (CONFIG_STM32_TIM5_ADC) || defined(CONFIG_STM32_TIM5_DAC)
|
||||
# undef CONFIG_STM32_TIM5
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM6_PWM || defined (CONFIG_STM32_TIM6_ADC) || defined(CONFIG_STM32_TIM6_DAC)
|
||||
# undef CONFIG_STM32_TIM6
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM7_PWM || defined (CONFIG_STM32_TIM7_ADC) || defined(CONFIG_STM32_TIM7_DAC)
|
||||
# undef CONFIG_STM32_TIM7
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM8_PWM || defined (CONFIG_STM32_TIM8_ADC) || defined(CONFIG_STM32_TIM8_DAC)
|
||||
# undef CONFIG_STM32_TIM8
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM9_PWM || defined (CONFIG_STM32_TIM9_ADC) || defined(CONFIG_STM32_TIM9_DAC)
|
||||
# undef CONFIG_STM32_TIM9
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM10_PWM || defined (CONFIG_STM32_TIM10_ADC) || defined(CONFIG_STM32_TIM10_DAC)
|
||||
# undef CONFIG_STM32_TIM10
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM11_PWM || defined (CONFIG_STM32_TIM11_ADC) || defined(CONFIG_STM32_TIM11_DAC)
|
||||
# undef CONFIG_STM32_TIM11
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM12_PWM || defined (CONFIG_STM32_TIM12_ADC) || defined(CONFIG_STM32_TIM12_DAC)
|
||||
# undef CONFIG_STM32_TIM12
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM13_PWM || defined (CONFIG_STM32_TIM13_ADC) || defined(CONFIG_STM32_TIM13_DAC)
|
||||
# undef CONFIG_STM32_TIM13
|
||||
#endif
|
||||
#if defined(CONFIG_STM32_TIM14_PWM || defined (CONFIG_STM32_TIM14_ADC) || defined(CONFIG_STM32_TIM14_DAC)
|
||||
# undef CONFIG_STM32_TIM14
|
||||
#endif
|
||||
|
||||
/* This module then only compiles if there are enabled timers that are not intended for
|
||||
* some other purpose.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_STM32_TIM1) || defined(CONFIG_STM32_TIM2) || defined(CONFIG_STM32_TIM3) || \
|
||||
defined(CONFIG_STM32_TIM4) || defined(CONFIG_STM32_TIM5) || defined(CONFIG_STM32_TIM6) || \
|
||||
defined(CONFIG_STM32_TIM7) || defined(CONFIG_STM32_TIM8)
|
||||
|
||||
+117
-109
@@ -4,6 +4,11 @@
|
||||
* Copyright (C) 2011 Uros Platise. All rights reserved.
|
||||
* Author: Uros Platise <uros.platise@isotel.eu>
|
||||
*
|
||||
* With modifications and updates by:
|
||||
*
|
||||
* Copyright (C) 2011 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
@@ -33,14 +38,13 @@
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
/** \file
|
||||
* \author Uros Platise
|
||||
* \brief STM32 Timer Device Driver
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_STM32_STM32_TIM_H
|
||||
#define __ARCH_ARM_SRC_STM32_STM32_TIM_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include "chip.h"
|
||||
@@ -49,107 +53,7 @@
|
||||
/************************************************************************************
|
||||
* Pre-processor Definitions
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
/** TIM Device Structure
|
||||
*/
|
||||
struct stm32_tim_dev_s {
|
||||
struct stm32_tim_ops_s *ops;
|
||||
};
|
||||
|
||||
|
||||
/** TIM Modes of Operation
|
||||
*/
|
||||
typedef enum {
|
||||
STM32_TIM_MODE_UNUSED = -1,
|
||||
|
||||
/* One of the following */
|
||||
STM32_TIM_MODE_MASK = 0x0310,
|
||||
STM32_TIM_MODE_DISABLED = 0x0000,
|
||||
STM32_TIM_MODE_UP = 0x0100,
|
||||
STM32_TIM_MODE_DOWN = 0x0110,
|
||||
STM32_TIM_MODE_UPDOWN = 0x0200,
|
||||
STM32_TIM_MODE_PULSE = 0x0300,
|
||||
|
||||
/* One of the following */
|
||||
STM32_TIM_MODE_CK_INT = 0x0000,
|
||||
// STM32_TIM_MODE_CK_INT_TRIG = 0x0400,
|
||||
// STM32_TIM_MODE_CK_EXT = 0x0800,
|
||||
// STM32_TIM_MODE_CK_EXT_TRIG = 0x0C00,
|
||||
|
||||
/* Clock sources, OR'ed with CK_EXT */
|
||||
// STM32_TIM_MODE_CK_CHINVALID = 0x0000,
|
||||
// STM32_TIM_MODE_CK_CH1 = 0x0001,
|
||||
// STM32_TIM_MODE_CK_CH2 = 0x0002,
|
||||
// STM32_TIM_MODE_CK_CH3 = 0x0003,
|
||||
// STM32_TIM_MODE_CK_CH4 = 0x0004
|
||||
|
||||
/* Todo: external trigger block */
|
||||
|
||||
} stm32_tim_mode_t;
|
||||
|
||||
|
||||
/** TIM Channel Modes
|
||||
*/
|
||||
typedef enum {
|
||||
STM32_TIM_CH_DISABLED = 0x00,
|
||||
|
||||
/* Common configuration */
|
||||
STM32_TIM_CH_POLARITY_POS = 0x00,
|
||||
STM32_TIM_CH_POLARITY_NEG = 0x01,
|
||||
|
||||
/* MODES: */
|
||||
STM32_TIM_CH_MODE_MASK = 0x06,
|
||||
|
||||
/* Output Compare Modes */
|
||||
STM32_TIM_CH_OUTPWM = 0x04, /** Enable standard PWM mode, active high when counter < compare */
|
||||
// STM32_TIM_CH_OUTCOMPARE = 0x06,
|
||||
|
||||
// TODO other modes ... as PWM capture, ENCODER and Hall Sensor
|
||||
// STM32_TIM_CH_INCAPTURE = 0x10,
|
||||
// STM32_TIM_CH_INPWM = 0x20
|
||||
// STM32_TIM_CH_DRIVE_OC -- open collector mode
|
||||
|
||||
} stm32_tim_channel_t;
|
||||
|
||||
|
||||
/** TIM Operations
|
||||
*/
|
||||
struct stm32_tim_ops_s {
|
||||
|
||||
/* Basic Timers */
|
||||
|
||||
int (*setmode)(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
|
||||
int (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
|
||||
void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint16_t period);
|
||||
|
||||
/* General and Advanced Timers Adds */
|
||||
|
||||
int (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode);
|
||||
int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint16_t compare);
|
||||
int (*getcapture)(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
|
||||
|
||||
int (*setisr)(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source);
|
||||
void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source);
|
||||
void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source);
|
||||
void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source);
|
||||
};
|
||||
|
||||
|
||||
/* Helpers */
|
||||
/* Helpers **************************************************************************/
|
||||
|
||||
#define STM32_TIM_SETMODE(d,mode) ((d)->ops->setmode(d,mode))
|
||||
#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq))
|
||||
@@ -162,17 +66,121 @@ struct stm32_tim_ops_s {
|
||||
#define STM32_TIM_DISABLEINT(d,s) ((d)->ops->disableint(d,s))
|
||||
#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s))
|
||||
|
||||
/************************************************************************************
|
||||
* Public Types
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C" {
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* TIM Device Structure */
|
||||
|
||||
struct stm32_tim_dev_s
|
||||
{
|
||||
struct stm32_tim_ops_s *ops;
|
||||
};
|
||||
|
||||
/* TIM Modes of Operation */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
STM32_TIM_MODE_UNUSED = -1,
|
||||
|
||||
/* One of the following */
|
||||
|
||||
STM32_TIM_MODE_MASK = 0x0310,
|
||||
STM32_TIM_MODE_DISABLED = 0x0000,
|
||||
STM32_TIM_MODE_UP = 0x0100,
|
||||
STM32_TIM_MODE_DOWN = 0x0110,
|
||||
STM32_TIM_MODE_UPDOWN = 0x0200,
|
||||
STM32_TIM_MODE_PULSE = 0x0300,
|
||||
|
||||
/* One of the following */
|
||||
|
||||
STM32_TIM_MODE_CK_INT = 0x0000,
|
||||
//STM32_TIM_MODE_CK_INT_TRIG = 0x0400,
|
||||
//STM32_TIM_MODE_CK_EXT = 0x0800,
|
||||
//STM32_TIM_MODE_CK_EXT_TRIG = 0x0C00,
|
||||
|
||||
/* Clock sources, OR'ed with CK_EXT */
|
||||
|
||||
//STM32_TIM_MODE_CK_CHINVALID = 0x0000,
|
||||
//STM32_TIM_MODE_CK_CH1 = 0x0001,
|
||||
//STM32_TIM_MODE_CK_CH2 = 0x0002,
|
||||
//STM32_TIM_MODE_CK_CH3 = 0x0003,
|
||||
//STM32_TIM_MODE_CK_CH4 = 0x0004
|
||||
|
||||
/* Todo: external trigger block */
|
||||
|
||||
} stm32_tim_mode_t;
|
||||
|
||||
/* TIM Channel Modes */
|
||||
|
||||
typedef enum
|
||||
{
|
||||
STM32_TIM_CH_DISABLED = 0x00,
|
||||
|
||||
/* Common configuration */
|
||||
|
||||
STM32_TIM_CH_POLARITY_POS = 0x00,
|
||||
STM32_TIM_CH_POLARITY_NEG = 0x01,
|
||||
|
||||
/* MODES: */
|
||||
|
||||
STM32_TIM_CH_MODE_MASK = 0x06,
|
||||
|
||||
/* Output Compare Modes */
|
||||
|
||||
STM32_TIM_CH_OUTPWM = 0x04, /** Enable standard PWM mode, active high when counter < compare */
|
||||
//STM32_TIM_CH_OUTCOMPARE = 0x06,
|
||||
|
||||
// TODO other modes ... as PWM capture, ENCODER and Hall Sensor
|
||||
//STM32_TIM_CH_INCAPTURE = 0x10,
|
||||
//STM32_TIM_CH_INPWM = 0x20
|
||||
//STM32_TIM_CH_DRIVE_OC -- open collector mode
|
||||
|
||||
} stm32_tim_channel_t;
|
||||
|
||||
/* TIM Operations */
|
||||
|
||||
struct stm32_tim_ops_s
|
||||
{
|
||||
/* Basic Timers */
|
||||
|
||||
int (*setmode)(FAR struct stm32_tim_dev_s *dev, stm32_tim_mode_t mode);
|
||||
int (*setclock)(FAR struct stm32_tim_dev_s *dev, uint32_t freq);
|
||||
void (*setperiod)(FAR struct stm32_tim_dev_s *dev, uint16_t period);
|
||||
|
||||
/* General and Advanced Timers Adds */
|
||||
|
||||
int (*setchannel)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, stm32_tim_channel_t mode);
|
||||
int (*setcompare)(FAR struct stm32_tim_dev_s *dev, uint8_t channel, uint16_t compare);
|
||||
int (*getcapture)(FAR struct stm32_tim_dev_s *dev, uint8_t channel);
|
||||
|
||||
int (*setisr)(FAR struct stm32_tim_dev_s *dev, int (*handler)(int irq, void *context), int source);
|
||||
void (*enableint)(FAR struct stm32_tim_dev_s *dev, int source);
|
||||
void (*disableint)(FAR struct stm32_tim_dev_s *dev, int source);
|
||||
void (*ackint)(FAR struct stm32_tim_dev_s *dev, int source);
|
||||
};
|
||||
|
||||
/************************************************************************************
|
||||
* Public Functions
|
||||
************************************************************************************/
|
||||
|
||||
/** Power-up timer and get its structure */
|
||||
/* Power-up timer and get its structure */
|
||||
|
||||
EXTERN FAR struct stm32_tim_dev_s * stm32_tim_init(int timer);
|
||||
|
||||
/** Power-down timer, mark it as unused */
|
||||
EXTERN int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev);
|
||||
/* Power-down timer, mark it as unused */
|
||||
|
||||
EXTERN int stm32_tim_deinit(FAR struct stm32_tim_dev_s * dev);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
|
||||
Reference in New Issue
Block a user