mirror of
https://github.com/apache/nuttx.git
synced 2026-09-23 07:14:28 +08:00
arm64/am62x: add core boot and serial support
Add the AM62x architecture support needed to boot NuttX on TI K3 AM62x platforms. This includes the chip integration, memory map, IRQ definitions, low-level console support, boot code, and the AM62x 16550 serial lower half. Signed-off-by: Piyush Patle <piyushpatle228@gmail.com>
This commit is contained in:
Piyush Patle
Xiang Xiao
@@ -26,6 +26,23 @@ choice
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prompt "ARM64 chip selection"
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default ARCH_CHIP_QEMU
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config ARCH_CHIP_AM62X
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bool "TI AM62x"
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select ARCH_CORTEX_A53
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select ARCH_HAVE_ADDRENV
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select ARCH_HAVE_RESET
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select ARCH_HAVE_IRQTRIGGER
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select ARCH_NEED_ADDRENV_MAPPING
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select ARCH_USE_MMU
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select ARMV8A_HAVE_GICv3
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select ARM64_HAVE_PSCI
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select ARCH_HAVE_IRQPRIO
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select ARCH_HAVE_LOWPUTC
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---help---
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Texas Instruments AM62x family (AM6232, AM6252, AM6254).
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Quad Cortex-A53 @ up to 1.4 GHz. Supported boards:
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PocketBeagle 2, BeaglePlay.
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config ARCH_CHIP_A64
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bool "Allwinner A64"
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select ARCH_CORTEX_A53
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@@ -362,6 +379,7 @@ config ARCH_FAMILY
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config ARCH_CHIP
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string
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default "am62x" if ARCH_CHIP_AM62X
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default "a64" if ARCH_CHIP_A64
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default "a527" if ARCH_CHIP_SUNXI_A527
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default "rk3399" if ARCH_CHIP_RK3399
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@@ -502,6 +520,10 @@ config ARM64_PA_BITS
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The choice could be: 32, 36, 42, 48
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if ARCH_CHIP_AM62X
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source "arch/arm64/src/am62x/Kconfig"
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endif
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if ARCH_CHIP_A64
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source "arch/arm64/src/a64/Kconfig"
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endif
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@@ -0,0 +1,107 @@
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/****************************************************************************
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* arch/arm64/include/am62x/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* Reference: AM62x TRM (SPRSP43) §2.1 Memory Map §9.2 GIC-600 */
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#ifndef __ARCH_ARM64_INCLUDE_AM62X_CHIP_H
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#define __ARCH_ARM64_INCLUDE_AM62X_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Size macros used in assembly and C */
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#define KB(x) ((x) << 10)
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#define MB(x) (KB(x) << 10)
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#define GB(x) (MB(UINT64_C(x)) << 10)
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/* GIC-600 addresses (TRM §9.2) ********************************************/
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/* Distributor — one per system */
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#define CONFIG_GICD_BASE 0x01800000
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/* Redistributor — one 128 KB frame per Cortex-A53 core */
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#define CONFIG_GICR_BASE 0x01880000
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/* Stride between consecutive per-core redistributor frames (128 KB) */
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#define CONFIG_GICR_OFFSET 0x20000
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/* Extract cluster ID from MPIDR_EL1.
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* AM62x has a single cluster (Aff1=0); mask off Aff0 (bits[7:0]).
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*/
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#define MPID_TO_CLUSTER_ID(mpid) ((mpid) & ~0xffUL)
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/* NuttX load address — must match U-Boot kernel_addr_r and the linker
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* script origin. 0x8200_0000 avoids U-Boot's reserved region at the
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* bottom of DDR (0x8000_0000–0x81FF_FFFF).
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*/
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#define CONFIG_LOAD_BASE 0x82000000
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/* Memory map constants — used by am62x_boot.c MMU region table and by
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* the common arm64 linker/boot code. These are NOT Kconfig symbols;
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* they are chip-level C macros, following the same pattern as a64/chip.h.
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* Board-specific DDR sizes are overridden in defconfig via CONFIG_RAM_SIZE
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* (decimal bytes) — these macros describe the default mapped window.
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*/
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/* DDR: 512 MB at 0x8000_0000 (common minimum for both boards) */
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#define CONFIG_RAMBANK1_ADDR 0x80000000
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#define CONFIG_RAMBANK1_SIZE MB(512)
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/* Device I/O flat-map: all peripherals in the lower 2 GB */
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#define CONFIG_DEVICEIO_BASEADDR 0x00000000
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#define CONFIG_DEVICEIO_SIZE GB(2)
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/****************************************************************************
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* Assembly Macros
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****************************************************************************/
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#ifdef __ASSEMBLY__
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/* get_cpu_id xreg0
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*
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* Read current CPU ID from MPIDR_EL1 Aff0 field [7:0].
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* On AM62x the four A53 cores are numbered 0-3 in Aff0.
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*/
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.macro get_cpu_id xreg0
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mrs \xreg0, mpidr_el1
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ubfx \xreg0, \xreg0, #0, #8
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.endm
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_ARM64_INCLUDE_AM62X_CHIP_H */
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@@ -0,0 +1,105 @@
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/****************************************************************************
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* arch/arm64/include/am62x/irq.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather,
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* only indirectly through nuttx/irq.h
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*/
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/* Reference: AM62x TRM (SPRSP43), Chapter 9 — Interrupt Architecture
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*
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* The AM62x GIC-600 supports:
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* - 16 SGIs (Software Generated Interrupts) IRQ 0 – 15
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* - 16 PPIs (Private Peripheral Interrupts) IRQ 16 – 31
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* - 480 SPIs (Shared Peripheral Interrupts) IRQ 32 – 511
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*
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* Total: 512 interrupt lines.
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*
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* All INTIDs listed here are INTID = GIC_SPI_number + 32.
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* E.g. UART0 GIC_SPI 178 -> INTID 210.
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*/
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#ifndef __ARCH_ARM64_INCLUDE_AM62X_IRQ_H
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#define __ARCH_ARM64_INCLUDE_AM62X_IRQ_H
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Total number of interrupt IDs allocated in the GIC INTID space.
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* NuttX arrays are sized to NR_IRQS entries, so set this to the maximum
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* INTID we actually use + 1. 512 covers all AM62x SPIs.
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*/
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#define NR_IRQS 512
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/* SGI interrupts (per-core, software-generated) */
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#define AM62X_IRQ_SGI0 0
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#define AM62X_IRQ_SGI1 1
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#define AM62X_IRQ_SGI2 2
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#define AM62X_IRQ_SGI3 3
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#define AM62X_IRQ_SGI4 4
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#define AM62X_IRQ_SGI5 5
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#define AM62X_IRQ_SGI6 6
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#define AM62X_IRQ_SGI7 7
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#define AM62X_IRQ_SGI8 8
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#define AM62X_IRQ_SGI9 9
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#define AM62X_IRQ_SGI10 10
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#define AM62X_IRQ_SGI11 11
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#define AM62X_IRQ_SGI12 12
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#define AM62X_IRQ_SGI13 13
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#define AM62X_IRQ_SGI14 14
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#define AM62X_IRQ_SGI15 15
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/* PPI interrupts (per-core, private peripherals)
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*
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* Generic timer PPIs follow the architected GIC assignments:
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* - Hypervisor timer PPI 10 -> INTID 26
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* - Virtual timer PPI 11 -> INTID 27
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* - Secure physical timer PPI 13 -> INTID 29
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* - Non-secure physical timer PPI 14 -> INTID 30
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*/
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#define AM62X_IRQ_PPI_HYPTIMER 26 /* Hypervisor timer */
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#define AM62X_IRQ_PPI_VTIMER 27 /* Virtual timer (EL1) */
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#define AM62X_IRQ_PPI_PTIMER 30 /* Physical timer NS EL1/EL0 */
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#define AM62X_IRQ_PPI_PTIMER_S 29 /* Physical timer secure EL3 */
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#define AM62X_IRQ_PPI_PTIMER_NS 30 /* Physical timer NS EL1/EL0 */
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/* Main domain SPI interrupts (INTID = SPI_offset + 32).
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* Source: AM62x TRM Table 9-17 (Interrupt Map).
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*/
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/* UART (main domain, 16550-compatible)
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* Source: Linux arch/arm64/boot/dts/ti/k3-am62.dtsi
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* UART0 GIC_SPI 178 -> INTID 210, UART6 GIC_SPI 184 -> INTID 216
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*/
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#define AM62X_IRQ_UART0 210 /* GIC_SPI 178: UART0 main domain */
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#define AM62X_IRQ_UART1 211 /* GIC_SPI 179 */
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#define AM62X_IRQ_UART2 212 /* GIC_SPI 180 */
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#define AM62X_IRQ_UART3 213 /* GIC_SPI 181 */
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#define AM62X_IRQ_UART4 214 /* GIC_SPI 182 */
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#define AM62X_IRQ_UART5 215 /* GIC_SPI 183 */
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#define AM62X_IRQ_UART6 216 /* GIC_SPI 184 */
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#endif /* __ARCH_ARM64_INCLUDE_AM62X_IRQ_H */
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@@ -0,0 +1,34 @@
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# ##############################################################################
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# arch/arm64/src/am62x/CMakeLists.txt
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more contributor
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# license agreements. See the NOTICE file distributed with this work for
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# additional information regarding copyright ownership. The ASF licenses this
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# file to you under the Apache License, Version 2.0 (the "License"); you may not
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# use this file except in compliance with the License. You may obtain a copy of
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# the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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# License for the specific language governing permissions and limitations under
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# the License.
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#
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# ##############################################################################
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# AM62x SoC sources that are always compiled
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list(APPEND SRCS am62x_boot.c am62x_16550serial.c)
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# Early UART assembly (needed for CONFIG_ARCH_EARLY_PRINT / semihosting console
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# before the full serial driver is up)
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if(CONFIG_ARCH_EARLY_PRINT)
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list(APPEND SRCS am62x_lowputc.S)
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endif()
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target_sources(arch PRIVATE ${SRCS})
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@@ -0,0 +1,12 @@
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#
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# arch/arm64/src/am62x/Kconfig
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#
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# For a description of the syntax of this configuration file,
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# see the file kconfig-language.txt in the NuttX tools repository.
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#
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if ARCH_CHIP_AM62X
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comment "AM62x peripheral selection is provided by board defconfig for now."
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endif # ARCH_CHIP_AM62X
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@@ -0,0 +1,39 @@
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############################################################################
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# arch/arm64/src/am62x/Make.defs
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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# Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
# contributor license agreements. See the NOTICE file distributed with
|
||||
# this work for additional information regarding copyright ownership. The
|
||||
# ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
# "License"); you may not use this file except in compliance with the
|
||||
# License. You may obtain a copy of the License at
|
||||
#
|
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# http://www.apache.org/licenses/LICENSE-2.0
|
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#
|
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# Unless required by applicable law or agreed to in writing, software
|
||||
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
# License for the specific language governing permissions and limitations
|
||||
# under the License.
|
||||
#
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############################################################################
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# Pull in arch/arm64/src/common/Make.defs which contributes the shared
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# AArch64 C and assembly sources (head.S, mmu, gic, arch_timer, etc.)
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include common/Make.defs
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# AM62x SoC-specific C sources (always compiled)
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CHIP_CSRCS = am62x_boot.c
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CHIP_CSRCS += am62x_16550serial.c
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# Early UART assembly (only when CONFIG_ARCH_EARLY_PRINT is set, which
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# is selected automatically when CONFIG_ARCH_HAVE_LOWPUTC is enabled
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# and the common arch layer needs early console output).
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ifeq ($(CONFIG_ARCH_EARLY_PRINT),y)
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CHIP_ASRCS = am62x_lowputc.S
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endif
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@@ -0,0 +1,148 @@
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/****************************************************************************
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* arch/arm64/src/am62x/am62x_16550serial.c
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*
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* SPDX-License-Identifier: Apache-2.0
|
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*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
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|
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/****************************************************************************
|
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* Included Files
|
||||
****************************************************************************/
|
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#include <nuttx/config.h>
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#ifdef CONFIG_16550_UART
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include <nuttx/serial/uart_16550.h>
|
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|
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#include "arm64_arch.h"
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#include "arm64_internal.h"
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/* TI AM62x-specific register byte offsets and bits not in uart_16550.h */
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#define AM62X_UART_IER_OFF 0x04 /* IER byte offset */
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#define AM62X_UART_FCR_OFF 0x08 /* FCR byte offset */
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#define AM62X_UART_LSR_OFF 0x14 /* LSR byte offset */
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#define AM62X_UART_EFR2_OFF 0x8c /* EFR2 byte offset (K3 extension) */
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/* K3 Errata i2310: resets RX timeout counter on each FIFO read */
|
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#define AM62X_EFR2_TIMEOUT_BEHAVE (1 << 6)
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/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/* Wait for the TX FIFO to drain completely before touching FCR.
|
||||
* Called before am62x_uart_hw_init to ensure TXRST doesn't discard
|
||||
* characters that are still in the FIFO (e.g. debug prints from boot).
|
||||
*/
|
||||
|
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static void am62x_uart_drain_tx(uintptr_t base)
|
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{
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int tries = 1000000;
|
||||
|
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while (tries-- > 0 &&
|
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!(getreg32(base + AM62X_UART_LSR_OFF) & UART_LSR_TEMT))
|
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{
|
||||
}
|
||||
}
|
||||
|
||||
/* TI AM62x-specific UART hardware initialisation.
|
||||
*
|
||||
* 1. TX drain: wait for TX shift register empty (TEMT) so TXRST does not
|
||||
* discard characters still in flight.
|
||||
* 2. FCR 3-step: TI K3 UARTs require FIFOEN asserted first, then
|
||||
* RXRST|TXRST, then the desired trigger level. The generic 16550
|
||||
* sequence (RXRST|TXRST without FIFOEN) disables the FIFO on TI
|
||||
* hardware.
|
||||
* 3. RX trigger = 0 (1-char): RDA fires on every received byte, keeping
|
||||
* the FIFO empty and preventing the spurious CTI path (K3 i2310).
|
||||
* 4. EFR2 TIMEOUT_BEHAVE (bit 6, offset 0x8c): resets the RX timeout
|
||||
* counter each time data is read from the FIFO, so a post-drain CTI
|
||||
* never fires with an empty FIFO.
|
||||
*
|
||||
* MDR1 is intentionally not touched -- U-Boot has already placed the UART
|
||||
* in 16x mode and writing MDR1 causes THRE to read 0 for several µs.
|
||||
*/
|
||||
|
||||
static void am62x_uart_hw_init(uintptr_t base)
|
||||
{
|
||||
am62x_uart_drain_tx(base);
|
||||
|
||||
putreg32(UART_FCR_FIFOEN,
|
||||
base + AM62X_UART_FCR_OFF);
|
||||
|
||||
putreg32(UART_FCR_FIFOEN | UART_FCR_RXRST | UART_FCR_TXRST,
|
||||
base + AM62X_UART_FCR_OFF);
|
||||
|
||||
putreg32(UART_FCR_FIFOEN | UART_FCR_RXTRIGGER_1,
|
||||
base + AM62X_UART_FCR_OFF);
|
||||
|
||||
/* Keep the UART quiet until the full 16550 driver attaches later in
|
||||
* up_initialize(). U-Boot can leave UART6 interrupt sources armed on
|
||||
* PocketBeagle2, which causes an immediate trap as soon as NuttX enables
|
||||
* global interrupts in irq_initialize().
|
||||
*/
|
||||
|
||||
putreg32(0, base + AM62X_UART_IER_OFF);
|
||||
putreg32(AM62X_EFR2_TIMEOUT_BEHAVE, base + AM62X_UART_EFR2_OFF);
|
||||
}
|
||||
|
||||
static void am62x_uartirq_setup(void)
|
||||
{
|
||||
#ifdef CONFIG_16550_UART0
|
||||
# ifdef CONFIG_ARCH_IRQPRIO
|
||||
(void)up_prioritize_irq(CONFIG_16550_UART0_IRQ, 0);
|
||||
# endif
|
||||
|
||||
# ifdef CONFIG_ARCH_HAVE_IRQTRIGGER
|
||||
/* TI's AM62 main-domain UARTs are level-high SPIs in the upstream
|
||||
* device tree. PocketBeagle2 uses UART6 (GIC_SPI 184 -> INTID 216).
|
||||
*/
|
||||
|
||||
(void)up_set_irq_type(CONFIG_16550_UART0_IRQ, IRQ_HIGH_LEVEL);
|
||||
# endif
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
void arm64_earlyserialinit(void)
|
||||
{
|
||||
/* U-Boot already leaves the AM62x console UART configured at 115200 8N1.
|
||||
* Keep that early console state intact until /dev/console is opened, but
|
||||
* apply the TI-specific FIFO sequence and timeout behavior immediately so
|
||||
* interactive input is safe as soon as the full 16550 driver takes over.
|
||||
*/
|
||||
|
||||
am62x_uart_hw_init(CONFIG_16550_UART0_BASE);
|
||||
u16550_earlyserialinit();
|
||||
}
|
||||
|
||||
void arm64_serialinit(void)
|
||||
{
|
||||
am62x_uartirq_setup();
|
||||
u16550_serialinit();
|
||||
}
|
||||
|
||||
#endif /* CONFIG_16550_UART */
|
||||
@@ -0,0 +1,161 @@
|
||||
/****************************************************************************
|
||||
* arch/arm64/src/am62x/am62x_boot.c
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <assert.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include <nuttx/cache.h>
|
||||
|
||||
#include <arch/chip/chip.h>
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
# include "arm64_smp.h"
|
||||
#endif
|
||||
|
||||
#include "arm64_arch.h"
|
||||
#include "arm64_internal.h"
|
||||
#include "arm64_mmu.h"
|
||||
#include "am62x_boot.h"
|
||||
#include "am62x_serial.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/* MMU region table.
|
||||
*
|
||||
* Two flat-mapped regions are required:
|
||||
*
|
||||
* 1. DEVICE_REGION — peripheral space 0x0000_0000 – 0x7FFF_FFFF.
|
||||
* Mapped as device-nGnRnE, read-write, secure. This covers UART, GIC,
|
||||
* GPIO, I2C, SPI, USB, MMC, etc. in one shot without needing to list
|
||||
* each peripheral separately.
|
||||
*
|
||||
* 2. DRAM0_S0 — the main DDR window starting at 0x8000_0000.
|
||||
* Mapped as normal cacheable memory, read-write, secure.
|
||||
* Size comes from CONFIG_RAMBANK1_SIZE (512 MB for PocketBeagle 2).
|
||||
*
|
||||
* Both addresses and sizes must be page-aligned (4 KB minimum).
|
||||
*/
|
||||
|
||||
static const struct arm_mmu_region g_mmu_regions[] =
|
||||
{
|
||||
MMU_REGION_FLAT_ENTRY("DEVICE_REGION",
|
||||
CONFIG_DEVICEIO_BASEADDR,
|
||||
CONFIG_DEVICEIO_SIZE,
|
||||
MT_DEVICE_NGNRNE | MT_RW | MT_SECURE),
|
||||
|
||||
MMU_REGION_FLAT_ENTRY("DRAM0_S0",
|
||||
CONFIG_RAMBANK1_ADDR,
|
||||
CONFIG_RAMBANK1_SIZE,
|
||||
MT_NORMAL | MT_RW | MT_SECURE),
|
||||
};
|
||||
|
||||
const struct arm_mmu_config g_mmu_config =
|
||||
{
|
||||
.num_regions = nitems(g_mmu_regions),
|
||||
.mmu_regions = g_mmu_regions,
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm64_el_init
|
||||
*
|
||||
* Description:
|
||||
* Called from arm64_head.S at EL2 or EL3 (whichever is the entry EL)
|
||||
* before dropping to EL1. Use this hook for:
|
||||
* - Early platform-level hardware that must be touched at high EL.
|
||||
* - Hypervisor / secure monitor initialisation.
|
||||
*
|
||||
* On AM62x the TI R5 SYSFW (TIFS) runs in the MCU domain and has already
|
||||
* completed secure world setup before releasing the Cortex-A53 cluster.
|
||||
* U-Boot then sets up DDR, clocks, and UART before loading NuttX.
|
||||
* There is nothing left for us to do at EL2/EL3.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void arm64_el_init(void)
|
||||
{
|
||||
/* Nothing to do — SYSFW and U-Boot have completed all high-EL init. */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm64_chip_boot
|
||||
*
|
||||
* Description:
|
||||
* Called from arm64_boot.c (common layer) after the C runtime is ready.
|
||||
* This is the SoC-level continuation of the boot sequence:
|
||||
* 1. Initialise the MMU with the region table above.
|
||||
* 2. Optionally initialise PSCI for SMP bring-up.
|
||||
* 3. Call the board-specific initialisation hook.
|
||||
* 4. Initialise the early serial console so boot messages work.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void arm64_chip_boot(void)
|
||||
{
|
||||
#ifdef CONFIG_ARCH_USE_MMU
|
||||
arm64_mmu_init(true);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_ARM64_PSCI) && defined(CONFIG_SMP)
|
||||
/* Keep PSCI out of the initial UP bring-up path until the basic
|
||||
* boot-to-NSH flow is stable on AM62x. PSCI is still available for
|
||||
* future SMP enablement.
|
||||
*/
|
||||
|
||||
arm64_psci_init("smc");
|
||||
#endif
|
||||
|
||||
am62x_board_initialize();
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
arm64_earlyserialinit();
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm64_netinitialize (stub)
|
||||
*
|
||||
* Description:
|
||||
* Network device initialisation hook called by the common layer when
|
||||
* CONFIG_NET is enabled and CONFIG_NETDEV_LATEINIT is not set.
|
||||
* Ethernet support is not part of the initial port.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT)
|
||||
void arm64_netinitialize(void)
|
||||
{
|
||||
/* TODO: add CPSW / MDIO Ethernet support in a later phase. */
|
||||
}
|
||||
#endif
|
||||
@@ -0,0 +1,85 @@
|
||||
/****************************************************************************
|
||||
* arch/arm64/src/am62x/am62x_boot.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM64_SRC_AM62X_AM62X_BOOT_H
|
||||
#define __ARCH_ARM64_SRC_AM62X_AM62X_BOOT_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/compiler.h>
|
||||
#include <sys/types.h>
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
|
||||
#include <arch/chip/chip.h>
|
||||
#include "arm64_internal.h"
|
||||
#include "arm64_arch.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: am62x_board_initialize
|
||||
*
|
||||
* Description:
|
||||
* Board-specific initialization called from am62x_boot.c after the MMU
|
||||
* and common peripherals are set up. Board code in
|
||||
* boards/arm64/am62x/<board>/src/ provides this function.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void am62x_board_initialize(void);
|
||||
|
||||
/****************************************************************************
|
||||
* Name: am62x_memory_initialize
|
||||
*
|
||||
* Description:
|
||||
* Called very early, before .bss is zeroed or .data is copied, to
|
||||
* perform any board-level memory initialization (e.g. DRAM training).
|
||||
* For boards where U-Boot already initialises DRAM this is a no-op.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void am62x_memory_initialize(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM64_SRC_AM62X_AM62X_BOOT_H */
|
||||
@@ -0,0 +1,172 @@
|
||||
/****************************************************************************
|
||||
* arch/arm64/src/am62x/am62x_lowputc.S
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************
|
||||
*
|
||||
* DESCRIPTION
|
||||
* Low-level UART output for TI AM62x, used before the C serial driver
|
||||
* is initialised (CONFIG_ARCH_EARLY_PRINT path).
|
||||
*
|
||||
* The AM62x console UART is a 16550-compatible peripheral. The base
|
||||
* address is selected at build time either by the generic 16550 console
|
||||
* configuration or by the legacy AM62X UART selection. U-Boot
|
||||
* configures it at 115200-8N1 before handing off to NuttX, so
|
||||
* arm64_earlyprintinit is a no-op — we simply inherit U-Boot's config.
|
||||
*
|
||||
* Register usage in arm64_lowputc follows the AAPCS64 ABI:
|
||||
* x0 — character to transmit (caller-provided, preserved across call)
|
||||
* x15 — UART base address (scratch, callee-save not required for leaf)
|
||||
* w2 — LSR value (scratch)
|
||||
*
|
||||
* All other callee-saved registers are untouched because arm64_lowputc
|
||||
* is a leaf function.
|
||||
*
|
||||
***************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "arm64_macro.inc"
|
||||
|
||||
/****************************************************************************
|
||||
* Public Symbols
|
||||
****************************************************************************/
|
||||
|
||||
.file "am62x_lowputc.S"
|
||||
|
||||
/****************************************************************************
|
||||
* Assembly Macros
|
||||
****************************************************************************/
|
||||
|
||||
/* Console UART base address.
|
||||
*
|
||||
* Prefer the configured serial console device. Fall back to enabled UARTs
|
||||
* only if no *_SERIAL_CONSOLE option is set.
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_16550_UART0_SERIAL_CONSOLE)
|
||||
# define CONSOLE_UART_BASE CONFIG_16550_UART0_BASE
|
||||
#elif defined(CONFIG_UART6_SERIAL_CONSOLE)
|
||||
# define CONSOLE_UART_BASE 0x02860000
|
||||
#elif defined(CONFIG_UART5_SERIAL_CONSOLE)
|
||||
# define CONSOLE_UART_BASE 0x02850000
|
||||
#elif defined(CONFIG_UART4_SERIAL_CONSOLE)
|
||||
# define CONSOLE_UART_BASE 0x02840000
|
||||
#elif defined(CONFIG_UART3_SERIAL_CONSOLE)
|
||||
# define CONSOLE_UART_BASE 0x02830000
|
||||
#elif defined(CONFIG_UART2_SERIAL_CONSOLE)
|
||||
# define CONSOLE_UART_BASE 0x02820000
|
||||
#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
|
||||
# define CONSOLE_UART_BASE 0x02810000
|
||||
#elif defined(CONFIG_UART0_SERIAL_CONSOLE)
|
||||
# define CONSOLE_UART_BASE 0x02800000
|
||||
#elif defined(CONFIG_AM62X_UART6)
|
||||
# define CONSOLE_UART_BASE 0x02860000
|
||||
#elif defined(CONFIG_AM62X_UART5)
|
||||
# define CONSOLE_UART_BASE 0x02850000
|
||||
#elif defined(CONFIG_AM62X_UART4)
|
||||
# define CONSOLE_UART_BASE 0x02840000
|
||||
#elif defined(CONFIG_AM62X_UART3)
|
||||
# define CONSOLE_UART_BASE 0x02830000
|
||||
#elif defined(CONFIG_AM62X_UART2)
|
||||
# define CONSOLE_UART_BASE 0x02820000
|
||||
#elif defined(CONFIG_AM62X_UART1)
|
||||
# define CONSOLE_UART_BASE 0x02810000
|
||||
#else
|
||||
# define CONSOLE_UART_BASE 0x02800000 /* Default: UART0 */
|
||||
#endif
|
||||
|
||||
/* 16550 register offsets */
|
||||
|
||||
#define UART_THR_OFF 0x00 /* Transmit Holding Register */
|
||||
#define UART_LSR_OFF 0x14 /* Line Status Register */
|
||||
#define UART_LSR_THRE (1 << 5)/* TX Holding Register Empty bit */
|
||||
|
||||
/****************************************************************************
|
||||
* Private Macros
|
||||
****************************************************************************/
|
||||
|
||||
/* early_uart_ready xb, wt
|
||||
* Spin until the TX holding register is empty.
|
||||
* xb — register holding the UART base address
|
||||
* wt — scratch word register for LSR read
|
||||
*/
|
||||
|
||||
.macro early_uart_ready xb, wt
|
||||
1:
|
||||
ldr \wt, [\xb, #UART_LSR_OFF] /* Read LSR */
|
||||
tst \wt, #UART_LSR_THRE /* Test THRE bit */
|
||||
b.eq 1b /* Loop while THRE == 0 */
|
||||
.endm
|
||||
|
||||
/* early_uart_transmit xb, wt
|
||||
* Write one byte to the THR.
|
||||
* xb — register holding the UART base address
|
||||
* wt — word register containing the byte to transmit
|
||||
*/
|
||||
|
||||
.macro early_uart_transmit xb, wt
|
||||
strb \wt, [\xb, #UART_THR_OFF] /* Write byte to THR */
|
||||
.endm
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm64_earlyprintinit
|
||||
*
|
||||
* Description:
|
||||
* Hardware-specific UART initialisation for early print.
|
||||
* On AM62x, U-Boot has already configured UART0 (clocks, baud rate,
|
||||
* pin mux) before the image is loaded. Nothing to do here.
|
||||
*
|
||||
* Input Parameters:
|
||||
* None
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
GTEXT(arm64_earlyprintinit)
|
||||
SECTION_FUNC(text, arm64_earlyprintinit)
|
||||
ret /* U-Boot already initialised UART */
|
||||
|
||||
/****************************************************************************
|
||||
* Name: arm64_lowputc
|
||||
*
|
||||
* Description:
|
||||
* Output one character to UART0 by polling the LSR THRE bit.
|
||||
* This function is safe to call before the MMU is enabled (flat map)
|
||||
* and before the C runtime is up.
|
||||
*
|
||||
* Input Parameters:
|
||||
* x0 - character to transmit
|
||||
*
|
||||
* Returned Value:
|
||||
* None
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
GTEXT(arm64_lowputc)
|
||||
SECTION_FUNC(text, arm64_lowputc)
|
||||
ldr x15, =CONSOLE_UART_BASE /* Load console UART base into x15 */
|
||||
early_uart_ready x15, w2 /* Wait for TX holding reg empty */
|
||||
early_uart_transmit x15, w0 /* Write character */
|
||||
ret
|
||||
@@ -0,0 +1,71 @@
|
||||
/****************************************************************************
|
||||
* arch/arm64/src/am62x/am62x_serial.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM64_SRC_AM62X_AM62X_SERIAL_H
|
||||
#define __ARCH_ARM64_SRC_AM62X_AM62X_SERIAL_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "arm64_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* IRQ numbers for the main-domain UARTs are defined in
|
||||
* arch/arm64/include/am62x/irq.h (AM62X_IRQ_UARTx) and in
|
||||
* hardware/am62x_uart.h (AM62X_UARTx_IRQ). No re-definition needed here.
|
||||
*/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
#define EXTERN extern "C"
|
||||
extern "C"
|
||||
{
|
||||
#else
|
||||
#define EXTERN extern
|
||||
#endif
|
||||
|
||||
/* Called from am62x_boot.c / USE_EARLYSERIALINIT path */
|
||||
|
||||
void arm64_earlyserialinit(void);
|
||||
|
||||
/* Called from arm64_initialize (common layer, up_initialize) */
|
||||
|
||||
void arm64_serialinit(void);
|
||||
|
||||
#undef EXTERN
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
#endif /* __ARCH_ARM64_SRC_AM62X_AM62X_SERIAL_H */
|
||||
@@ -0,0 +1,48 @@
|
||||
/****************************************************************************
|
||||
* arch/arm64/src/am62x/chip.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM64_SRC_AM62X_CHIP_H
|
||||
#define __ARCH_ARM64_SRC_AM62X_CHIP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
# include <nuttx/arch.h>
|
||||
#endif
|
||||
|
||||
/* All GIC addresses and memory-map constants live in the include-layer
|
||||
* chip.h (arch/arm64/include/am62x/chip.h) which is pulled in via
|
||||
* <arch/chip/chip.h>. Nothing extra needed here.
|
||||
*
|
||||
* The hardware register headers are in hardware/ and are included
|
||||
* directly by the driver files that need them.
|
||||
*/
|
||||
|
||||
/* Number of GIC SPI target registers for AM62x (480 SPIs / 32 = 15) */
|
||||
|
||||
#define CONFIG_NUM_GIC_ITARGETS_REGS 15
|
||||
|
||||
#endif /* __ARCH_ARM64_SRC_AM62X_CHIP_H */
|
||||
@@ -0,0 +1,117 @@
|
||||
/****************************************************************************
|
||||
* arch/arm64/src/am62x/hardware/am62x_memorymap.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* Reference: AM62x TRM (SPRSP43), Chapter 2 - Memory Map */
|
||||
|
||||
#ifndef __ARCH_ARM64_SRC_AM62X_HARDWARE_AM62X_MEMORYMAP_H
|
||||
#define __ARCH_ARM64_SRC_AM62X_HARDWARE_AM62X_MEMORYMAP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* Main Domain Peripheral Base Addresses (TRM §2.1) ************************/
|
||||
|
||||
/* UART (16550-compatible, main domain) */
|
||||
|
||||
#define AM62X_UART0_BASE 0x02800000ul /* UART0 main domain console */
|
||||
#define AM62X_UART1_BASE 0x02810000ul
|
||||
#define AM62X_UART2_BASE 0x02820000ul
|
||||
#define AM62X_UART3_BASE 0x02830000ul
|
||||
#define AM62X_UART4_BASE 0x02840000ul
|
||||
#define AM62X_UART5_BASE 0x02850000ul
|
||||
#define AM62X_UART6_BASE 0x02860000ul
|
||||
|
||||
/* MCU Domain UART (used by R5 firmware, do not use from A53 without care) */
|
||||
|
||||
#define AM62X_MCU_UART0_BASE 0x04a00000ul
|
||||
|
||||
/* GIC-600 (TRM §9.2) */
|
||||
|
||||
#define AM62X_GIC_BASE 0x01800000ul /* GIC top-level */
|
||||
#define AM62X_GICD_BASE 0x01800000ul /* Distributor */
|
||||
#define AM62X_GICR_BASE 0x01880000ul /* Redistributor (4 cores) */
|
||||
#define AM62X_GICR_STRIDE 0x00020000ul /* Per-core stride */
|
||||
|
||||
/* Timers */
|
||||
|
||||
#define AM62X_DMTIMER0_BASE 0x2400000ul
|
||||
#define AM62X_DMTIMER1_BASE 0x2410000ul
|
||||
#define AM62X_DMTIMER2_BASE 0x2420000ul
|
||||
#define AM62X_DMTIMER3_BASE 0x2430000ul
|
||||
|
||||
/* GPIO */
|
||||
|
||||
#define AM62X_GPIO0_BASE 0x00600000ul
|
||||
#define AM62X_GPIO1_BASE 0x00601000ul
|
||||
|
||||
/* I2C */
|
||||
|
||||
#define AM62X_I2C0_BASE 0x20000000ul
|
||||
#define AM62X_I2C1_BASE 0x20010000ul
|
||||
#define AM62X_I2C2_BASE 0x20020000ul
|
||||
#define AM62X_I2C3_BASE 0x20030000ul
|
||||
|
||||
/* SPI (McSPI) */
|
||||
|
||||
#define AM62X_SPI0_BASE 0x20100000ul
|
||||
#define AM62X_SPI1_BASE 0x20110000ul
|
||||
#define AM62X_SPI2_BASE 0x20120000ul
|
||||
|
||||
/* USB */
|
||||
|
||||
#define AM62X_USB0_BASE 0x31100000ul
|
||||
#define AM62X_USB1_BASE 0x31200000ul
|
||||
|
||||
/* MMC/SD */
|
||||
|
||||
#define AM62X_MMCSD0_BASE 0xfa10000ul
|
||||
#define AM62X_MMCSD1_BASE 0xfa00000ul
|
||||
#define AM62X_MMCSD2_BASE 0xfa20000ul
|
||||
|
||||
/* Watchdog */
|
||||
|
||||
#define AM62X_WDT0_BASE 0x23100000ul
|
||||
#define AM62X_WDT1_BASE 0x23110000ul
|
||||
|
||||
/* CTRL_MMR (Pad config / system control) */
|
||||
|
||||
#define AM62X_CTRLMMR_BASE 0x000f0000ul
|
||||
#define AM62X_PADCFG_BASE 0x000f0000ul
|
||||
|
||||
/* DDR Base (512 MB on PocketBeagle 2 / BeaglePlay) */
|
||||
|
||||
#define AM62X_DDR_BASE 0x80000000ul
|
||||
#define AM62X_DDR_SIZE 0x20000000ul /* 512 MB */
|
||||
|
||||
/* Device I/O region for MMU flat mapping */
|
||||
|
||||
#define AM62X_DEVICEIO_BASE 0x00000000ul
|
||||
#define AM62X_DEVICEIO_SIZE 0x80000000ul /* Peripheral space below DDR */
|
||||
|
||||
#endif /* __ARCH_ARM64_SRC_AM62X_HARDWARE_AM62X_MEMORYMAP_H */
|
||||
@@ -0,0 +1,167 @@
|
||||
/****************************************************************************
|
||||
* arch/arm64/src/am62x/hardware/am62x_uart.h
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*
|
||||
* Licensed to the Apache Software Foundation (ASF) under one or more
|
||||
* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
||||
* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
||||
* License. You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
||||
* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/* Reference: AM62x TRM (SPRSP43), Chapter 12 - UART.
|
||||
* The AM62x UART is a 16550-compatible peripheral with TI K3 extensions.
|
||||
* Register layout matches the industry-standard 16550 at offsets
|
||||
* 0x00-0x1c. TI-specific registers begin at 0x20 (MDR1) and beyond.
|
||||
*/
|
||||
|
||||
#ifndef __ARCH_ARM64_SRC_AM62X_HARDWARE_AM62X_UART_H
|
||||
#define __ARCH_ARM64_SRC_AM62X_HARDWARE_AM62X_UART_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* UART register offsets (standard 16550 layout) ****************************/
|
||||
|
||||
#define UART_RHR_OFFSET 0x00 /* Receiver Holding Register (read) */
|
||||
#define UART_THR_OFFSET 0x00 /* Transmitter Holding Register (wr) */
|
||||
#define UART_IER_OFFSET 0x04 /* Interrupt Enable Register */
|
||||
#define UART_IIR_OFFSET 0x08 /* Interrupt Identification Reg (rd) */
|
||||
#define UART_FCR_OFFSET 0x08 /* FIFO Control Register (write) */
|
||||
#define UART_EFR_OFFSET 0x08 /* Enhanced Feature Register (Mode B)*/
|
||||
#define UART_LCR_OFFSET 0x0c /* Line Control Register */
|
||||
#define UART_MCR_OFFSET 0x10 /* Modem Control Register */
|
||||
#define UART_LSR_OFFSET 0x14 /* Line Status Register */
|
||||
#define UART_MSR_OFFSET 0x18 /* Modem Status Register */
|
||||
#define UART_DLL_OFFSET 0x00 /* Divisor Latch Low (LCR[7]=1) */
|
||||
#define UART_DLH_OFFSET 0x04 /* Divisor Latch High (LCR[7]=1) */
|
||||
|
||||
/* UART register offsets (TI-specific extensions) ***************************/
|
||||
|
||||
#define UART_MDR1_OFFSET 0x20 /* Mode Definition Register 1 */
|
||||
#define UART_SYSC_OFFSET 0x54 /* System Configuration Register */
|
||||
#define UART_SYSS_OFFSET 0x58 /* System Status Register */
|
||||
#define UART_RFL_OFFSET 0x64 /* RX FIFO level register */
|
||||
#define UART_EFR2_OFFSET 0x8c /* Enhanced Feature Register 2 (K3) */
|
||||
#define UART_TO_L_OFFSET 0x98 /* RX timeout low register (K3) */
|
||||
#define UART_TO_H_OFFSET 0x9c /* RX timeout high register (K3) */
|
||||
|
||||
/* IER bits *****************************************************************/
|
||||
|
||||
#define UART_IER_RHR (1 << 0) /* RX data available + CTI */
|
||||
#define UART_IER_THR (1 << 1) /* TX holding register empty */
|
||||
#define UART_IER_LINE (1 << 2) /* Receiver line status */
|
||||
#define UART_IER_MODEM (1 << 3) /* Modem status */
|
||||
|
||||
/* IIR bits (read) **********************************************************/
|
||||
|
||||
#define UART_IIR_PENDING (1 << 0) /* 1 = no interrupt pending */
|
||||
#define UART_IIR_ID_MASK 0x3e /* Interrupt ID bits [5:1] */
|
||||
#define UART_IIR_ID_RLS 0x06 /* Receiver line status */
|
||||
#define UART_IIR_ID_RDA 0x04 /* Received data available */
|
||||
#define UART_IIR_ID_CTI 0x0c /* Character timeout indication */
|
||||
#define UART_IIR_ID_THRE 0x02 /* THR empty */
|
||||
#define UART_IIR_ID_MSR 0x00 /* Modem status */
|
||||
|
||||
/* FCR bits *****************************************************************/
|
||||
|
||||
#define UART_FCR_FIFOEN (1 << 0) /* Enable TX/RX FIFOs */
|
||||
#define UART_FCR_RXRST (1 << 1) /* Reset RX FIFO */
|
||||
#define UART_FCR_TXRST (1 << 2) /* Reset TX FIFO */
|
||||
#define UART_FCR_TXTRIG_SHIFT 4
|
||||
#define UART_FCR_RXTRIG_SHIFT 6
|
||||
#define UART_FCR_TXTRIG(n) (((n) & 3) << UART_FCR_TXTRIG_SHIFT)
|
||||
#define UART_FCR_RXTRIG(n) (((n) & 3) << UART_FCR_RXTRIG_SHIFT)
|
||||
|
||||
/* LCR bits *****************************************************************/
|
||||
|
||||
#define UART_LCR_WLS_5 0x00 /* 5-bit word length */
|
||||
#define UART_LCR_WLS_6 0x01 /* 6-bit word length */
|
||||
#define UART_LCR_WLS_7 0x02 /* 7-bit word length */
|
||||
#define UART_LCR_WLS_8 0x03 /* 8-bit word length */
|
||||
#define UART_LCR_STB (1 << 2) /* 2 stop bits */
|
||||
#define UART_LCR_PEN (1 << 3) /* Parity enable */
|
||||
#define UART_LCR_EPS (1 << 4) /* Even parity select */
|
||||
#define UART_LCR_BRK (1 << 6) /* Break control */
|
||||
#define UART_LCR_CONFIG_MODE_A 0x80 /* TI config mode A (DLAB=1) */
|
||||
#define UART_LCR_CONFIG_MODE_B 0xbf /* TI config mode B (EFR access) */
|
||||
|
||||
/* MCR bits *****************************************************************/
|
||||
|
||||
#define UART_MCR_DTR (1 << 0) /* Data terminal ready */
|
||||
#define UART_MCR_RTS (1 << 1) /* Request to send */
|
||||
#define UART_MCR_OUT2 (1 << 3) /* IRQ output enable (OUT2) */
|
||||
|
||||
/* LSR bits *****************************************************************/
|
||||
|
||||
#define UART_LSR_DR (1 << 0) /* Data ready in RX FIFO */
|
||||
#define UART_LSR_OE (1 << 1) /* Overrun error */
|
||||
#define UART_LSR_PE (1 << 2) /* Parity error */
|
||||
#define UART_LSR_FE (1 << 3) /* Framing error */
|
||||
#define UART_LSR_BI (1 << 4) /* Break interrupt */
|
||||
#define UART_LSR_THRE (1 << 5) /* TX holding register empty */
|
||||
#define UART_LSR_TEMT (1 << 6) /* TX shift register empty */
|
||||
#define UART_LSR_RXFE (1 << 7) /* RX FIFO error */
|
||||
|
||||
/* EFR bits *****************************************************************/
|
||||
|
||||
#define UART_EFR_ENHANCEDEN (1 << 4) /* Enable enhanced functions */
|
||||
|
||||
/* EFR2 bits (K3-specific) **************************************************/
|
||||
|
||||
/* K3 Errata i2310: set this bit to allow clearing a spurious CTI that
|
||||
* fires with an empty RX FIFO. The bit changes how the timeout counter
|
||||
* resets; momentarily asserting it together with a max timeout value and
|
||||
* reading IIR deasserts the stuck interrupt.
|
||||
*/
|
||||
|
||||
#define UART_EFR2_TIMEOUT_BEHAVE (1 << 6)
|
||||
|
||||
/* MDR1 bits ****************************************************************/
|
||||
|
||||
#define UART_MDR1_MODE_16X 0x00 /* UART 16x mode (normal) */
|
||||
#define UART_MDR1_MODE_DISABLE 0x07 /* Disable UART */
|
||||
|
||||
/* SYSC bits ****************************************************************/
|
||||
|
||||
#define UART_SYSC_SOFTRESET (1 << 1) /* Software reset */
|
||||
#define UART_SYSC_IDLEMODE_NO (1 << 3) /* No-idle mode */
|
||||
|
||||
/* SYSS bits ****************************************************************/
|
||||
|
||||
#define UART_SYSS_RESETDONE (1 << 0) /* Reset complete */
|
||||
|
||||
/* UART functional clock.
|
||||
* AM62x UART is clocked from HSDIV4_CLKOUT1, configured by TIFS to 48 MHz.
|
||||
* Reference: AM62x TRM section 12.3.1 and TIFS documentation.
|
||||
*/
|
||||
|
||||
#define AM62X_UART_SCLK 48000000ul
|
||||
|
||||
/* UART IRQ numbers (raw GIC INTIDs = GIC_SPI_number + 32).
|
||||
* Source: Linux kernel arch/arm64/boot/dts/ti/k3-am62.dtsi.
|
||||
* UART0 → GIC_SPI 178 → INTID 210
|
||||
* UART6 → GIC_SPI 184 → INTID 216
|
||||
*/
|
||||
|
||||
#define AM62X_UART0_IRQ 210 /* GIC_SPI 178 */
|
||||
#define AM62X_UART1_IRQ 211 /* GIC_SPI 179 */
|
||||
#define AM62X_UART2_IRQ 212 /* GIC_SPI 180 */
|
||||
#define AM62X_UART3_IRQ 213 /* GIC_SPI 181 */
|
||||
#define AM62X_UART4_IRQ 214 /* GIC_SPI 182 */
|
||||
#define AM62X_UART5_IRQ 215 /* GIC_SPI 183 */
|
||||
#define AM62X_UART6_IRQ 216 /* GIC_SPI 184 */
|
||||
|
||||
#endif /* __ARCH_ARM64_SRC_AM62X_HARDWARE_AM62X_UART_H */
|
||||
Reference in New Issue
Block a user