arch/esp32[s2|s3]: Add common I2S arch layer support

Add common I2S arch layer support for Xtensa based Espressif devices

Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>

arch/xtensa/src/common/espressif/Kconfig

@@ -28,6 +28,35 @@ config ESPRESSIF_TEMP
 	---help---
 		A built-in sensor used to measure the chip's internal temperature.
 
+config ESPRESSIF_I2S
+	bool
+	default n
+
+config ESPRESSIF_I2S0
+	bool "I2S 0"
+	default n
+	depends on !ESP32_I2S && !ESP32S2_I2S && !ESP32S3_I2S
+	select ESPRESSIF_I2S
+	select I2S
+	select ESP32S3_DMA if ARCH_CHIP_ESP32S3
+	select ESP32S3_GPIO_IRQ if ARCH_CHIP_ESP32S3
+	select ESP32S2_GPIO_IRQ if ARCH_CHIP_ESP32S2
+	select ESP32_GPIO_IRQ if ARCH_CHIP_ESP32
+	select SCHED_HPWORK
+	select ARCH_DMA
+
+config ESPRESSIF_I2S1
+	bool "I2S 1"
+	depends on !ARCH_CHIP_ESP32S2
+	default n
+	select ESPRESSIF_I2S
+	select I2S
+	select ESP32S3_DMA if ARCH_CHIP_ESP32S3
+	select ESP32S3_GPIO_IRQ if ARCH_CHIP_ESP32S3
+	select ESP32_GPIO_IRQ if ARCH_CHIP_ESP32
+	select SCHED_HPWORK
+	select ARCH_DMA
+
 config ESPRESSIF_I2C_PERIPH_MASTER_MODE
 	bool
 	depends on (ESP32S3_I2C_PERIPH_MASTER_MODE || ESP32S2_I2C_PERIPH_MASTER_MODE || ESP32_I2C_PERIPH_MASTER_MODE)
@@ -345,6 +374,246 @@ config ESPRESSIF_TEMP_THREAD_STACKSIZE
 
 endmenu # ESPRESSIF_TEMP
 
+menu "I2S Configuration"
+	depends on ESPRESSIF_I2S
+
+config ESPRESSIF_I2S_MAXINFLIGHT
+	int "I2S queue size"
+	default 4
+	---help---
+		This is the total number of transfers, both RX and TX, that can be
+		enqueued before the caller is required to wait.  This setting
+		determines the number certain queue data structures that will be
+		pre-allocated.
+
+if ESPRESSIF_I2S0
+
+config ESPRESSIF_I2S0_RX
+	bool "Enable I2S receiver"
+	default y
+	---help---
+		Enable I2S receiver (port 0)
+
+config ESPRESSIF_I2S0_TX
+	bool "Enable I2S transmitter"
+	default y
+	---help---
+		Enable I2S transmitter (port 0)
+
+choice ESPRESSIF_I2S0_ROLE
+	prompt "I2S0 role"
+	default ESPRESSIF_I2S0_ROLE_MASTER
+	---help---
+		Selects the operation role of the I2S0.
+
+config ESPRESSIF_I2S0_ROLE_MASTER
+	bool "Master"
+
+config ESPRESSIF_I2S0_ROLE_SLAVE
+	bool "Slave"
+
+endchoice # I2S0 role
+
+choice ESPRESSIF_I2S0_DATA_BIT_WIDTH
+	prompt "Bit width"
+	default ESPRESSIF_I2S0_DATA_BIT_WIDTH_16BIT
+	---help---
+		Selects the valid data bits per sample.
+		Note that this option may be overwritten by the audio
+		according to the bit width of the file being played
+
+config ESPRESSIF_I2S0_DATA_BIT_WIDTH_8BIT
+	bool "8 bits"
+
+config ESPRESSIF_I2S0_DATA_BIT_WIDTH_16BIT
+	bool "16 bits"
+
+config ESPRESSIF_I2S0_DATA_BIT_WIDTH_24BIT
+	bool "24 bits"
+
+config ESPRESSIF_I2S0_DATA_BIT_WIDTH_32BIT
+	bool "32 bits"
+
+endchoice # Bit width
+
+config ESPRESSIF_I2S0_SAMPLE_RATE
+	int "I2S0 sample rate"
+	default 44100
+	range 8000 48000
+	---help---
+		Selects the sample rate.
+		Note that this option may be overwritten by the audio
+		according to the bit width of the file being played
+
+config ESPRESSIF_I2S0_BCLKPIN
+	int "I2S0 BCLK pin"
+	default 4 if ARCH_CHIP_ESP32S3 || ARCH_CHIP_ESP32
+	default 35 if ARCH_CHIP_ESP32S2
+	range 0 45 if (ARCH_CHIP_ESP32S2 && ESPRESSIF_I2S0_ROLE_MASTER)
+	range 0 46 if (ARCH_CHIP_ESP32S2 && ESPRESSIF_I2S0_ROLE_SLAVE)
+	range 0 33 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_MASTER)
+	range 0 39 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_SLAVE)
+	range 0 48 if ARCH_CHIP_ESP32S3
+
+config ESPRESSIF_I2S0_WSPIN
+	int "I2S0 WS pin"
+	default 5 if ARCH_CHIP_ESP32S3 || ARCH_CHIP_ESP32
+	default 34 if ARCH_CHIP_ESP32S2
+	range 0 45 if (ARCH_CHIP_ESP32S2 && ESPRESSIF_I2S0_ROLE_MASTER)
+	range 0 46 if (ARCH_CHIP_ESP32S2 && ESPRESSIF_I2S0_ROLE_SLAVE)
+	range 0 33 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_MASTER)
+	range 0 39 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_SLAVE)
+	range 0 48 if ARCH_CHIP_ESP32S3
+
+config ESPRESSIF_I2S0_DINPIN
+	int "I2S0 DIN pin"
+	depends on ESPRESSIF_I2S0_RX
+	default 19 if ARCH_CHIP_ESP32S3 || ARCH_CHIP_ESP32
+	default 37 if ARCH_CHIP_ESP32S2
+	range 0 46 if ARCH_CHIP_ESP32S2
+	range 0 48 if ARCH_CHIP_ESP32S3
+	range 0 39 if ARCH_CHIP_ESP32
+
+config ESPRESSIF_I2S0_DOUTPIN
+	int "I2S0 DOUT pin"
+	depends on ESPRESSIF_I2S0_TX
+	default 18 if ARCH_CHIP_ESP32S3 || ARCH_CHIP_ESP32
+	default 36 if ARCH_CHIP_ESP32S2
+	range 0 46 if ARCH_CHIP_ESP32S2
+	range 0 48 if ARCH_CHIP_ESP32S3
+	range 0 33 if ARCH_CHIP_ESP32
+
+config ESPRESSIF_I2S0_MCLK
+	bool "Enable I2S Master Clock"
+	depends on ESPRESSIF_I2S0_ROLE_MASTER
+	default n
+	---help---
+		Enable I2S master clock
+
+config ESPRESSIF_I2S0_MCLKPIN
+	int "I2S MCLK pin"
+	depends on ESPRESSIF_I2S0_MCLK
+	default 0 if ARCH_CHIP_ESP32S3 || ARCH_CHIP_ESP32
+	default 33 if ARCH_CHIP_ESP32S2
+	range 0 45 if ARCH_CHIP_ESP32S2
+	range 0 48 if ARCH_CHIP_ESP32S3
+	range 0 3 if ARCH_CHIP_ESP32
+
+endif # ESPRESSIF_I2S0
+
+if ESPRESSIF_I2S1
+
+config ESPRESSIF_I2S1_RX
+	bool "Enable I2S receiver"
+	default y
+	---help---
+		Enable I2S receiver (port 1)
+
+config ESPRESSIF_I2S1_TX
+	bool "Enable I2S transmitter"
+	default y
+	---help---
+		Enable I2S transmitter (port 1)
+
+choice ESPRESSIF_I2S1_ROLE
+	prompt "I2S1 role"
+	default ESPRESSIF_I2S1_ROLE_MASTER
+	---help---
+		Selects the operation role of the I2S0.
+
+config ESPRESSIF_I2S1_ROLE_MASTER
+	bool "Master"
+
+config ESPRESSIF_I2S1_ROLE_SLAVE
+	bool "Slave"
+
+endchoice # I2S1 role
+
+choice ESPRESSIF_I2S1_DATA_BIT_WIDTH
+	prompt "Bit width"
+	default ESPRESSIF_I2S1_DATA_BIT_WIDTH_16BIT
+	---help---
+		Selects the valid data bits per sample.
+		Note that this option may be overwritten by the audio
+		according to the bit width of the file being played
+
+config ESPRESSIF_I2S1_DATA_BIT_WIDTH_8BIT
+	bool "8 bits"
+
+config ESPRESSIF_I2S1_DATA_BIT_WIDTH_16BIT
+	bool "16 bits"
+
+config ESPRESSIF_I2S1_DATA_BIT_WIDTH_24BIT
+	bool "24 bits"
+
+config ESPRESSIF_I2S1_DATA_BIT_WIDTH_32BIT
+	bool "32 bits"
+
+endchoice # Bit width
+
+config ESPRESSIF_I2S1_SAMPLE_RATE
+	int "I2S1 sample rate"
+	default 44100
+	range 8000 48000
+	---help---
+		Selects the sample rate.
+		Note that this option may be overwritten by the audio
+		according to the bit width of the file being played
+
+config ESPRESSIF_I2S1_BCLKPIN
+	int "I2S1 BCLK pin"
+	default 22
+	range 0 33 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_MASTER)
+	range 0 39 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_SLAVE)
+	range 0 48 if ARCH_CHIP_ESP32S3
+
+config ESPRESSIF_I2S1_WSPIN
+	int "I2S1 WS pin"
+	default 23
+	range 0 33 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_MASTER)
+	range 0 39 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_SLAVE)
+	range 0 48 if ARCH_CHIP_ESP32S3
+
+config ESPRESSIF_I2S1_DINPIN
+	int "I2S1 DIN pin"
+	depends on ESPRESSIF_I2S1_RX
+	default 26
+	range 0 39 if ARCH_CHIP_ESP32
+	range 0 48 if ARCH_CHIP_ESP32S3
+
+config ESPRESSIF_I2S1_DOUTPIN
+	int "I2S1 DOUT pin"
+	depends on ESPRESSIF_I2S1_TX
+	default 25
+	range 0 39 if ARCH_CHIP_ESP32
+	range 0 48 if ARCH_CHIP_ESP32S3
+
+config ESPRESSIF_I2S1_MCLK
+	bool "Enable I2S Master Clock"
+	depends on ESPRESSIF_I2S1_ROLE_MASTER
+	default n
+	---help---
+		Enable I2S master clock
+
+config ESPRESSIF_I2S1_MCLKPIN
+	int "I2S1 MCLK pin"
+	depends on ESPRESSIF_I2S1_MCLK
+	default 1 if ARCH_CHIP_ESP32S3
+	default 0 if ARCH_CHIP_ESP32
+	range 0 48 if ARCH_CHIP_ESP32S3
+	range 0 3 if ARCH_CHIP_ESP32
+
+endif # ESPRESSIF_I2S1
+
+config I2S_DMADESC_NUM
+	int "I2S DMA maximum number of descriptors"
+	default 2
+	---help---
+		Configure the maximum number of out-link/in-link descriptors to
+		be chained for a I2S DMA transfer.
+
+endmenu # I2S configuration
+
 menu "I2C bitbang configuration"
 	depends on ESPRESSIF_I2C_BITBANG
 

arch/xtensa/src/common/espressif/Make.defs

@@ -42,6 +42,10 @@ ifeq ($(CONFIG_ESPRESSIF_TEMP),y)
 CHIP_CSRCS += esp_temperature_sensor.c
 endif
 
+ifeq ($(CONFIG_ESPRESSIF_I2S),y)
+CHIP_CSRCS += esp_i2s.c
+endif
+
 ifeq ($(CONFIG_ESPRESSIF_I2C_BITBANG),y)
 CHIP_CSRCS += esp_i2c_bitbang.c
 endif

arch/xtensa/src/common/espressif/esp_i2s.h

@@ -0,0 +1,87 @@
+/****************************************************************************
+ * arch/xtensa/src/common/espressif/esp_i2s.h
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_I2S_H
+#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_I2S_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <nuttx/audio/i2s.h>
+
+#ifndef __ASSEMBLY__
+
+#undef EXTERN
+#if defined(__cplusplus)
+#define EXTERN extern "C"
+extern "C"
+{
+#else
+#define EXTERN extern
+#endif
+
+#ifdef CONFIG_ESPRESSIF_I2S
+
+#define ESPRESSIF_I2S0 0
+#define ESPRESSIF_I2S1 1
+
+#if defined(CONFIG_ARCH_CHIP_ESP32S3)
+#define ESP32S3_I2S0 0
+#define ESP32S3_I2S1 1
+#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
+#define ESP32S2_I2S0 0
+#elif defined(CONFIG_ARCH_CHIP_ESP32)
+#define ESP32_I2S0 0
+#define ESP32_I2S1 1
+#endif
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: esp_i2sbus_initialize
+ *
+ * Description:
+ *   Initialize the selected I2S port
+ *
+ * Input Parameters:
+ *   port - Port number (for hardware that has multiple I2S interfaces)
+ *
+ * Returned Value:
+ *   Valid I2S device structure reference on success; a NULL on failure
+ *
+ ****************************************************************************/
+
+struct i2s_dev_s *esp_i2sbus_initialize(int port);
+
+#endif /* CONFIG_ESPRESSIF_I2S */
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_I2S_H */

arch/xtensa/src/esp32/Kconfig

@@ -311,7 +311,7 @@ config ESP32_SDMMC
 		No yet implemented
 
 config ESP32_I2S
-	bool "I2S"
+	bool "I2S (legacy implementation)"
 	select I2S
 	---help---
 		See the Board Selection menu to configure the pins used by I2S.

arch/xtensa/src/esp32/hal.mk

@@ -110,6 +110,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
@@ -123,6 +124,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c
 
 ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)

arch/xtensa/src/esp32s2/Kconfig

@@ -229,7 +229,7 @@ config ESP32S2_RNG
 		ESP32-S2 supports a RNG that passed on Dieharder test suite.
 
 config ESP32S2_I2S
-	bool "I2S"
+	bool "I2S (legacy implementation)"
 	default n
 	select I2S
 	select ARCH_DMA

arch/xtensa/src/esp32s2/hal.mk

@@ -108,6 +108,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
@@ -118,6 +119,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)flash_ops.c
 

arch/xtensa/src/esp32s3/Kconfig

@@ -365,7 +365,7 @@ config ESP32S3_I2C
 	default n
 
 config ESP32S3_I2S
-	bool "I2S"
+	bool "I2S (legacy implementation)"
 	select I2S
 	---help---
 		See the Board Selection menu to configure the pins used by I2S.

arch/xtensa/src/esp32s3/hal.mk

@@ -116,6 +116,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c
@@ -126,11 +127,13 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c
+CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c
 CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_wrap.c