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arch/esp32[s2|s3]: Add common I2S arch layer support
Add common I2S arch layer support for Xtensa based Espressif devices Signed-off-by: Eren Terzioglu <eren.terzioglu@espressif.com>
This commit is contained in:
Eren Terzioglu
committed by
Xiang Xiao
Xiang Xiao
parent
fd4914b953
commit
873a6319bb
@@ -28,6 +28,35 @@ config ESPRESSIF_TEMP
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---help---
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A built-in sensor used to measure the chip's internal temperature.
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config ESPRESSIF_I2S
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bool
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default n
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config ESPRESSIF_I2S0
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bool "I2S 0"
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default n
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depends on !ESP32_I2S && !ESP32S2_I2S && !ESP32S3_I2S
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select ESPRESSIF_I2S
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select I2S
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select ESP32S3_DMA if ARCH_CHIP_ESP32S3
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select ESP32S3_GPIO_IRQ if ARCH_CHIP_ESP32S3
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select ESP32S2_GPIO_IRQ if ARCH_CHIP_ESP32S2
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select ESP32_GPIO_IRQ if ARCH_CHIP_ESP32
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select SCHED_HPWORK
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select ARCH_DMA
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config ESPRESSIF_I2S1
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bool "I2S 1"
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depends on !ARCH_CHIP_ESP32S2
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default n
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select ESPRESSIF_I2S
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select I2S
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select ESP32S3_DMA if ARCH_CHIP_ESP32S3
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select ESP32S3_GPIO_IRQ if ARCH_CHIP_ESP32S3
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select ESP32_GPIO_IRQ if ARCH_CHIP_ESP32
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select SCHED_HPWORK
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select ARCH_DMA
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config ESPRESSIF_I2C_PERIPH_MASTER_MODE
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bool
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depends on (ESP32S3_I2C_PERIPH_MASTER_MODE || ESP32S2_I2C_PERIPH_MASTER_MODE || ESP32_I2C_PERIPH_MASTER_MODE)
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@@ -345,6 +374,246 @@ config ESPRESSIF_TEMP_THREAD_STACKSIZE
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endmenu # ESPRESSIF_TEMP
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menu "I2S Configuration"
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depends on ESPRESSIF_I2S
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config ESPRESSIF_I2S_MAXINFLIGHT
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int "I2S queue size"
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default 4
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---help---
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This is the total number of transfers, both RX and TX, that can be
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enqueued before the caller is required to wait. This setting
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determines the number certain queue data structures that will be
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pre-allocated.
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if ESPRESSIF_I2S0
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config ESPRESSIF_I2S0_RX
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bool "Enable I2S receiver"
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default y
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---help---
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Enable I2S receiver (port 0)
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config ESPRESSIF_I2S0_TX
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bool "Enable I2S transmitter"
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default y
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---help---
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Enable I2S transmitter (port 0)
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choice ESPRESSIF_I2S0_ROLE
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prompt "I2S0 role"
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default ESPRESSIF_I2S0_ROLE_MASTER
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---help---
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Selects the operation role of the I2S0.
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config ESPRESSIF_I2S0_ROLE_MASTER
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bool "Master"
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config ESPRESSIF_I2S0_ROLE_SLAVE
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bool "Slave"
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endchoice # I2S0 role
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choice ESPRESSIF_I2S0_DATA_BIT_WIDTH
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prompt "Bit width"
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default ESPRESSIF_I2S0_DATA_BIT_WIDTH_16BIT
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---help---
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Selects the valid data bits per sample.
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Note that this option may be overwritten by the audio
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according to the bit width of the file being played
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config ESPRESSIF_I2S0_DATA_BIT_WIDTH_8BIT
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bool "8 bits"
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config ESPRESSIF_I2S0_DATA_BIT_WIDTH_16BIT
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bool "16 bits"
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config ESPRESSIF_I2S0_DATA_BIT_WIDTH_24BIT
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bool "24 bits"
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config ESPRESSIF_I2S0_DATA_BIT_WIDTH_32BIT
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bool "32 bits"
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endchoice # Bit width
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config ESPRESSIF_I2S0_SAMPLE_RATE
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int "I2S0 sample rate"
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default 44100
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range 8000 48000
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---help---
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Selects the sample rate.
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Note that this option may be overwritten by the audio
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according to the bit width of the file being played
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config ESPRESSIF_I2S0_BCLKPIN
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int "I2S0 BCLK pin"
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default 4 if ARCH_CHIP_ESP32S3 || ARCH_CHIP_ESP32
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default 35 if ARCH_CHIP_ESP32S2
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range 0 45 if (ARCH_CHIP_ESP32S2 && ESPRESSIF_I2S0_ROLE_MASTER)
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range 0 46 if (ARCH_CHIP_ESP32S2 && ESPRESSIF_I2S0_ROLE_SLAVE)
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range 0 33 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_MASTER)
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range 0 39 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_SLAVE)
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range 0 48 if ARCH_CHIP_ESP32S3
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config ESPRESSIF_I2S0_WSPIN
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int "I2S0 WS pin"
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default 5 if ARCH_CHIP_ESP32S3 || ARCH_CHIP_ESP32
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default 34 if ARCH_CHIP_ESP32S2
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range 0 45 if (ARCH_CHIP_ESP32S2 && ESPRESSIF_I2S0_ROLE_MASTER)
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range 0 46 if (ARCH_CHIP_ESP32S2 && ESPRESSIF_I2S0_ROLE_SLAVE)
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range 0 33 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_MASTER)
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range 0 39 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_SLAVE)
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range 0 48 if ARCH_CHIP_ESP32S3
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config ESPRESSIF_I2S0_DINPIN
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int "I2S0 DIN pin"
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depends on ESPRESSIF_I2S0_RX
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default 19 if ARCH_CHIP_ESP32S3 || ARCH_CHIP_ESP32
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default 37 if ARCH_CHIP_ESP32S2
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range 0 46 if ARCH_CHIP_ESP32S2
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range 0 48 if ARCH_CHIP_ESP32S3
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range 0 39 if ARCH_CHIP_ESP32
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config ESPRESSIF_I2S0_DOUTPIN
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int "I2S0 DOUT pin"
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depends on ESPRESSIF_I2S0_TX
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default 18 if ARCH_CHIP_ESP32S3 || ARCH_CHIP_ESP32
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default 36 if ARCH_CHIP_ESP32S2
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range 0 46 if ARCH_CHIP_ESP32S2
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range 0 48 if ARCH_CHIP_ESP32S3
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range 0 33 if ARCH_CHIP_ESP32
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config ESPRESSIF_I2S0_MCLK
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bool "Enable I2S Master Clock"
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depends on ESPRESSIF_I2S0_ROLE_MASTER
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default n
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---help---
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Enable I2S master clock
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config ESPRESSIF_I2S0_MCLKPIN
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int "I2S MCLK pin"
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depends on ESPRESSIF_I2S0_MCLK
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default 0 if ARCH_CHIP_ESP32S3 || ARCH_CHIP_ESP32
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default 33 if ARCH_CHIP_ESP32S2
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range 0 45 if ARCH_CHIP_ESP32S2
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range 0 48 if ARCH_CHIP_ESP32S3
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range 0 3 if ARCH_CHIP_ESP32
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endif # ESPRESSIF_I2S0
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if ESPRESSIF_I2S1
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config ESPRESSIF_I2S1_RX
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bool "Enable I2S receiver"
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default y
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---help---
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Enable I2S receiver (port 1)
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config ESPRESSIF_I2S1_TX
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bool "Enable I2S transmitter"
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default y
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---help---
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Enable I2S transmitter (port 1)
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choice ESPRESSIF_I2S1_ROLE
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prompt "I2S1 role"
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default ESPRESSIF_I2S1_ROLE_MASTER
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---help---
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Selects the operation role of the I2S0.
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config ESPRESSIF_I2S1_ROLE_MASTER
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bool "Master"
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config ESPRESSIF_I2S1_ROLE_SLAVE
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bool "Slave"
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endchoice # I2S1 role
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choice ESPRESSIF_I2S1_DATA_BIT_WIDTH
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prompt "Bit width"
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default ESPRESSIF_I2S1_DATA_BIT_WIDTH_16BIT
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---help---
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Selects the valid data bits per sample.
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Note that this option may be overwritten by the audio
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according to the bit width of the file being played
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config ESPRESSIF_I2S1_DATA_BIT_WIDTH_8BIT
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bool "8 bits"
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config ESPRESSIF_I2S1_DATA_BIT_WIDTH_16BIT
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bool "16 bits"
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config ESPRESSIF_I2S1_DATA_BIT_WIDTH_24BIT
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bool "24 bits"
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config ESPRESSIF_I2S1_DATA_BIT_WIDTH_32BIT
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bool "32 bits"
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endchoice # Bit width
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config ESPRESSIF_I2S1_SAMPLE_RATE
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int "I2S1 sample rate"
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default 44100
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range 8000 48000
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---help---
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Selects the sample rate.
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Note that this option may be overwritten by the audio
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according to the bit width of the file being played
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config ESPRESSIF_I2S1_BCLKPIN
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int "I2S1 BCLK pin"
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default 22
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range 0 33 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_MASTER)
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range 0 39 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_SLAVE)
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range 0 48 if ARCH_CHIP_ESP32S3
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config ESPRESSIF_I2S1_WSPIN
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int "I2S1 WS pin"
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default 23
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range 0 33 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_MASTER)
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range 0 39 if (ARCH_CHIP_ESP32 && ESPRESSIF_I2S0_ROLE_SLAVE)
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range 0 48 if ARCH_CHIP_ESP32S3
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config ESPRESSIF_I2S1_DINPIN
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int "I2S1 DIN pin"
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depends on ESPRESSIF_I2S1_RX
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default 26
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range 0 39 if ARCH_CHIP_ESP32
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range 0 48 if ARCH_CHIP_ESP32S3
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config ESPRESSIF_I2S1_DOUTPIN
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int "I2S1 DOUT pin"
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depends on ESPRESSIF_I2S1_TX
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default 25
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range 0 39 if ARCH_CHIP_ESP32
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range 0 48 if ARCH_CHIP_ESP32S3
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config ESPRESSIF_I2S1_MCLK
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bool "Enable I2S Master Clock"
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depends on ESPRESSIF_I2S1_ROLE_MASTER
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default n
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---help---
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Enable I2S master clock
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config ESPRESSIF_I2S1_MCLKPIN
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int "I2S1 MCLK pin"
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depends on ESPRESSIF_I2S1_MCLK
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default 1 if ARCH_CHIP_ESP32S3
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default 0 if ARCH_CHIP_ESP32
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range 0 48 if ARCH_CHIP_ESP32S3
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range 0 3 if ARCH_CHIP_ESP32
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endif # ESPRESSIF_I2S1
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config I2S_DMADESC_NUM
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int "I2S DMA maximum number of descriptors"
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default 2
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---help---
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Configure the maximum number of out-link/in-link descriptors to
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be chained for a I2S DMA transfer.
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endmenu # I2S configuration
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menu "I2C bitbang configuration"
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depends on ESPRESSIF_I2C_BITBANG
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@@ -42,6 +42,10 @@ ifeq ($(CONFIG_ESPRESSIF_TEMP),y)
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CHIP_CSRCS += esp_temperature_sensor.c
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endif
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ifeq ($(CONFIG_ESPRESSIF_I2S),y)
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CHIP_CSRCS += esp_i2s.c
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endif
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ifeq ($(CONFIG_ESPRESSIF_I2C_BITBANG),y)
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CHIP_CSRCS += esp_i2c_bitbang.c
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endif
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,87 @@
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/****************************************************************************
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* arch/xtensa/src/common/espressif/esp_i2s.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_I2S_H
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#define __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_I2S_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/audio/i2s.h>
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#ifdef CONFIG_ESPRESSIF_I2S
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#define ESPRESSIF_I2S0 0
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#define ESPRESSIF_I2S1 1
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#if defined(CONFIG_ARCH_CHIP_ESP32S3)
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#define ESP32S3_I2S0 0
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#define ESP32S3_I2S1 1
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#elif defined(CONFIG_ARCH_CHIP_ESP32S2)
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#define ESP32S2_I2S0 0
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#elif defined(CONFIG_ARCH_CHIP_ESP32)
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#define ESP32_I2S0 0
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#define ESP32_I2S1 1
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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/****************************************************************************
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* Name: esp_i2sbus_initialize
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*
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* Description:
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* Initialize the selected I2S port
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*
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* Input Parameters:
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* port - Port number (for hardware that has multiple I2S interfaces)
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*
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* Returned Value:
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* Valid I2S device structure reference on success; a NULL on failure
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*
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****************************************************************************/
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struct i2s_dev_s *esp_i2sbus_initialize(int port);
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#endif /* CONFIG_ESPRESSIF_I2S */
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_XTENSA_SRC_COMMON_ESPRESSIF_ESP_I2S_H */
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@@ -311,7 +311,7 @@ config ESP32_SDMMC
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No yet implemented
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config ESP32_I2S
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bool "I2S"
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bool "I2S (legacy implementation)"
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select I2S
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---help---
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See the Board Selection menu to configure the pins used by I2S.
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@@ -110,6 +110,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
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@@ -123,6 +124,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c
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ifeq ($(CONFIG_ESPRESSIF_SIMPLE_BOOT),y)
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@@ -229,7 +229,7 @@ config ESP32S2_RNG
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ESP32-S2 supports a RNG that passed on Dieharder test suite.
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config ESP32S2_I2S
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bool "I2S"
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bool "I2S (legacy implementation)"
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default n
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select I2S
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select ARCH_DMA
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@@ -108,6 +108,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
|
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CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal_iram.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
|
||||
@@ -118,6 +119,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)flash_ops.c
|
||||
|
||||
|
||||
@@ -365,7 +365,7 @@ config ESP32S3_I2C
|
||||
default n
|
||||
|
||||
config ESP32S3_I2S
|
||||
bool "I2S"
|
||||
bool "I2S (legacy implementation)"
|
||||
select I2S
|
||||
---help---
|
||||
See the Board Selection menu to configure the pins used by I2S.
|
||||
|
||||
@@ -116,6 +116,7 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)ledc_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)pcnt_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)rmt_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)i2s_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)mcpwm_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)timer_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)cache_hal.c
|
||||
@@ -126,11 +127,13 @@ CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)hal$(DELIM)uart_hal.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log_noos.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)log$(DELIM)log.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gdma_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)gpio_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)ledc_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)pcnt_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)rmt_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2c_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)i2s_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)mcpwm_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)soc$(DELIM)$(CHIP_SERIES)$(DELIM)temperature_sensor_periph.c
|
||||
CHIP_CSRCS += chip$(DELIM)$(ESP_HAL_3RDPARTY_REPO)$(DELIM)components$(DELIM)spi_flash$(DELIM)spi_flash_wrap.c
|
||||
|
||||
Reference in New Issue
Block a user