mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 16:50:55 +08:00
Merge branch 'master' of bitbucket.org:AVyhovanec/nuttx
This commit is contained in:
Aleksandr Vyhovanec
@@ -3130,7 +3130,7 @@
|
||||
point numbers.
|
||||
* lib/stdio/lib_libdtoa.c and lib_libvsprintf.c: Correct some floating
|
||||
point options.
|
||||
* arch/arm/lpc43xx/lpc32_usb0dev.c: Add framework for development of
|
||||
* arch/arm/lpc43xx/lpc43_usb0dev.c: Add framework for development of
|
||||
an USB0, device-side driver for the LPC43XX. The initial check-in,
|
||||
however, is simply for the LPC31xx driver with name changes. The
|
||||
LPC31xx has the same USB IP, but will require some additional initialization
|
||||
@@ -4440,7 +4440,7 @@
|
||||
* binfmt/binfmt_execmodule.c: Here is a place where I forget
|
||||
to update the call to sched_releasetcb() to pass the thread
|
||||
type as the second parameter (2013-03-23).
|
||||
* arch/arm/src/lm, kinetis, lpc32, and nuc1xx: Add kernel build
|
||||
* arch/arm/src/lm, kinetis, lpc43, and nuc1xx: Add kernel build
|
||||
support to all ARMv7-M and ARMv6-M chips. There are no
|
||||
configurations in place to to verify these additions!
|
||||
(2013-03-24).
|
||||
@@ -10964,7 +10964,7 @@
|
||||
(2015-09-09).
|
||||
* configs/nucleo-f303re: Support for the STMicro Nucleo F303RE board
|
||||
from Paul Alexander Patience (2015-09-10).
|
||||
* arch/arm/src/lpc43xx/lpc32_ehci.c and .h: LPC43xx EHCI driver from
|
||||
* arch/arm/src/lpc43xx/lpc43_ehci.c and .h: LPC43xx EHCI driver from
|
||||
Ilya Averyanov (2015-09-10).
|
||||
* ARMv7-M, all "lazy" interrupt stack logic. Assembly instruction
|
||||
that fetches the saved value is incorrect; replace with more
|
||||
@@ -12348,7 +12348,7 @@
|
||||
adds DEBUGASSERT for invalid geometry and additional memory debug
|
||||
logic. Also fixes the dangling pointer on error bug. From Ken
|
||||
Pettit (2016-07-14).
|
||||
* arch/arm/src/lpc32xx: Extend LPC43xx EMC code to support SDRAM on a
|
||||
* arch/arm/src/lpc43xx: Extend LPC43xx EMC code to support SDRAM on a
|
||||
dynamic memory interface. From Vytautas Lukenskas (2016-07-19).
|
||||
* arch/sim/src: Add the simulated QSPI (N25Q) flash to the simulation
|
||||
and modify sim up_spiflash.c to enable it to run with different MTD
|
||||
@@ -12772,6 +12772,9 @@
|
||||
* STM32 DMA2D: fix an error in up_dma2dcreatelayer where an invalid
|
||||
pointer was returned when a certain underlying function failed. From
|
||||
Jens Gräf (2016-10-07).
|
||||
|
||||
7.19 2016-12-26 Gregory Nutt <gnutt@nuttx.org>
|
||||
|
||||
* include/nuttx/fs/nxffs.h: Needs forward reference to struct mtd_dev_s
|
||||
and needs to include stdbool.h (2016-10-09).
|
||||
* STM32F103 Minimum: Note in Kconfig that the board supports buttons.
|
||||
@@ -12844,16 +12847,16 @@
|
||||
(2016-10-19).
|
||||
* libc/locale: Allows c++ code to compile with or without
|
||||
CONFIG_LIBC_LOCALE and will generate a link error if CONFIG_LIBC_LOCALE
|
||||
is not defined and setlocale is referneced. With CONFIG_LIBC_LOCALE
|
||||
is not defined and setlocale is referenced. With CONFIG_LIBC_LOCALE
|
||||
defined setlocale will act as if MB string is not supported and return
|
||||
"C" for POSIX. C and "". From David Sidrane (2016-10-19).
|
||||
* Add vectors for interrupt levels 2-6 (2016-10-20).
|
||||
* strtof: Add strtof() as simply a copy of strtod with types and
|
||||
* Xtensa ESP32: Add vectors for interrupt levels 2-6 (2016-10-20).
|
||||
* strtof(): Add strtof() as simply a copy of strtod with types and
|
||||
limits changed (2016-10-20).
|
||||
* arch/arm/src/stm32v7: Register the watchdog device at the configured
|
||||
device path CONFIG_WATCHDOG_DEVPATH vs. hard-coded /dev/wdt. From Frank
|
||||
Benkert (2016-10-21).
|
||||
* configs/*/defdonf The buttons example was changed to archbuttons. As
|
||||
* configs/*/defconfig: The buttons example was changed to archbuttons. As
|
||||
a result all of the button configurations are broken and need some
|
||||
renaming in the defconfig files. Noted by Frank Berkert (2016-10-21).
|
||||
* configs/stm32f103-minimum: Add support to PWM on STM32F103-Minimum
|
||||
@@ -12909,7 +12912,7 @@
|
||||
found in the F4. From David Sidrane (2016-10-26).
|
||||
* arch/arm/src/stm32f7: stm32f76xx77xx_pinmap.h Missed one. From
|
||||
David Sidrane (2016-10-26).
|
||||
* LPC32xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. From Vytautas
|
||||
* LPC43xx serial: Fix a typo in ioctl TIOCSRS485 ioctl. From Vytautas
|
||||
Lukenskas (2016-10-27).
|
||||
* sched/clock: Correct clock initialization. The correct range for
|
||||
the month is 0-11 but is entered as 1-12 in the .config file
|
||||
@@ -12919,7 +12922,7 @@
|
||||
* sched/Kconfig: Add ranges to START_YEAR, MONTH, and DAY (2016-10-28).
|
||||
* configs/nucleo-f303re: Add STM32 F303RE hello configuration; remove
|
||||
duplicate setting from board.h. From Marc Rechté (2016-10-18).
|
||||
* arch/arm/src/lpc32xx: Restore RS485 mode on serial port open (if
|
||||
* arch/arm/src/lpc43xx: Restore RS485 mode on serial port open (if
|
||||
RS485 is enabled via menuconfig). From Vytautas Lukenskas (2016-10-28).
|
||||
* arch/arm/src/stm32f7: otgdev fixed typo. From David Sidrane
|
||||
(2016-10-28).
|
||||
@@ -12949,14 +12952,12 @@
|
||||
From Paul A. Patience (2016-11-02).
|
||||
* drivers/ and drivers/spi: Fix Kconfig warning. This commit moves the
|
||||
ARCH_HAVE_SPI options outside the check for SPI. Those options don't
|
||||
depend on SPI, and Kconfig files in arch/ enable them even if SPI isn't
|
||||
enabled.
|
||||
|
||||
Sourcing the driver's Kconfig in drivers/Kconfig only if support for
|
||||
the driver is enabled prevents us from defining these ARCH_HAVE options
|
||||
in the driver's Kconfig. We should probably remove the other checks in
|
||||
drivers/Kconfig and check if the drivers are enabled only in their
|
||||
Kconfig. From Paul A. Patience (2016-11-02).
|
||||
depend on SPI, and Kconfig files in arch/ enable them even if SPI
|
||||
isn't enabled. Source the driver's Kconfig in drivers/Kconfig only
|
||||
if support for the driver is enabled prevents us from defining these
|
||||
ARCH_HAVE options in the driver's Kconfig. We should probably remove
|
||||
the other checks in drivers/Kconfig and check if the drivers are
|
||||
enabled only in their Kconfig. From Paul A. Patience (2016-11-02).
|
||||
* Move protoypes for the non-standard include/semaphore.h file to the
|
||||
non-standard include/nuttx/semaphore.h with the other non-standard
|
||||
semaphore interfaces (2016-11-02).
|
||||
@@ -13100,7 +13101,7 @@
|
||||
argument so that there can be additional usage. From Sebastien Lorquet
|
||||
(2016-11-17).
|
||||
* All timer lower half drivers. Port Sebastien's changes to all all
|
||||
other implementations of the timer lower half. Very many just and
|
||||
other implementations of the timer lower half. Many changes and
|
||||
untested. Expect some problems. (2016-11-17).
|
||||
* sched/irq: irq_csection() has a bad assumption in the SMP case. It
|
||||
assumed that the state of certain variables. That was true on entry
|
||||
@@ -13130,5 +13131,348 @@
|
||||
So this change adds locking (via enter_critical section) to wdog
|
||||
expiration logic for the the case if the SMP configuration
|
||||
(2016-11-18).
|
||||
* SAM3/4: Add delay between setting and clearing the endpoint RESET bit
|
||||
in sam_ep_resume(). We need to add a delay between setting and
|
||||
clearing the endpoint reset bit in SAM_UDP_RSTEP. Without the delay the
|
||||
USB controller will (may?) not reset the endpoint. If the endpoint is
|
||||
not being reset, the Data Toggle (DTGLE) bit will not to be cleared
|
||||
which will cause the next transaction to fail if DTGLE is 1. If that
|
||||
happens the host will time-out and reset the bus. Adding this delay
|
||||
may also fix the USBMSC_STALL_RACEWAR in usbmsc_scsi.c, however this
|
||||
has not been verified yet. From Wolfgang Reißnegger (2016-11-18).
|
||||
* SAM3/4: Remove unused 'halted' flag in UDP driver. From Wolfgang
|
||||
Reißnegger (2016-11-18).
|
||||
* SAM3/4: Remove 'stalled' flag in UDP driver. The flag is not necessary.
|
||||
The state of the endpoint can be determined using 'epstate' instead.
|
||||
From Wolfgang Reißnegger (2016-11-18).
|
||||
* USBMSC: Fix length of mode6 sense reply packet. From Wolfgang
|
||||
Reißnegger (2016-11-18).
|
||||
* configs/dk-tm4c129x: Typo fix. From Wolfgang Reißnegger (2016-11-18).
|
||||
* Typo fix in sam_udp.c. From Wolfgang Reißnegger (2016-11-18).
|
||||
* STM32: STM32F303xB and STM32F303xC chips have 4 ADCs. From Paul A.
|
||||
Patience (2016-11-19).
|
||||
* vfork(): Fix a race condition in the SMP case. Existing logic
|
||||
depended on the fact that the child would not run until waitpid was
|
||||
called because the child had the same priority as the parent. BUT
|
||||
in the SMP case that is not true... the child may run immediately on
|
||||
a different CPU (2016-11-19).
|
||||
* arch/: Add option to use low-priority work queue to all Ethernet
|
||||
drivers in arch that support CONFIG_NET_NOINTS (2016-11-19).
|
||||
* sched/clock: Correct calculation for the case of Tickless mode with
|
||||
a 32-bit timer. In that case, the calculation was returning
|
||||
millisecond accuracy. That is not good when the timer accuracy is < 1
|
||||
msec. From Rajan Gill (2016-11-19).
|
||||
* sched/task: task_restart() test not supported on SMP systems. This is
|
||||
not fully implemented (2016-11-19).
|
||||
* This commit adds a new internal interfaces and fixes a problem with
|
||||
three APIs in the SMP configuration. The new internal interface is
|
||||
sched_cpu_pause(tcb). This function will pause a CPU if the task
|
||||
associated with 'tcb' is running on that CPU. This allows a different
|
||||
CPU to modify that OS data stuctures associated with the CPU. When the
|
||||
other CPU is resumed, those modifications can safely take place. The
|
||||
three fixes are to handle cases in the SMP configuration where one CPU
|
||||
does need to make modifications to TCB and data structures on a task
|
||||
that could be running running on another CPU. Those three cases are
|
||||
task_delete(), task_restart(), and execution of signal handles. In
|
||||
all three cases the solutions is basically the same: (1) Call
|
||||
sched_cpu_pause(tcb) to pause the CPU on which the task is running,
|
||||
(2) perform the necessary operations, then (3) call up_cpu_resume() to
|
||||
restart the paused CPU (2016-11-20).
|
||||
* task_restart: Make sure new task starts with pre-emption disabled and
|
||||
not in a critical section (2016-11-21).
|
||||
* Fix a typo in a spinlock macro (2016-11-21).
|
||||
* Spinlocks: Added capability to provide architecture-specific memory
|
||||
barriers. This was for i.MX6 but does not help with the SMP problems.
|
||||
It is still a good feature (2016-11-21).
|
||||
* Remove a assertion condition that appears to rarely cause false-alarm
|
||||
assertions. Teported by Petteri Aimonen (2016-11-21).
|
||||
* The examples/qencoder app was trying to init the encoder by a direct
|
||||
call into the board, cheating in a local header to declare the normally
|
||||
unavailable function prototype. From Sebastien Lorquet (2016-11-22).
|
||||
* configs: All QE encoder files. Last change made timer hard-coded to 3.
|
||||
Make configurable (2016-11-22).
|
||||
* configs: Remove all traces of the no-longer existent ARCHBUTTONS
|
||||
example. Remove all button configurations that depended on the
|
||||
obsoleted ARCHBUTTON example (2016-11-22).
|
||||
* nucleo-l476rg: Add better selection of timer (2016-11-22).
|
||||
* implementation of dumpgpio for stm32l4, was required for pwm debug.
|
||||
From Sebastien Lorquet (2016-11-22).
|
||||
* SMP: Add logic to avoid a deadlock condition when CPU1 is hung waiting
|
||||
for g_cpu_irqlock and CPU0 is waitin for g_cpu_paused (2016-11-22).
|
||||
* Misoc: Add timer driver. From Ramtin Amin (2016-11-22).
|
||||
* Misoc: Add commits and warnings about missing caculation of the timer
|
||||
reload value (2016-11-22).
|
||||
* SAM3/4: Name of method is now setcallback, not sethandler (2016-11-22).
|
||||
* sam4s-xplained-pro/nsh: Configuration uses old, improper timer interface.
|
||||
CONFIG_TIMER disabled in configuration. (2016-11-22).
|
||||
* sam4s-xplained-pro: Remove obsolete timer initialization logic
|
||||
(2016-11-22).
|
||||
* Misoc LM32: Make system timer configurable via CONFIG_USEC_PER_TICK.
|
||||
From Ramtin Amin (2016-11-23).
|
||||
* LPC43xx: Add timer driver; configs/bambino-200e: Add support for timer
|
||||
driver. From Alan Carvalho de Assis (2016-11-23).
|
||||
* SMP: Fix backward condition in test (2016-11-23).
|
||||
* ARMv7-A SMP: Add a little logic to signal handling (2016-11-24).
|
||||
* Misoc LM32: Add signal handling logic. From Ramtin Amin (2016-11-24).
|
||||
* SMP: Add spin_trylock(). Use this in conditions where other CPUs need
|
||||
to stopped but we cannot call enter_critical_section (2016-11-24).
|
||||
* Fix for F1 RTC Clock, tested on F103. From Maciej Wójcik (2016-11-25).
|
||||
* SMP: Fix yet another potential deadlock (2016-11-25).
|
||||
* Enable CONFIG_RTC in the hymini-stm32v/nsh2 (kitchensink) config.
|
||||
From Maciej Wójcik (2016-11-26).
|
||||
* This adds support for keeping i.MX6 inter-processor communication data
|
||||
in a non-cached address region (2016-11-26).
|
||||
* i.MX6: Disable non-cached region support. Add SCU register definitions
|
||||
(2016-11-26).
|
||||
* i.MX6: Add some controls to enable SMP cache coherency in SMP mode
|
||||
(2016-11-26).
|
||||
* ARMv7-A: Fix some SCU SMP logic (2016-11-26).
|
||||
* ARMv7-A/i.MX6: Modify handling of the SMP cache coherency
|
||||
configuration so that it is identical to the steps from the TRM.
|
||||
Makes no differenct, however (2016-11-27).
|
||||
* The Smoothie project needs to compile C++ inside config/boardname/src/
|
||||
to use with High Priority Interruption, then I modified the board
|
||||
configs Makefile to support it. It works fine for the first time
|
||||
compilation, but if we execute "touch config/boardname/src/Pin.cxx"
|
||||
and execute "make" it will not detect that Pin.cxx was modified. I
|
||||
think there is some other place I should modify, but I didn't find
|
||||
it. From Alan Carvalho de Assis (2016-11-27).
|
||||
* ARMv7-A/i.MX6 SMP: Move SMP coherent cache setup to earlier in
|
||||
initialization of CPUn, n>0 (2016-11-27).
|
||||
* ARMv7 GIC: SGIs are non-maskable but go through the same path as other,
|
||||
maskable interrupts. Added logic to serialize SGI processing when
|
||||
necessary (2016-11-27).
|
||||
* sched_note: Extend OS instrumentation to include some SMP events
|
||||
(2016-11-27).
|
||||
* sched_note: Add spinlock instrumentation; In SMP configurations,
|
||||
select to log only notes from certain CPUs (2016-11-28).
|
||||
* Misoc LM3: Add Misoc Ethernet driver. Integrate network support into
|
||||
configs/misoc/hello. Remove configs/misoc/include/generated directory.
|
||||
I suppose the the intent now is that this is a symbolic link? DANGER!
|
||||
This means that you cannot compile this code with first generating
|
||||
these files a providing a symbolic link to this location! From Ramtin
|
||||
Amin (2016-11-28).
|
||||
* Add tools/showsize.sh (2016-11-28).
|
||||
* configs/misoc: Add a sample directory containing generated sources.
|
||||
This is really only useful for performing test builds. You really
|
||||
must generate the Misoc architecture for a real-life build. From
|
||||
Ramtin Amin (2016-11-28).
|
||||
* sched_note: Permit spinlock and critical section notes in in-memory
|
||||
buffer iff sched_not_get() interfaces is disabled (2016-11-28).
|
||||
* STM32 DAC: Fix shift value whenever there are is a DAC2 and, hence,
|
||||
up to three interfaces. From Marc Rechté (2016-11-29).
|
||||
* Back out a debug change that was included in commit (2016-11-29).
|
||||
* i.MX6: Don't output the alphabet if CONFIG_DEBUG_FEATURES is not set
|
||||
(2016-11-29).
|
||||
* Misoc LM32: Add logic to flush/invalidate caches. From Ramtin Amin
|
||||
(2016-11-29).
|
||||
* drivers/net/: Adapt all Ethernet drivers to work as though
|
||||
CONFIG_NET_MULTIBUFFER were set. Remove all references to
|
||||
CONFIG_NET_MULTIBUFFER (2016-11-29).
|
||||
* stm32_otghshost: if STM32F446 increase number of channels to 16. From
|
||||
Janne Rosberg (2016-11-30).
|
||||
* usbhost_composite: fix end offset in usbhost_copyinterface(). From
|
||||
Janne Rosberg (2016-11-30).
|
||||
* usbhost_cdcacm: add CDC_SUBCLASS_ACM and CDC_PROTO_ATM to supported
|
||||
class and proto. From Janne Rosberg (2016-11-30).
|
||||
* LPC43 SD/MMC: Correct some git definitions on SMMC control register
|
||||
in lpc43_sdmmc.h. From Alan Carvalho de Assis (2016-11-30).
|
||||
* STM32L4: Correct USART1/2 definitions. Use default mbed UART4
|
||||
settings. From Sebastien Lorquet (2016-12-01).
|
||||
* boardctl: Add new boardctl() command ,BOARDIOC_NX_START, to start the
|
||||
NX server as a kernel thread (2016-12-01).
|
||||
* GPDMA driver for the LPC43xx. The GPDMA block is basically the same
|
||||
as the LPC17xx. Only the clock configuration is different and LPC43xx
|
||||
has four different DMA request sources, where LPC17xx has only two.
|
||||
From Alan Carvalho de Assis (2016-12-01).
|
||||
* Remove RGMP and RGMP drivers (2016-12-02).
|
||||
* i.MX6: Add an untested SPI driver taken directly from the i.MX1 port
|
||||
(2016-12-02).
|
||||
* Eliminate CONFIG_NO_NOINTS. There is no longer any support for
|
||||
interrupt level processing of the network stack. Lots of files changed
|
||||
-> lots of testing needed (2016-12-03).
|
||||
* Fix DEBUGASSERT() in group_signal.c. From Masayuki Ishikawa
|
||||
(2016-12-04).
|
||||
* Add support for the SAM5CMP-DB board. From Masayuki Ishikawa
|
||||
(2016-12-04).
|
||||
* SAM3/4: Add SMP support for the dual-core SAM4CM. From Masayuki
|
||||
Ishikawa (2016-12-04).
|
||||
* C Library: Allow option to enable IP address conversions even when the
|
||||
IP address family is not supported (2016-12-04).
|
||||
* SSD1306: Fix errors in SPI mode configuration. From Gong Darcy
|
||||
(2016-12-04).
|
||||
* SAMA5 does not build when executing from SDRAM before board
|
||||
frequencies are not constant. Rather, the bootloader configures the
|
||||
clocking and we must derive the clocking from the MCK left by the
|
||||
bootloader. This means lots more computations. This is untested on
|
||||
initial commit because I don't have a good PWM test setup right now
|
||||
(2016-12-04).
|
||||
* Olimex-LPC1766-STK: Enable procfs in NSH configuration. Automount
|
||||
/proc on startup (2016-12-05).
|
||||
* SAM4CMP-DB: Add hooks to auto-mount the procfs file system on startup
|
||||
in board bring-up logic (2016-12-05).
|
||||
* Remove all references to BOARDIOC_PWMSETUP and board_pwm_setup()
|
||||
(2016-12-05).
|
||||
* Remove all references to BOARDIOC_ADCSETUP and board_adc_setup()
|
||||
(2016-12-05).
|
||||
* Added Timers 2-5 and control of SAI and I2S PLLs. From David Sidrane
|
||||
(2016-12-05).
|
||||
* Added support for stmf469 SAI and I2S PLL configuration and STM446
|
||||
fixes. From David Sidrane (2016-12-05).
|
||||
* Expanded otgfs support to stm32F469 and stm32f446. Added missing bits
|
||||
definitions, Used stm32F469 and stm32f446 bit definitions, Removed
|
||||
unsed header file. From David Sidrane (2016-12-05).
|
||||
* Remove BOARDIOC_CAN_INITIALIZE. CAN initialization is now done in the
|
||||
board initialization logic just like every other device driver
|
||||
(2016-12-06).
|
||||
* STM32F7: Allow the config to override the clock edge setting. From
|
||||
David Sidrane (2016-12-06).
|
||||
* For Cortex-A9, should also set ACTLR.FW in SMP mode to enble TLB and
|
||||
cache broadcasts. Does not fix SMP cache problem (2016-12-07).
|
||||
* sched notes: Add additional note to see if/when CPU is started in SMP
|
||||
mode (2016-12-07).
|
||||
* EFM32: Fix a compilation error. From Pierre-noel Bouteville
|
||||
(2016-12-07).
|
||||
* pthreads: Add pthread_cleanup_push() and pthread_cleanup_pop()
|
||||
(2016-12-08).
|
||||
* BUGFIX:STM32F427 was rebooting. Over reached family. From David
|
||||
Sidrane (2016-12-08).
|
||||
* Add pthread_setcanceltype() and pthread_testcancel() (2016-12-09).
|
||||
* Added STM32F469 RAM size and deliberated STM32F446 size. From David
|
||||
Sidrane (2016-12-09).
|
||||
* Typo in stm32f76xx77xx_pinmap.h edited online with Bitbucket. From
|
||||
David Sidrane (2016-12-09).
|
||||
* stm32_allocateheap.c edited online with Bitbucket. From David Sidrane
|
||||
(2016-12-09).
|
||||
* LPC43xx SD card: Correct pin configuration options needed for SD card
|
||||
pins. From Alan Carvalho de Assis (2016-12-09).
|
||||
* pthread_mutex_destroy(): Fix an error in destroying a mutex which can
|
||||
occur after a pthread has been canceled while holding the mutex
|
||||
(2016-12-09).
|
||||
* Add support for cancellation points (2016-12-09).
|
||||
* Forgot to add some files in the last commit (2016-12-10).
|
||||
* Correct some default font IDs. From Pierre-Noel Bouteville
|
||||
(2016-12-10).
|
||||
* task_delete() now obeys all cancellation point semantics (2016-12-10).
|
||||
* Add task_setcancelstate(), task_setcanceltype(), and task_testcancel().
|
||||
These are non-standard interfaces analogous to the correponding pthread_
|
||||
interfaces that provide cancellation controls for tasks (2016-12-10).
|
||||
* i.MX6 interrupt handling: Additional logic needed to handle nested
|
||||
interrupts when an interrupt stack is used (2016-12-13).
|
||||
* SAMV7 MCAN: Prevent Interrupt-Flooding of ACKE when not connected to
|
||||
CAN-BUS. An Acknowledge-Error will occur every time no other CAN Node
|
||||
acknowledges the message sent. This will also occur if the device is
|
||||
not connected to the can-bus. The CAN-Standard declares, that the Chip
|
||||
has to retry a given message as long as it is not sent successfully (or
|
||||
it is not cancelled by the application). Every time the chip tries to
|
||||
resend the message an Acknowledge-Error-Interrupt is generated. At high
|
||||
baud rates this can lead in extremely high CPU load just for handling
|
||||
the interrupts (and possibly the error handling in the application). To
|
||||
prevent this Interrupt-Flooding we disable the ACKE once it is seen as
|
||||
long we didn't transfer at least one message successfully. From Frank
|
||||
Benkert (2016-12-13).
|
||||
* i.MX6: Remove non-cached, inter-cpu memory region. Not a useful
|
||||
concept (2016-12-13).
|
||||
* minnsh Configurations: Remove minnsh configurations and support logic:
|
||||
up_getc() and lowinstream. This was an interesting exercise to see
|
||||
just how small you could get NuttX, but otherwise it was not useful:
|
||||
(1) the NSH code violated the OS interface layer by callup up_getc and
|
||||
up_putc directly, and (2) while waiting for character input, NSH would
|
||||
call up_getc() which would hog all of the CPU. Not a reasonable
|
||||
solution other than as a proof of concept (2016-12-13).
|
||||
* Calypso Boards: Remove all Calypso board configurations (2016-12-13).
|
||||
* Calypso: Remove Calypso architecture support and support for Calypso
|
||||
SERCOMM driver (2016-12-13).
|
||||
* ESP32 core v2: Two changes (1) flushes the UART TX buffer in the esp32
|
||||
serial shutdown routine. The ROM bootloader does not flush the FIFO
|
||||
before handing over to user code, so some of this output is not
|
||||
currently seen when the UART is reconfigured in early stages of
|
||||
startup. And changes the openocd config file's default flash voltage
|
||||
from 1.8V to 3.3V. This is not necessary right now, but may save some
|
||||
hard-to-debug moments down the track (3.3V-only flash running at 1.8V
|
||||
often half-works and does weird things...). From Angus Gratton
|
||||
(2016-12-14).
|
||||
* Xtensa ESP32: Add missing ENTRY() and RET() macros in C callable
|
||||
assembly language. At one time I though the that the ESP32 support the
|
||||
CALL0 ABI. I was mistaken so there may be a few more like this
|
||||
(2016-12-14).
|
||||
* Xtensa ESP32: Fix a couple of bugs associated with handling of CPU
|
||||
interrupts (2016-12-14).
|
||||
* Xtensa ESP32: Fix several build-related issues associated with vector
|
||||
section (2016-12-15).
|
||||
* Xtensa ESP32: Fix missing CALL0 ABI condition (2016-12-15).
|
||||
* Xtensa EPS32: Make sure that all C callable assembly functions includes
|
||||
ENTRY prologue and RET epilogue (2016-12-15).
|
||||
* Xtensa ESP32: Fix windowspill register handling + Use r6, not r2 when
|
||||
passing paramters with call4 (2016-12-16).
|
||||
* Xtensa ESP32: Use r6, not r2 when passing paramters with call4
|
||||
(2016-12-16).
|
||||
* Xtensa ESP32: Correct a logic problem the prevented dumping the IDLE
|
||||
thread's stack on an assertion (2016-12-16).
|
||||
* Xtensa ESP32: Fix some missing SMP logic (2016-12-16).
|
||||
* Xtensa ESP32: Basically a redesign of the interrupt dispatch logic
|
||||
(2016-12-16).
|
||||
* Xtensa ESP32: Level 1 interrupts should return via RFE (2016-12-17).
|
||||
* Xtensa ESP32: One register getting clobber on context save (2016-12-17).
|
||||
* STM32 F7: Fix some STM32F7 copy paste errors. From David Sidrane
|
||||
(2016-12-17).
|
||||
* CDC/ACM Device Class: uart_ops_s portion of cdcacm will not be
|
||||
initalized with correct functions if CONFIG_SERIAL_DMA is lit
|
||||
(2016-12-17).
|
||||
* Xtensa ESP32: Using wrong register to disable interrupts (2016-12-17).
|
||||
* Xtensa ESP32: Fix clobbered a9 in co-processor context save/restore
|
||||
(2016-12-17).
|
||||
* Xtensa ESP32: Need to clone some logic for synchronous context switch.
|
||||
Window spill logic in the conmon restores logic is inappropriate in
|
||||
this context (2016-12-17).
|
||||
* sscanf(): Add scansets to the scanf function. Enabled
|
||||
CONFIG_LIBC_SCANSET option. From Aleksandr Vyhovanec (2016-12-17).
|
||||
* Xtensa ESP32: Fix context save logic when called in window ABI
|
||||
configuration. Add an IDLE stack. Don't depend on the mystery stack
|
||||
received from the bootloader (2016-12-18).
|
||||
* Xtensa ESP32: Need to spill registers to memory as the last dying
|
||||
action before switching to a new thread (2016-12-18).
|
||||
* ESP32 Serial: Add logic to prevent infinite loops in interrupt handler
|
||||
(2016-12-18).
|
||||
* Xtensa ESP32: Automatically mount /proc at start-up (2016-12-19).
|
||||
* Xtensa ESP32: Corrects timer initialization and timer input frequency
|
||||
(2016-12-19).
|
||||
* Tiva PWM: Support PWM_PULSECOUNT feature for TI tiva. From Young.Mu
|
||||
(2016-12-20).
|
||||
* Xtensa ESP32: Missing prologue/epilogue macros on C callable function
|
||||
(2016-12-20).
|
||||
* Xtensa ESP32: Update APP CPU startup logic to match current Expressif
|
||||
example code. Fix errors APP CPU startup (2016-12-20).
|
||||
* fs/procfs: Fix procfs status for SMP case (2016-12-20).
|
||||
* Xtensa ESP32: Clock frequency is different if running from IRAM or is
|
||||
booting from FLASH. This is a booltloader issue (2016-12-20).
|
||||
* Xtensa ESP32: Basic port is function in both single CPU and dual CPU
|
||||
SMP configurations. There is an NSH configuration for each CPU
|
||||
configuration (2016-12-21).
|
||||
* STM32 F4: Merge in support for the Olimex STM32 P407 board (2016-12-21).
|
||||
* Xtensa ESP32: Add an OS test to verify the port (2016-12-22).
|
||||
* Xtensa ESP32: Corrects a problem with dispatching to signal handlers:
|
||||
Cannot vector directly to the signal handling function as in other ABIs
|
||||
under the Xtensa Window ABI. In that case, we need to go through a
|
||||
tiny hook when performs the correct window call (call4) otherwise
|
||||
registers will be scrambled in the signal handler (2016-12-22).
|
||||
* SAMV7 CAN: Make delete_filter functions more robust. From Frank
|
||||
Benkert (2016-12-23).
|
||||
* Xtensa ESP32: Add stack checking logic (2016-12-23).
|
||||
* sched note: record ID enumeration now results on constant values; ID
|
||||
values do not change with configuration. This makes writing
|
||||
post-processing software much easier (2016-12-24).
|
||||
* STM32 F3: Forgot to update chip.h for STM32F303x[BC]'s 4 ADCs
|
||||
(2016-12-24).
|
||||
* STM32 F4: Allow dma in 1 bit mode in STM32F4xxx. From David Sidrane
|
||||
(2016-12-24).
|
||||
* termios.h: Fix CRTSCTS define to include input and output flow.
|
||||
From Lorenz Meier (2016-12-26).
|
||||
* SMP: Enforce this rule: Tasks which are normally restored when
|
||||
sched_unlock() is called must remain pending (1) if we are in a
|
||||
critical section, i.e., g_cpu_irqlock is locked , or (2) other CPUs
|
||||
still have pre-emption disabled, i.e., g_cpu_schedlock is locked. In
|
||||
those cases, the release of the pending tasks must be deferred until
|
||||
those conditions are met (2016-12-26).
|
||||
|
||||
7.19 2016-xx-xx Gregory Nutt <gnutt@nuttx.org>
|
||||
7.20 2017-xx-xx Gregory Nutt <gnutt@nuttx.org>
|
||||
|
||||
+118
-42
@@ -8,7 +8,7 @@
|
||||
<tr align="center" bgcolor="#e4e4e4">
|
||||
<td>
|
||||
<h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
|
||||
<p>Last Updated: October 8, 2016</p>
|
||||
<p>Last Updated: December 26, 2016</p>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
@@ -317,7 +317,7 @@
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<li>POSIX/ANSI-like task controls, named message queues, counting semaphores, clocks/timers, signals, pthreads, environment variables, filesystem.</li>
|
||||
<li>POSIX/ANSI-like task controls, named message queues, counting semaphores, clocks/timers, signals, pthreads, cancellation points, environment variables, filesystem.</li>
|
||||
</p>
|
||||
</tr>
|
||||
|
||||
@@ -1339,11 +1339,11 @@
|
||||
<h2>Released Versions</h2>
|
||||
<p>
|
||||
In addition to the ever-changing GIT repository, there are frozen released versions of NuttX available.
|
||||
The current release is NuttX 7.18.
|
||||
NuttX 7.18 is the 118<sup>th</sup> release of NuttX.
|
||||
It was released on October 8, 2016, and is available for download from the
|
||||
The current release is NuttX 7.19.
|
||||
NuttX 7.19 is the 119<sup>th</sup> release of NuttX.
|
||||
It was released on December 26, 2016, and is available for download from the
|
||||
<a href="https://bitbucket.org/nuttx/nuttx/downloads/">Bitbucket.org</a> website.
|
||||
Note that the release consists of two tarballs: <code>nuttx-7.18.tar.gz</code> and <code>apps-7.18.tar.gz</code>.
|
||||
Note that the release consists of two tarballs: <code>nuttx-7.19.tar.gz</code> and <code>apps-7.19.tar.gz</code>.
|
||||
Both may be needed (see the top-level <code>nuttx/README.txt</code> file for build information).
|
||||
</p>
|
||||
|
||||
@@ -1352,7 +1352,7 @@
|
||||
<ul>
|
||||
<li><b>nuttx</b>.
|
||||
<ul><p>
|
||||
Release notes for NuttX 7.18 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
|
||||
Release notes for NuttX 7.19 are available <a href="https://bitbucket.org/nuttx/nuttx/downloads/">here</a>.
|
||||
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>.
|
||||
The ChangeLog for all releases of NuttX is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ChangeLog" target="_blank">Bitbucket GIT</a>.
|
||||
The ChangeLog for the current release is at the bottom of that file.
|
||||
@@ -1360,7 +1360,7 @@
|
||||
</li></ul>
|
||||
<li><b>apps</b>.
|
||||
<ul><p>
|
||||
Release notes for NuttX 7.18 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
|
||||
Release notes for NuttX 7.19 are available <a href="https://bitbucket.org/nuttx/apps/downloads/">here</a>.
|
||||
Release notes for all released versions on NuttX are available in the <a href="https://bitbucket.org/nuttx/nuttx/src/master/ReleaseNotes" target="_blank">Bitbucket GIT</a>
|
||||
The ChangeLog for the all releases of <code>apps/</code> is available in the ChangeLog file that can viewed in the <a href="https://bitbucket.org/nuttx/apps/src/master/ChangeLog.txt" target="_blank">Bitbucket GIT</a>.
|
||||
The ChangeLog for the current release is at the bottom of that file.
|
||||
@@ -1408,7 +1408,7 @@
|
||||
<li><a href="#linuxusermode">Linux/Cygwin user mode simulation</a> (1)</li>
|
||||
<li>ARM
|
||||
<ul>
|
||||
<li><a href="#arm7tdmi">ARM7TDMI</b></a> (5)</li>
|
||||
<li><a href="#arm7tdmi">ARM7TDMI</b></a> (4)</li>
|
||||
<li><a href="#arm920t">ARM920T</a> (1)</li>
|
||||
<li><a href="#arm926ejs">ARM926EJS</a> (4)</li>
|
||||
<li><a href="#armv4">Other ARMv4</a> (1)</li>
|
||||
@@ -1418,7 +1418,7 @@
|
||||
<li><a href="#armcortexr4">ARM Cortex-R4</a> (1)</li>
|
||||
<li><a href="#armcortexm0">ARM Cortex-M0/M0+</a> (7)</li>
|
||||
<li><a href="#armcortexm3">ARM Cortex-M3</a> (35)</li>
|
||||
<li><a href="#armcortexm4">ARM Cortex-M4</a> (31)</li>
|
||||
<li><a href="#armcortexm4">ARM Cortex-M4</a> (32)</li>
|
||||
<li><a href="#armcortexm7">ARM Cortex-M7</a> (7)</li>
|
||||
</ul>
|
||||
<li>Atmel AVR
|
||||
@@ -1445,6 +1445,10 @@
|
||||
<li><a href="#pic32mzmips">PIC32MZ</a> (MIPS M14K) (1)</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Misoc
|
||||
<ul>
|
||||
<li><a href="#misoclm32">LM32</a> (1)</li>
|
||||
</ul>
|
||||
<li>Renesas/Hitachi:
|
||||
<ul>
|
||||
<li><a href="#superh">Renesas/Hitachi SuperH</a> (1/2)</li>
|
||||
@@ -1453,6 +1457,15 @@
|
||||
</li>
|
||||
</td>
|
||||
<td bgcolor="#e4e4e4" valign="top" width="33%">
|
||||
<li><a href="#riscv">RISC-V</a> (1)
|
||||
<ul>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Xtensa LX6:
|
||||
<ul>
|
||||
<li><a href="#esp32">ESP32</a> (1)</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>ZiLOG
|
||||
<ul>
|
||||
<li><a href="#zilogz16f">ZiLOG ZNEO Z16F</a> (2)</li>
|
||||
@@ -1502,6 +1515,11 @@
|
||||
<li><a href="#at91sama5d4">Atmel SAMA5D4</a> <small>(ARM Cortex-A5)</small></li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Expressif
|
||||
<ul>
|
||||
<li><a href="#esp32">ESP32</a> <small>(Dual Xtensa LX6)</small</li>
|
||||
</ul>
|
||||
</li>
|
||||
<li>Freescale
|
||||
<ul>
|
||||
<li><a href="#m68hcs12">M68HCS12</a></li>
|
||||
@@ -1533,13 +1551,13 @@
|
||||
<li><a href="#pic32mzec">PIC32MZEC Family</a> <small>(MIPS32 M14K)</small></li>
|
||||
</ul>
|
||||
</li>
|
||||
</td>
|
||||
<td bgcolor="#e4e4e4" valign="top" width="33%">
|
||||
<li>Moxa
|
||||
<ul>
|
||||
<li><a href="#moxart">Moxa NP51x0</a> <small>(ARMv4)</small></li>
|
||||
</ul>
|
||||
</li>
|
||||
</td>
|
||||
<td bgcolor="#e4e4e4" valign="top" width="33%">
|
||||
<li>nuvoTon
|
||||
<ul>
|
||||
<li><a href="#nuvotonnu120">nuvoTon NUC120</a> <small>(ARM Cortex-M0)</small></li>
|
||||
@@ -1604,7 +1622,6 @@
|
||||
<li>Texas Instruments (some formerly Luminary)
|
||||
<ul>
|
||||
<li><a href="#tms320c5471">TI TMS320-C5471</a> <small>(ARM7TDMI)</small></li>
|
||||
<li><a href="#ticalypso">TI Calypso</a> <small>(ARM7TDMI)</small></li>
|
||||
<li><a href="#titms320dm320">TI TMS320-DM320</a> <small>(ARM9E6JS)</small></li>
|
||||
<li><a href="#tilms6432">TI/Stellaris LM3S6432</a> <small>(ARM Cortex-M3)</small></li>
|
||||
<li><a href="#tilm3s6432s2e">TI/Stellaris LM3S6432S2E</a> <small>(ARM Cortex-M3)</small></li>
|
||||
@@ -1695,31 +1712,6 @@
|
||||
<td><br></td>
|
||||
<td><hr></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<a name="ticalypso"><b>TI Calypso</b>.</a>
|
||||
This port supports the TI "Calypso" MCU used in various cell phones (and, in particular,
|
||||
by the <a href="http://bb.osmocom.org/trac/">Osmocom-bb project</a>).
|
||||
Like the c5471, NuttX operates on the ARM7 of this dual core processor.
|
||||
Board support is available for the Motorola C139, C155 and W220 phones and for the Pirelli DP-L10 phone.
|
||||
</p>
|
||||
<ul>
|
||||
<p>
|
||||
<b>STATUS:</b>
|
||||
This port was contributed by Denis Carilki and includes the work of Denis Carikli, Alan Carvalho de Assis, and Stefan Richter.
|
||||
Calypso support first appeared in NuttX-6.17 with LCD drivers.
|
||||
Support for the Calypso keyboard was added in NuttX-6.24 by Denis Carilki.
|
||||
Refer to the NuttX board README files for the <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/compal_e88/README.txt" target="_blank">Compal E88</a>, <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/compal_e99/README.txt" target="_blank">Compal E99</a> and <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pirelli_dpl10/README.txt" target="_blank">Pirelli DP-L10</a> phones for further information.
|
||||
</p>
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td><hr></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
@@ -3160,7 +3152,7 @@ nsh>
|
||||
<li>
|
||||
<p>
|
||||
<b>Kamami STM32 Butterfly 2</b>
|
||||
Support for the <a href="https://kamami.pl/zestawy-uruchomieniowe-stm32/178507-stm32butterfly2.html">Kamami STM32 Butterfly 2</a> was contributed by Michał Łyszczek in NuttX-7/18. That port features the STMicro STM32F107VC MCU.
|
||||
Support for the <a href="https://kamami.pl/zestawy-uruchomieniowe-stm32/178507-stm32butterfly2.html">Kamami STM32 Butterfly 2</a> was contributed by Michał Łyszczek in NuttX-7.18. That port features the STMicro STM32F107VC MCU.
|
||||
</p>
|
||||
<p>
|
||||
<b>STATUS:</b>
|
||||
@@ -3743,11 +3735,14 @@ nsh>
|
||||
<li><b>NuttX-7.3</b>
|
||||
Support for the Olimex STM32 H405 board was added in NuttX-7.3.
|
||||
</li>
|
||||
<li>
|
||||
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/stm3240g-eval/README.txt" target="_blank">README</a> file for further information.
|
||||
<li><b>NuttX-7.19</b>
|
||||
Support for the Olimex STM32 P405 board was added in NuttX-7.19.
|
||||
</li>
|
||||
</ul>
|
||||
</p>
|
||||
<p>
|
||||
Refer to the STM3240G-EVAL board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/stm3240g-eval/README.txt" target="_blank">README</a> file for further information.
|
||||
</p>
|
||||
<p>
|
||||
<b>STMicro STM32F4-Discovery</b>.
|
||||
This port uses the STMicro STM32F4-Discovery board featuring the STM32F407VGT6 MCU.
|
||||
@@ -3817,6 +3812,11 @@ nsh>
|
||||
Networking configurations were added in NuttX-7.18.
|
||||
See the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-e407/README.txt" target="_blank">README</a> file for further information about the NuttX port.
|
||||
</p>
|
||||
<p>
|
||||
<b>Olimex STM32 P407</b>.
|
||||
Support for the Olimex STM32 P407 development board appeared in NuttX-7.19.
|
||||
See the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-p407/README.txt" target="_blank">README</a> file for further information about the NuttX port.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
@@ -4332,7 +4332,7 @@ Mem: 29232 5920 23312 23312
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<a name="at91sam4c"><b>Atmel SAM4C</b>.</a>
|
||||
<a name="at91sam4c"><b>Atmel SAM4CM</b>.</a>
|
||||
General architectural support was provided for SAM4CM family in NuttX 7.3
|
||||
This was <i>architecture-only</i> support, meaning that support for the boards with these chips is available, but no support for any publicly available boards was included.
|
||||
The SAM4CM port should be compatible with most of the SAM3/4 drivers (like HSMCI, DMAC, etc.) but those have not be verified on hardware as of this writing.
|
||||
@@ -4340,6 +4340,18 @@ Mem: 29232 5920 23312 23312
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>Atmel SAM4CMP-DB</b>.
|
||||
Support for the SAM4CMP-DB board was contributed to NuttX by Masayuki Ishikawa in NuttX-7.19.
|
||||
The SAM4CM is a dual-CPU part and SMP was included for the ARMv7-M and SAM3/4 families.
|
||||
The SAM4CMP-DB board support includes an NSH configuration that operates in an SMP configuration.
|
||||
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/sam4cmp-db/README.txt" target="_blank">README</a> file for further information.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td><hr></td>
|
||||
@@ -4856,6 +4868,23 @@ Mem: 29232 5920 23312 23312
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
<a name="misoclm32"><b>Misoc LM32</b>.</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>Misoc LM32 Architectural Support</b>.
|
||||
Architectural support for the Misoc LM32 was contributed by Ramtin Amin in NuttX 7.19. Driver support is basic in this initial release: Serial, Timer, and Ethernet. "Board" support is a available for developing with Misoc LM32 under Qemu or on your custom FPGA.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
@@ -5222,6 +5251,53 @@ BFD_ASSERT (*plt_offset != (bfd_vma) -1);
|
||||
</ul>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
<a name="riscv"><b>RISC-V</b>.</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>RISC-V Architectural Support</b>.
|
||||
Basic support for the RISC-V architecture was contributed by Ken Pettit in NuttX-7.19. The initial release is <i>thin</i> but a great starting point for anyone interested in RISC-V development with NuttX.
|
||||
</p>
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
<a name="esp32"><b>ESP32 <small>(Dual Xtensa LX6)</small></b>.</a>
|
||||
</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><br></td>
|
||||
<td>
|
||||
<p>
|
||||
<b>Xtensa LX6 ESP32 Architectural Support</b>.
|
||||
Basic architectural support for Xtensa LX6 processors and the port for the Expressif ESP32 were added in NuttX-7.19.
|
||||
The basic ESP32 port is function in both single CPU and dual CPU SMP configurations.
|
||||
</p>
|
||||
<p>
|
||||
<b>Expressif ESP32 Core v2 Board</b>
|
||||
The NuttX release includes support for Expressif ESP32 Core v2 board.
|
||||
There is an NSH configuration for each CPU configuration and an OS test configuration for verificatin of the port.
|
||||
</p>
|
||||
<p>
|
||||
<b>STATUS</b>.
|
||||
ESP32 support in NuttX-7.19 is functional, but very preliminary.
|
||||
There is little yet in the way of device driver support.
|
||||
Outstanding issues include missing clock configuration logic, missing partition tables to support correct configuration from FLASH, and some serial driver pin configuration issues.
|
||||
The configuration is usable despite these limitations.
|
||||
Refer to the NuttX board <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/esp32-core/README.txt" target="_blank">README</a> file for further information.
|
||||
</td>
|
||||
</tr>
|
||||
|
||||
<tr>
|
||||
<td valign="top"><img height="20" width="20" src="favicon.ico"></td>
|
||||
<td bgcolor="#5eaee1">
|
||||
|
||||
@@ -1008,10 +1008,6 @@ drivers/
|
||||
| |-- Kconfig
|
||||
| |-- Make.defs
|
||||
| `-- <i>(Common sensor driver source files)</i>
|
||||
|-- sercomm/
|
||||
| |-- Kconfig
|
||||
| |-- Make.defs
|
||||
| `-- <i>(Files for the Calypso SERCOMM driver)</i>
|
||||
|-- serial/
|
||||
| |-- Kconfig
|
||||
| |-- Make.defs
|
||||
@@ -1170,8 +1166,6 @@ include/
|
||||
| | `-- <i>(Power management header files)</i>
|
||||
| |-sensors/
|
||||
| | `-- <i>(Sensor device driver header files)</i>
|
||||
| |-sercomm/
|
||||
| | `-- <i>(SERCOMM driver header files)</i>
|
||||
| |-serial/
|
||||
| | `-- <i>(Serial driver header files)</i>
|
||||
| |-spi/
|
||||
|
||||
+601
-179
File diff suppressed because it is too large
Load Diff
@@ -8,7 +8,7 @@
|
||||
<tr align="center" bgcolor="#e4e4e4">
|
||||
<td>
|
||||
<h1><big><font color="#3c34ec"><i>NuttX README Files</i></font></big></h1>
|
||||
<p>Last Updated: December 4, 2016</p>
|
||||
<p>Last Updated: December 21, 2016</p>
|
||||
</td>
|
||||
</tr>
|
||||
</table>
|
||||
@@ -70,12 +70,6 @@ nuttx/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/cc3200-launchpad/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- cloudctrl/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/cloudctrl/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- compal_e86/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/compal_e86/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- compal_e88/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/compal_e88/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- compal_e99/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/compal_e99/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- demo9s12ne64/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/demo9s12ne64/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- dk-tm4c129x/
|
||||
@@ -183,6 +177,8 @@ nuttx/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-p107/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- olimex-stm32-p207/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-p207/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- olimex-stm32-p407/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-stm32-p407/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- olimex-strp711/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/olimex-strp711/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- open1788/
|
||||
@@ -199,8 +195,6 @@ nuttx/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pic32mx7mmb/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- pic32mz-starterkit/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pic32mz-starterkit/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- pirelli_dpl10/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/pirelli_dpl10/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- qemu-i486/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/configs/qemu-i486/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- sabre-6quad/
|
||||
@@ -328,8 +322,6 @@ nuttx/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/mtd/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
| |- sensors/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/sensors/README.txt" target="_blank">README.txt</a>
|
||||
| |- sercomm/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/sercomm/README.txt" target="_blank">README.txt</a>
|
||||
| |- syslog/
|
||||
| | `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/syslog/README.txt" target="_blank">README.txt</a>
|
||||
| `- <a href="https://bitbucket.org/nuttx/nuttx/src/master/drivers/README.txt" target="_blank"><b><i>README.txt</i></b></a>
|
||||
|
||||
+2
-10
@@ -1287,12 +1287,6 @@ nuttx/
|
||||
| | `- README.txt
|
||||
| |- cloudctrl
|
||||
| | `- README.txt
|
||||
| |- compal_e86
|
||||
| | `- README.txt
|
||||
| |- compal_e88
|
||||
| | `- README.txt
|
||||
| |- compal_e99
|
||||
| | `- README.txt
|
||||
| |- demo0s12ne64/
|
||||
| | `- README.txt
|
||||
| |- dk-tm4c129x/
|
||||
@@ -1399,6 +1393,8 @@ nuttx/
|
||||
| | `- README.txt
|
||||
| |- olimex-stm32-p207/
|
||||
| | `- README.txt
|
||||
| |- olimex-stm32-p407/
|
||||
| | `- README.txt
|
||||
| |- olimex-strp711/
|
||||
| | `- README.txt
|
||||
| |- open1788/
|
||||
@@ -1415,8 +1411,6 @@ nuttx/
|
||||
| | `- README.txt
|
||||
| |- pic32mz-starterkit/
|
||||
| | `- README.txt
|
||||
| |- pirelli_dpl10/
|
||||
| | `- README.txt
|
||||
| |- qemu-i486/
|
||||
| | `- README.txt
|
||||
| |- sabre-6quad/
|
||||
@@ -1544,8 +1538,6 @@ nuttx/
|
||||
| | `- README.txt
|
||||
| |- sensors/
|
||||
| | `- README.txt
|
||||
| |- sercomm/
|
||||
| | `- README.txt
|
||||
| |- syslog/
|
||||
| | `- README.txt
|
||||
| `- README.txt
|
||||
|
||||
+791
File diff suppressed because it is too large
Load Diff
@@ -1,4 +1,4 @@
|
||||
NuttX TODO List (Last updated December 3, 2016)
|
||||
NuttX TODO List (Last updated December 11, 2016)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
This file summarizes known NuttX bugs, limitations, inconsistencies with
|
||||
@@ -9,7 +9,7 @@ issues related to each board port.
|
||||
|
||||
nuttx/:
|
||||
|
||||
(13) Task/Scheduler (sched/)
|
||||
(12) Task/Scheduler (sched/)
|
||||
(1) SMP
|
||||
(1) Memory Management (mm/)
|
||||
(1) Power Management (drivers/pm)
|
||||
@@ -22,7 +22,7 @@ nuttx/:
|
||||
(12) Network (net/, drivers/net)
|
||||
(4) USB (drivers/usbdev, drivers/usbhost)
|
||||
(0) Other drivers (drivers/)
|
||||
(11) Libraries (libc/, libm/)
|
||||
(12) Libraries (libc/, libm/)
|
||||
(11) File system/Generic drivers (fs/, drivers/)
|
||||
(9) Graphics Subsystem (graphics/)
|
||||
(2) Build system / Toolchains
|
||||
@@ -101,16 +101,37 @@ o Task/Scheduler (sched/)
|
||||
Status: Open
|
||||
Priority: Medium Low for now
|
||||
|
||||
Title: ISSUES WITH atexit() AND on_exit()
|
||||
Title: ISSUES WITH atexit(), on_exit(), AND pthread_cleanup_pop()
|
||||
Description: These functions execute with the following bad properties:
|
||||
|
||||
1. They run with interrupts disabled,
|
||||
2. They run in supervisor mode (if applicable), and
|
||||
3. They do not obey any setup of PIC or address
|
||||
environments. Do they need to?
|
||||
4. In the case of task_delete() and pthread_cancel(), these
|
||||
callbacks will run on the thread of execution and address
|
||||
context of the caller of task. That is very bad!
|
||||
|
||||
The fix for all of these issues it to have the callbacks
|
||||
run on the caller's thread (as with signal handlers).
|
||||
run on the caller's thread as is currently done with
|
||||
signal handlers. Signals are delivered differently in
|
||||
PROTECTED and KERNEL modes: The deliver is involes a
|
||||
signal handling trampoline function in the user address
|
||||
space and two signal handlers: One to call the signal
|
||||
handler trampoline in user mode (SYS_signal_handler) and
|
||||
on in with the signal handler trampoline to return to
|
||||
supervisor mode (SYS_signal_handler_return)
|
||||
|
||||
The primary difference is in the location of the signal
|
||||
handling trampoline:
|
||||
|
||||
- In PROTECTED mode, there is on a single user space blob
|
||||
with a header at the beginning of the block (at a well-
|
||||
known location. There is a pointer to the signal handler
|
||||
trampoline function in that header.
|
||||
- In the KERNEL mode, a special process signal handler
|
||||
trampoline is used at a well-known location in every
|
||||
process address space (ARCH_DATA_RESERVE->ar_sigtramp).
|
||||
Status: Open
|
||||
Priority: Medium Low. This is an important change to some less
|
||||
important interfaces. For the average user, these
|
||||
@@ -144,20 +165,6 @@ o Task/Scheduler (sched/)
|
||||
incompatibilities could show up in porting some code).
|
||||
Priority: Low
|
||||
|
||||
Title: REMOVE TASK_DELETE
|
||||
Description: Need to remove or fix task delete. This interface is non-
|
||||
standard and not safe. Arbitrary deleting tasks can cause
|
||||
serious problems such as memory leaks. Better to remove it
|
||||
than to retain it as a latent bug.
|
||||
|
||||
Currently used within the OS and also part of the
|
||||
implementation of pthread_cancel() and task_restart() (which
|
||||
should also go for the same reasons). It is used in
|
||||
NxWM::CNxConsole to terminate console tasks and also in
|
||||
apps/netutils/thttpd to kill CGI tasks that timeout.
|
||||
Status: Open
|
||||
Priority: Low and not easily removable.
|
||||
|
||||
Title: RELEASE SEMAPHORES HELD BY CANCELED THREADS:
|
||||
Description: Commit: fecb9040d0e54baf14b729e556a832febfe8229e: "In
|
||||
case a thread is doing a blocking operation (e.g. read())
|
||||
@@ -491,12 +498,6 @@ o Signals (sched/signal, arch/)
|
||||
o pthreads (sched/pthreads)
|
||||
^^^^^^^^^^^^^^^^^
|
||||
|
||||
Title: CANCELLATION POINTS
|
||||
Description: pthread_cancel(): Should implement cancellation points and
|
||||
pthread_testcancel()
|
||||
Status: Open. No changes are planned.
|
||||
Priority: Low, probably not that useful
|
||||
|
||||
Title: PTHREAD_PRIO_PROTECT
|
||||
Description: Extend pthread_mutexattr_setprotocol() support PTHREAD_PRIO_PROTECT:
|
||||
|
||||
@@ -557,6 +558,44 @@ o pthreads (sched/pthreads)
|
||||
solution. So I discarded a few hours of programming. Not a
|
||||
big loss from the experience I gained."
|
||||
|
||||
Title: ISSUES WITH CANCELLATION POINTS
|
||||
Description: According to POIX cancellation points must occur when a thread is executing
|
||||
the following functions. There are some execptions as noted:
|
||||
|
||||
accept() mq_timedsend() NA putpmsg() sigtimedwait()
|
||||
04 aio_suspend() NA msgrcv() pwrite() NA sigwait()
|
||||
NA clock_nanosleep() NA msgsnd() read() sigwaitinfo()
|
||||
close() NA msync() NA readv() 01 sleep()
|
||||
connect() nanosleep() recv() 02 system()
|
||||
-- creat() open() recvfrom() NA tcdrain()
|
||||
fcntl() pause() NA recvmsg() 01 usleep()
|
||||
NA fdatasync() poll() select() -- wait()
|
||||
fsync() pread() sem_timedwait() waitid()
|
||||
NA getmsg() NA pselect() sem_wait() waitpid()
|
||||
NA getpmsg() pthread_cond_timedwait() send() write()
|
||||
NA lockf() pthread_cond_wait() NA sendmsg() NA writev()
|
||||
mq_receive() pthread_join() sendto()
|
||||
mq_send() pthread_testcancel() 03 sigpause()
|
||||
mq_timedreceive() NA putmsg() sigsuspend()
|
||||
|
||||
NA Not supported
|
||||
-- Doesn't need instrumentation. Handled by lower level calls.
|
||||
nn See note nn
|
||||
|
||||
NOTE 01: sleep() and usleep() are user-space functions in the C library and cannot
|
||||
serve as cancellation points. They are, however, simple wrappers around nanosleep
|
||||
which is a true cancellation point.
|
||||
NOTE 02: system() is actually implemented in apps/ as part of NSH. It cannot be
|
||||
a cancellation point either.
|
||||
NOTE 03: sigpause() is a user-space function in the C library and cannot serve as
|
||||
cancellation points. It is, however, a simple wrapper around sigsuspend()
|
||||
which is a true cancellation point.
|
||||
NOTE 04: aio_suspend() is a user-space function in the C library and cannot serve as
|
||||
cancellation points. It does call around sigtimedwait() which is a true cancellation
|
||||
point.
|
||||
Status: Not really open. This is just the way it is.
|
||||
Priority: Nothing additional is planned.
|
||||
|
||||
o Message Queues (sched/mqueue)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
@@ -1451,10 +1490,28 @@ o Libraries (libc/, libm/)
|
||||
2016-07-30: Numerous fixes and performance improvements from
|
||||
David Alessio.
|
||||
|
||||
Status: Open
|
||||
Priority: Low for casual users but clearly high if you need care about
|
||||
Status: Open
|
||||
Priority: Low for casual users but clearly high if you need care about
|
||||
these incorrect corner case behaviors in the math libraries.
|
||||
|
||||
Title: Repartition libc functionality.
|
||||
Description: There are many things implemented within the kernel (for example
|
||||
under sched/pthread) that probably should be migrated in the
|
||||
C library where it belongs.
|
||||
|
||||
I would really like to see a little flavor of a micro-kernel
|
||||
at the OS interface: I would like to see more primitive OS
|
||||
system calls with more higher level logic in the C library.
|
||||
|
||||
One awkard thing is the incompatibility of KERNEL vs FLAT
|
||||
builds: In the kernel build, it would be nice to move many
|
||||
of the thread-specific data items out of the TCB and into
|
||||
the process address environment where they belong. It is
|
||||
difficult to make this compatible with the FLAT build,
|
||||
however.
|
||||
Status: Open
|
||||
Priority: Low
|
||||
|
||||
o File system / Generic drivers (fs/, drivers/)
|
||||
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
|
||||
|
||||
|
||||
@@ -77,6 +77,8 @@ config ARCH_X86
|
||||
|
||||
config ARCH_XTENSA
|
||||
bool "Xtensa"
|
||||
select ARCH_HAVE_STACKCHECK
|
||||
select ARCH_HAVE_CUSTOMOPT
|
||||
---help---
|
||||
Cadence® Tensilica® Xtensa® actictures.
|
||||
|
||||
|
||||
@@ -158,7 +158,6 @@ arch/arm - ARM-based micro-controllers
|
||||
MCU support
|
||||
arch/arm/include/a1x and arch/arm/src/a1x
|
||||
arch/arm/include/c5471 and arch/arm/src/c5471
|
||||
arch/arm/include/calypso and arch/arm/src/calypso
|
||||
arch/arm/include/dm320 and arch/arm/src/dm320
|
||||
arch/arm/include/efm32 and arch/arm/src/efm32
|
||||
arch/arm/include/imx1 and arch/arm/src/imx1
|
||||
|
||||
@@ -31,16 +31,6 @@ config ARCH_CHIP_C5471
|
||||
---help---
|
||||
TI TMS320 C5471, A180, or DA180 (ARM7TDMI)
|
||||
|
||||
config ARCH_CHIP_CALYPSO
|
||||
bool "Calypso"
|
||||
select ARCH_ARM7TDMI
|
||||
select ARCH_HAVE_HEAP2
|
||||
select ARCH_HAVE_LOWVECTORS
|
||||
select OTHER_UART_SERIALDRIVER
|
||||
select ARCH_HAVE_POWEROFF
|
||||
---help---
|
||||
TI Calypso-based cell phones (ARM7TDMI)
|
||||
|
||||
config ARCH_CHIP_DM320
|
||||
bool "TMS320 DM320"
|
||||
select ARCH_ARM926EJS
|
||||
@@ -409,7 +399,6 @@ config ARCH_CHIP
|
||||
string
|
||||
default "a1x" if ARCH_CHIP_A1X
|
||||
default "c5471" if ARCH_CHIP_C5471
|
||||
default "calypso" if ARCH_CHIP_CALYPSO
|
||||
default "dm320" if ARCH_CHIP_DM320
|
||||
default "efm32" if ARCH_CHIP_EFM32
|
||||
default "imx1" if ARCH_CHIP_IMX1
|
||||
@@ -625,9 +614,6 @@ endif
|
||||
if ARCH_CHIP_C5471
|
||||
source arch/arm/src/c5471/Kconfig
|
||||
endif
|
||||
if ARCH_CHIP_CALYPSO
|
||||
source arch/arm/src/calypso/Kconfig
|
||||
endif
|
||||
if ARCH_CHIP_DM320
|
||||
source arch/arm/src/dm320/Kconfig
|
||||
endif
|
||||
|
||||
@@ -36,25 +36,4 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H
|
||||
#define __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
/* Not a useful feature */
|
||||
|
||||
#undef SMP_INTERCPU_NONCACHED
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED)
|
||||
/* In SMP configurations, save spinlocks and other inter-CPU communications
|
||||
* data in a non-cached memory region.
|
||||
*/
|
||||
|
||||
# define SP_SECTION __attribute__((section(".nocache")))
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_ARMV7_A_SPINLOCK_H */
|
||||
|
||||
@@ -1,67 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#define CALYPSO_PLL26_52_MHZ ((2 << 8) | 0)
|
||||
#define CALYPSO_PLL26_86_7_MHZ ((10 << 8) | 2)
|
||||
#define CALYPSO_PLL26_87_MHZ ((3 << 8) | 0)
|
||||
#define CALYPSO_PLL13_104_MHZ ((8 << 8) | 0)
|
||||
|
||||
enum mclk_div {
|
||||
_ARM_MCLK_DIV_1 = 0,
|
||||
ARM_MCLK_DIV_1 = 1,
|
||||
ARM_MCLK_DIV_2 = 2,
|
||||
ARM_MCLK_DIV_3 = 3,
|
||||
ARM_MCLK_DIV_4 = 4,
|
||||
ARM_MCLK_DIV_5 = 5,
|
||||
ARM_MCLK_DIV_6 = 6,
|
||||
ARM_MCLK_DIV_7 = 7,
|
||||
ARM_MCLK_DIV_1_5 = 0x80 | 1,
|
||||
ARM_MCLK_DIV_2_5 = 0x80 | 2,
|
||||
};
|
||||
|
||||
void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div);
|
||||
void calypso_pll_set(uint16_t inp);
|
||||
void calypso_clk_dump(void);
|
||||
|
||||
/* CNTL_RST */
|
||||
enum calypso_rst {
|
||||
RESET_DSP = (1 << 1),
|
||||
RESET_EXT = (1 << 2),
|
||||
RESET_WDOG = (1 << 3),
|
||||
};
|
||||
|
||||
void calypso_reset_set(enum calypso_rst calypso_rst, int active);
|
||||
int calypso_reset_get(enum calypso_rst);
|
||||
|
||||
enum calypso_bank {
|
||||
CALYPSO_nCS0 = 0,
|
||||
CALYPSO_nCS1 = 2,
|
||||
CALYPSO_nCS2 = 4,
|
||||
CALYPSO_nCS3 = 6,
|
||||
CALYPSO_nCS7 = 8,
|
||||
CALYPSO_CS4 = 0xa,
|
||||
CALYPSO_nCS6 = 0xc,
|
||||
};
|
||||
|
||||
enum calypso_mem_width {
|
||||
CALYPSO_MEM_8bit = 0,
|
||||
CALYPSO_MEM_16bit = 1,
|
||||
CALYPSO_MEM_32bit = 2,
|
||||
};
|
||||
|
||||
void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws,
|
||||
enum calypso_mem_width width, int we);
|
||||
|
||||
/* Enable or disable the internal bootrom mapped to 0x0000'0000 */
|
||||
void calypso_bootrom(int enable);
|
||||
|
||||
/* Enable or disable the debug unit */
|
||||
void calypso_debugunit(int enable);
|
||||
|
||||
/* configure the RHEA bus bridge[s] */
|
||||
void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
|
||||
uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1);
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_CLOCK_H */
|
||||
@@ -1,31 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H
|
||||
|
||||
#ifndef ARRAY_SIZE
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Check at compile time that something is of a particular type.
|
||||
* Always evaluates to 1 so you may use it easily in comparisons.
|
||||
*/
|
||||
#define typecheck(type,x) \
|
||||
({ type __dummy; \
|
||||
typeof(x) __dummy2; \
|
||||
(void)(&__dummy == &__dummy2); \
|
||||
1; \
|
||||
})
|
||||
|
||||
#ifdef DEBUG
|
||||
#define dputchar(x) putchar(x)
|
||||
#define dputs(x) puts(x)
|
||||
#define dphex(x,y) phex(x,y)
|
||||
#define printd(x, ...) printf(x, ##__VA_ARGS__)
|
||||
#else
|
||||
#define dputchar(x)
|
||||
#define dputs(x)
|
||||
#define dphex(x,y)
|
||||
#define printd(x, args ...)
|
||||
#endif
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_DEBUG_H */
|
||||
@@ -1,17 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H
|
||||
|
||||
#define __attribute_const__ __attribute__((__const__))
|
||||
|
||||
/* type properties */
|
||||
#define __packed __attribute__((packed))
|
||||
#define __aligned(alignment) __attribute__((aligned(alignment)))
|
||||
#define __unused __attribute__((unused))
|
||||
|
||||
/* linkage */
|
||||
#define __section(name) __attribute__((section(name)))
|
||||
|
||||
/* force placement in zero-waitstate memory */
|
||||
#define __ramtext __section(".ramtext")
|
||||
|
||||
#endif /* !__ARCH_ARM_INCLUDE_CALYPSO_DEFINES_H */
|
||||
@@ -1,81 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/include/calypso/irq.h
|
||||
* Driver for Calypso IRQ controller
|
||||
*
|
||||
* (C) 2010 by Harald Welte <laforge@gnumonks.org>
|
||||
* (C) 2011 by Stefan Richter <ichgeh@l--putt.de>
|
||||
*
|
||||
* This source code is derivated from Osmocom-BB project and was
|
||||
* relicensed as BSD with permission from original authors.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __INCLUDE_NUTTX_IRQ_H
|
||||
#error "This file should never be included directly! Use <nuttx/irq.h>"
|
||||
#endif
|
||||
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
enum irq_nr {
|
||||
IRQ_WATCHDOG = 0,
|
||||
IRQ_TIMER1 = 1,
|
||||
IRQ_TIMER2 = 2,
|
||||
IRQ_TSP_RX = 3,
|
||||
IRQ_TPU_FRAME = 4,
|
||||
IRQ_TPU_PAGE = 5,
|
||||
IRQ_SIMCARD = 6,
|
||||
IRQ_UART_MODEM = 7,
|
||||
IRQ_KEYPAD_GPIO = 8,
|
||||
IRQ_RTC_TIMER = 9,
|
||||
IRQ_RTC_ALARM_I2C = 10,
|
||||
IRQ_ULPD_GAUGING = 11,
|
||||
IRQ_EXTERNAL = 12,
|
||||
IRQ_SPI = 13,
|
||||
IRQ_DMA = 14,
|
||||
IRQ_API = 15,
|
||||
IRQ_SIM_DETECT = 16,
|
||||
IRQ_EXTERNAL_FIQ = 17,
|
||||
IRQ_UART_IRDA = 18,
|
||||
IRQ_ULPD_GSM_TIMER = 19,
|
||||
IRQ_GEA = 20,
|
||||
_NR_IRQS
|
||||
};
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/* Don't use _NR_IRQS!!! Won't work in preprocessor... */
|
||||
#define NR_IRQS 21
|
||||
|
||||
#define IRQ_SYSTIMER IRQ_TIMER2
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_IRQ_H */
|
||||
@@ -1,28 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H
|
||||
|
||||
#define __arch_getb(a) (*(volatile unsigned char *)(a))
|
||||
#define __arch_getw(a) (*(volatile unsigned short *)(a))
|
||||
#define __arch_getl(a) (*(volatile unsigned int *)(a))
|
||||
|
||||
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
|
||||
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
|
||||
#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
|
||||
|
||||
#define __raw_writeb(v,a) __arch_putb(v,a)
|
||||
#define __raw_writew(v,a) __arch_putw(v,a)
|
||||
#define __raw_writel(v,a) __arch_putl(v,a)
|
||||
|
||||
#define __raw_readb(a) __arch_getb(a)
|
||||
#define __raw_readw(a) __arch_getw(a)
|
||||
#define __raw_readl(a) __arch_getl(a)
|
||||
|
||||
#define writeb(v,a) __arch_putb(v,a)
|
||||
#define writew(v,a) __arch_putw(v,a)
|
||||
#define writel(v,a) __arch_putl(v,a)
|
||||
|
||||
#define readb(a) __arch_getb(a)
|
||||
#define readw(a) __arch_getw(a)
|
||||
#define readl(a) __arch_getl(a)
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_MEMORY_H */
|
||||
@@ -1,25 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H
|
||||
|
||||
/* Enable or Disable a timer */
|
||||
void hwtimer_enable(int num, int on);
|
||||
|
||||
/* Configure pre-scaler and if timer is auto-reload */
|
||||
void hwtimer_config(int num, uint8_t pre_scale, int auto_reload);
|
||||
|
||||
/* Load a timer with the given value */
|
||||
void hwtimer_load(int num, uint16_t val);
|
||||
|
||||
/* Read the current timer value */
|
||||
uint16_t hwtimer_read(int num);
|
||||
|
||||
/* Enable or disable the watchdog */
|
||||
void wdog_enable(int on);
|
||||
|
||||
/* Reset cpu using watchdog */
|
||||
void wdog_reset(void);
|
||||
|
||||
/* power up the timers */
|
||||
void hwtimer_init(void);
|
||||
|
||||
#endif /* __ARCH_ARM_INCLUDE_CALYPSO_TIMER_H */
|
||||
@@ -1,6 +0,0 @@
|
||||
#ifndef __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
|
||||
#define __ARCH_ARM_INCLUDE_CALYPSO_UWIRE_H
|
||||
void uwire_init(void);
|
||||
int uwire_xfer(int cs, int bitlen, const void *dout, void *din);
|
||||
#endif
|
||||
|
||||
@@ -1374,7 +1374,7 @@
|
||||
# define STM32_NLCD 0 /* (0) No LCD */
|
||||
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
|
||||
# define STM32_NGPIO 37 /* GPIOA-F */
|
||||
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
|
||||
# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */
|
||||
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
|
||||
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* (1) CRC calculation unit */
|
||||
@@ -1414,7 +1414,7 @@
|
||||
# define STM32_NLCD 0 /* (0) No LCD */
|
||||
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
|
||||
# define STM32_NGPIO 52 /* GPIOA-F */
|
||||
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
|
||||
# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */
|
||||
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
|
||||
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* (1) CRC calculation unit */
|
||||
@@ -1494,7 +1494,7 @@
|
||||
# define STM32_NLCD 0 /* (0) No LCD */
|
||||
# define STM32_NUSBOTG 0 /* USB FS device, but no USB OTG FS/HS */
|
||||
# define STM32_NGPIO 87 /* GPIOA-F */
|
||||
# define STM32_NADC 3 /* (3) 12-bit ADC1-3 */
|
||||
# define STM32_NADC 4 /* (3) 12-bit ADC1-4 */
|
||||
# define STM32_NDAC 2 /* (2) 12-bit DAC1-2 */
|
||||
# define STM32_NCAPSENSE 0 /* (0) No capacitive sensing channels */
|
||||
# define STM32_NCRC 1 /* (1) CRC calculation unit */
|
||||
|
||||
@@ -75,7 +75,7 @@
|
||||
* This function must be provided via the architecture-specific logoic.
|
||||
*
|
||||
* Input Parameters:
|
||||
* lock - The address of spinlock object.
|
||||
* lock - The address of spinlock object (r0).
|
||||
*
|
||||
* Returned Value:
|
||||
* The spinlock is always locked upon return. The value of previous value
|
||||
@@ -84,6 +84,8 @@
|
||||
* obtain the lock) or SP_UNLOCKED if the spinlock was previously unlocked
|
||||
* (meaning that we successfully obtained the lock)
|
||||
*
|
||||
* Modifies: r1, r2, and lr
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
.globl up_testset
|
||||
@@ -98,7 +100,7 @@ up_testset:
|
||||
1:
|
||||
ldrexb r2, [r0] /* Test if spinlock is locked or not */
|
||||
cmp r2, r1 /* Already locked? */
|
||||
beq 2f /* If alrady locked, return SP_LOCKED */
|
||||
beq 2f /* If already locked, return SP_LOCKED */
|
||||
|
||||
/* Not locked ... attempt to lock it */
|
||||
|
||||
|
||||
@@ -64,6 +64,10 @@ g_fiqtmp:
|
||||
.word 0 /* Saved lr */
|
||||
.word 0 /* Saved spsr */
|
||||
#endif
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3 && defined(CONFIG_ARMV7A_HAVE_GICv2)
|
||||
g_nestlevel:
|
||||
.word 0 /* Interrupt nesting level */
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
* Private Functions
|
||||
@@ -172,13 +176,53 @@ arm_vectorirq:
|
||||
mov r0, sp /* Get r0=xcp */
|
||||
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
#ifdef CONFIG_ARMV7A_HAVE_GICv2
|
||||
/* We will switch to the interrupt stack, UNLESS we are processing a
|
||||
* nested interrupt in which case we are already using the interrupt
|
||||
* stack. SGI interrupts may be nested because they are non-maskable.
|
||||
*/
|
||||
|
||||
ldr r5, .Lirqnestlevel /* r1=Points to interrupt nesting level */
|
||||
ldr r1, [r5] /* Get r1= nesting level */
|
||||
add r1, r1, #1 /* Increment nesting level */
|
||||
str r1, [r5] /* Save r1= nesting level */
|
||||
|
||||
cmp r1, #1 /* r1>1 if nested */
|
||||
bgt .Lintnested /* Use current SP if nested */
|
||||
#endif
|
||||
|
||||
/* Call arm_decodeirq() on the interrupt stack */
|
||||
|
||||
ldr sp, .Lirqstackbase /* SP = interrupt stack base */
|
||||
str r0, [sp] /* Save the user stack pointer */
|
||||
mov r4, sp /* Save the SP in a preserved register */
|
||||
bic sp, sp, #7 /* Force 8-byte alignment */
|
||||
bl arm_decodeirq /* Call the handler */
|
||||
ldr sp, [r4] /* Restore the user stack pointer */
|
||||
|
||||
#ifdef CONFIG_ARMV7A_HAVE_GICv2
|
||||
b .Lintreturn
|
||||
|
||||
/* Call arm_decodeirq() on whatever stack is in place */
|
||||
|
||||
.Lintnested:
|
||||
mov r4, sp /* Save the SP in a preserved register */
|
||||
bic sp, sp, #7 /* Force 8-byte alignment */
|
||||
bl arm_decodeirq /* Call the handler */
|
||||
mov sp, r4 /* Restore the possibly unaligned stack pointer */
|
||||
|
||||
/* Decrement the nesting level (r5 should be preserved) */
|
||||
|
||||
.Lintreturn:
|
||||
ldr r1, [r5] /* Get r1= nesting level */
|
||||
cmp r1, #0 /* A sanity check*/
|
||||
subgt r1, r1, #1 /* Decrement nesting level */
|
||||
strgt r1, [r5] /* Save r1= nesting level */
|
||||
#endif
|
||||
|
||||
#else
|
||||
/* Call arm_decodeirq() on the user stack */
|
||||
|
||||
mov r4, sp /* Save the SP in a preserved register */
|
||||
bic sp, sp, #7 /* Force 8-byte alignment */
|
||||
bl arm_decodeirq /* Call the handler */
|
||||
@@ -227,6 +271,10 @@ arm_vectorirq:
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
.Lirqstackbase:
|
||||
.word g_intstackbase
|
||||
#ifdef CONFIG_ARMV7A_HAVE_GICv2
|
||||
.Lirqnestlevel:
|
||||
.word g_nestlevel
|
||||
#endif
|
||||
#endif
|
||||
.size arm_vectorirq, . - arm_vectorirq
|
||||
.align 5
|
||||
@@ -937,7 +985,7 @@ arm_vectorfiq:
|
||||
.word g_fiqtmp
|
||||
#if CONFIG_ARCH_INTERRUPTSTACK > 3
|
||||
.Lfiqstackbase:
|
||||
.word g_intstackbase
|
||||
.word g_fiqstackbase
|
||||
#endif
|
||||
|
||||
#else
|
||||
@@ -965,5 +1013,21 @@ g_intstackbase:
|
||||
.size g_intstackbase, 4
|
||||
.size g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
|
||||
|
||||
.globl g_fiqstackalloc
|
||||
.type g_fiqstackalloc, object
|
||||
.globl g_fiqstackbase
|
||||
.type g_fiqstackbase, object
|
||||
|
||||
/************************************************************************************
|
||||
* Name: g_fiqstackalloc/g_fiqstackbase
|
||||
************************************************************************************/
|
||||
|
||||
g_fiqstackalloc:
|
||||
.skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4)
|
||||
g_fiqstackbase:
|
||||
.skip 4
|
||||
.size g_fiqstackbase, 4
|
||||
.size g_fiqstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3)
|
||||
|
||||
#endif /* CONFIG_ARCH_INTERRUPTSTACK > 3 */
|
||||
.end
|
||||
|
||||
@@ -605,9 +605,6 @@
|
||||
#define MMU_L2_VECTROFLAGS (PTE_TYPE_SMALL | PTE_WRITE_THROUGH | PTE_AP_R1)
|
||||
#define MMU_L2_VECTORFLAGS MMU_L2_VECTRWFLAGS
|
||||
|
||||
#define MMU_L1_INTERCPUFLAGS (PMD_TYPE_PTE | PMD_PTE_PXN | PMD_PTE_DOM(0))
|
||||
#define MMU_L2_INTERCPUFLAGS (PTE_TYPE_SMALL | PTE_DEVICE | PTE_AP_RW1)
|
||||
|
||||
/* Mapped section size */
|
||||
|
||||
#define SECTION_SHIFT (20)
|
||||
|
||||
@@ -50,22 +50,6 @@
|
||||
#include "up_arch.h"
|
||||
#include "up_internal.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
@@ -46,18 +46,6 @@
|
||||
#if ((defined(CONFIG_BUILD_PROTECTED) && defined(__KERNEL__)) || \
|
||||
defined(CONFIG_BUILD_KERNEL)) && !defined(CONFIG_DISABLE_SIGNALS)
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
@@ -1,115 +0,0 @@
|
||||
#
|
||||
# For a description of the syntax of this configuration file,
|
||||
# see the file kconfig-language.txt in the NuttX tools repository.
|
||||
#
|
||||
|
||||
comment "Calypso Configuration Options"
|
||||
|
||||
menu "Modem UART Configuration"
|
||||
|
||||
config UART_MODEM_BAUD
|
||||
int "Modem UART BAUD"
|
||||
default 115200
|
||||
|
||||
config UART_MODEM_PARITY
|
||||
int "Modem UART parity"
|
||||
default 0
|
||||
---help---
|
||||
Modem UART parity. 0=None, 1=Odd, 2=Even. Default: None
|
||||
|
||||
config UART_MODEM_BITS
|
||||
int "Modem UART number of bits"
|
||||
default 8
|
||||
---help---
|
||||
Modem UART number of bits. Default: 8
|
||||
|
||||
config UART_MODEM_2STOP
|
||||
int "Modem UART two stop bits"
|
||||
default 0
|
||||
---help---
|
||||
0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
|
||||
|
||||
config UART_MODEM_RXBUFSIZE
|
||||
int "Modem UART Rx buffer size"
|
||||
default 256
|
||||
---help---
|
||||
Modem UART Rx buffer size. Default: 256
|
||||
|
||||
config UART_MODEM_TXBUFSIZE
|
||||
int "Modem UART Tx buffer size"
|
||||
default 256
|
||||
---help---
|
||||
Modem UART Tx buffer size. Default: 256
|
||||
|
||||
config UART_MODEM_HWFLOWCONTROL
|
||||
bool "Hardware flow control"
|
||||
default n
|
||||
---help---
|
||||
Enabled Modem UART hardware flow control. Default: n
|
||||
|
||||
endmenu
|
||||
|
||||
menu "IrDA UART Configuration"
|
||||
|
||||
config UART_IRDA_BAUD
|
||||
int "IrDA UART BAUD"
|
||||
default 115200
|
||||
|
||||
config UART_IRDA_PARITY
|
||||
int "IrDA UART parity"
|
||||
default 0
|
||||
---help---
|
||||
IrDA UART parity. 0=None, 1=Odd, 2=Even. Default: None
|
||||
|
||||
config UART_IRDA_BITS
|
||||
int "IrDA UART number of bits"
|
||||
default 8
|
||||
---help---
|
||||
IrDA UART number of bits. Default: 8
|
||||
|
||||
config UART_IRDA_2STOP
|
||||
int "IrDA UART two stop bits"
|
||||
default 0
|
||||
---help---
|
||||
0=1 stop bit, 1=Two stop bits. Default: 1 stop bit
|
||||
|
||||
config UART_IRDA_RXBUFSIZE
|
||||
int "IrDA UART Rx buffer size"
|
||||
default 256
|
||||
---help---
|
||||
IrDA UART Rx buffer size. Default: 256
|
||||
|
||||
config UART_IRDA_TXBUFSIZE
|
||||
int "IrDA UART Tx buffer size"
|
||||
default 256
|
||||
---help---
|
||||
IrDA UART Tx buffer size. Default: 256
|
||||
|
||||
config UART_IRDA_HWFLOWCONTROL
|
||||
bool "Hardware flow control"
|
||||
default n
|
||||
---help---
|
||||
Enabled IrDA UART hardware flow control. Default: n
|
||||
|
||||
endmenu
|
||||
|
||||
choice
|
||||
prompt "Serial Console Selection"
|
||||
default SERIAL_CONSOLE_NONE
|
||||
depends on DEV_CONSOLE
|
||||
|
||||
# See drivers/Kconfig
|
||||
config USE_SERCOMM_CONSOLE
|
||||
bool "SERCOMM console"
|
||||
select SERCOMM_CONSOLE
|
||||
|
||||
config SERIAL_MODEM_CONSOLE
|
||||
bool "Serial console on modem UART"
|
||||
|
||||
config SERIAL_IRDA_CONSOLE
|
||||
bool "Serial console on IrDA UART"
|
||||
|
||||
config SERIAL_CONSOLE_NONE
|
||||
bool "No serial console"
|
||||
|
||||
endchoice
|
||||
@@ -1,71 +0,0 @@
|
||||
############################################################################
|
||||
# calypso/Make.defs
|
||||
#
|
||||
# Copyright (C) 2007, 2013-2015 Gregory Nutt. All rights reserved.
|
||||
# Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
#
|
||||
# Copyright (C) 2011 Stefan Richter. All rights reserved.
|
||||
# Author: Stefan Richter <ichgeh@l--putt.de>
|
||||
#
|
||||
# Redistribution and use in source and binary forms, with or without
|
||||
# modification, are permitted provided that the following conditions
|
||||
# are met:
|
||||
#
|
||||
# 1. Redistributions of source code must retain the above copyright
|
||||
# notice, this list of conditions and the following disclaimer.
|
||||
# 2. Redistributions in binary form must reproduce the above copyright
|
||||
# notice, this list of conditions and the following disclaimer in
|
||||
# the documentation and/or other materials provided with the
|
||||
# distribution.
|
||||
# 3. Neither the name Gregory Nutt nor the names of its contributors may be
|
||||
# used to endorse or promote products derived from this software
|
||||
# without specific prior written permission.
|
||||
#
|
||||
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
# POSSIBILITY OF SUCH DAMAGE.
|
||||
#
|
||||
############################################################################
|
||||
|
||||
HEAD_ASRC = calypso_head.S
|
||||
|
||||
CMN_ASRCS = up_saveusercontext.S up_fullcontextrestore.S up_vectors.S
|
||||
CMN_ASRCS += up_nommuhead.S vfork.S
|
||||
CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c up_copyfullstate.c
|
||||
CMN_CSRCS += up_createstack.c up_dataabort.c up_mdelay.c up_udelay.c
|
||||
CMN_CSRCS += up_doirq.c up_exit.c up_idle.c up_initialstate.c up_initialize.c
|
||||
CMN_CSRCS += up_interruptcontext.c up_prefetchabort.c up_releasepending.c
|
||||
CMN_CSRCS += up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c
|
||||
CMN_CSRCS += up_sigdeliver.c up_stackframe.c up_syscall.c up_unblocktask.c
|
||||
CMN_CSRCS += up_undefinedinsn.c up_usestack.c calypso_power.c up_vfork.c
|
||||
|
||||
ifeq ($(CONFIG_ELF),y)
|
||||
CMN_CSRCS += up_elf.c
|
||||
else ifeq ($(CONFIG_MODULE),y)
|
||||
CMN_CSRCS += up_elf.c
|
||||
endif
|
||||
|
||||
ifeq ($(CONFIG_STACK_COLORATION),y)
|
||||
CMN_CSRCS += up_checkstack.c
|
||||
endif
|
||||
|
||||
CHIP_ASRCS = calypso_lowputc.S
|
||||
CHIP_CSRCS = calypso_irq.c calypso_heap.c calypso_serial.c clock.c
|
||||
CHIP_CSRCS += calypso_uwire.c calypso_armio.c calypso_keypad.c
|
||||
|
||||
ifeq ($(CONFIG_SPI),y)
|
||||
CHIP_CSRCS += calypso_spi.c
|
||||
endif
|
||||
|
||||
ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
||||
CHIP_CSRCS += calypso_timer.c
|
||||
endif
|
||||
@@ -1,103 +0,0 @@
|
||||
/****************************************************************************
|
||||
* Driver for shared features of ARMIO modules
|
||||
*
|
||||
* Copyright (C) 2011 Stefan Richter. All rights reserved.
|
||||
* Author: Stefan Richter <ichgeh@l--putt.de>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/irq.h>
|
||||
|
||||
#include <arch/calypso/memory.h>
|
||||
#include <arch/calypso/armio.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
/****************************************************************************
|
||||
* HW access
|
||||
****************************************************************************/
|
||||
|
||||
#define BASE_ADDR_ARMIO 0xfffe4800
|
||||
#define ARMIO_REG(x) (BASE_ADDR_ARMIO + (x))
|
||||
|
||||
enum armio_reg {
|
||||
LATCH_IN = 0x00,
|
||||
LATCH_OUT = 0x02,
|
||||
IO_CNTL = 0x04,
|
||||
CNTL_REG = 0x06,
|
||||
LOAD_TIM = 0x08,
|
||||
KBR_LATCH_REG = 0x0a,
|
||||
KBC_REG = 0x0c,
|
||||
BUZZ_LIGHT_REG = 0x0e,
|
||||
LIGHT_LEVEL = 0x10,
|
||||
BUZZER_LEVEL = 0x12,
|
||||
GPIO_EVENT_MODE = 0x14,
|
||||
KBD_GPIO_INT = 0x16,
|
||||
KBD_GPIO_MASKIT = 0x18,
|
||||
GPIO_DEBOUNCING = 0x1a,
|
||||
GPIO_LATCH = 0x1c,
|
||||
};
|
||||
|
||||
#define KBD_INT (1 << 0)
|
||||
#define GPIO_INT (1 << 1)
|
||||
|
||||
/****************************************************************************
|
||||
* ARMIO interrupt handler
|
||||
* forward keypad events
|
||||
* forward GPIO events
|
||||
****************************************************************************/
|
||||
|
||||
static int kbd_gpio_irq(int irq, uint32_t *regs)
|
||||
{
|
||||
return calypso_kbd_irq(irq, regs);
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Initialize ARMIO
|
||||
****************************************************************************/
|
||||
|
||||
void calypso_armio(void)
|
||||
{
|
||||
/* Enable ARMIO clock */
|
||||
|
||||
putreg16(1 << 5, ARMIO_REG(CNTL_REG));
|
||||
|
||||
/* Mask GPIO interrupt and keypad interrupt */
|
||||
|
||||
putreg16(KBD_INT | GPIO_INT, ARMIO_REG(KBD_GPIO_MASKIT));
|
||||
|
||||
/* Attach and enable the interrupt */
|
||||
|
||||
irq_attach(IRQ_KEYPAD_GPIO, (xcpt_t)kbd_gpio_irq);
|
||||
up_enable_irq(IRQ_KEYPAD_GPIO);
|
||||
}
|
||||
@@ -1,23 +0,0 @@
|
||||
/* Place a branch to the real head at the entry point */
|
||||
.section .text.start
|
||||
b __start
|
||||
|
||||
|
||||
/* Exception Vectors like they are needed for the exception vector
|
||||
indirection of the internal boot ROM. The following section must
|
||||
be liked to appear at 0x80001c */
|
||||
.section .text.exceptions
|
||||
_undef_instr:
|
||||
b up_vectorundefinsn
|
||||
_sw_interr:
|
||||
b up_vectorswi
|
||||
_prefetch_abort:
|
||||
b up_vectorprefetch
|
||||
_data_abort:
|
||||
b up_vectordata
|
||||
_reserved:
|
||||
b _reserved
|
||||
_irq:
|
||||
b up_vectorirq
|
||||
_fiq:
|
||||
b up_vectorfiq
|
||||
@@ -1,357 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/calypso/calypso_irq.c
|
||||
* Driver for Calypso IRQ controller
|
||||
*
|
||||
* (C) 2010 by Harald Welte <laforge@gnumonks.org>
|
||||
* (C) 2011 by Stefan Richter <ichgeh@l--putt.de>
|
||||
*
|
||||
* This source code is derivated from Osmocom-BB project and was
|
||||
* relicensed as BSD with permission from original authors.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <arch/calypso/memory.h>
|
||||
#include <arch/calypso/clock.h>
|
||||
|
||||
#include "arm.h"
|
||||
#include "up_internal.h"
|
||||
#include "up_arch.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define BASE_ADDR_IRQ 0xfffffa00
|
||||
#define BASE_ADDR_IBOOT_EXC 0x0080001C
|
||||
|
||||
enum irq_reg
|
||||
{
|
||||
IT_REG1 = 0x00,
|
||||
IT_REG2 = 0x02,
|
||||
MASK_IT_REG1 = 0x08,
|
||||
MASK_IT_REG2 = 0x0a,
|
||||
IRQ_NUM = 0x10,
|
||||
FIQ_NUM = 0x12,
|
||||
IRQ_CTRL = 0x14,
|
||||
};
|
||||
|
||||
#define ILR_IRQ(x) (0x20 + (x*2))
|
||||
#define IRQ_REG(x) (BASE_ADDR_IRQ + (x))
|
||||
|
||||
#ifndef ARRAY_SIZE
|
||||
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Public Data
|
||||
****************************************************************************/
|
||||
|
||||
/* g_current_regs[] holds a references to the current interrupt level
|
||||
* register storage structure. If is non-NULL only during interrupt
|
||||
* processing. Access to g_current_regs[] must be through the macro
|
||||
* CURRENT_REGS for portability.
|
||||
*/
|
||||
|
||||
volatile uint32_t *g_current_regs[1];
|
||||
extern uint32_t _exceptions;
|
||||
|
||||
/****************************************************************************
|
||||
* Private Data
|
||||
****************************************************************************/
|
||||
|
||||
static uint8_t default_irq_prio[] =
|
||||
{
|
||||
[IRQ_WATCHDOG] = 0xff,
|
||||
[IRQ_TIMER1] = 0xff,
|
||||
[IRQ_TIMER2] = 0xff,
|
||||
[IRQ_TSP_RX] = 0,
|
||||
[IRQ_TPU_FRAME] = 3,
|
||||
[IRQ_TPU_PAGE] = 0xff,
|
||||
[IRQ_SIMCARD] = 0xff,
|
||||
[IRQ_UART_MODEM] = 8,
|
||||
[IRQ_KEYPAD_GPIO] = 4,
|
||||
[IRQ_RTC_TIMER] = 9,
|
||||
[IRQ_RTC_ALARM_I2C] = 10,
|
||||
[IRQ_ULPD_GAUGING] = 2,
|
||||
[IRQ_EXTERNAL] = 12,
|
||||
[IRQ_SPI] = 0xff,
|
||||
[IRQ_DMA] = 0xff,
|
||||
[IRQ_API] = 0xff,
|
||||
[IRQ_SIM_DETECT] = 0,
|
||||
[IRQ_EXTERNAL_FIQ] = 7,
|
||||
[IRQ_UART_IRDA] = 2,
|
||||
[IRQ_ULPD_GSM_TIMER] = 1,
|
||||
[IRQ_GEA] = 0xff,
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Private Functions
|
||||
****************************************************************************/
|
||||
|
||||
static void _irq_enable(enum irq_nr nr, int enable)
|
||||
{
|
||||
uintptr_t reg = IRQ_REG(MASK_IT_REG1);
|
||||
uint16_t val;
|
||||
|
||||
if (nr > 15)
|
||||
{
|
||||
reg = IRQ_REG(MASK_IT_REG2);
|
||||
nr -= 16;
|
||||
}
|
||||
|
||||
val = getreg16(reg);
|
||||
if (enable)
|
||||
{
|
||||
val &= ~(1 << nr);
|
||||
}
|
||||
else
|
||||
{
|
||||
val |= (1 << nr);
|
||||
}
|
||||
|
||||
putreg16(val, reg);
|
||||
}
|
||||
|
||||
static void set_default_priorities(void)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(default_irq_prio); i++)
|
||||
{
|
||||
uint16_t val;
|
||||
uint8_t prio = default_irq_prio[i];
|
||||
|
||||
if (prio > 31)
|
||||
{
|
||||
prio = 31;
|
||||
}
|
||||
|
||||
val = getreg16(IRQ_REG(ILR_IRQ(i)));
|
||||
val &= ~(0x1f << 2);
|
||||
val |= prio << 2;
|
||||
|
||||
/* Make edge mode default. Hopefully causes less trouble */
|
||||
|
||||
val |= 0x02;
|
||||
|
||||
putreg16(val, IRQ_REG(ILR_IRQ(i)));
|
||||
}
|
||||
}
|
||||
|
||||
/* Install the exception handlers to where the ROM loader jumps */
|
||||
|
||||
static void calypso_exceptions_install(void)
|
||||
{
|
||||
uint32_t *exceptions_dst = (uint32_t *) BASE_ADDR_IBOOT_EXC;
|
||||
uint32_t *exceptions_src = &_exceptions;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < 7; i++)
|
||||
{
|
||||
*exceptions_dst++ = *exceptions_src++;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_irqinitialize
|
||||
*
|
||||
* Description:
|
||||
* Setup the IRQ and FIQ controllers
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_irqinitialize(void)
|
||||
{
|
||||
/* Prepare hardware */
|
||||
|
||||
calypso_exceptions_install();
|
||||
CURRENT_REGS = NULL;
|
||||
|
||||
/* Switch to internal ROM */
|
||||
|
||||
calypso_bootrom(1);
|
||||
|
||||
/* Set default priorities */
|
||||
|
||||
set_default_priorities();
|
||||
|
||||
/* Mask all interrupts off */
|
||||
|
||||
putreg16(0xffff, IRQ_REG(MASK_IT_REG1));
|
||||
putreg16(0xffff, IRQ_REG(MASK_IT_REG2));
|
||||
|
||||
/* clear all pending interrupts */
|
||||
putreg16(0, IRQ_REG(IT_REG1));
|
||||
putreg16(0, IRQ_REG(IT_REG2));
|
||||
|
||||
/* Enable interrupts globally to the ARM core */
|
||||
|
||||
#ifndef CONFIG_SUPPRESS_INTERRUPTS
|
||||
up_irq_restore(SVC_MODE | PSR_F_BIT);
|
||||
#endif
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_disable_irq
|
||||
*
|
||||
* Description:
|
||||
* Disable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_disable_irq(int irq)
|
||||
{
|
||||
if ((unsigned)irq < NR_IRQS)
|
||||
{
|
||||
_irq_enable(irq, 0);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_enable_irq
|
||||
*
|
||||
* Description:
|
||||
* Enable the IRQ specified by 'irq'
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_enable_irq(int irq)
|
||||
{
|
||||
if ((unsigned)irq < NR_IRQS)
|
||||
{
|
||||
_irq_enable(irq, 1);
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: up_prioritize_irq
|
||||
*
|
||||
* Description:
|
||||
* Set the priority of an IRQ.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef CONFIG_ARCH_IRQPRIO
|
||||
int up_prioritize_irq(int nr, int prio)
|
||||
{
|
||||
uint16_t val;
|
||||
|
||||
if (prio == -1)
|
||||
{
|
||||
prio = default_irq_prio[nr];
|
||||
}
|
||||
|
||||
if (prio > 31)
|
||||
{
|
||||
prio = 31;
|
||||
}
|
||||
|
||||
val = prio << 2;
|
||||
putreg16(val, IRQ_REG(ILR_IRQ(nr)));
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Entry point for interrupts
|
||||
****************************************************************************/
|
||||
|
||||
void up_decodeirq(uint32_t *regs)
|
||||
{
|
||||
uint8_t num, tmp;
|
||||
uint32_t *saved_regs;
|
||||
|
||||
/* XXX: What is this???
|
||||
* Passed to but ignored in IRQ handlers
|
||||
* Only valid meaning is apparently non-NULL == IRQ context */
|
||||
|
||||
saved_regs = (uint32_t *)CURRENT_REGS;
|
||||
CURRENT_REGS = regs;
|
||||
|
||||
/* Detect & deliver the IRQ */
|
||||
|
||||
num = getreg8(IRQ_REG(IRQ_NUM)) & 0x1f;
|
||||
irq_dispatch(num, regs);
|
||||
|
||||
/* Start new IRQ agreement */
|
||||
|
||||
tmp = getreg8(IRQ_REG(IRQ_CTRL));
|
||||
tmp |= 0x01;
|
||||
putreg8(tmp, IRQ_REG(IRQ_CTRL));
|
||||
|
||||
CURRENT_REGS = saved_regs;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Entry point for FIQs
|
||||
****************************************************************************/
|
||||
|
||||
void calypso_fiq(void)
|
||||
{
|
||||
uint8_t num, tmp;
|
||||
uint32_t *regs;
|
||||
|
||||
/* XXX: What is this???
|
||||
* Passed to but ignored in IRQ handlers
|
||||
* Only valid meaning is apparently non-NULL == IRQ context */
|
||||
|
||||
regs = (uint32_t *)CURRENT_REGS;
|
||||
CURRENT_REGS = (uint32_t *)#
|
||||
|
||||
/* Detect & deliver like an IRQ but we are in FIQ context */
|
||||
|
||||
num = getreg8(IRQ_REG(FIQ_NUM)) & 0x1f;
|
||||
irq_dispatch(num, regs);
|
||||
|
||||
/* Start new FIQ agreement */
|
||||
|
||||
tmp = getreg8(IRQ_REG(IRQ_CTRL));
|
||||
tmp |= 0x02;
|
||||
putreg8(tmp, IRQ_REG(IRQ_CTRL));
|
||||
|
||||
CURRENT_REGS = regs;
|
||||
}
|
||||
@@ -1,385 +0,0 @@
|
||||
/****************************************************************************
|
||||
* Driver for Calypso keypad hardware
|
||||
*
|
||||
* Copyright (C) 2011 Stefan Richter. All rights reserved.
|
||||
* Author: Stefan Richter <ichgeh@l--putt.de>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <nuttx/arch.h>
|
||||
#include <nuttx/semaphore.h>
|
||||
#include <nuttx/irq.h>
|
||||
#include <nuttx/fs/fs.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <semaphore.h>
|
||||
#include <errno.h>
|
||||
#include <unistd.h>
|
||||
#include <sched.h>
|
||||
|
||||
#include <arch/calypso/defines.h>
|
||||
#include <arch/calypso/memory.h>
|
||||
#include <arch/calypso/timer.h>
|
||||
#include <arch/calypso/armio.h>
|
||||
|
||||
/****************************************************************************
|
||||
* HW access
|
||||
****************************************************************************/
|
||||
|
||||
#define BASE_ADDR_ARMIO 0xfffe4800
|
||||
#define ARMIO_REG(x) ((void *)BASE_ADDR_ARMIO + (x))
|
||||
|
||||
enum armio_reg
|
||||
{
|
||||
LATCH_IN = 0x00,
|
||||
LATCH_OUT = 0x02,
|
||||
IO_CNTL = 0x04,
|
||||
CNTL_REG = 0x06,
|
||||
LOAD_TIM = 0x08,
|
||||
KBR_LATCH_REG = 0x0a,
|
||||
KBC_REG = 0x0c,
|
||||
BUZZ_LIGHT_REG = 0x0e,
|
||||
LIGHT_LEVEL = 0x10,
|
||||
BUZZER_LEVEL = 0x12,
|
||||
GPIO_EVENT_MODE = 0x14,
|
||||
KBD_GPIO_INT = 0x16,
|
||||
KBD_GPIO_MASKIT = 0x18,
|
||||
GPIO_DEBOUNCING = 0x1a,
|
||||
GPIO_LATCH = 0x1c,
|
||||
};
|
||||
|
||||
#define KBD_INT (1 << 0)
|
||||
#define GPIO_INT (1 << 1)
|
||||
|
||||
/****************************************************************************
|
||||
* Decoder functions for matrix and power button
|
||||
****************************************************************************/
|
||||
|
||||
static int btn_dec(uint32_t * btn_state, uint8_t col, uint8_t reg,
|
||||
char *buf, size_t buflen, size_t * len)
|
||||
{
|
||||
uint8_t diff = (*btn_state ^ reg) & 0x1f;
|
||||
|
||||
while (diff)
|
||||
{
|
||||
uint8_t val = diff & ~(diff - 1);
|
||||
uint8_t sc = val >> 1;
|
||||
sc |= sc << 2;
|
||||
sc += col;
|
||||
sc += (sc & 0x20) ? 0x26 : 0x3f;
|
||||
|
||||
if (reg & val)
|
||||
{
|
||||
sc |= 0x20;
|
||||
}
|
||||
|
||||
/* Check for space in buffer and dispatch */
|
||||
|
||||
if (*len < buflen)
|
||||
{
|
||||
buf[(*len)++] = sc;
|
||||
}
|
||||
else
|
||||
{
|
||||
break;
|
||||
}
|
||||
|
||||
/* Only change diff if dispatched/buffer not full */
|
||||
|
||||
diff ^= val;
|
||||
}
|
||||
|
||||
/* Store new state of the buttons (but only if they where dispatch) */
|
||||
|
||||
*btn_state >>= 5;
|
||||
#ifdef INCLUDE_ALL_COLS
|
||||
*btn_state |= (reg ^ diff) << 20;
|
||||
#else
|
||||
*btn_state |= (reg ^ diff) << 15;
|
||||
#endif
|
||||
return diff;
|
||||
}
|
||||
|
||||
static int pwr_btn_dec(uint32_t * state, uint8_t reg, char *buf, size_t * len)
|
||||
{
|
||||
if (reg)
|
||||
{
|
||||
/* Check for pressed power button. If pressed, ignore other
|
||||
* buttons since it collides with an entire row.
|
||||
*/
|
||||
|
||||
if (~*state & 0x80000000)
|
||||
{
|
||||
buf[0] = 'z';
|
||||
*len = 1;
|
||||
*state |= 0x80000000;
|
||||
}
|
||||
|
||||
return 1; /* break loop in caller */
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Check for released power button. */
|
||||
|
||||
if (*state & 0x80000000)
|
||||
{
|
||||
buf[0] = 'Z';
|
||||
*len = 1;
|
||||
|
||||
*state &= 0x7fffffff;
|
||||
|
||||
/* Don't scan others when released; might trigger
|
||||
* false keystrokes otherwise
|
||||
*/
|
||||
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
|
||||
return 0; /* Continue with other columns */
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Keypad: Fileops Prototypes and Structures
|
||||
****************************************************************************/
|
||||
|
||||
typedef FAR struct file file_t;
|
||||
|
||||
static int keypad_open(file_t * filep);
|
||||
static int keypad_close(file_t * filep);
|
||||
static ssize_t keypad_read(file_t * filep, FAR char *buffer, size_t buflen);
|
||||
#ifndef CONFIG_DISABLE_POLL
|
||||
static int keypad_poll(file_t * filep, FAR struct pollfd *fds, bool setup);
|
||||
#endif
|
||||
|
||||
static const struct file_operations keypad_ops =
|
||||
{
|
||||
keypad_open, /* open */
|
||||
keypad_close, /* close */
|
||||
keypad_read, /* read */
|
||||
0, /* write */
|
||||
0, /* seek */
|
||||
0, /* ioctl */
|
||||
#ifndef CONFIG_DISABLE_POLL
|
||||
keypad_poll /* poll */
|
||||
#endif
|
||||
};
|
||||
|
||||
static sem_t kbdsem;
|
||||
|
||||
/****************************************************************************
|
||||
* Keypad: Fileops
|
||||
****************************************************************************/
|
||||
|
||||
static int keypad_open(file_t * filep)
|
||||
{
|
||||
register uint16_t reg;
|
||||
|
||||
/* Unmask keypad interrupt */
|
||||
|
||||
reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
|
||||
writew(reg & ~KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
static int keypad_close(file_t * filep)
|
||||
{
|
||||
register uint16_t reg;
|
||||
|
||||
/* Mask keypad interrupt */
|
||||
|
||||
reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
|
||||
writew(reg | KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
static ssize_t keypad_read(file_t * filep, FAR char *buf, size_t buflen)
|
||||
{
|
||||
static uint32_t btn_state = 0;
|
||||
register uint16_t reg;
|
||||
uint16_t col, col_mask;
|
||||
size_t len = 0;
|
||||
|
||||
if (buf == NULL || buflen < 1)
|
||||
{
|
||||
/* Well... nothing to do */
|
||||
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
retry:
|
||||
col = 1;
|
||||
col_mask = 0x1e;
|
||||
|
||||
if (!btn_state)
|
||||
{
|
||||
/* Drive all cols low such that all buttons cause events */
|
||||
|
||||
writew(0, ARMIO_REG(KBC_REG));
|
||||
|
||||
/* No button currently pressed, use IRQ */
|
||||
|
||||
reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
|
||||
writew(reg & ~KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
|
||||
sem_wait(&kbdsem);
|
||||
}
|
||||
else
|
||||
{
|
||||
writew(0x1f, ARMIO_REG(KBC_REG));
|
||||
usleep(80000);
|
||||
}
|
||||
|
||||
/* Scan columns */
|
||||
|
||||
#ifdef INCLUDE_ALL_COLS
|
||||
while (col <= 6)
|
||||
{
|
||||
#else
|
||||
while (col <= 5)
|
||||
{
|
||||
#endif
|
||||
/* Read keypad latch and immediately set new column since
|
||||
* synchronization takes about 5usec. For the 1st round, the
|
||||
* interrupt has prepared this and the context switch takes
|
||||
* long enough to serve as a delay.
|
||||
*/
|
||||
|
||||
reg = readw(ARMIO_REG(KBR_LATCH_REG));
|
||||
writew(col_mask, ARMIO_REG(KBC_REG));
|
||||
|
||||
/* Turn pressed buttons into 1s */
|
||||
|
||||
reg = 0x1f & ~reg;
|
||||
|
||||
if (col == 1)
|
||||
{
|
||||
/* Power/End switch */
|
||||
|
||||
if (pwr_btn_dec(&btn_state, reg, buf, &len))
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Non-power switches */
|
||||
|
||||
if (btn_dec(&btn_state, col, reg, buf, buflen, &len))
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Select next column and respective mask */
|
||||
|
||||
col_mask = 0x1f & ~(1 << col++);
|
||||
|
||||
/* We have to wait for synchronization of the inputs. The
|
||||
* processing is too fast if no/few buttons are processed.
|
||||
*/
|
||||
|
||||
usleep(5);
|
||||
|
||||
/* XXX: usleep seems to suffer hugh overhead. Better this!?
|
||||
* If nothing else can be done, it's overhead still wastes
|
||||
* time 'usefully'.
|
||||
*/
|
||||
/* sched_yield(); up_udelay(2); */
|
||||
}
|
||||
|
||||
/* If we don't have anything to return, retry to avoid EOF */
|
||||
|
||||
if (!len)
|
||||
{
|
||||
goto retry;
|
||||
}
|
||||
|
||||
return len;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Keypad interrupt handler
|
||||
* mask interrupts
|
||||
* prepare column drivers for scan
|
||||
* posts keypad semaphore
|
||||
****************************************************************************/
|
||||
|
||||
int calypso_kbd_irq(int irq, uint32_t * regs)
|
||||
{
|
||||
register uint16_t reg;
|
||||
|
||||
/* Mask keypad interrupt */
|
||||
|
||||
reg = readw(ARMIO_REG(KBD_GPIO_MASKIT));
|
||||
writew(reg | KBD_INT, ARMIO_REG(KBD_GPIO_MASKIT));
|
||||
|
||||
/* Turn off column drivers */
|
||||
|
||||
writew(0x1f, ARMIO_REG(KBC_REG));
|
||||
|
||||
/* Let the userspace know */
|
||||
|
||||
sem_post(&kbdsem);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Initialize device, add /dev/... nodes
|
||||
****************************************************************************/
|
||||
|
||||
void up_keypad(void)
|
||||
{
|
||||
/* kbssem semaphore helps leaving IRQ ctx as soon as possible. This
|
||||
* semaphore is used for signaling and, hence, should not have priority
|
||||
* inheritance enabled.
|
||||
*/
|
||||
|
||||
sem_init(&kbdsem, 0, 0);
|
||||
sem_setprotocol(&kbdsem, SEM_PRIO_NONE);
|
||||
|
||||
/* Drive cols low in idle state such that all buttons cause events */
|
||||
|
||||
writew(0, ARMIO_REG(KBC_REG));
|
||||
|
||||
(void)register_driver("/dev/keypad", &keypad_ops, 0444, NULL);
|
||||
}
|
||||
|
||||
int keypad_kbdinit(void)
|
||||
{
|
||||
calypso_armio();
|
||||
up_keypad();
|
||||
|
||||
return OK;
|
||||
}
|
||||
@@ -1,50 +0,0 @@
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdio.h>
|
||||
|
||||
#include <nuttx/board.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
|
||||
#include "calypso_spi.h"
|
||||
|
||||
/****************************************************************************
|
||||
* Name: board_power_off
|
||||
*
|
||||
* Description:
|
||||
* Power off the board.
|
||||
*
|
||||
* If this function returns, then it was not possible to power-off the
|
||||
* board due to some other constraints.
|
||||
*
|
||||
* Input Parameters:
|
||||
* status - Status information provided with the power off event.
|
||||
*
|
||||
* Returned Value:
|
||||
* If this function returns, then it was not possible to power-off the
|
||||
* board due to some constraints. The return value int this case is a
|
||||
* board-specific reason for the failure to shutdown.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifdef CONFIG_BOARDCTL_POWEROFF
|
||||
int board_power_off(int status)
|
||||
{
|
||||
struct spi_dev_s *spi = calypso_spibus_initialize(0);
|
||||
uint16_t tx;
|
||||
|
||||
SPI_SETBITS(spi, 16);
|
||||
(void)SPI_HWFEATURES(spi, 0);
|
||||
|
||||
tx = (1 << 6) | (1 << 1);
|
||||
SPI_SNDBLOCK(spi, &tx, 1);
|
||||
|
||||
tx = (1 << 6) | (30 << 1);
|
||||
SPI_SNDBLOCK(spi, &tx, 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,314 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/calypso/calypso_spi.c
|
||||
* SPI driver for TI Calypso
|
||||
*
|
||||
* Copyright (C) 2010 Harald Welte <laforge@gnumonks.org>
|
||||
* Copyright (C) 2011 Stefan Richter <ichgeh@l--putt.de>
|
||||
*
|
||||
* Part of this source code is derivated from Osmocom-BB project and was
|
||||
* relicensed as BSD with permission from original authors.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include <nuttx/spi/spi.h>
|
||||
|
||||
#include <unistd.h>
|
||||
#include <semaphore.h>
|
||||
#include <debug.h>
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
#include "calypso_spi.h"
|
||||
|
||||
#warning "MOST OF SPI API IS INCOMPLETE! (Wrapper around Osmocom driver)"
|
||||
extern void spi_init(void);
|
||||
extern int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din);
|
||||
|
||||
#ifndef CONFIG_SPI_EXCHANGE
|
||||
#error "Calypso HW only supports exchange. Enable CONFIG_SPI_EXCHANGE!"
|
||||
#endif
|
||||
|
||||
struct calypso_spidev_s
|
||||
{
|
||||
struct spi_dev_s spidev; /* External driver interface */
|
||||
int nbits; /* Number of transfered bits */
|
||||
sem_t exclsem; /* Supports mutually exclusive access */
|
||||
};
|
||||
|
||||
static int spi_lock(FAR struct spi_dev_s *dev, bool lock)
|
||||
{
|
||||
struct calypso_spidev_s *priv = (struct calypso_spidev_s *)dev;
|
||||
|
||||
if (lock)
|
||||
{
|
||||
/* Take the semaphore (perhaps waiting) */
|
||||
|
||||
while (sem_wait(&priv->exclsem) != 0)
|
||||
{
|
||||
/* The only case that an error should occur here is if the wait
|
||||
* was awakened by a signal.
|
||||
*/
|
||||
|
||||
DEBUGASSERT(errno == EINTR);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
(void)sem_post(&priv->exclsem);
|
||||
}
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/* STUBS! */
|
||||
|
||||
static void spi_select(FAR struct spi_dev_s *dev, enum spi_dev_e devid,
|
||||
bool selected)
|
||||
{
|
||||
}
|
||||
|
||||
static uint32_t spi_setfrequency(FAR struct spi_dev_s *dev, uint32_t frequency)
|
||||
{
|
||||
return frequency;
|
||||
}
|
||||
|
||||
static void spi_setmode(FAR struct spi_dev_s *dev, enum spi_mode_e mode)
|
||||
{
|
||||
}
|
||||
|
||||
/* Osmocom wrapper */
|
||||
|
||||
static void spi_setbits(FAR struct spi_dev_s *dev, int nbits)
|
||||
{
|
||||
((FAR struct calypso_spidev_s *)dev)->nbits = nbits;
|
||||
}
|
||||
|
||||
static void spi_exchange(FAR struct spi_dev_s *dev, FAR const void *txbuffer,
|
||||
FAR void *rxbuffer, size_t nwords)
|
||||
{
|
||||
FAR struct calypso_spidev_s *priv = (FAR struct calypso_spidev_s *)dev;
|
||||
size_t i;
|
||||
|
||||
for (i = 0; i < nwords; i++)
|
||||
{
|
||||
spi_xfer(0, priv->nbits, txbuffer + i, rxbuffer + i);
|
||||
}
|
||||
}
|
||||
|
||||
static uint16_t spi_send(FAR struct spi_dev_s *dev, uint16_t wd)
|
||||
{
|
||||
uint16_t buf = wd;
|
||||
spi_exchange(dev, &buf, &buf, 1);
|
||||
return buf;
|
||||
}
|
||||
|
||||
static const struct spi_ops_s g_spiops =
|
||||
{
|
||||
.lock = spi_lock,
|
||||
.select = spi_select,
|
||||
.setfrequency = spi_setfrequency,
|
||||
.setmode = spi_setmode,
|
||||
.setbits = spi_setbits,
|
||||
#ifdef CONFIG_SPI_HWFEATURES
|
||||
.hwfeatures = 0,
|
||||
#endif
|
||||
.status = 0,
|
||||
#ifdef CONFIG_SPI_CMDDATA
|
||||
.cmddata = 0,
|
||||
#endif
|
||||
.send = spi_send,
|
||||
#ifdef CONFIG_SPI_EXCHANGE
|
||||
.exchange = spi_exchange,
|
||||
#else
|
||||
.sndblock = spi_sndblock,
|
||||
.recvblock = spi_recvblock,
|
||||
#endif
|
||||
.registercallback = 0,
|
||||
};
|
||||
|
||||
static struct calypso_spidev_s g_spidev =
|
||||
{
|
||||
.spidev = { &g_spiops },
|
||||
.nbits = 0,
|
||||
.exclsem = SEM_INITIALIZER(1)
|
||||
};
|
||||
|
||||
void spi_init(void)
|
||||
{
|
||||
putreg16(SPI_SET1_EN_CLK | SPI_SET1_WR_IRQ_DIS | SPI_SET1_RDWR_IRQ_DIS,
|
||||
SPI_REG(REG_SET1));
|
||||
|
||||
putreg16(0x0001, SPI_REG(REG_SET2));
|
||||
}
|
||||
|
||||
int spi_xfer(uint8_t dev_idx, uint8_t bitlen, const void *dout, void *din)
|
||||
{
|
||||
uint8_t bytes_per_xfer;
|
||||
uint8_t reg_status, reg_ctrl = 0;
|
||||
uint32_t tmp;
|
||||
|
||||
if (bitlen == 0)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
if (bitlen > 32)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (dev_idx > 4)
|
||||
{
|
||||
return -1;
|
||||
}
|
||||
|
||||
bytes_per_xfer = bitlen / 8;
|
||||
if (bitlen % 8)
|
||||
{
|
||||
bytes_per_xfer ++;
|
||||
}
|
||||
|
||||
reg_ctrl |= (bitlen - 1) << SPI_CTRL_NB_SHIFT;
|
||||
reg_ctrl |= (dev_idx & 0x7) << SPI_CTRL_AD_SHIFT;
|
||||
|
||||
if (bitlen <= 8)
|
||||
{
|
||||
tmp = *(uint8_t *)dout;
|
||||
tmp <<= 24 + (8-bitlen); /* align to MSB */
|
||||
}
|
||||
else if (bitlen <= 16)
|
||||
{
|
||||
tmp = *(uint16_t *)dout;
|
||||
tmp <<= 16 + (16-bitlen); /* align to MSB */
|
||||
}
|
||||
else
|
||||
{
|
||||
tmp = *(uint32_t *)dout;
|
||||
tmp <<= (32-bitlen); /* align to MSB */
|
||||
}
|
||||
|
||||
spiinfo("spi_xfer(dev_idx=%u, bitlen=%u, data_out=0x%08x): ",
|
||||
dev_idx, bitlen, tmp);
|
||||
|
||||
/* fill transmit registers */
|
||||
|
||||
putreg16(tmp >> 16, SPI_REG(REG_TX_MSB));
|
||||
putreg16(tmp & 0xffff, SPI_REG(REG_TX_LSB));
|
||||
|
||||
/* initiate transfer */
|
||||
|
||||
if (din)
|
||||
{
|
||||
reg_ctrl |= SPI_CTRL_RDWR;
|
||||
}
|
||||
else
|
||||
{
|
||||
reg_ctrl |= SPI_CTRL_WR;
|
||||
}
|
||||
|
||||
putreg16(reg_ctrl, SPI_REG(REG_CTRL));
|
||||
spiinfo("reg_ctrl=0x%04x ", reg_ctrl);
|
||||
|
||||
/* wait until the transfer is complete */
|
||||
|
||||
while (1)
|
||||
{
|
||||
reg_status = getreg16(SPI_REG(REG_STATUS));
|
||||
spiinfo("status=0x%04x ", reg_status);
|
||||
if (din && (reg_status & SPI_STATUS_RE))
|
||||
{
|
||||
break;
|
||||
}
|
||||
else if (reg_status & SPI_STATUS_WE)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* FIXME: calibrate how much delay we really need (seven 13MHz cycles) */
|
||||
|
||||
usleep(1000);
|
||||
|
||||
if (din)
|
||||
{
|
||||
tmp = getreg16(SPI_REG(REG_RX_MSB)) << 16;
|
||||
tmp |= getreg16(SPI_REG(REG_RX_LSB));
|
||||
spiinfo("data_in=0x%08x ", tmp);
|
||||
|
||||
if (bitlen <= 8)
|
||||
{
|
||||
*(uint8_t *)din = tmp & 0xff;
|
||||
}
|
||||
else if (bitlen <= 16)
|
||||
{
|
||||
*(uint16_t *)din = tmp & 0xffff;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(uint32_t *)din = tmp;
|
||||
}
|
||||
}
|
||||
|
||||
spiinfo("\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Name: calypso_spibus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SPI port
|
||||
*
|
||||
* Input Parameter:
|
||||
* Port number (for hardware that has mutiple SPI interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on succcess; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct spi_dev_s *calypso_spibus_initialize(int port)
|
||||
{
|
||||
switch (port)
|
||||
{
|
||||
case 0: /* SPI master device */
|
||||
spi_init();
|
||||
return (FAR struct spi_dev_s *)&g_spidev;
|
||||
|
||||
case 1: /* uWire device */
|
||||
return NULL;
|
||||
|
||||
default:
|
||||
return NULL;
|
||||
}
|
||||
}
|
||||
@@ -1,59 +0,0 @@
|
||||
#ifndef ___ARCH_ARM_SRC_CALYPSO_CALYPSO_SPI_H
|
||||
#define ___ARCH_ARM_SRC_CALYPSO_CALYPSO_SPI_H
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
#define BASE_ADDR_SPI 0xfffe3000
|
||||
#define SPI_REG(n) (BASE_ADDR_SPI+(n))
|
||||
|
||||
#define SPI_SET1_EN_CLK (1 << 0)
|
||||
#define SPI_SET1_WR_IRQ_DIS (1 << 4)
|
||||
#define SPI_SET1_RDWR_IRQ_DIS (1 << 5)
|
||||
|
||||
#define SPI_CTRL_RDWR (1 << 0)
|
||||
#define SPI_CTRL_WR (1 << 1)
|
||||
#define SPI_CTRL_NB_SHIFT 2
|
||||
#define SPI_CTRL_AD_SHIFT 7
|
||||
|
||||
#define SPI_STATUS_RE (1 << 0) /* Read End */
|
||||
#define SPI_STATUS_WE (1 << 1) /* Write End */
|
||||
|
||||
/****************************************************************************
|
||||
* Public Types
|
||||
****************************************************************************/
|
||||
|
||||
enum spi_regs
|
||||
{
|
||||
REG_SET1 = 0x00,
|
||||
REG_SET2 = 0x02,
|
||||
REG_CTRL = 0x04,
|
||||
REG_STATUS = 0x06,
|
||||
REG_TX_LSB = 0x08,
|
||||
REG_TX_MSB = 0x0a,
|
||||
REG_RX_LSB = 0x0c,
|
||||
REG_RX_MSB = 0x0e,
|
||||
};
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Name: calypso_spibus_initialize
|
||||
*
|
||||
* Description:
|
||||
* Initialize the selected SPI port
|
||||
*
|
||||
* Input Parameter:
|
||||
* Port number (for hardware that has mutiple SPI interfaces)
|
||||
*
|
||||
* Returned Value:
|
||||
* Valid SPI device structure reference on succcess; a NULL on failure
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
FAR struct spi_dev_s *calypso_spibus_initialize(int port);
|
||||
|
||||
#endif /* ___ARCH_ARM_SRC_CALYPSO_CALYPSO_SPI_H */
|
||||
@@ -1,227 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/calypso/calypso_timer.c
|
||||
* Calypso DBB internal Timer Driver
|
||||
*
|
||||
* (C) 2010 by Harald Welte <laforge@gnumonks.org>
|
||||
* (C) 2011 by Stefan Richter <ichgeh@l--putt.de>
|
||||
*
|
||||
* This source code is derivated from Osmocom-BB project and was
|
||||
* relicensed as BSD with permission from original authors.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <stdio.h>
|
||||
#include <stdint.h>
|
||||
#include <nuttx/arch.h>
|
||||
|
||||
#include <arch/calypso/defines.h>
|
||||
#include <arch/calypso/memory.h>
|
||||
#include <arch/calypso/timer.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#define BASE_ADDR_TIMER 0xfffe3800
|
||||
#define TIMER2_OFFSET 0x3000
|
||||
|
||||
#define TIMER_REG(n, m) (((n)-1) ? (BASE_ADDR_TIMER + TIMER2_OFFSET + (m)) : (BASE_ADDR_TIMER + (m)))
|
||||
|
||||
enum timer_reg
|
||||
{
|
||||
CNTL_TIMER = 0x00,
|
||||
LOAD_TIMER = 0x02,
|
||||
READ_TIMER = 0x04,
|
||||
};
|
||||
|
||||
enum timer_ctl
|
||||
{
|
||||
CNTL_START = (1 << 0),
|
||||
CNTL_AUTO_RELOAD = (1 << 1),
|
||||
CNTL_CLOCK_ENABLE = (1 << 5),
|
||||
};
|
||||
|
||||
/* Regular Timers (1 and 2) */
|
||||
|
||||
void hwtimer_enable(int num, int on)
|
||||
{
|
||||
uint8_t ctl;
|
||||
|
||||
if (num < 1 || num > 2)
|
||||
{
|
||||
printf("Unknown timer %d\n", num);
|
||||
return;
|
||||
}
|
||||
|
||||
ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
|
||||
if (on)
|
||||
{
|
||||
ctl |= CNTL_START | CNTL_CLOCK_ENABLE;
|
||||
}
|
||||
else
|
||||
{
|
||||
ctl &= ~CNTL_START;
|
||||
}
|
||||
|
||||
putreg8(ctl, TIMER_REG(num, CNTL_TIMER));
|
||||
}
|
||||
|
||||
void hwtimer_config(int num, uint8_t pre_scale, int auto_reload)
|
||||
{
|
||||
uint8_t ctl;
|
||||
|
||||
ctl = (pre_scale & 0x7) << 2;
|
||||
if (auto_reload)
|
||||
ctl |= CNTL_AUTO_RELOAD;
|
||||
|
||||
putreg8(ctl, TIMER_REG(num, CNTL_TIMER));
|
||||
}
|
||||
|
||||
void hwtimer_load(int num, uint16_t val)
|
||||
{
|
||||
putreg16(val, TIMER_REG(num, LOAD_TIMER));
|
||||
}
|
||||
|
||||
uint16_t hwtimer_read(int num)
|
||||
{
|
||||
uint8_t ctl = getreg8(TIMER_REG(num, CNTL_TIMER));
|
||||
|
||||
/* Somehow a read results in an abort */
|
||||
|
||||
if ((ctl & (CNTL_START | CNTL_CLOCK_ENABLE)) != (CNTL_START | CNTL_CLOCK_ENABLE))
|
||||
{
|
||||
return 0xffff;
|
||||
}
|
||||
|
||||
return getreg16(TIMER_REG(num, READ_TIMER));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Watchdog Timer
|
||||
****************************************************************************/
|
||||
|
||||
#define BASE_ADDR_WDOG 0xfffff800
|
||||
#define WDOG_REG(m) (BASE_ADDR_WDOG + m)
|
||||
|
||||
enum wdog_reg
|
||||
{
|
||||
WD_CNTL_TIMER = CNTL_TIMER,
|
||||
WD_LOAD_TIMER = LOAD_TIMER,
|
||||
WD_READ_TIMER = 0x02,
|
||||
WD_MODE = 0x04,
|
||||
};
|
||||
|
||||
enum wdog_ctl
|
||||
{
|
||||
WD_CTL_START = (1 << 7),
|
||||
WD_CTL_AUTO_RELOAD = (1 << 8)
|
||||
};
|
||||
|
||||
enum wdog_mode
|
||||
{
|
||||
WD_MODE_DIS_ARM = 0xF5,
|
||||
WD_MODE_DIS_CONFIRM = 0xA0,
|
||||
WD_MODE_ENABLE = (1 << 15)
|
||||
};
|
||||
|
||||
#define WD_CTL_PRESCALE(value) (((value)&0x07) << 9)
|
||||
|
||||
static void wdog_irq(__unused enum irq_nr nr)
|
||||
{
|
||||
puts("=> WATCHDOG\n");
|
||||
}
|
||||
|
||||
void wdog_enable(int on)
|
||||
{
|
||||
if (!on)
|
||||
{
|
||||
putreg16(WD_MODE_DIS_ARM, WDOG_REG(WD_MODE));
|
||||
putreg16(WD_MODE_DIS_CONFIRM, WDOG_REG(WD_MODE));
|
||||
}
|
||||
}
|
||||
|
||||
void wdog_reset(void)
|
||||
{
|
||||
/* Enable watchdog */
|
||||
|
||||
putreg16(WD_MODE_ENABLE, WDOG_REG(WD_MODE));
|
||||
|
||||
/* Force expiration */
|
||||
|
||||
putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
|
||||
putreg16(0x0000, WDOG_REG(WD_LOAD_TIMER));
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Public Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timerisr
|
||||
*
|
||||
* Description:
|
||||
* The timer ISR will perform a variety of services for
|
||||
* various portions of the systems.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
int up_timerisr(int irq, uint32_t *regs)
|
||||
{
|
||||
/* Process timer interrupt */
|
||||
|
||||
sched_process_timer();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************
|
||||
* Function: up_timer_initialize
|
||||
*
|
||||
* Description:
|
||||
* Setup Calypso HW timer 2 to cause system ticks.
|
||||
*
|
||||
* This function is called during start-up to initialize
|
||||
* the timer interrupt.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
void up_timer_initialize(void)
|
||||
{
|
||||
up_disable_irq(IRQ_SYSTIMER);
|
||||
|
||||
/* The timer runs at 13MHz / 32, i.e. 406.25kHz */
|
||||
/* 4062 ticks until expiry yields 100Hz interrupt */
|
||||
|
||||
hwtimer_load(2, 4062);
|
||||
hwtimer_config(2, 0, 1);
|
||||
hwtimer_enable(2, 1);
|
||||
|
||||
/* Attach and enable the timer interrupt */
|
||||
|
||||
irq_attach(IRQ_SYSTIMER, (xcpt_t)up_timerisr);
|
||||
up_enable_irq(IRQ_SYSTIMER);
|
||||
}
|
||||
@@ -1,161 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/calypso/calypso_uwire.c
|
||||
* Driver for Calypso uWire Master Controller
|
||||
*
|
||||
* (C) 2010 by Sylvain Munaut <tnt@246tNt.com>
|
||||
*
|
||||
* This source code is derivated from Osmocom-BB project and was
|
||||
* relicensed as BSD with permission from original authors.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
#include <debug.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#define BASE_ADDR_UWIRE 0xfffe4000
|
||||
#define UWIRE_REG(n) (BASE_ADDR_UWIRE+(n))
|
||||
|
||||
enum uwire_regs
|
||||
{
|
||||
REG_DATA = 0x00,
|
||||
REG_CSR = 0x02,
|
||||
REG_SR1 = 0x04,
|
||||
REG_SR2 = 0x06,
|
||||
REG_SR3 = 0x08,
|
||||
};
|
||||
|
||||
#define UWIRE_CSR_BITS_RD(n) (((n) & 0x1f) << 0)
|
||||
#define UWIRE_CSR_BITS_WR(n) (((n) & 0x1f) << 5)
|
||||
#define UWIRE_CSR_IDX(n) (((n) & 3) << 10)
|
||||
#define UWIRE_CSR_CS_CMD (1 << 12)
|
||||
#define UWIRE_CSR_START (1 << 13)
|
||||
#define UWIRE_CSR_CSRB (1 << 14)
|
||||
#define UWIRE_CSR_RDRB (1 << 15)
|
||||
|
||||
#define UWIRE_CSn_EDGE_RD (1 << 0) /* 1=falling 0=rising */
|
||||
#define UWIRE_CSn_EDGE_WR (1 << 1) /* 1=falling 0=rising */
|
||||
#define UWIRE_CSn_CS_LVL (1 << 2)
|
||||
#define UWIRE_CSn_FRQ_DIV2 (0 << 3)
|
||||
#define UWIRE_CSn_FRQ_DIV4 (1 << 3)
|
||||
#define UWIRE_CSn_FRQ_DIV8 (2 << 3)
|
||||
#define UWIRE_CSn_CKH
|
||||
|
||||
#define UWIRE_CSn_SHIFT(n) (((n) & 1) ? 6 : 0)
|
||||
#define UWIRE_CSn_REG(n) (((n) & 2) ? REG_SR2 : REG_SR1)
|
||||
|
||||
#define UWIRE_SR3_CLK_EN (1 << 0)
|
||||
#define UWIRE_SR3_CLK_DIV2 (0 << 1)
|
||||
#define UWIRE_SR3_CLK_DIV4 (1 << 1)
|
||||
#define UWIRE_SR3_CLK_DIV7 (2 << 1)
|
||||
#define UWIRE_SR3_CLK_DIV10 (3 << 1)
|
||||
|
||||
static inline void _uwire_wait(int mask, int val)
|
||||
{
|
||||
while ((getreg16(UWIRE_REG(REG_CSR)) & mask) != val);
|
||||
}
|
||||
|
||||
void uwire_init(void)
|
||||
{
|
||||
putreg16(UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2, UWIRE_REG(REG_SR3));
|
||||
|
||||
/* FIXME only init CS0 for now */
|
||||
|
||||
putreg16(((UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2) << UWIRE_CSn_SHIFT(0)),
|
||||
UWIRE_REG(UWIRE_CSn_REG(0)));
|
||||
putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
|
||||
_uwire_wait(UWIRE_CSR_CSRB, 0);
|
||||
}
|
||||
|
||||
int uwire_xfer(int cs, int bitlen, const void *dout, void *din)
|
||||
{
|
||||
uint16_t tmp = 0;
|
||||
|
||||
if (bitlen <= 0 || bitlen > 16)
|
||||
return -1;
|
||||
|
||||
if (cs < 0 || cs > 4)
|
||||
return -1;
|
||||
|
||||
/* FIXME uwire_init always selects CS0 for now */
|
||||
|
||||
_info("uwire_xfer(dev_idx=%u, bitlen=%u\n", cs, bitlen);
|
||||
|
||||
/* select the chip */
|
||||
|
||||
putreg16(UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD, UWIRE_REG(REG_CSR));
|
||||
_uwire_wait(UWIRE_CSR_CSRB, 0);
|
||||
|
||||
if (dout)
|
||||
{
|
||||
if (bitlen <= 8)
|
||||
tmp = *(uint8_t *)dout;
|
||||
else if (bitlen <= 16)
|
||||
tmp = *(uint16_t *)dout;
|
||||
|
||||
tmp <<= 16 - bitlen; /* align to MSB */
|
||||
putreg16(tmp, UWIRE_REG(REG_DATA));
|
||||
_info(", data_out=0x%04hx", tmp);
|
||||
}
|
||||
|
||||
tmp = (dout ? UWIRE_CSR_BITS_WR(bitlen) : 0) |
|
||||
(din ? UWIRE_CSR_BITS_RD(bitlen) : 0) |
|
||||
UWIRE_CSR_START;
|
||||
putreg16(tmp, UWIRE_REG(REG_CSR));
|
||||
_uwire_wait(UWIRE_CSR_CSRB, 0);
|
||||
|
||||
if (din)
|
||||
{
|
||||
_uwire_wait(UWIRE_CSR_RDRB, UWIRE_CSR_RDRB);
|
||||
|
||||
tmp = getreg16(UWIRE_REG(REG_DATA));
|
||||
_info(", data_in=0x%08x", tmp);
|
||||
|
||||
if (bitlen <= 8)
|
||||
*(uint8_t *)din = tmp & 0xff;
|
||||
else if (bitlen <= 16)
|
||||
*(uint16_t *)din = tmp & 0xffff;
|
||||
}
|
||||
|
||||
/* unselect the chip */
|
||||
|
||||
putreg16(UWIRE_CSR_IDX(0) | 0, UWIRE_REG(REG_CSR));
|
||||
_uwire_wait(UWIRE_CSR_CSRB, 0);
|
||||
|
||||
_info(")\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
@@ -1,211 +0,0 @@
|
||||
/****************************************************************************
|
||||
* calypso/chip.h
|
||||
*
|
||||
* Copyright (C) 2011 Stefan Richter. All rights reserved.
|
||||
* Author: Stefan Richter <ichgeh@l--putt.de>
|
||||
*
|
||||
* based on: c5471/chip.h
|
||||
* Copyright (C) 2007 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name Gregory Nutt nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_CALYPSO_CHIP_H
|
||||
#define __ARCH_ARM_SRC_CALYPSO_CHIP_H
|
||||
|
||||
/****************************************************************************
|
||||
* Included Files
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Pre-processor Definitions
|
||||
****************************************************************************/
|
||||
|
||||
/* UARTs ********************************************************************/
|
||||
|
||||
#define UART_IRDA_BASE 0xffff5000
|
||||
#define UART_MODEM_BASE 0xffff5800
|
||||
#define UART_UIR 0xffff6000
|
||||
#define UARTn_IO_RANGE 0x00000800
|
||||
|
||||
/* Common UART Registers. Expressed as offsets from the BASE address */
|
||||
|
||||
#define UART_RHR_OFFS 0x00000000 /* Rcv Holding Register */
|
||||
#define UART_THR_OFFS 0x00000000 /* Xmit Holding Register */
|
||||
#define UART_FCR_OFFS 0x00000002 /* FIFO Control Register */
|
||||
#define UART_RFCR_OFFS 0x00000002 /* Rcv FIFO Control Register */
|
||||
#define UART_TFCR_OFFS 0x00000002 /* Xmit FIFO Control Register */
|
||||
#define UART_SCR_OFFS 0x00000010 /* Status Control Register */
|
||||
#define UART_LCR_OFFS 0x00000003 /* Line Control Register */
|
||||
#define UART_LSR_OFFS 0x00000005 /* Line Status Register */
|
||||
#define UART_SSR_OFFS 0x00000011 /* Supplementary Status Register */
|
||||
#define UART_MCR_OFFS 0x00000004 /* Modem Control Register */
|
||||
#define UART_MSR_OFFS 0x00000006 /* Modem Status Register */
|
||||
#define UART_IER_OFFS 0x00000001 /* Interrupt Enable Register */
|
||||
#define UART_ISR_OFFS 0x00000002 /* Interrupt Status Register */
|
||||
#define UART_EFR_OFFS 0x00000002 /* Enhanced Feature Register */
|
||||
#define UART_XON1_OFFS 0x00000004 /* XON1 Character Register */
|
||||
#define UART_XON2_OFFS 0x00000005 /* XON2 Character Register */
|
||||
#define UART_XOFF1_OFFS 0x00000006 /* XOFF1 Character Register */
|
||||
#define UART_XOFF2_OFFS 0x00000007 /* XOFF2 Character Register */
|
||||
#define UART_SPR_OFFS 0x00000007 /* Scratch-pad Register */
|
||||
#define UART_DIV_LOW_OFFS 0x00000000 /* Divisor for baud generation */
|
||||
#define UART_DIV_HIGH_OFFS 0x00000001
|
||||
#define UART_TCR_OFFS 0x00000006 /* Transmission Control Register */
|
||||
#define UART_TLR_OFFS 0x00000007 /* Trigger Level Register */
|
||||
#define UART_MDR_OFFS 0x00000008 /* Mode Definition Register */
|
||||
|
||||
/* UART Settings ************************************************************/
|
||||
|
||||
/* Miscellaneous UART settings. */
|
||||
|
||||
#define UART_REGISTER_BITS 8
|
||||
#define UART_IRQ_MODEM IRQ_UART_MODEM
|
||||
#define UART_IRQ_IRDA IRQ_UART_IRDA
|
||||
|
||||
#define UART_RX_FIFO_NOEMPTY 0x00000001
|
||||
#define UART_SSR_TXFULL 0x00000001
|
||||
#define UART_LSR_TREF 0x00000020
|
||||
|
||||
#define UART_XMIT_FIFO_SIZE 64
|
||||
#define UART_IRDA_XMIT_FIFO_SIZE 64
|
||||
|
||||
/* UART_LCR Register */
|
||||
/* Bits 31-7: Reserved */
|
||||
#define UART_LCR_BOC 0x00000040 /* Bit 6: Break Control */
|
||||
/* Bit 5: Parity Type 2 */
|
||||
#define UART_LCR_PAREVEN 0x00000010 /* Bit 4: Parity Type 1 */
|
||||
#define UART_LCR_PARODD 0x00000000
|
||||
#define UART_LCR_PARMARK 0x00000010
|
||||
#define UART_LCR_PARSPACE 0x00000011
|
||||
#define UART_LCR_PAREN 0x00000008 /* Bit 3: Paity Enable */
|
||||
#define UART_LCR_PARDIS 0x00000000
|
||||
#define UART_LCR_2STOP 0x00000004 /* Bit 2: Number of stop bits */
|
||||
#define UART_LCR_1STOP 0x00000000
|
||||
#define UART_LCR_5BITS 0x00000000 /* Bits 0-1: Word-length */
|
||||
#define UART_LCR_6BITS 0x00000001
|
||||
#define UART_LCR_7BITS 0x00000002
|
||||
#define UART_LCR_8BITS 0x00000003
|
||||
|
||||
#define UART_FCR_FTL 0x000000f0
|
||||
#define UART_FCR_FIFO_EN 0x00000001
|
||||
#define UART_FCR_TX_CLR 0x00000002
|
||||
#define UART_FCR_RX_CLR 0x00000004
|
||||
|
||||
#define UART_IER_RECVINT 0x00000001
|
||||
#define UART_IER_XMITINT 0x00000002
|
||||
#define UART_IER_LINESTSINT 0x00000004
|
||||
#define UART_IER_MODEMSTSINT 0x00000008 /* IrDA UART only */
|
||||
#define UART_IER_XOFFINT 0x00000020
|
||||
#define UART_IER_RTSINT 0x00000040 /* IrDA UART only */
|
||||
#define UART_IER_CTSINT 0x00000080 /* IrDA UART only */
|
||||
#define UART_IER_INTMASK 0x000000ff
|
||||
|
||||
#define BAUD_115200 0x00000007
|
||||
#define BAUD_57600 0x00000014
|
||||
#define BAUD_38400 0x00000021
|
||||
#define BAUD_19200 0x00000006
|
||||
#define BAUD_9600 0x0000000C
|
||||
#define BAUD_4800 0x00000018
|
||||
#define BAUD_2400 0x00000030
|
||||
#define BAUD_1200 0x00000060
|
||||
|
||||
#define MDR_UART_MODE 0x00000000 /* Both IrDA and Modem UARTs */
|
||||
#define MDR_SIR_MODE 0x00000001 /* IrDA UART only */
|
||||
#define MDR_AUTOBAUDING_MODE 0x00000002 /* Modem UART only */
|
||||
#define MDR_RESET_MODE 0x00000007 /* Both IrDA and Modem UARTs */
|
||||
|
||||
/* SPI **********************************************************************/
|
||||
|
||||
#define MAX_SPI 3
|
||||
|
||||
#define SPI_REGISTER_BASE 0xffff2000
|
||||
|
||||
/* ARMIO ********************************************************************/
|
||||
/* Timers / Watchdog ********************************************************/
|
||||
|
||||
#define C5471_TIMER0_CTRL 0xffff2a00
|
||||
#define C5471_TIMER0_CNT 0xffff2a04
|
||||
#define C5471_TIMER1_CTRL 0xffff2b00
|
||||
#define C5471_TIMER1_CNT 0xffff2b04
|
||||
#define C5471_TIMER2_CTRL 0xffff2c00
|
||||
#define C5471_TIMER2_CNT 0xffff2c04
|
||||
|
||||
/* Interrupts ***************************************************************/
|
||||
|
||||
#define HAVE_SRC_IRQ_BIN_REG 0
|
||||
|
||||
#define INT_FIRST_IO 0xffff2d00
|
||||
#define INT_IO_RANGE 0x5C
|
||||
|
||||
#define IT_REG 0xffff2d00
|
||||
#define MASK_IT_REG 0xffff2d04
|
||||
#define SRC_IRQ_REG 0xffff2d08
|
||||
#define SRC_FIQ_REG 0xffff2d0c
|
||||
#define SRC_IRQ_BIN_REG 0xffff2d10
|
||||
#define INT_CTRL_REG 0xffff2d18
|
||||
|
||||
#define ILR_IRQ0_REG 0xffff2d1C /* 0-Timer 0 */
|
||||
#define ILR_IRQ1_REG 0xffff2d20 /* 1-Timer 1 */
|
||||
#define ILR_IRQ2_REG 0xffff2d24 /* 2-Timer 2 */
|
||||
#define ILR_IRQ3_REG 0xffff2d28 /* 3-GPIO0 */
|
||||
#define ILR_IRQ4_REG 0xffff2d2c /* 4-Ethernet */
|
||||
#define ILR_IRQ5_REG 0xffff2d30 /* 5-KBGPIO[7:0] */
|
||||
#define ILR_IRQ6_REG 0xffff2d34 /* 6-Uart serial */
|
||||
#define ILR_IRQ7_REG 0xffff2d38 /* 7-Uart IRDA */
|
||||
#define ILR_IRQ8_REG 0xffff2d3c /* 8-KBGPIO[15:8] */
|
||||
#define ILR_IRQ9_REG 0xffff2d40 /* 9-GPIO3 */
|
||||
#define ILR_IRQ10_REG 0xffff2d44 /* 10-GPIO2 */
|
||||
#define ILR_IRQ11_REG 0xffff2d48 /* 11-I2C */
|
||||
#define ILR_IRQ12_REG 0xffff2d4c /* 12-GPIO1 */
|
||||
#define ILR_IRQ13_REG 0xffff2d50 /* 13-SPI */
|
||||
#define ILR_IRQ14_REG 0xffff2d54 /* 14-GPIO[19:4] */
|
||||
#define ILR_IRQ15_REG 0xffff2d58 /* 15-API */
|
||||
|
||||
/* CLKM *********************************************************************/
|
||||
|
||||
#define CLKM 0xffff2f00
|
||||
#define CLKM_CTL_RST 0xffff2f10
|
||||
#define CLKM_RESET 0xffff2f18
|
||||
|
||||
#define CLKM_RESET_EIM 0x00000008
|
||||
#define CLKM_EIM_CLK_STOP 0x00000010
|
||||
#define CLKM_CTL_RST_LEAD_RESET 0x00000000
|
||||
#define CLKM_CTL_RST_EXT_RESET 0x00000002
|
||||
|
||||
/****************************************************************************
|
||||
* Inline Functions
|
||||
****************************************************************************/
|
||||
|
||||
/****************************************************************************
|
||||
* Public Function Prototypes
|
||||
****************************************************************************/
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_CALYPSO_CHIP_H */
|
||||
@@ -1,230 +0,0 @@
|
||||
/****************************************************************************
|
||||
* arch/arm/src/calypso/clock.c
|
||||
* Driver for Calypso clock management
|
||||
*
|
||||
* (C) 2010 by Harald Welte <laforge@gnumonks.org>
|
||||
*
|
||||
* This source code is derivated from Osmocom-BB project and was
|
||||
* relicensed as BSD with permission from original authors.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdio.h>
|
||||
|
||||
//#define DEBUG
|
||||
#include <arch/calypso/debug.h>
|
||||
|
||||
#include <arch/calypso/memory.h>
|
||||
#include <arch/calypso/clock.h>
|
||||
|
||||
#include "up_arch.h"
|
||||
|
||||
#define REG_DPLL 0xffff9800
|
||||
#define DPLL_LOCK (1 << 0)
|
||||
#define DPLL_BREAKLN (1 << 1)
|
||||
#define DPLL_BYPASS_DIV_SHIFT 2 /* 2 bits */
|
||||
#define DPLL_PLL_ENABLE (1 << 4)
|
||||
#define DPLL_PLL_DIV_SHIFT 5 /* 2 bits */
|
||||
#define DPLL_PLL_MULT_SHIFT 7 /* 5 bits */
|
||||
#define DPLL_TEST (1 << 12)
|
||||
#define DPLL_IOB (1 << 13) /* Initialize on break */
|
||||
#define DPLL_IAI (1 << 14) /* Initialize after Idle */
|
||||
|
||||
#define BASE_ADDR_CLKM 0xfffffd00
|
||||
#define CLKM_REG(m) (BASE_ADDR_CLKM+(m))
|
||||
|
||||
enum clkm_reg
|
||||
{
|
||||
CNTL_ARM_CLK = 0,
|
||||
CNTL_CLK = 2,
|
||||
CNTL_RST = 4,
|
||||
CNTL_ARM_DIV = 8,
|
||||
};
|
||||
|
||||
/* CNTL_ARM_CLK */
|
||||
|
||||
#define ARM_CLK_BIG_SLEEP (1 << 0) /* MCU Master Clock enabled? */
|
||||
#define ARM_CLK_CLKIN_SEL0 (1 << 1) /* MCU source clock (0 = DPLL output, 1 = VTCXO or CLKIN */
|
||||
#define ARM_CLK_CLKIN_SEL (1 << 2) /* 0 = VTCXO or 1 = CLKIN */
|
||||
#define ARM_CLK_MCLK_DIV5 (1 << 3) /* enable 1.5 or 2.5 division factor */
|
||||
#define ARM_CLK_MCLK_DIV_SHIFT 4 /* 3 bits */
|
||||
#define ARM_CLK_DEEP_POWER_SHIFT 8
|
||||
#define ARM_CLK_DEEP_SLEEP 12
|
||||
|
||||
/* CNTL_CLK */
|
||||
#define CLK_IRQ_CLK_DIS (1 << 0) /* IRQ clock control (0 always, 1 according ARM_MCLK_EN) */
|
||||
#define CLK_BRIDGE_CLK_DIS (1 << 1)
|
||||
#define CLK_TIMER_CLK_DIS (1 << 2)
|
||||
#define CLK_DPLL_DIS (1 << 3) /* 0: DPLL is not stopped during SLEEP */
|
||||
#define CLK_CLKOUT_EN (1 << 4) /* Enable CLKOUT output pins */
|
||||
#define CLK_EN_IDLE3_FLG (1 << 5) /* DSP idle flag control (1 =
|
||||
* SAM/HOM register forced to HOM when DSP IDLE3) */
|
||||
#define CLK_VCLKOUT_DIV2 (1 << 6) /* 1: VCLKOUT-FR is divided by 2 */
|
||||
#define CLK_VTCXO_DIV2 (1 << 7) /* 1: VTCXO is dividied by 2 */
|
||||
|
||||
#define BASE_ADDR_MEMIF 0xfffffb00
|
||||
#define MEMIF_REG(x) (BASE_ADDR_MEMIF+(x))
|
||||
|
||||
enum memif_reg
|
||||
{
|
||||
API_RHEA_CTL = 0x0e,
|
||||
EXTRA_CONF = 0x10,
|
||||
};
|
||||
|
||||
static void dump_reg16(uint32_t addr, char *name)
|
||||
{
|
||||
printf("%s=0x%04x\n", name, getreg16(addr));
|
||||
}
|
||||
|
||||
void calypso_clk_dump(void)
|
||||
{
|
||||
dump_reg16(REG_DPLL, "REG_DPLL");
|
||||
dump_reg16(CLKM_REG(CNTL_ARM_CLK), "CNTL_ARM_CLK");
|
||||
dump_reg16(CLKM_REG(CNTL_CLK), "CNTL_CLK");
|
||||
dump_reg16(CLKM_REG(CNTL_RST), "CNTL_RST");
|
||||
dump_reg16(CLKM_REG(CNTL_ARM_DIV), "CNTL_ARM_DIV");
|
||||
}
|
||||
|
||||
void calypso_pll_set(uint16_t inp)
|
||||
{
|
||||
uint8_t mult = inp >> 8;
|
||||
uint8_t div = inp & 0xff;
|
||||
uint16_t reg = getreg16(REG_DPLL);
|
||||
|
||||
reg &= ~0x0fe0;
|
||||
reg |= (div & 0x3) << DPLL_PLL_DIV_SHIFT;
|
||||
reg |= (mult & 0x1f) << DPLL_PLL_MULT_SHIFT;
|
||||
reg |= DPLL_PLL_ENABLE;
|
||||
|
||||
putreg16(reg, REG_DPLL);
|
||||
}
|
||||
|
||||
void calypso_reset_set(enum calypso_rst calypso_rst, int active)
|
||||
{
|
||||
uint8_t reg = getreg8(CLKM_REG(CNTL_RST));
|
||||
|
||||
if (active)
|
||||
reg |= calypso_rst;
|
||||
else
|
||||
reg &= ~calypso_rst;
|
||||
|
||||
putreg8(reg, CLKM_REG(CNTL_RST));
|
||||
}
|
||||
|
||||
int calypso_reset_get(enum calypso_rst calypso_rst)
|
||||
{
|
||||
uint8_t reg = getreg8(CLKM_REG(CNTL_RST));
|
||||
|
||||
if (reg & calypso_rst)
|
||||
return 1;
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
||||
void calypso_clock_set(uint8_t vtcxo_div2, uint16_t inp, enum mclk_div mclk_div)
|
||||
{
|
||||
uint16_t cntl_clock = getreg16(CLKM_REG(CNTL_CLK));
|
||||
uint16_t cntl_arm_clk = getreg16(CLKM_REG(CNTL_ARM_CLK));
|
||||
|
||||
/* First set the vtcxo_div2 */
|
||||
|
||||
cntl_clock &= ~CLK_VCLKOUT_DIV2;
|
||||
if (vtcxo_div2)
|
||||
cntl_clock |= CLK_VTCXO_DIV2;
|
||||
else
|
||||
cntl_clock &= ~CLK_VTCXO_DIV2;
|
||||
|
||||
putreg16(cntl_clock, CLKM_REG(CNTL_CLK));
|
||||
|
||||
/* Then configure the MCLK divider */
|
||||
|
||||
cntl_arm_clk &= ~ARM_CLK_CLKIN_SEL0;
|
||||
if (mclk_div & 0x80)
|
||||
{
|
||||
mclk_div &= ~0x80;
|
||||
cntl_arm_clk |= ARM_CLK_MCLK_DIV5;
|
||||
}
|
||||
else
|
||||
cntl_arm_clk &= ~ARM_CLK_MCLK_DIV5;
|
||||
|
||||
cntl_arm_clk &= ~(0x7 << ARM_CLK_MCLK_DIV_SHIFT);
|
||||
cntl_arm_clk |= (mclk_div << ARM_CLK_MCLK_DIV_SHIFT);
|
||||
putreg16(cntl_arm_clk, CLKM_REG(CNTL_ARM_CLK));
|
||||
|
||||
/* Then finally set the PLL */
|
||||
|
||||
calypso_pll_set(inp);
|
||||
}
|
||||
|
||||
void calypso_mem_cfg(enum calypso_bank bank, uint8_t ws,
|
||||
enum calypso_mem_width width, int we)
|
||||
{
|
||||
putreg16((ws & 0x1f) | ((width & 3) << 5) | ((we & 1) << 7),
|
||||
BASE_ADDR_MEMIF + bank);
|
||||
}
|
||||
|
||||
void calypso_bootrom(int enable)
|
||||
{
|
||||
uint16_t conf = getreg16(MEMIF_REG(EXTRA_CONF));
|
||||
|
||||
conf |= (3 << 8);
|
||||
|
||||
if (enable)
|
||||
conf &= ~(1 << 9);
|
||||
|
||||
putreg16(conf, MEMIF_REG(EXTRA_CONF));
|
||||
}
|
||||
|
||||
void calypso_debugunit(int enable)
|
||||
{
|
||||
uint16_t conf = getreg16(MEMIF_REG(EXTRA_CONF));
|
||||
|
||||
if (enable)
|
||||
conf &= ~(1 << 11);
|
||||
else
|
||||
conf |= (1 << 11);
|
||||
|
||||
putreg16(conf, MEMIF_REG(EXTRA_CONF));
|
||||
}
|
||||
|
||||
#define REG_RHEA_CNTL 0xfffff900
|
||||
#define REG_API_CNTL 0xfffff902
|
||||
#define REG_ARM_RHEA 0xfffff904
|
||||
|
||||
void calypso_rhea_cfg(uint8_t fac0, uint8_t fac1, uint8_t timeout,
|
||||
uint8_t ws_h, uint8_t ws_l, uint8_t w_en0, uint8_t w_en1)
|
||||
{
|
||||
putreg16(fac0 | (fac1 << 4) | (timeout << 8), REG_RHEA_CNTL);
|
||||
putreg16(ws_h | (ws_l << 5), REG_API_CNTL);
|
||||
putreg16(w_en0 | (w_en1 << 1), REG_ARM_RHEA);
|
||||
}
|
||||
@@ -191,11 +191,6 @@
|
||||
# define _DATA_INIT &_eronly
|
||||
# define _START_DATA &_sdata
|
||||
# define _END_DATA &_edata
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
# define _START_NOCACHE &_snocache
|
||||
# define _END_NOCACHE &_enocache
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* This is the value used to mark the stack for subsequent stack monitoring
|
||||
@@ -284,11 +279,6 @@ EXTERN uint32_t _edata; /* End+1 of .data */
|
||||
EXTERN uint32_t _sbss; /* Start of .bss */
|
||||
EXTERN uint32_t _ebss; /* End+1 of .bss */
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
EXTERN uint32_t _snocache; /* Start of .nocache */
|
||||
EXTERN uint32_t _enocache; /* End+1 of .nocache */
|
||||
#endif
|
||||
|
||||
/* Sometimes, functions must be executed from RAM. In this case, the following
|
||||
* macro may be used (with GCC!) to specify a function that will execute from
|
||||
* RAM. For example,
|
||||
|
||||
@@ -281,7 +281,8 @@ static void efm32_leuart_setbaud(uintptr_t base, uint32_t baud)
|
||||
|
||||
void efm32_lowsetup(void)
|
||||
{
|
||||
#if defined(HAVE_UART_DEVICE) || defined(HAVE_LEUART_DEVICE)
|
||||
#if defined(HAVE_UART_DEVICE) || defined(HAVE_LEUART_DEVICE) || \
|
||||
defined(HAVE_SPI_DEVICE)
|
||||
uint32_t regval;
|
||||
#endif
|
||||
|
||||
|
||||
@@ -126,9 +126,7 @@
|
||||
* address in the top-level memory map are candidates for other mapping uses:
|
||||
*
|
||||
* 00018000-000fffff Reserved -- Not used
|
||||
* 00400000-007fffff Reserved -- Used as the virtual address an inter-CPU,
|
||||
* un-cached memory region in SMP
|
||||
* configurations
|
||||
* 00400000-007fffff Reserved -- Not used
|
||||
* 00d00000-00ffffff Reserved -- Not used
|
||||
* 0220c000-023fffff Reserved -- Not used
|
||||
* 80000000-efffffff Reserved -- Level 2 page table (See below)
|
||||
@@ -929,8 +927,6 @@
|
||||
* the address space.
|
||||
*/
|
||||
|
||||
#define INTERCPU_L2_PAGES 1 /* Pages allowed for inter-processor communications */
|
||||
|
||||
#ifndef CONFIG_ARCH_LOWVECTORS
|
||||
/* Memory map
|
||||
* VIRTUAL ADDRESS RANGE L1 PG TABLE L2 PG TABLE DESCRIPTION
|
||||
@@ -938,10 +934,6 @@
|
||||
* ---------- ---------- ------------ ----------------------------
|
||||
* 0x80000000 0x803fffff 0x000002000 0x000000400 Vectors (1MiB)
|
||||
* 0x80100000 0x806fffff 0x000002400 0x000001800 Paging (6MiB)
|
||||
*
|
||||
* If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES
|
||||
* pages are taken from the end of the Paging L2 page table to hold non-
|
||||
* cacheable, inter-processor communication data.
|
||||
*/
|
||||
|
||||
/* Vector L2 page table offset/size */
|
||||
@@ -959,18 +951,10 @@
|
||||
# define VECTOR_L2_END_PADDR (VECTOR_L2_PBASE + VECTOR_L2_SIZE)
|
||||
# define VECTOR_L2_END_VADDR (VECTOR_L2_VBASE + VECTOR_L2_SIZE)
|
||||
|
||||
# if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED)
|
||||
/* Paging L2 page table offset/size */
|
||||
/* Paging L2 page table offset/size */
|
||||
|
||||
# define PGTABLE_L2_OFFSET 0x000002400
|
||||
# define PGTABLE_L2_SIZE 0x000001400
|
||||
|
||||
# else
|
||||
/* Paging L2 page table offset/size */
|
||||
|
||||
# define PGTABLE_L2_OFFSET 0x000002400
|
||||
# define PGTABLE_L2_SIZE 0x000001800
|
||||
# endif
|
||||
# define PGTABLE_L2_OFFSET 0x000002400
|
||||
# define PGTABLE_L2_SIZE 0x000001800
|
||||
|
||||
#else
|
||||
/* Memory map
|
||||
@@ -978,24 +962,12 @@
|
||||
* START END OFFSET SIZE
|
||||
* ---------- ---------- ------------ ----------------------------
|
||||
* 0x80000000 0x806fffff 0x000002000 0x000001c00 Paging (7MiB)
|
||||
*
|
||||
* If SMP is enabled, then 1MiB of address spaces for the INTERCPU_L2_PAGES
|
||||
* pages are taken from the end of the Paging L2 page table to hold non-
|
||||
* cacheable, inter-processor communication data.
|
||||
*/
|
||||
|
||||
# if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED)
|
||||
/* Paging L2 page table offset/size */
|
||||
|
||||
# define PGTABLE_L2_OFFSET 0x000002000
|
||||
# define PGTABLE_L2_SIZE 0x000001800
|
||||
|
||||
# else
|
||||
/* Paging L2 page table offset/size */
|
||||
|
||||
# define PGTABLE_L2_OFFSET 0x000002000
|
||||
# define PGTABLE_L2_SIZE 0x000001c00
|
||||
# endif
|
||||
# define PGTABLE_L2_OFFSET 0x000002000
|
||||
# define PGTABLE_L2_SIZE 0x000001c00
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1013,23 +985,6 @@
|
||||
#define PGTABLE_L2_END_PADDR (PGTABLE_L2_PBASE + PGTABLE_L2_SIZE)
|
||||
#define PGTABLE_L2_END_VADDR (PGTABLE_L2_VBASE + PGTABLE_L2_SIZE)
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED)
|
||||
/* Non-cached inter-processor communication data */
|
||||
|
||||
# define INTERCPU_L2_OFFSET (PGTABLE_L2_OFFSET + PGTABLE_L2_SIZE)
|
||||
# define INTERCPU_L2_SIZE (0x00000400)
|
||||
|
||||
/* Non-cached inter-processor communication page table base addresses */
|
||||
|
||||
# define INTERCPU_L2_PBASE (PGTABLE_BASE_PADDR + INTERCPU_L2_OFFSET)
|
||||
# define INTERCPU_L2_VBASE (PGTABLE_BASE_VADDR + INTERCPU_L2_OFFSET)
|
||||
|
||||
/* Non-cached inter-processor communication end addresses */
|
||||
|
||||
# define INTERCPU_L2_END_PADDR (INTERCPU_L2_PBASE + INTERCPU_L2_SIZE)
|
||||
# define INTERCPU_L2_END_VADDR (INTERCPU_L2_VBASE + INTERCPU_L2_SIZE)
|
||||
#endif
|
||||
|
||||
/* Base address of the interrupt vector table.
|
||||
*
|
||||
* IMX_VECTOR_PADDR - Unmapped, physical address of vector table in SRAM
|
||||
@@ -1052,8 +1007,7 @@
|
||||
* START END CONTENT
|
||||
* ---------- ---------- ---------------------------
|
||||
* 0x00000000 0x00010000 Vectors (VECTOR_TABLE_SIZE)
|
||||
* 0x00010000 0x00011000 Inter-CPU communications
|
||||
* 0x00011000 0x0003c000 Unused
|
||||
* 0x00010000 0x0003c000 Unused
|
||||
* 0x0003c000 0x00004000 Page table (PGTABLE_SIZE)
|
||||
*/
|
||||
|
||||
@@ -1061,27 +1015,13 @@
|
||||
# define IMX_VECTOR_VSRAM IMX_OCRAM_VBASE
|
||||
# define IMX_VECTOR_VADDR 0x00000000
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED)
|
||||
/* Inter-processor communications.
|
||||
*
|
||||
* NOTICE that we use the unused virtual address space at 0x00400000 for
|
||||
* the inter-CPU virtual communication area.
|
||||
*/
|
||||
|
||||
# define INTERCPU_PADDR (IMX_VECTOR_PADDR + VECTOR_TABLE_SIZE)
|
||||
# define INTERCPU_VADDR (0x00400000)
|
||||
# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12)
|
||||
# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM + VECTOR_TABLE_SIZE)
|
||||
#endif
|
||||
|
||||
#else /* Vectors located at 0xffff:0000 -- this probably does not work */
|
||||
/* OCRAM Memory Map:
|
||||
* ---------- ---------- ---------------------------
|
||||
* START END CONTENT
|
||||
* ---------- ---------- ---------------------------
|
||||
* 0x00000000 0x00004000 Page table (PGTABLE_SIZE)
|
||||
* 0x00004000 0x0002f000 Unused
|
||||
* 0x0002f000 0x00030000 Inter-CPU communications
|
||||
* 0x00004000 0x00030000 Unused
|
||||
* 0x00030000 0x00010000 Vectors (VECTOR_TABLE_SIZE)
|
||||
*/
|
||||
|
||||
@@ -1089,18 +1029,6 @@
|
||||
# define IMX_VECTOR_VSRAM (IMX_OCRAM_VBASE + IMX_OCRAM_SIZE - VECTOR_TABLE_SIZE)
|
||||
# define IMX_VECTOR_VADDR 0xffff0000
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED)
|
||||
/* Inter-processor communications
|
||||
*
|
||||
* NOTICE that we use the unused virtual address space at 0x00400000 for
|
||||
* the inter-CPU virtual communication area.
|
||||
*/
|
||||
|
||||
# define INTERCPU_PADDR (IMX_VECTOR_PADDR - INTERCPU_L2_SIZE)
|
||||
# define INTERCPU_VADDR (0x00400000)
|
||||
# define INTERCPU_SIZE (INTERCPU_L2_PAGES << 12)
|
||||
# define INTERCPU_VSRAM (IMX_VECTOR_VSRAM - INTERCPU_L2_SIZE)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/************************************************************************************
|
||||
|
||||
@@ -235,48 +235,6 @@ static void imx_vectormapping(void)
|
||||
# define imx_vectormapping()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx_intercpu_mapping
|
||||
*
|
||||
* Description:
|
||||
* Setup a special mapping for the non-cached, inter-cpu communications
|
||||
* area.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED)
|
||||
static void imx_intercpu_mapping(void)
|
||||
{
|
||||
uint32_t intercpu_paddr = INTERCPU_PADDR & PTE_SMALL_PADDR_MASK;
|
||||
uint32_t intercpu_vaddr = INTERCPU_VADDR & PTE_SMALL_PADDR_MASK;
|
||||
uint32_t end_paddr = INTERCPU_PADDR + INTERCPU_SIZE;
|
||||
|
||||
DEBUGASSERT(intercpu_vaddr == (uint32_t)&_snocache);
|
||||
|
||||
/* We want to keep the inter-cpu region in on-chip RAM (OCRAM). The
|
||||
* i.MX6 has 256Kb of OCRAM positioned at physical address 0x0090:0000.
|
||||
*/
|
||||
|
||||
while (intercpu_paddr < end_paddr)
|
||||
{
|
||||
mmu_l2_setentry(INTERCPU_L2_VBASE, intercpu_paddr, intercpu_vaddr,
|
||||
MMU_L2_INTERCPUFLAGS);
|
||||
intercpu_paddr += 4096;
|
||||
intercpu_vaddr += 4096;
|
||||
}
|
||||
|
||||
/* Now set the level 1 descriptor to refer to the level 2 page table. */
|
||||
|
||||
mmu_l1_setentry(INTERCPU_L2_PBASE & PMD_PTE_PADDR_MASK,
|
||||
INTERCPU_VADDR & PMD_PTE_PADDR_MASK,
|
||||
MMU_L1_INTERCPUFLAGS);
|
||||
}
|
||||
#else
|
||||
/* No inter-cpu communications area */
|
||||
|
||||
# define imx_intercpu_mapping()
|
||||
#endif
|
||||
|
||||
/****************************************************************************
|
||||
* Name: imx_copyvectorblock
|
||||
*
|
||||
@@ -477,15 +435,6 @@ void arm_boot(void)
|
||||
imx_vectormapping();
|
||||
PROGRESS('D');
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED)
|
||||
/* Provide a special mapping for the OCRAM interrupt vector positioned in
|
||||
* high memory.
|
||||
*/
|
||||
|
||||
imx_intercpu_mapping();
|
||||
PROGRESS('E');
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARCH_RAMFUNCS
|
||||
/* Copy any necessary code sections from FLASH to RAM. The correct
|
||||
* destination in OCRAM is given by _sramfuncs and _eramfuncs. The
|
||||
@@ -498,14 +447,14 @@ void arm_boot(void)
|
||||
*dest++ = *src++;
|
||||
}
|
||||
|
||||
PROGRESS('F');
|
||||
PROGRESS('E');
|
||||
|
||||
/* Flush the copied RAM functions into physical RAM so that will
|
||||
* be available when fetched into the I-Cache.
|
||||
*/
|
||||
|
||||
arch_clean_dcache((uintptr_t)&_sramfuncs, (uintptr_t)&_eramfuncs)
|
||||
PROGRESS('G');
|
||||
PROGRESS('F');
|
||||
#endif
|
||||
|
||||
/* Setup up vector block. _vector_start and _vector_end are exported from
|
||||
@@ -513,23 +462,23 @@ void arm_boot(void)
|
||||
*/
|
||||
|
||||
imx_copyvectorblock();
|
||||
PROGRESS('H');
|
||||
PROGRESS('G');
|
||||
|
||||
/* Disable the watchdog timer */
|
||||
|
||||
imx_wdtdisable();
|
||||
PROGRESS('I');
|
||||
PROGRESS('H');
|
||||
|
||||
/* Initialize clocking to settings provided by board-specific logic */
|
||||
|
||||
imx_clockconfig();
|
||||
PROGRESS('J');
|
||||
PROGRESS('I');
|
||||
|
||||
#ifdef CONFIG_ARCH_FPU
|
||||
/* Initialize the FPU */
|
||||
|
||||
arm_fpuconfig();
|
||||
PROGRESS('K');
|
||||
PROGRESS('J');
|
||||
#endif
|
||||
|
||||
/* Perform board-specific memroy initialization, This must include
|
||||
@@ -541,7 +490,7 @@ void arm_boot(void)
|
||||
*/
|
||||
|
||||
imx_memory_initialize();
|
||||
PROGRESS('L');
|
||||
PROGRESS('K');
|
||||
|
||||
#ifdef NEED_SDRAM_REMAPPING
|
||||
/* SDRAM was configured in a temporary state to support low-level
|
||||
@@ -550,7 +499,7 @@ void arm_boot(void)
|
||||
*/
|
||||
|
||||
imx_remap();
|
||||
PROGRESS('M');
|
||||
PROGRESS('L');
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_BOOT_SDRAM_DATA
|
||||
@@ -559,7 +508,7 @@ void arm_boot(void)
|
||||
*/
|
||||
|
||||
arm_data_initialize();
|
||||
PROGRESS('N');
|
||||
PROGRESS('M');
|
||||
#endif
|
||||
|
||||
/* Perform board-specific device initialization. This would include
|
||||
@@ -567,23 +516,12 @@ void arm_boot(void)
|
||||
*/
|
||||
|
||||
imx_board_initialize();
|
||||
PROGRESS('O');
|
||||
|
||||
#if defined(CONFIG_SMP) && defined(SMP_INTERCPU_NONCACHED)
|
||||
/* Initialize the uncached, inter-CPU communications area */
|
||||
|
||||
for (dest = &_snocache; dest < &_enocache; )
|
||||
{
|
||||
*dest++ = 0;
|
||||
}
|
||||
|
||||
PROGRESS('P');
|
||||
#endif
|
||||
PROGRESS('N');
|
||||
|
||||
/* Perform common, low-level chip initialization (might do nothing) */
|
||||
|
||||
imx_lowsetup();
|
||||
PROGRESS('Q');
|
||||
PROGRESS('O');
|
||||
|
||||
#ifdef USE_EARLYSERIALINIT
|
||||
/* Perform early serial initialization if we are going to use the serial
|
||||
@@ -591,7 +529,7 @@ void arm_boot(void)
|
||||
*/
|
||||
|
||||
imx_earlyserialinit();
|
||||
PROGRESS('R');
|
||||
PROGRESS('P');
|
||||
#endif
|
||||
|
||||
/* Now we can enable all other CPUs. The enabled CPUs will start execution
|
||||
@@ -600,6 +538,6 @@ void arm_boot(void)
|
||||
*/
|
||||
|
||||
imx_cpu_enable();
|
||||
PROGRESS('S');
|
||||
PROGRESS('Q');
|
||||
PROGRESS('\n');
|
||||
}
|
||||
|
||||
@@ -115,10 +115,6 @@ static void up_output_compare(uint32_t sr, uint32_t of)
|
||||
|
||||
if ((sr & of) != 0)
|
||||
{
|
||||
/* Clear the pending output compare interrupt */
|
||||
|
||||
putreg32(of, IMX_GPT_SR);
|
||||
|
||||
/* Process timer interrupt event */
|
||||
|
||||
sched_process_timer();
|
||||
@@ -140,9 +136,16 @@ static void up_output_compare(uint32_t sr, uint32_t of)
|
||||
|
||||
int up_timerisr(int irq, uint32_t *regs)
|
||||
{
|
||||
/* Sample the SR (once) and process all pending output compare interrupt */
|
||||
/* Sample the SR (once) */
|
||||
|
||||
uint32_t sr = getreg32(IMX_GPT_SR);
|
||||
|
||||
/* Clear GPT status register */
|
||||
|
||||
putreg32(sr, IMX_GPT_SR);
|
||||
|
||||
/* Process all pending output compare interrupt */
|
||||
|
||||
up_output_compare(sr, GPT_INT_OF1);
|
||||
up_output_compare(sr, GPT_INT_OF2);
|
||||
up_output_compare(sr, GPT_INT_OF3);
|
||||
|
||||
@@ -70,7 +70,7 @@ CMN_CSRCS += up_dumpnvic.c
|
||||
endif
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c kl_getc.c
|
||||
CHIP_CSRCS = kl_clockconfig.c kl_gpio.c kl_idle.c kl_irq.c
|
||||
CHIP_CSRCS += kl_lowputc.c kl_serial.c kl_start.c kl_cfmconfig.c
|
||||
|
||||
ifneq ($(CONFIG_SCHED_TICKLESS),y)
|
||||
|
||||
@@ -71,7 +71,7 @@ endif
|
||||
|
||||
CHIP_ASRCS =
|
||||
CHIP_CSRCS = lpc11_clockconfig.c lpc11_gpio.c lpc11_i2c.c lpc11_idle.c
|
||||
CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_getc.c lpc11_serial.c
|
||||
CHIP_CSRCS += lpc11_irq.c lpc11_lowputc.c lpc11_serial.c
|
||||
CHIP_CSRCS += lpc11_spi.c lpc11_ssp.c lpc11_start.c
|
||||
|
||||
# Configuration-dependent LPC11xx files
|
||||
|
||||
@@ -1,47 +0,0 @@
|
||||
/************************************************************************************
|
||||
* arch/arm/src/lpc11/lpc11_getc.h
|
||||
*
|
||||
* Copyright (C) 2015, 2016 Gregory Nutt. All rights reserved.
|
||||
* Author: Gregory Nutt <gnutt@nuttx.org>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* 3. Neither the name NuttX nor the names of its contributors may be
|
||||
* used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
|
||||
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
|
||||
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
|
||||
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
|
||||
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
|
||||
* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
|
||||
* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
|
||||
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
|
||||
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
************************************************************************************/
|
||||
|
||||
#ifndef __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H
|
||||
#define __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H
|
||||
|
||||
/************************************************************************************
|
||||
* Included Files
|
||||
************************************************************************************/
|
||||
|
||||
#include <nuttx/config.h>
|
||||
#include "lpc11_serial.h"
|
||||
#include "chip/lpc11_uart.h"
|
||||
|
||||
#endif /* __ARCH_ARM_SRC_LPC11XX_LPC11_GETC_H */
|
||||
@@ -2086,6 +2086,7 @@ static int lpc17_recvlong(FAR struct sdio_dev_s *dev, uint32_t cmd, uint32_t rlo
|
||||
rlong[2] = getreg32(LPC17_SDCARD_RESP2);
|
||||
rlong[3] = getreg32(LPC17_SDCARD_RESP3);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
@@ -603,23 +603,23 @@
|
||||
#define PINCONF_QEI_PHA (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_3)
|
||||
#define PINCONF_QEI_PHB (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_2)
|
||||
|
||||
#define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_13)
|
||||
#define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_8)
|
||||
#define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_0)
|
||||
#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_6)
|
||||
#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_10)
|
||||
#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_9)
|
||||
#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_4)
|
||||
#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_10)
|
||||
#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_5)
|
||||
#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_11)
|
||||
#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_6)
|
||||
#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_12)
|
||||
#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_7)
|
||||
#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_11)
|
||||
#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_12)
|
||||
#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_13)
|
||||
#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_14)
|
||||
#define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13)
|
||||
#define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_8)
|
||||
#define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_0)
|
||||
#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6)
|
||||
#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_10)
|
||||
#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9)
|
||||
#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_4)
|
||||
#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10)
|
||||
#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_5)
|
||||
#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11)
|
||||
#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_6)
|
||||
#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12)
|
||||
#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_7)
|
||||
#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_11)
|
||||
#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_12)
|
||||
#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_13)
|
||||
#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_14)
|
||||
#define PINCONF_SD_POW_1 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_1)
|
||||
#define PINCONF_SD_POW_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_5)
|
||||
#define PINCONF_SD_POW_3 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_9)
|
||||
|
||||
@@ -603,23 +603,23 @@
|
||||
#define PINCONF_QEI_PHA (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_3)
|
||||
#define PINCONF_QEI_PHB (PINCONF_FUNC1|PINCONF_PINSA|PINCONF_PIN_2)
|
||||
|
||||
#define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_13)
|
||||
#define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_8)
|
||||
#define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_0)
|
||||
#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_6)
|
||||
#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_10)
|
||||
#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_9)
|
||||
#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_4)
|
||||
#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_10)
|
||||
#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_5)
|
||||
#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_11)
|
||||
#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_6)
|
||||
#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_12)
|
||||
#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_7)
|
||||
#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_11)
|
||||
#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_12)
|
||||
#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_13)
|
||||
#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_14)
|
||||
#define PINCONF_SD_CD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_13)
|
||||
#define PINCONF_SD_CD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_8)
|
||||
#define PINCONF_SD_CLK (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_0)
|
||||
#define PINCONF_SD_CMD_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_6)
|
||||
#define PINCONF_SD_CMD_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_10)
|
||||
#define PINCONF_SD_DAT0_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_9)
|
||||
#define PINCONF_SD_DAT0_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_4)
|
||||
#define PINCONF_SD_DAT1_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_10)
|
||||
#define PINCONF_SD_DAT1_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_5)
|
||||
#define PINCONF_SD_DAT2_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_11)
|
||||
#define PINCONF_SD_DAT2_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_6)
|
||||
#define PINCONF_SD_DAT3_1 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINS1|PINCONF_PIN_12)
|
||||
#define PINCONF_SD_DAT3_2 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_7)
|
||||
#define PINCONF_SD_DAT4 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_11)
|
||||
#define PINCONF_SD_DAT5 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_12)
|
||||
#define PINCONF_SD_DAT6 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_13)
|
||||
#define PINCONF_SD_DAT7 (PINCONF_FUNC7|PINCONF_INBUFFER|PINCONF_GLITCH|PINCONF_SLEW_FAST|PINCONF_PINSC|PINCONF_PIN_14)
|
||||
#define PINCONF_SD_POW_1 (PINCONF_FUNC5|PINCONF_PINSD|PINCONF_PIN_1)
|
||||
#define PINCONF_SD_POW_2 (PINCONF_FUNC7|PINCONF_PINS1|PINCONF_PIN_5)
|
||||
#define PINCONF_SD_POW_3 (PINCONF_FUNC7|PINCONF_PINSC|PINCONF_PIN_9)
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user