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arch/arm/stm32*: Cleanup stm32 irq reporting

Browse Source 
Rename STM32_IRQ_NEXTINT to STM32_IRQ_NEXTINTS across all stm32
variants.
In stm32_dumpnvic() dynamically print NVIC enable and priority
registers based on STM32_IRQ_NEXTINTS.
Use PRIx32 format specifier instead of 'x' (since uint32_t on arm is
actually a long unsigned int).
Simplify if/else chain in stm32_irqinfo() to determine irq reg/bit.
There's no stm32_irqinfo.c; remove mention in stm32f0l0g0/Make.defs.

Signed-off-by Peter Barada <peter.barada@gmail.com>
This commit is contained in:
Peter Barada
2026-03-25 14:14:25 -04:00
committed by Xiang Xiao
parent 2a4c5c8bee
commit 870c96350f
22 changed files with 267 additions and 399 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/include/stm32/stm32f10xxx_irq.h
+5 -6
View File
@@ -116,8 +116,7 @@
# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4 and 5 global interrupt */
# define STM32_IRQ_DMA2CH5 (76) /* 60: DMA2 Channel 5 global interrupt */
# define STM32_IRQ_NEXTINT (61)
# define NR_IRQS (77)
# define STM32_IRQ_NEXTINTS (61)
/* Connectivity Line Devices */
@@ -191,8 +190,7 @@
# define STM32_IRQ_CAN2SCE (82) /* 66: CAN2 SCE interrupt */
# define STM32_IRQ_OTGFS (83) /* 67: USB On The Go FS global interrupt */
# define STM32_IRQ_NEXTINT (68)
# define NR_IRQS (84)
# define STM32_IRQ_NEXTINTS (68)
/* Medium and High Density Devices */
@@ -258,8 +256,7 @@
# define STM32_IRQ_DMA2CH3 (74) /* 58: DMA2 Channel 3 global interrupt */
# define STM32_IRQ_DMA2CH45 (75) /* 59: DMA2 Channel 4&5 global interrupt */
# define STM32_IRQ_NEXTINT (60)
# define NR_IRQS (76)
# define STM32_IRQ_NEXTINTS (60)
/* Convenience definitions for interrupts with multiple functions */
@@ -269,6 +266,8 @@
# define STM32_IRQ_CAN1RX0 STM32_IRQ_USBLPCANRX0
#endif
# define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************
* Public Types
****************************************************************************/
arch/arm/include/stm32/stm32f20xxx_irq.h
+2 -2
View File
@@ -139,8 +139,8 @@
#define STM32_IRQ_HASH (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_RNG (STM32_IRQ_FIRST + 80) /* 80: Hash and Rng global interrupt */
#define STM32_IRQ_NEXTINT (81)
#define NR_IRQS (STM32_IRQ_FIRST + 81)
#define STM32_IRQ_NEXTINTS (81)
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************
* Public Types
arch/arm/include/stm32/stm32f30xxx_irq.h
+2 -2
View File
@@ -150,8 +150,8 @@
#define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST + 80) /* 80: Reserved */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
#define STM32_IRQ_NEXTINT (82)
#define NR_IRQS (STM32_IRQ_FIRST + 82)
#define STM32_IRQ_NEXTINTS (82)
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************
* Public Types
arch/arm/include/stm32/stm32f33xxx_irq.h
+2 -2
View File
@@ -140,8 +140,8 @@
#define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST + 80) /* 80: Reserved */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
#define STM32_IRQ_NEXTINT (82)
#define NR_IRQS (STM32_IRQ_FIRST + 82)
#define STM32_IRQ_NEXTINTS (82)
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************
* Public Types
arch/arm/include/stm32/stm32f37xxx_irq.h
+2 -2
View File
@@ -135,8 +135,8 @@
#define STM32_IRQ_RESERVED80 (STM32_IRQ_FIRST + 80) /* 80: Reserved */
#define STM32_IRQ_FPU (STM32_IRQ_FIRST + 81) /* 81: FPU global interrupt */
#define STM32_IRQ_NEXTINT (82)
#define NR_IRQS (STM32_IRQ_FIRST + 82)
#define STM32_IRQ_NEXTINTS (82)
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************
* Public Types
arch/arm/include/stm32/stm32f40xxx_irq.h
+8 -12
View File
@@ -306,25 +306,21 @@
#if defined(CONFIG_STM32_STM32F401) || defined(CONFIG_STM32_STM32F411) || \
defined(CONFIG_STM32_STM32F405) || defined(CONFIG_STM32_STM32F407)
# define STM32_IRQ_NEXTINT (82)
# define NR_IRQS (STM32_IRQ_FIRST+82)
# define STM32_IRQ_NEXTINTS (82)
#elif defined(CONFIG_STM32_STM32F410)
# define STM32_IRQ_NEXTINT (98)
# define NR_IRQS (STM32_IRQ_FIRST+98)
# define STM32_IRQ_NEXTINTS (98)
#elif defined(CONFIG_STM32_STM32F427)
# define STM32_IRQ_NEXTINT (87)
# define NR_IRQS (STM32_IRQ_FIRST+87)
# define STM32_IRQ_NEXTINTS (87)
#elif defined(CONFIG_STM32_STM32F429)
# define STM32_IRQ_NEXTINT (91)
# define NR_IRQS (STM32_IRQ_FIRST+91)
# define STM32_IRQ_NEXTINTS (91)
#elif defined(CONFIG_STM32_STM32F446) || defined(CONFIG_STM32_STM32F412)
# define STM32_IRQ_NEXTINT (97)
# define NR_IRQS (STM32_IRQ_FIRST+97)
# define STM32_IRQ_NEXTINTS (97)
#elif defined(CONFIG_STM32_STM32F469)
# define STM32_IRQ_NEXTINT (93)
# define NR_IRQS (STM32_IRQ_FIRST+93)
# define STM32_IRQ_NEXTINTS (93)
#endif
# define NR_IRQS (STM32_IRQ_FIRST+STM32_IRQ_NEXTINTS)
/****************************************************************************
* Public Types
****************************************************************************/
arch/arm/include/stm32/stm32g4xxxx_irq.h
+1 -1
View File
@@ -169,7 +169,7 @@
#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 100) /* 100: CORDIC trigonometric accelerator interrupt */
#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 101) /* 101: FMAC filter math accelerator interrupt */
#define STM32_IRQ_NEXTINT (102)
#define STM32_IRQ_NEXTINTS (102)
#define NR_IRQS (STM32_IRQ_FIRST + 102)
/****************************************************************************
arch/arm/include/stm32/stm32l15xxx_irq.h
+5 -6
View File
@@ -96,8 +96,7 @@
# define STM32_IRQ_TIM6 (STM32_IRQ_FIRST + 43) /* 43: TIM6 global interrupt */
# define STM32_IRQ_TIM7 (STM32_IRQ_FIRST + 44) /* 44: TIM7 global interrupt */
# define STM32_IRQ_NEXTINT (45)
# define NR_IRQS (STM32_IRQ_FIRST + 45)
# define STM32_IRQ_NEXTINTS (45)
/* External interrupts (vectors >= 16) medium+ density devices */
@@ -159,8 +158,7 @@
# define STM32_IRQ_AES (STM32_IRQ_FIRST + 52) /* 52: AES global interrupt */
# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST + 53) /* 53: Comparator Channel Acquisition Interrupt */
# define STM32_IRQ_NEXTINT (54)
# define NR_IRQS (STM32_IRQ_FIRST + 54)
# define STM32_IRQ_NEXTINTS (54)
/* External interrupts (vectors >= 16) high density devices */
@@ -225,12 +223,13 @@
# define STM32_IRQ_AES (STM32_IRQ_FIRST + 55) /* 55: AES global interrupt */
# define STM32_IRQ_COMPACQ (STM32_IRQ_FIRST + 56) /* 56: Comparator Channel Acquisition Interrupt */
# define STM32_IRQ_NEXTINT (57)
# define NR_IRQS (STM32_IRQ_FIRST + 57)
# define STM32_IRQ_NEXTINTS (57)
#else
# error "Unknown STM32L density"
#endif
# define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
/****************************************************************************
* Public Types
****************************************************************************/
arch/arm/include/stm32f0l0g0/irq.h
+1 -1
View File
@@ -80,7 +80,7 @@
# error Unrecognized STM32 Cortex M0 family
#endif
#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINT)
#define NR_IRQS (STM32_IRQ_EXTINT + STM32_IRQ_NEXTINTS)
/****************************************************************************
* Public Types
arch/arm/include/stm32f0l0g0/stm32c0_irq.h
+1 -1
View File
@@ -85,7 +85,7 @@
#define STM32_IRQ_FDCAN1_0 (STM32_IRQ_EXTINT + 30) /* 30: FDCAN global interrupt 0 */
#define STM32_IRQ_FDCAN1_1 (STM32_IRQ_EXTINT + 31) /* 31: FDCAN global interrupt 1 */
#define STM32_IRQ_NEXTINT (32)
#define STM32_IRQ_NEXTINTS (32)
/****************************************************************************
* Public Types
arch/arm/include/stm32f0l0g0/stm32f0_irq.h
+1 -1
View File
@@ -97,7 +97,7 @@
#define STM32_IRQ_CAN (STM32_IRQ_EXTINT + 30) /* 30: HDMI CAN */
#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB */
#define STM32_IRQ_NEXTINT (32) /* 32 external interrupts */
#define STM32_IRQ_NEXTINTS (32) /* 32 external interrupts */
/****************************************************************************
* Public Types
arch/arm/include/stm32f0l0g0/stm32g0_irq.h
+1 -1
View File
@@ -163,7 +163,7 @@
# define STM32_IRQ_RNG (STM32_IRQ_EXTINT + 31) /* 31: RNG */
#endif
#define STM32_IRQ_NEXTINT (32)
#define STM32_IRQ_NEXTINTS (32)
/****************************************************************************
* Public Types
arch/arm/include/stm32f0l0g0/stm32l0_irq.h
+1 -1
View File
@@ -90,7 +90,7 @@
#define STM32_IRQ_LCD (STM32_IRQ_EXTINT + 30) /* 30: LCD global interrupt */
#define STM32_IRQ_USB (STM32_IRQ_EXTINT + 31) /* 31: USB global interrupt */
#define STM32_IRQ_NEXTINT (32)
#define STM32_IRQ_NEXTINTS (32)
/****************************************************************************
* Public Types
arch/arm/include/stm32h5/stm32h5xx_irq.h
+3 -3
View File
@@ -200,11 +200,11 @@
#endif
#if defined(CONFIG_STM32H5_STM32H56XXX) || defined(CONFIG_STM32H5_STM32H57XXX)
# define STM32_IRQ_NEXTINTS 131
# define STM32_IRQ_NEXTINTS 131
#elif defined(CONFIG_STM32H5_STM32H52XXX) || defined(CONFIG_STM32H5_STM32H53XXX)
# define STM32_IRQ_NEXTINTS 133
# define STM32_IRQ_NEXTINTS 133
#endif
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
#endif /* __ARCH_ARM_INCLUDE_STM32H5_STM32H5XX_IRQ_H */
#endif /* __ARCH_ARM_INCLUDE_STM32H5_STM32H5XX_IRQ_H */
arch/arm/include/stm32u5/stm32u5xx_irq.h
+1 -1
View File
@@ -195,7 +195,7 @@
defined(CONFIG_STM32U5_STM32U575XX) || defined(CONFIG_STM32U5_STM32U585XX) || \
defined(CONFIG_STM32U5_STM32U59XX) || defined(CONFIG_STM32U5_STM32U59AXX) || \
defined(CONFIG_STM32U5_STM32U5A5XX) || defined(CONFIG_STM32U5_STM32U5A9XX)
# define STM32_IRQ_NEXTINTS 125
# define STM32_IRQ_NEXTINTS 125
#else
# error "Unsupported STM32U5 chip"
#endif
arch/arm/src/stm32/chip.h
+4 -4
View File
@@ -49,11 +49,11 @@
* Pre-processor Definitions
****************************************************************************/
/* Provide the required number of peripheral interrupt vector definitions as
* well. The definition STM32_IRQ_NEXTINT simply comes from the chip-specific
* IRQ header file included by arch/stm32/irq.h.
/* Provide the required number of peripheral interrupt vector
* definitions as * well. The definition STM32_IRQ_NEXTINTS simply comes
* from the chip-specific * IRQ header file included by arch/stm32/irq.h.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINT
#define ARMV7M_PERIPHERAL_INTERRUPTS STM32_IRQ_NEXTINTS
#endif /* __ARCH_ARM_SRC_STM32_CHIP_H */
arch/arm/src/stm32/stm32_dumpgpio.c
+1 -1
View File
@@ -131,7 +131,7 @@ int stm32_dumpgpio(uint32_t pinset, const char *msg)
}
else
{
_info(" GPIO%c not enabled: APB2ENR: %08x\n",
_info(" GPIO%c not enabled: APB2ENR: %08" PRIx32 "\n",
g_portchar[port], getreg32(STM32_RCC_APB2ENR));
}
arch/arm/src/stm32/stm32_irq.c
+70 -30
View File
@@ -78,50 +78,90 @@
static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
unsigned int i;
unsigned int j;
unsigned int nregs;
unsigned int off;
unsigned int nintr;
unsigned int nreg_per_line = 4;
unsigned int nenable_per_reg = 32;
unsigned int nenable_per_line = nenable_per_reg * nreg_per_line;
unsigned int nprio_per_reg = 4;
unsigned int nprio_per_line = nprio_per_reg * nreg_per_line;
char buf[64];
flags = enter_critical_section();
nintr = STM32_IRQ_NEXTINTS;
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
irqinfo(" INTCTRL: %08" PRIx32 " VECTAB: %08" PRIx32 "\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x "
"SYSTICK: %08x\n",
irqinfo(" SYSH ENABLE MEMFAULT: %08" PRIx32 " BUSFAULT: %08"
PRIx32 " USGFAULT: %08" PRIx32 " SYSTICK: %08" PRIx32 "\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA),
getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA),
getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE),
getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
for (i = 0; i < nintr; i += nenable_per_line)
{
if (!i)
{
off = snprintf(buf, sizeof(buf), " IRQ ENAB 0:");
}
else
{
off = snprintf(buf, sizeof(buf), " %3u:", i);
}
nregs = nintr - i;
if (nregs > nenable_per_line)
{
nregs = nenable_per_line;
}
for (j = 0; j < nregs; j += nenable_per_reg)
{
off += snprintf(&buf[off], sizeof(buf)-off, " %08" PRIx32,
getreg32(NVIC_IRQ_ENABLE(i + j)));
}
irqinfo("%s\n", buf);
}
irqinfo(" SYSH_PRIO: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 "\n",
getreg32(NVIC_SYSH4_7_PRIORITY),
getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY),
getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY),
getreg32(NVIC_IRQ12_15_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY),
getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY),
getreg32(NVIC_IRQ28_31_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY),
getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY),
getreg32(NVIC_IRQ44_47_PRIORITY));
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY),
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY),
getreg32(NVIC_IRQ60_63_PRIORITY));
irqinfo(" %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY));
for (i = 0;
i < nintr;
i += nprio_per_line)
{
if (!i)
{
off = snprintf(buf, sizeof(buf), " IRQ PRIO 0:");
}
else
{
off = snprintf(buf, sizeof(buf), " %3u:", i);
}
nregs = nintr - i;
if (nregs > nprio_per_line)
{
nregs = nprio_per_line;
}
for (j = 0; j < nregs; j += nprio_per_reg)
{
off += snprintf(&buf[off], sizeof(buf)-off, " %08" PRIx32,
getreg32(NVIC_IRQ_PRIORITY(i + j)));
}
irqinfo("%s\n", buf);
}
leave_critical_section(flags);
}
arch/arm/src/stm32f0l0g0/Make.defs
-4
View File
@@ -57,10 +57,6 @@ ifeq ($(CONFIG_STM32F0L0G0_GPIOIRQ),y)
CHIP_CSRCS += stm32_gpioint.c
endif
ifeq ($(CONFIG_ARCH_IRQPRIO),y)
CHIP_CSRCS += stm32_irqprio.c
endif
ifeq ($(CONFIG_STM32F0L0G0_HAVE_HSI48),y)
CHIP_CSRCS += stm32_hsi48.c
endif
arch/arm/src/stm32f0l0g0/stm32_irq.c
+10 -8
View File
@@ -69,25 +69,27 @@ static void stm32_dumpnvic(const char *msg, int irq)
flags = enter_critical_section();
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" ISER: %08x ICER: %08x\n",
irqinfo(" ISER: %08" PRIx32 " ICER: %08" PRIx32 "\n",
getreg32(ARMV6M_NVIC_ISER), getreg32(ARMV6M_NVIC_ICER));
irqinfo(" ISPR: %08x ICPR: %08x\n",
irqinfo(" ISPR: %08" PRIx32 " ICPR: %08" PRIx32 "\n",
getreg32(ARMV6M_NVIC_ISPR), getreg32(ARMV6M_NVIC_ICPR));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
irqinfo(" IRQ PRIO: %08" PRIx32 " %08" PRIx32 " %08" PRIx32
" %08" PRIx32 "\n",
getreg32(ARMV6M_NVIC_IPR0), getreg32(ARMV6M_NVIC_IPR1),
getreg32(ARMV6M_NVIC_IPR2), getreg32(ARMV6M_NVIC_IPR3));
irqinfo(" %08x %08x %08x %08x\n",
irqinfo(" %08" PRIx32 " %08" PRIx32 " %08" PRIx32
" %08" PRIx32 "\n",
getreg32(ARMV6M_NVIC_IPR4), getreg32(ARMV6M_NVIC_IPR5),
getreg32(ARMV6M_NVIC_IPR6), getreg32(ARMV6M_NVIC_IPR7));
irqinfo("SYSCON:\n");
irqinfo(" CPUID: %08x\n",
irqinfo(" CPUID: %08" PRIx32 "\n",
getreg32(ARMV6M_SYSCON_CPUID));
irqinfo(" ICSR: %08x AIRCR: %08x\n",
irqinfo(" ICSR: %08" PRIx32 " AIRCR: %08" PRIx32 "\n",
getreg32(ARMV6M_SYSCON_ICSR), getreg32(ARMV6M_SYSCON_AIRCR));
irqinfo(" SCR: %08x CCR: %08x\n",
irqinfo(" SCR: %08" PRIx32 " CCR: %08" PRIx32 "\n",
getreg32(ARMV6M_SYSCON_SCR), getreg32(ARMV6M_SYSCON_CCR));
irqinfo(" SHPR2: %08x SHPR3: %08x\n",
irqinfo(" SHPR2: %08" PRIx32 " SHPR3: %08" PRIx32 "\n",
getreg32(ARMV6M_SYSCON_SHPR2), getreg32(ARMV6M_SYSCON_SHPR3));
leave_critical_section(flags);
arch/arm/src/stm32f7/stm32_irq.c
+72 -128
View File
@@ -79,85 +79,90 @@
static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
unsigned int i;
unsigned int j;
unsigned int nregs;
unsigned int off;
unsigned int nintr;
unsigned int nreg_per_line = 4;
unsigned int nenable_per_reg = 32;
unsigned int nenable_per_line = nenable_per_reg * nreg_per_line;
unsigned int nprio_per_reg = 4;
unsigned int nprio_per_line = nprio_per_reg * nreg_per_line;
char buf[64];
flags = enter_critical_section();
nintr = STM32_IRQ_NEXTINTS;
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08" PRIx32 " VECTAB: %08" PRIx32 "\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
irqinfo(" SYSH ENABLE MEMFAULT: %08" PRIx32 " BUSFAULT: %08" PRIx32 " "
"USGFAULT: %08" PRIx32 " SYSTICK: %08" PRIx32 "\n",
irqinfo(" SYSH ENABLE MEMFAULT: %08" PRIx32 " BUSFAULT: %08"
PRIx32 " USGFAULT: %08" PRIx32 " SYSTICK: %08" PRIx32 "\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA),
getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA),
getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
irqinfo(" IRQ ENABLE: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 "\n",
getreg32(NVIC_IRQ0_31_ENABLE),
getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
for (i = 0; i < nintr; i += nenable_per_line)
{
if (!i)
{
off = snprintf(buf, sizeof(buf), " IRQ ENAB 0:");
}
else
{
off = snprintf(buf, sizeof(buf), " %3u:", i);
}
nregs = nintr - i;
if (nregs > nenable_per_line)
{
nregs = nenable_per_line;
}
for (j = 0; j < nregs; j += nenable_per_reg)
{
off += snprintf(&buf[off], sizeof(buf)-off, " %08" PRIx32,
getreg32(NVIC_IRQ_ENABLE(i + j)));
}
irqinfo("%s\n", buf);
}
irqinfo(" SYSH_PRIO: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 "\n",
getreg32(NVIC_SYSH4_7_PRIORITY),
getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " "
"%08" PRIx32 "\n",
getreg32(NVIC_IRQ0_3_PRIORITY),
getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY),
getreg32(NVIC_IRQ12_15_PRIORITY));
#if STM32_IRQ_NEXTINTS > 15
irqinfo(" %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " "
"%08" PRIx32 "\n",
getreg32(NVIC_IRQ16_19_PRIORITY),
getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY),
getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 31
irqinfo(" %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " "
"%08" PRIx32 "\n",
getreg32(NVIC_IRQ32_35_PRIORITY),
getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY),
getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 47
irqinfo(" %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " "
"%08" PRIx32 "\n",
getreg32(NVIC_IRQ48_51_PRIORITY),
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY),
getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 63
irqinfo(" %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " "
"%08" PRIx32 "\n",
getreg32(NVIC_IRQ64_67_PRIORITY),
getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY),
getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 79
irqinfo(" %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " "
"%08" PRIx32 "\n",
getreg32(NVIC_IRQ80_83_PRIORITY),
getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY),
getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 95
irqinfo(" %08" PRIx32 " %08" PRIx32 " %08" PRIx32 " "
"%08" PRIx32 "\n",
getreg32(NVIC_IRQ96_99_PRIORITY),
getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY),
getreg32(NVIC_IRQ108_111_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 111
# warning Missing logic
#endif
for (i = 0;
i < nintr;
i += nprio_per_line)
{
if (!i)
{
off = snprintf(buf, sizeof(buf), " IRQ PRIO 0:");
}
else
{
off = snprintf(buf, sizeof(buf), " %3u:", i);
}
nregs = nintr - i;
if (nregs > nprio_per_line)
{
nregs = nprio_per_line;
}
for (j = 0; j < nregs; j += nprio_per_reg)
{
off += snprintf(&buf[off], sizeof(buf)-off, " %08" PRIx32,
getreg32(NVIC_IRQ_PRIORITY(i + j)));
}
irqinfo("%s\n", buf);
}
leave_critical_section(flags);
}
@@ -234,7 +239,7 @@ static inline void stm32_prioritize_syscall(int priority)
static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
unsigned int extint = irq - STM32_IRQ_FIRST;
int n;
DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS);
@@ -242,70 +247,9 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= STM32_IRQ_FIRST)
{
#if STM32_IRQ_NEXTINTS <= 32
if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else
#elif STM32_IRQ_NEXTINTS <= 64
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else
#elif STM32_IRQ_NEXTINTS <= 96
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < 64)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else
#elif STM32_IRQ_NEXTINTS <= 128
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < 64)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else if (extint < 96)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (extint - 96);
}
else
#else
# warning Missing logic
#endif
{
return ERROR; /* Invalid interrupt */
}
n = irq - STM32_IRQ_FIRST;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
*bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */
arch/arm/src/stm32h7/stm32_irq.c
+74 -182
View File
@@ -79,78 +79,90 @@
static void stm32_dumpnvic(const char *msg, int irq)
{
irqstate_t flags;
unsigned int i;
unsigned int j;
unsigned int nregs;
unsigned int off;
unsigned int nintr;
unsigned int nreg_per_line = 4;
unsigned int nenable_per_reg = 32;
unsigned int nenable_per_line = nenable_per_reg * nreg_per_line;
unsigned int nprio_per_reg = 4;
unsigned int nprio_per_line = nprio_per_reg * nreg_per_line;
char buf[64];
flags = enter_critical_section();
nintr = STM32_IRQ_NEXTINTS;
irqinfo("NVIC (%s, irq=%d):\n", msg, irq);
irqinfo(" INTCTRL: %08x VECTAB: %08x\n",
irqinfo(" INTCTRL: %08" PRIx32 " VECTAB: %08" PRIx32 "\n",
getreg32(NVIC_INTCTRL), getreg32(NVIC_VECTAB));
#if 0
irqinfo(" SYSH ENABLE MEMFAULT: %08x BUSFAULT: %08x USGFAULT: %08x "
"SYSTICK: %08x\n",
irqinfo(" SYSH ENABLE MEMFAULT: %08" PRIx32 " BUSFAULT: %08"
PRIx32 " USGFAULT: %08" PRIx32 " SYSTICK: %08" PRIx32 "\n",
getreg32(NVIC_SYSHCON_MEMFAULTENA),
getreg32(NVIC_SYSHCON_BUSFAULTENA),
getreg32(NVIC_SYSHCON_USGFAULTENA),
getreg32(NVIC_SYSTICK_CTRL_ENABLE));
#endif
irqinfo(" IRQ ENABLE: %08x %08x %08x\n",
getreg32(NVIC_IRQ0_31_ENABLE),
getreg32(NVIC_IRQ32_63_ENABLE),
getreg32(NVIC_IRQ64_95_ENABLE));
irqinfo(" SYSH_PRIO: %08x %08x %08x\n",
for (i = 0; i < nintr; i += nenable_per_line)
{
if (!i)
{
off = snprintf(buf, sizeof(buf), " IRQ ENAB 0:");
}
else
{
off = snprintf(buf, sizeof(buf), " %3u:", i);
}
nregs = nintr - i;
if (nregs > nenable_per_line)
{
nregs = nenable_per_line;
}
for (j = 0; j < nregs; j += nenable_per_reg)
{
off += snprintf(&buf[off], sizeof(buf)-off, " %08" PRIx32,
getreg32(NVIC_IRQ_ENABLE(i + j)));
}
irqinfo("%s\n", buf);
}
irqinfo(" SYSH_PRIO: %08" PRIx32 " %08" PRIx32 " %08" PRIx32 "\n",
getreg32(NVIC_SYSH4_7_PRIORITY),
getreg32(NVIC_SYSH8_11_PRIORITY),
getreg32(NVIC_SYSH12_15_PRIORITY));
irqinfo(" IRQ PRIO: %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ0_3_PRIORITY),
getreg32(NVIC_IRQ4_7_PRIORITY),
getreg32(NVIC_IRQ8_11_PRIORITY),
getreg32(NVIC_IRQ12_15_PRIORITY));
#if STM32_IRQ_NEXTINTS > 15
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ16_19_PRIORITY),
getreg32(NVIC_IRQ20_23_PRIORITY),
getreg32(NVIC_IRQ24_27_PRIORITY),
getreg32(NVIC_IRQ28_31_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 31
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ32_35_PRIORITY),
getreg32(NVIC_IRQ36_39_PRIORITY),
getreg32(NVIC_IRQ40_43_PRIORITY),
getreg32(NVIC_IRQ44_47_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 47
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ48_51_PRIORITY),
getreg32(NVIC_IRQ52_55_PRIORITY),
getreg32(NVIC_IRQ56_59_PRIORITY),
getreg32(NVIC_IRQ60_63_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 63
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ64_67_PRIORITY),
getreg32(NVIC_IRQ68_71_PRIORITY),
getreg32(NVIC_IRQ72_75_PRIORITY),
getreg32(NVIC_IRQ76_79_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 79
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ80_83_PRIORITY),
getreg32(NVIC_IRQ84_87_PRIORITY),
getreg32(NVIC_IRQ88_91_PRIORITY),
getreg32(NVIC_IRQ92_95_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 95
irqinfo(" %08x %08x %08x %08x\n",
getreg32(NVIC_IRQ96_99_PRIORITY),
getreg32(NVIC_IRQ100_103_PRIORITY),
getreg32(NVIC_IRQ104_107_PRIORITY),
getreg32(NVIC_IRQ108_111_PRIORITY));
#endif
#if STM32_IRQ_NEXTINTS > 111
# warning Missing logic
#endif
for (i = 0;
i < nintr;
i += nprio_per_line)
{
if (!i)
{
off = snprintf(buf, sizeof(buf), " IRQ PRIO 0:");
}
else
{
off = snprintf(buf, sizeof(buf), " %3u:", i);
}
nregs = nintr - i;
if (nregs > nprio_per_line)
{
nregs = nprio_per_line;
}
for (j = 0; j < nregs; j += nprio_per_reg)
{
off += snprintf(&buf[off], sizeof(buf)-off, " %08" PRIx32,
getreg32(NVIC_IRQ_PRIORITY(i + j)));
}
irqinfo("%s\n", buf);
}
/* TODO: Make sure this covers all interrupts that are available. */
@@ -229,7 +241,7 @@ static inline void stm32_prioritize_syscall(int priority)
static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
uintptr_t offset)
{
unsigned int extint = irq - STM32_IRQ_FIRST;
int n;
DEBUGASSERT(irq >= STM32_IRQ_NMI && irq < NR_IRQS);
@@ -237,129 +249,9 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
if (irq >= STM32_IRQ_FIRST)
{
#if STM32_IRQ_NEXTINTS <= 32
if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else
#elif STM32_IRQ_NEXTINTS <= 64
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else
#elif STM32_IRQ_NEXTINTS <= 96
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < 64)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else
#elif STM32_IRQ_NEXTINTS <= 128
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < 64)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else if (extint < 96)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (extint - 96);
}
else
#elif STM32_IRQ_NEXTINTS <= 160
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < 64)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else if (extint < 96)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else if (extint < 128)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (extint - 96);
}
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ128_159_ENABLE + offset);
*bit = 1 << (extint - 128);
}
else
#elif STM32_IRQ_NEXTINTS <= 192
if (extint < 32)
{
*regaddr = (NVIC_IRQ0_31_ENABLE + offset);
*bit = 1 << extint;
}
else if (extint < 64)
{
*regaddr = (NVIC_IRQ32_63_ENABLE + offset);
*bit = 1 << (extint - 32);
}
else if (extint < 96)
{
*regaddr = (NVIC_IRQ64_95_ENABLE + offset);
*bit = 1 << (extint - 64);
}
else if (extint < 128)
{
*regaddr = (NVIC_IRQ96_127_ENABLE + offset);
*bit = 1 << (extint - 96);
}
else if (extint < 160)
{
*regaddr = (NVIC_IRQ128_159_ENABLE + offset);
*bit = 1 << (extint - 128);
}
else if (extint < STM32_IRQ_NEXTINTS)
{
*regaddr = (NVIC_IRQ160_191_ENABLE + offset);
*bit = 1 << (extint - 160);
}
else
#else
# error Missing logic
#endif
{
return ERROR; /* Invalid interrupt */
}
n = irq - STM32_IRQ_FIRST;
*regaddr = NVIC_IRQ_ENABLE(n) + offset;
*bit = (uint32_t)1 << (n & 0x1f);
}
/* Handle processor exceptions. Only a few can be disabled */