Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-05-20 04:16:35 +08:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

add chip GD32F450 of GD32MCU

Browse Source 
Modify the file according to the checks

update the board config files, and modify the gd32f4xx_progmem.c

Add chip GD32F450 of GD32MCU

delete the micro FAR, modify code style

Add chip GD32F450 of GD32MCU
This commit is contained in:
GD32-MCU
2022-09-06 14:18:48 +08:00
committed by Xiang Xiao
parent e8f4d74ad0
commit 85c8144afa
79 changed files with 31020 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/Kconfig
+19
View File
@@ -69,6 +69,21 @@ config ARCH_CHIP_EOSS3
---help---
QuickLogic EOS S3 (ARM Cortex-M4)
config ARCH_CHIP_GD32F4
bool "GD32MCU GD32 F4"
select ARCH_CORTEXM4
select ARCH_HAVE_MPU
select ARCH_HAVE_FETCHADD
select ARCH_HAVE_I2CRESET
select ARCH_HAVE_HEAPCHECK
select ARCH_HAVE_PROGMEM
select ARCH_HAVE_SPI_BITORDER
select ARCH_HAVE_TICKLESS
select ARM_HAVE_MPU_UNIFIED
select ARMV7M_HAVE_STACKCHECK
---help---
GD32MCU GD32 architectures (ARM Cortex-M4).
config ARCH_CHIP_IMX1
bool "NXP/Freescale iMX.1"
select ARCH_ARM920T
@@ -863,6 +878,7 @@ config ARCH_CHIP
default "dm320" if ARCH_CHIP_DM320
default "efm32" if ARCH_CHIP_EFM32
default "eoss3" if ARCH_CHIP_EOSS3
default "gd32f4" if ARCH_CHIP_GD32F4
default "imx1" if ARCH_CHIP_IMX1
default "imx6" if ARCH_CHIP_IMX6
default "imxrt" if ARCH_CHIP_IMXRT
@@ -1188,6 +1204,9 @@ endif
if ARCH_CHIP_EOSS3
source "arch/arm/src/eoss3/Kconfig"
endif
if ARCH_CHIP_GD32F4
source "arch/arm/src/gd32f4/Kconfig"
endif
if ARCH_CHIP_IMX1
source "arch/arm/src/imx1/Kconfig"
endif
arch/arm/include/gd32f4/chip.h
+113
View File
@@ -0,0 +1,113 @@
/****************************************************************************
* arch/arm/include/gd32f4/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_INCLUDE_GD32F4_CHIP_H
#define __ARCH_ARM_INCLUDE_GD32F4_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* Check the GD32F4 family configuration.
* It must be done in arch/arm/src/gd32f4/Kconfig !
*/
#if defined(CONFIG_ARCH_CHIP_GD32F450IK)
# define GD32_NGPIO_PORTS 9 /* GPIOA-I */
# define GD32_NCRC 1 /* CRC calculation unit */
# define GD32_NTRNG 1 /* True random number generator (RNG) */
# define GD32_NDMA 2 /* DMA0,1 */
# define GD32_NIPA 1 /* Image processing accelerator */
# define GD32_NIREF 1 /* Programmable current reference */
# define GD32_NADC 3 /* 12-bit ADC0-2, 19 channels */
# define GD32_NDAC 2 /* 12-bit DAC0,1 */
# define GD32_NATIMER 2 /* Two advanced timers TIMER0 and 7 that support DMA */
# define GD32_NGTIMER 4 /* 16-bit general timers TIMER2 and 3
* 32-bit general timers TIMER1 and 4 that support DMA */
# define GD32_NGTIMNDMA 6 /* 16-bit general timers TIMER8-13 that not support DMA */
# define GD32_NBTIMER 2 /* Two basic timers, TIMER5,6 that support DMA */
# define GD32_NUSART 8 /* USART0-2 and 5, UART 3,4 and 6,7 */
# define GD32_NI2C 3 /* I2C0-2 */
# define GD32_NSPI 6 /* SPI0-5 */
# define GD32_NI2S 2 /* I2S1-2 (multiplexed with SPI1-2) */
# define GD32_NDCI 1 /* Digital camera interface (DCI) */
# define GD32_NTLI 1 /* TFT-LCD interface (TLI) */
# define GD32_NSDIO 1 /* Secure digital input/output interface */
# define GD32_NEXMC 1 /* External memory controller */
# define GD32_NCAN 2 /* CAN0-1 */
# define GD32_NETHERNET 1 /* 10/100 Ethernet MAC */
# define GD32_NUSBFS 1 /* USB FS*/
# define GD32_NUSBHS 1 /* USB HS*/
#elif defined(CONFIG_ARCH_CHIP_GD32F450ZK)
# define GD32_NGPIO_PORTS 8 /* GPIOA-H */
# define GD32_NCRC 1 /* CRC calculation unit */
# define GD32_NTRNG 1 /* True random number generator (RNG) */
# define GD32_NDMA 2 /* DMA0,1 */
# define GD32_NIPA 1 /* Image processing accelerator */
# define GD32_NIREF 1 /* Programmable current reference */
# define GD32_NADC 3 /* 12-bit ADC0-2, 19 channels */
# define GD32_NDAC 2 /* 12-bit DAC0,1 */
# define GD32_NATIMER 2 /* Two advanced timers TIMER0 and 7 that support DMA */
# define GD32_NGTIMER 4 /* 16-bit general timers TIMER2 and 3
* 32-bit general timers TIMER1 and 4 that support DMA */
# define GD32_NGTIMNDMA 6 /* 16-bit general timers TIMER8-13 that not support DMA */
# define GD32_NBTIMER 2 /* Two basic timers, TIMER5,6 that support DMA */
# define GD32_NUSART 8 /* USART0-2 and 5, UART 3,4 and 6,7 */
# define GD32_NI2C 3 /* I2C0-2 */
# define GD32_NSPI 6 /* SPI0-5 */
# define GD32_NI2S 2 /* I2S1-2 (multiplexed with SPI1-2) */
# define GD32_NDCI 1 /* Digital camera interface (DCI) */
# define GD32_NTLI 1 /* TFT-LCD interface (TLI) */
# define GD32_NSDIO 1 /* Secure digital input/output interface */
# define GD32_NEXMC 1 /* External memory controller */
# define GD32_NCAN 2 /* CAN0-1 */
# define GD32_NETHERNET 1 /* 10/100 Ethernet MAC */
# define GD32_NUSBFS 1 /* USB FS*/
# define GD32_NUSBHS 1 /* USB HS*/
#else
# error "Unknown GD32F4 chip type"
#endif
/* Get customizations for each supported chip and provide alternate function
* pin-mapping
*
* NOTE: Each GPIO pin may serve either for general purpose I/O or for a
* special alternate function (such as USART, CAN, USB, SDIO, etc.). That
* particular pin-mapping will depend on the package and GD32 family. If
* you are incorporating a new GD32 chip into NuttX, you will need to add
* the pin-mapping to a header file and to include that header file below.
* The chip-specific pin-mapping is defined in the chip datasheet.
*/
/* NVIC priority levels *****************************************************/
#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits set in minimum priority */
#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
#define NVIC_SYSH_PRIORITY_STEP 0x10 /* Four bits of interrupt priority used */
#endif /* __ARCH_ARM_INCLUDE_GD32F4_CHIP_H */
arch/arm/include/gd32f4/gd32f4xx_irq.h
+249
View File
@@ -0,0 +1,249 @@
/****************************************************************************
* arch/arm/include/gd32f4/gd32f4xx_irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_GD32_GD32F4XX_IRQ_H
#define __ARCH_ARM_INCLUDE_GD32_GD32F4XX_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* IRQ numbers.
* The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in
* the IRQ to handle mapping tables.
*
* Processor Exceptions (vectors 0-15). These common definitions can
* be found in nuttx/arch/arm/include/gd32/irq.h
*
* External interrupts (vectors >= 16)
*/
#define GD32_IRQ_WWDGT (GD32_IRQ_EXINT+0) /* 0: window watchdog timer interrupt */
#define GD32_IRQ_LVD (GD32_IRQ_EXINT+1) /* 1: LVD through EXTI line detect interrupt */
#define GD32_IRQ_TAMPER_STAMP (GD32_IRQ_EXINT+2) /* 2: tamper and timestamp through EXTI line detect */
#define GD32_IRQ_RTC_WKUP (GD32_IRQ_EXINT+3) /* 3: RTC wakeup through EXTI line interrupt */
#define GD32_IRQ_FMC (GD32_IRQ_EXINT+4) /* 4: FMC interrupt */
#define GD32_IRQ_RCU_CTC (GD32_IRQ_EXINT+5) /* 5: RCU and CTC interrupt */
#define GD32_IRQ_EXTI0 (GD32_IRQ_EXINT+6) /* 6: EXTI Line 0 interrupt */
#define GD32_IRQ_EXTI1 (GD32_IRQ_EXINT+7) /* 7: EXTI Line 1 interrupt */
#define GD32_IRQ_EXTI2 (GD32_IRQ_EXINT+8) /* 8: EXTI Line 2 interrupt */
#define GD32_IRQ_EXTI3 (GD32_IRQ_EXINT+9) /* 9: EXTI Line 3 interrupt */
#define GD32_IRQ_EXTI4 (GD32_IRQ_EXINT+10) /* 10: EXTI Line 4 interrupt */
#define GD32_IRQ_DMA0_CHANNEL0 (GD32_IRQ_EXINT+11) /* 11: DMA0 channel0 Interrupt */
#define GD32_IRQ_DMA0_CHANNEL1 (GD32_IRQ_EXINT+12) /* 12: DMA0 channel1 Interrupt */
#define GD32_IRQ_DMA0_CHANNEL2 (GD32_IRQ_EXINT+13) /* 13: DMA0 channel2 Interrupt */
#define GD32_IRQ_DMA0_CHANNEL3 (GD32_IRQ_EXINT+14) /* 14: DMA0 channel3 Interrupt */
#define GD32_IRQ_DMA0_CHANNEL4 (GD32_IRQ_EXINT+15) /* 15: DMA0 channel4 Interrupt */
#define GD32_IRQ_DMA0_CHANNEL5 (GD32_IRQ_EXINT+16) /* 16: DMA0 channel5 Interrupt */
#define GD32_IRQ_DMA0_CHANNEL6 (GD32_IRQ_EXINT+17) /* 17: DMA0 channel6 Interrupt */
#define GD32_IRQ_ADC (GD32_IRQ_EXINT+18) /* 18: ADC interrupt */
#define GD32_IRQ_CAN0_TX (GD32_IRQ_EXINT+19) /* 19: CAN0 TX interrupt */
#define GD32_IRQ_CAN0_RX0 (GD32_IRQ_EXINT+20) /* 20: CAN0 RX0 interrupt */
#define GD32_IRQ_CAN0_RX1 (GD32_IRQ_EXINT+21) /* 21: CAN0 RX1 interrupt */
#define GD32_IRQ_CAN0_EWMC (GD32_IRQ_EXINT+22) /* 22: CAN0 EWMC interrupt */
#define GD32_IRQ_EXTI5_9 (GD32_IRQ_EXINT+23) /* 23: EXTI[9:5] interrupts */
#define GD32_IRQ_TIMER0_BRK_TIMER8 (GD32_IRQ_EXINT+24) /* 24: TIMER0 break and TIMER8 interrupts */
#define GD32_IRQ_TIMER0_UP_TIMER9 (GD32_IRQ_EXINT+25) /* 25: TIMER0 update and TIMER9 interrupts */
#define GD32_IRQ_TIMER0_TRG_CMT_TIMER10 (GD32_IRQ_EXINT+26) /* 26: TIMER0 trigger and commutation and TIMER10 interrupts */
#define GD32_IRQ_TIMER0_CHANNEL (GD32_IRQ_EXINT+27) /* 27: TIMER0 channel capture compare interrupt */
#define GD32_IRQ_TIMER1 (GD32_IRQ_EXINT+28) /* 28: TIMER1 interrupt */
#define GD32_IRQ_TIMER2 (GD32_IRQ_EXINT+29) /* 29: TIMER2 interrupt */
#define GD32_IRQ_TIMER3 (GD32_IRQ_EXINT+30) /* 30: TIMER3 interrupt */
#define GD32_IRQ_I2C0_EV (GD32_IRQ_EXINT+31) /* 31: I2C0 event interrupt */
#define GD32_IRQ_I2C0_ER (GD32_IRQ_EXINT+32) /* 32: I2C0 error interrupt */
#define GD32_IRQ_I2C1_EV (GD32_IRQ_EXINT+33) /* 33: I2C1 event interrupt */
#define GD32_IRQ_I2C1_ER (GD32_IRQ_EXINT+34) /* 34: I2C1 error interrupt */
#define GD32_IRQ_SPI0 (GD32_IRQ_EXINT+35) /* 35: SPI0 interrupt */
#define GD32_IRQ_SPI1 (GD32_IRQ_EXINT+36) /* 36: SPI1 interrupt */
#define GD32_IRQ_USART0 (GD32_IRQ_EXINT+37) /* 37: USART0 interrupt */
#define GD32_IRQ_USART1 (GD32_IRQ_EXINT+38) /* 38: USART1 interrupt */
#define GD32_IRQ_USART2 (GD32_IRQ_EXINT+39) /* 39: USART2 interrupt */
#define GD32_IRQ_EXTI10_15 (GD32_IRQ_EXINT+40) /* 40: EXTI[15:10] interrupts */
#define GD32_IRQ_RTC_Alarm (GD32_IRQ_EXINT+41) /* 41: RTC alarm interrupt */
#define GD32_IRQ_USBFS_WKUP (GD32_IRQ_EXINT+42) /* 42: USBFS wakeup interrupt */
#define GD32_IRQ_TIMER7_BRK_TIMER11 (GD32_IRQ_EXINT+43) /* 43: TIMER7 break and TIMER11 interrupts */
#define GD32_IRQ_TIMER7_UP_TIMER12 (GD32_IRQ_EXINT+44) /* 44: TIMER7 update and TIMER12 interrupts */
#define GD32_IRQ_TIMER7_TRG_CMT_TIMER13 (GD32_IRQ_EXINT+45) /* 45: TIMER7 trigger and commutation and TIMER13 interrupts */
#define GD32_IRQ_TIMER7_CHANNEL (GD32_IRQ_EXINT+46) /* 46: TIMER7 channel capture compare interrupt */
#define GD32_IRQ_DMA0_CHANNEL7 (GD32_IRQ_EXINT+47) /* 47: DMA0 channel7 interrupt */
#if defined(CONFIG_GD32F4_GD32F450)
#define GD32_IRQ_EXMC (GD32_IRQ_EXINT+48) /* 48: EXMC interrupt */
#define GD32_IRQ_SDIO (GD32_IRQ_EXINT+49) /* 49: SDIO interrupt */
#define GD32_IRQ_TIMER4 (GD32_IRQ_EXINT+50) /* 50: TIMER4 interrupt */
#define GD32_IRQ_SPI2 (GD32_IRQ_EXINT+51) /* 51: SPI2 interrupt */
#define GD32_IRQ_UART3 (GD32_IRQ_EXINT+52) /* 52: UART3 interrupt */
#define GD32_IRQ_UART4 (GD32_IRQ_EXINT+53) /* 53: UART4 interrupt */
#define GD32_IRQ_TIMER5_DAC (GD32_IRQ_EXINT+54) /* 54: TIMER5 and DAC0 DAC1 underrun error interrupts */
#define GD32_IRQ_TIMER6 (GD32_IRQ_EXINT+55) /* 55: TIMER6 interrupt */
#define GD32_IRQ_DMA1_CHANNEL0 (GD32_IRQ_EXINT+56) /* 56: DMA1 channel0 interrupt */
#define GD32_IRQ_DMA1_CHANNEL1 (GD32_IRQ_EXINT+57) /* 57: DMA1 channel1 interrupt */
#define GD32_IRQ_DMA1_CHANNEL2 (GD32_IRQ_EXINT+58) /* 58: DMA1 channel2 interruptt */
#define GD32_IRQ_DMA1_CHANNEL3 (GD32_IRQ_EXINT+59) /* 59: DMA1 channel3 interrupt */
#define GD32_IRQ_DMA1_CHANNEL4 (GD32_IRQ_EXINT+60) /* 60: DMA1 channel4 interrupt */
#define GD32_IRQ_ENET (GD32_IRQ_EXINT+61) /* 61: ENET interrupt */
#define GD32_IRQ_ENET_WKUP (GD32_IRQ_EXINT+62) /* 62: ENET wakeup interrupt */
#define GD32_IRQ_CAN1_TX (GD32_IRQ_EXINT+63) /* 63: CAN1 TX interrupt */
#define GD32_IRQ_CAN1_RX0 (GD32_IRQ_EXINT+64) /* 64: CAN1 RX0 interrupt */
#define GD32_IRQ_CAN1_RX1 (GD32_IRQ_EXINT+65) /* 65: CAN1 RX1 interrupt */
#define GD32_IRQ_CAN1_EWMC (GD32_IRQ_EXINT+66) /* 66: CAN1 EWMC interrupt */
#define GD32_IRQ_USBFS (GD32_IRQ_EXINT+67) /* 67: USBFS interrupt */
#define GD32_IRQ_DMA1_CHANNEL5 (GD32_IRQ_EXINT+68) /* 68: DMA1 channel5 interrupt */
#define GD32_IRQ_DMA1_CHANNEL6 (GD32_IRQ_EXINT+69) /* 69: DMA1 channel6 interrupt */
#define GD32_IRQ_DMA1_CHANNEL7 (GD32_IRQ_EXINT+70) /* 70: DMA1 channel7 interrupt */
#define GD32_IRQ_USART5 (GD32_IRQ_EXINT+71) /* 71: USART5 interrupt */
#define GD32_IRQ_I2C2_EV (GD32_IRQ_EXINT+72) /* 72: I2C2 event interrupt */
#define GD32_IRQ_I2C2_ER (GD32_IRQ_EXINT+73) /* 73: I2C2 error interrupt */
#define GD32_IRQ_USBHS_EP1_Out (GD32_IRQ_EXINT+74) /* 74: USBHS endpoint 1 out interrupt */
#define GD32_IRQ_USBHS_EP1_In (GD32_IRQ_EXINT+75) /* 75: USBHS endpoint 1 in interrupt */
#define GD32_IRQ_USBHS_WKUP (GD32_IRQ_EXINT+76) /* 76: USBHS wakeup through EXTI line interrupt */
#define GD32_IRQ_USBHS (GD32_IRQ_EXINT+77) /* 77: USBHS interrupt */
#define GD32_IRQ_DCI (GD32_IRQ_EXINT+78) /* 78: DCI interrupt */
#define GD32_IRQ_TRNG (GD32_IRQ_EXINT+80) /* 80: TRNG interrupt */
#define GD32_IRQ_FPU (GD32_IRQ_EXINT+81) /* 81: FPU interrupt */
#define GD32_IRQ_UART6 (GD32_IRQ_EXINT+82) /* 82: UART6 interrupt */
#define GD32_IRQ_UART7 (GD32_IRQ_EXINT+83) /* 83: UART7 interrupt */
#define GD32_IRQ_SPI3 (GD32_IRQ_EXINT+84) /* 84: SPI3 interrupt */
#define GD32_IRQ_SPI4 (GD32_IRQ_EXINT+85) /* 85: SPI4 interrupt */
#define GD32_IRQ_SPI5 (GD32_IRQ_EXINT+86) /* 86: SPI5 interrupt */
#define GD32_IRQ_TLI (GD32_IRQ_EXINT+88) /* 88: TLI interrupt */
#define GD32_IRQ_TLI_ER (GD32_IRQ_EXINT+89) /* 89: TLI error interrupt */
#define GD32_IRQ_IPA (GD32_IRQ_EXINT+90) /* 90: IPA interrupt */
#elif defined(CONFIG_GD32F4_GD32F407)
#define GD32_IRQ_EXMC (GD32_IRQ_EXINT+48) /* 48: EXMC interrupt */
#define GD32_IRQ_SDIO (GD32_IRQ_EXINT+49) /* 49: SDIO interrupt */
#define GD32_IRQ_TIMER4 (GD32_IRQ_EXINT+50) /* 50: TIMER4 interrupt */
#define GD32_IRQ_SPI2 (GD32_IRQ_EXINT+51) /* 51: SPI2 interrupt */
#define GD32_IRQ_UART3 (GD32_IRQ_EXINT+52) /* 52: UART3 interrupt */
#define GD32_IRQ_UART4 (GD32_IRQ_EXINT+53) /* 53: UART4 interrupt */
#define GD32_IRQ_TIMER5_DAC (GD32_IRQ_EXINT+54) /* 54: TIMER5 and DAC0 DAC1 underrun error interrupts */
#define GD32_IRQ_TIMER6 (GD32_IRQ_EXINT+55) /* 55: TIMER6 interrupt */
#define GD32_IRQ_DMA1_CHANNEL0 (GD32_IRQ_EXINT+56) /* 56: DMA1 channel0 interrupt */
#define GD32_IRQ_DMA1_CHANNEL1 (GD32_IRQ_EXINT+57) /* 57: DMA1 channel1 interrupt */
#define GD32_IRQ_DMA1_CHANNEL2 (GD32_IRQ_EXINT+58) /* 58: DMA1 channel2 interruptt */
#define GD32_IRQ_DMA1_CHANNEL3 (GD32_IRQ_EXINT+59) /* 59: DMA1 channel3 interrupt */
#define GD32_IRQ_DMA1_CHANNEL4 (GD32_IRQ_EXINT+60) /* 60: DMA1 channel4 interrupt */
#define GD32_IRQ_ENET (GD32_IRQ_EXINT+61) /* 61: ENET interrupt */
#define GD32_IRQ_ENET_WKUP (GD32_IRQ_EXINT+62) /* 62: ENET wakeup interrupt */
#define GD32_IRQ_CAN1_TX (GD32_IRQ_EXINT+63) /* 63: CAN1 TX interrupt */
#define GD32_IRQ_CAN1_RX0 (GD32_IRQ_EXINT+64) /* 64: CAN1 RX0 interrupt */
#define GD32_IRQ_CAN1_RX1 (GD32_IRQ_EXINT+65) /* 65: CAN1 RX1 interrupt */
#define GD32_IRQ_CAN1_EWMC (GD32_IRQ_EXINT+66) /* 66: CAN1 EWMC interrupt */
#define GD32_IRQ_USBFS (GD32_IRQ_EXINT+67) /* 67: USBFS interrupt */
#define GD32_IRQ_DMA1_CHANNEL5 (GD32_IRQ_EXINT+68) /* 68: DMA1 channel5 interrupt */
#define GD32_IRQ_DMA1_CHANNEL6 (GD32_IRQ_EXINT+69) /* 69: DMA1 channel6 interrupt */
#define GD32_IRQ_DMA1_CHANNEL7 (GD32_IRQ_EXINT+70) /* 70: DMA1 channel7 interrupt */
#define GD32_IRQ_USART5 (GD32_IRQ_EXINT+71) /* 71: USART5 interrupt */
#define GD32_IRQ_I2C2_EV (GD32_IRQ_EXINT+72) /* 72: I2C2 event interrupt */
#define GD32_IRQ_I2C2_ER (GD32_IRQ_EXINT+73) /* 73: I2C2 error interrupt */
#define GD32_IRQ_USBHS_EP1_Out (GD32_IRQ_EXINT+74) /* 74: USBHS endpoint 1 out interrupt */
#define GD32_IRQ_USBHS_EP1_In (GD32_IRQ_EXINT+75) /* 75: USBHS endpoint 1 in interrupt */
#define GD32_IRQ_USBHS_WKUP (GD32_IRQ_EXINT+76) /* 76: USBHS wakeup through EXTI line interrupt */
#define GD32_IRQ_USBHS (GD32_IRQ_EXINT+77) /* 77: USBHS interrupt */
#define GD32_IRQ_DCI (GD32_IRQ_EXINT+78) /* 78: DCI interrupt */
#define GD32_IRQ_TRNG (GD32_IRQ_EXINT+80) /* 80: TRNG interrupt */
#define GD32_IRQ_FPU (GD32_IRQ_EXINT+81) /* 81: FPU interrupt */
#elif defined(CONFIG_GD32F4_GD32F405)
#define GD32_IRQ_SDIO (GD32_IRQ_EXINT+49) /* 49: SDIO interrupt */
#define GD32_IRQ_TIMER4 (GD32_IRQ_EXINT+50) /* 50: TIMER4 interrupt */
#define GD32_IRQ_SPI2 (GD32_IRQ_EXINT+51) /* 51: SPI2 interrupt */
#define GD32_IRQ_UART3 (GD32_IRQ_EXINT+52) /* 52: UART3 interrupt */
#define GD32_IRQ_UART4 (GD32_IRQ_EXINT+53) /* 53: UART4 interrupt */
#define GD32_IRQ_TIMER5_DAC (GD32_IRQ_EXINT+54) /* 54: TIMER5 and DAC0 DAC1 underrun error interrupts */
#define GD32_IRQ_TIMER6 (GD32_IRQ_EXINT+55) /* 55: TIMER6 interrupt */
#define GD32_IRQ_DMA1_CHANNEL0 (GD32_IRQ_EXINT+56) /* 56: DMA1 channel0 interrupt */
#define GD32_IRQ_DMA1_CHANNEL1 (GD32_IRQ_EXINT+57) /* 57: DMA1 channel1 interrupt */
#define GD32_IRQ_DMA1_CHANNEL2 (GD32_IRQ_EXINT+58) /* 58: DMA1 channel2 interruptt */
#define GD32_IRQ_DMA1_CHANNEL3 (GD32_IRQ_EXINT+59) /* 59: DMA1 channel3 interrupt */
#define GD32_IRQ_DMA1_CHANNEL4 (GD32_IRQ_EXINT+60) /* 60: DMA1 channel4 interrupt */
#define GD32_IRQ_CAN1_TX (GD32_IRQ_EXINT+63) /* 63: CAN1 TX interrupt */
#define GD32_IRQ_CAN1_RX0 (GD32_IRQ_EXINT+64) /* 64: CAN1 RX0 interrupt */
#define GD32_IRQ_CAN1_RX1 (GD32_IRQ_EXINT+65) /* 65: CAN1 RX1 interrupt */
#define GD32_IRQ_CAN1_EWMC (GD32_IRQ_EXINT+66) /* 66: CAN1 EWMC interrupt */
#define GD32_IRQ_USBFS (GD32_IRQ_EXINT+67) /* 67: USBFS interrupt */
#define GD32_IRQ_DMA1_CHANNEL5 (GD32_IRQ_EXINT+68) /* 68: DMA1 channel5 interrupt */
#define GD32_IRQ_DMA1_CHANNEL6 (GD32_IRQ_EXINT+69) /* 69: DMA1 channel6 interrupt */
#define GD32_IRQ_DMA1_CHANNEL7 (GD32_IRQ_EXINT+70) /* 70: DMA1 channel7 interrupt */
#define GD32_IRQ_USART5 (GD32_IRQ_EXINT+71) /* 71: USART5 interrupt */
#define GD32_IRQ_I2C2_EV (GD32_IRQ_EXINT+72) /* 72: I2C2 event interrupt */
#define GD32_IRQ_I2C2_ER (GD32_IRQ_EXINT+73) /* 73: I2C2 error interrupt */
#define GD32_IRQ_USBHS_EP1_Out (GD32_IRQ_EXINT+74) /* 74: USBHS endpoint 1 out interrupt */
#define GD32_IRQ_USBHS_EP1_In (GD32_IRQ_EXINT+75) /* 75: USBHS endpoint 1 in interrupt */
#define GD32_IRQ_USBHS_WKUP (GD32_IRQ_EXINT+76) /* 76: USBHS wakeup through EXTI line interrupt */
#define GD32_IRQ_USBHS (GD32_IRQ_EXINT+77) /* 77: USBHS interrupt */
#define GD32_IRQ_DCI (GD32_IRQ_EXINT+78) /* 78: DCI interrupt */
#define GD32_IRQ_TRNG (GD32_IRQ_EXINT+80) /* 80: TRNG interrupt */
#define GD32_IRQ_FPU (GD32_IRQ_EXINT+81) /* 81: FPU interrupt */
#else
#error "Unkonwn GD32F4xx chip."
#endif /* CONFIG_GD32F4_GD32F450 */
#if defined(CONFIG_GD32F4_GD32F450)
# define GD32_IRQ_NEXTINT (91)
# define NR_IRQS (GD32_IRQ_EXINT + GD32_IRQ_NEXTINT)
#elif defined(CONFIG_GD32F4_GD32F407)
# define GD32_IRQ_NEXTINT (82)
# define NR_IRQS (GD32_IRQ_EXINT + GD32_IRQ_NEXTINT)
#elif defined(CONFIG_GD32F4_GD32F405)
# define GD32_IRQ_NEXTINT (82)
# define NR_IRQS (GD32_IRQ_EXINT + GD32_IRQ_NEXTINT)
#else
# error "Unknown GD32F4xx chip!"
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_GD32_GD32F4XX_IRQ_H */
arch/arm/include/gd32f4/irq.h
+105
View File
@@ -0,0 +1,105 @@
/****************************************************************************
* arch/arm/include/gd32f4/irq.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/* This file should never be included directly but, rather,
* only indirectly through nuttx/irq.h
*/
#ifndef __ARCH_ARM_INCLUDE_GD32F4_IRQ_H
#define __ARCH_ARM_INCLUDE_GD32F4_IRQ_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include <arch/gd32f4/chip.h>
/****************************************************************************
* Pre-processor Prototypes
****************************************************************************/
/* IRQ numbers.
* The IRQ number corresponds vector number and hence map directly to
* bits in the NVIC. This does, however, waste several words of memory in
* the IRQ to handle mapping tables.
*/
/* Processor Exceptions (vectors 0-15) */
#define GD32_IRQ_RESERVED (0) /* Reserved vector (only used with CONFIG_DEBUG_FEATURES) */
/* Vector 0: Reset stack pointer value */
/* Vector 1: Reset (not handler as an IRQ) */
#define GD32_IRQ_NMI (2) /* Vector 2: Non-Maskable Interrupt (NMI) */
#define GD32_IRQ_HARDFAULT (3) /* Vector 3: Hard fault */
#define GD32_IRQ_MEMFAULT (4) /* Vector 4: Memory management (MPU) */
#define GD32_IRQ_BUSFAULT (5) /* Vector 5: Bus fault */
#define GD32_IRQ_USAGEFAULT (6) /* Vector 6: Usage fault */
#define GD32_IRQ_SVCALL (11) /* Vector 11: SVC call */
#define GD32_IRQ_DBGMONITOR (12) /* Vector 12: Debug Monitor */
/* Vector 13: Reserved */
#define GD32_IRQ_PENDSV (14) /* Vector 14: Pendable system service request */
#define GD32_IRQ_SYSTICK (15) /* Vector 15: System tick */
/* External interrupts (vectors >= 16).
* These definitions are chip-specific
*/
#define GD32_IRQ_EXINT (16) /* Vector number of the first external interrupt */
/****************************************************************************
* Included Files
****************************************************************************/
#if defined(CONFIG_GD32F4_GD32F4XX)
# include <arch/gd32f4/gd32f4xx_irq.h>
#else
# error "Uknown GD32 chip"
#endif
/****************************************************************************
* Public Types
****************************************************************************/
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#ifdef __cplusplus
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#undef EXTERN
#ifdef __cplusplus
}
#endif
#endif
#endif /* __ARCH_ARM_INCLUDE_GD32F4_IRQ_H */
arch/arm/src/gd32f4/Kconfig
+2501
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/Make.defs
+57
View File
@@ -0,0 +1,57 @@
############################################################################
# arch/arm/src/gd32f4/Make.defs
#
# Licensed to the Apache Software Foundation (ASF) under one or more
# contributor license agreements. See the NOTICE file distributed with
# this work for additional information regarding copyright ownership. The
# ASF licenses this file to you under the Apache License, Version 2.0 (the
# "License"); you may not use this file except in compliance with the
# License. You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
# WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
# License for the specific language governing permissions and limitations
# under the License.
#
############################################################################
include armv7-m/Make.defs
CHIP_CSRCS = gd32f4xx_allocateheap.c gd32f4xx_start.c gd32f4xx_rcu.c
CHIP_CSRCS += gd32f4xx_serial.c gd32f4xx_lowputc.c
CHIP_CSRCS += gd32f4xx_gpio.c gd32f4xx_syscfg.c
CHIP_CSRCS += gd32f4xx_irq.c gd32f4xx_exti.c
CHIP_CSRCS += gd32f4xx_dma.c
ifneq ($(CONFIG_SCHED_TICKLESS),y)
CHIP_CSRCS += gd32f4xx_timerisr.c
else
CHIP_CSRCS += gd32f4xx_tickless.c
endif
ifneq ($(CONFIG_ARCH_IDLE_CUSTOM),y)
CHIP_CSRCS += gd32f4xx_idle.c
endif
#ifneq ($(CONFIG_ARCH_CUSTOM_PMINIT),y)
#CHIP_CSRCS += gd32f4xx_pminitialize.c
#endif
#ifneq ($(CONFIG_GD32F4_PROGMEM),y)
CHIP_CSRCS += gd32f4xx_fmc.c gd32f4xx_progmem.c
#endif
ifeq ($(CONFIG_GD32F4_ENETMAC),y)
CHIP_CSRCS += gd32f4xx_enet.c
endif
ifeq ($(CONFIG_GD32F4_PMU),y)
CHIP_CSRCS += gd32f4xx_pmu.c
endif
ifeq ($(CONFIG_GD32F4_SPI),y)
CHIP_CSRCS += gd32f4xx_spi.c
endif
arch/arm/src/gd32f4/chip.h
+57
View File
@@ -0,0 +1,57 @@
/****************************************************************************
* arch/arm/src/gd32f4/chip.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_CHIP_H
#define __ARCH_ARM_SRC_GD32F4_CHIP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* Include the chip capabilities file */
#include <arch/gd32f4/chip.h>
/* Include the chip interrupt definition file */
#include <arch/gd32f4/irq.h>
/* Include the chip memory map */
#include "hardware/gd32f4xx_memorymap.h"
/* Include the chip pinmap */
#include "hardware/gd32f4xx_pinmap.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Provide the required number of peripheral interrupt vector definitions as
* well. The definition GD32_IRQ_NEXTINT simply comes from the chip-specific
* IRQ header file included by arch/gd32f4/irq.h.
*/
#define ARMV7M_PERIPHERAL_INTERRUPTS GD32_IRQ_NEXTINT
#endif /* __ARCH_ARM_SRC_GD32F4_CHIP_H */
arch/arm/src/gd32f4/gd32f4xx.h
+50
View File
@@ -0,0 +1,50 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include "arm_internal.h"
/* Peripherals **************************************************************/
#include "chip.h"
#include "gd32f4xx_exti.h"
#include "gd32f4xx_enet.h"
#include "gd32f4xx_dma.h"
#include "gd32f4xx_gpio.h"
#include "gd32f4xx_rcu.h"
#include "gd32f4xx_usart.h"
#include "gd32f4xx_lowputc.h"
#include "gd32f4xx_fmc.h"
#include "gd32f4xx_pmu.h"
#include "gd32f4xx_spi.h"
#include "gd32f4xx_syscfg.h"
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_H */
arch/arm/src/gd32f4/gd32f4xx_allocateheap.c
+395
View File
@@ -0,0 +1,395 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_allocateheap.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <string.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/kmalloc.h>
#include <nuttx/userspace.h>
#include <arch/board/board.h>
#include "chip.h"
#include "mpu.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The GD32F4xx all contains System SRAM and tightly-coupled memory
* SRAM (TCMSRAM) on the chip.
* The following definitions must be provided to specify the size and
* location of System SRAM:
*
* CONFIG_RAM_END : SRAM end address
*
* The TCMSRAM is different to SRAM, and it be accessed only by the data
* bus of the Cortex®-M4 core, and can not be used for DMA. When used DMA,
* then the following should be defined to exclude TCMSRAM from the heap:
*
* CONFIG_GD32F4_TCMEXCLUDE : Exclude TCMSRAM from the HEAP
*
* In addition to internal SRAM, external RAM may also be available through
* the EXMC. When external RAM is want to be used, then the following
* definitions should to be provided:
*
* CONFIG_GD32F4_EXMC=y : Enable the EXMC
* CONFIG_GD32F4_EXTERNAL_RAM=y : Indicates that via the EXMC, external
* RAM can be used.
* CONFIG_HEAP2_BASE : External RAM base address
* CONFIG_HEAP2_SIZE : External RAM size
* CONFIG_MM_REGIONS : Must be set to the value match to how
* many RAMs you have used.
*/
#if !defined(CONFIG_GD32F4_EXMC)
# undef CONFIG_GD32F4_EXTERNAL_RAM
#endif
/* The heap is in one contiguous block starting at g_idle_topstack and
* extending through CONFIG_RAM_END.
*/
#if defined(CONFIG_GD32F4_GD32F4XX)
/* Set the end of system SRAM */
# if defined(CONFIG_GD32F4_GD32F450)
# if defined(CONFIG_GD32F4_GD32F450XI)
# define SRAM_END 0x20070000
# else
# define SRAM_END 0x20030000
# endif
# else
# define SRAM_END 0x20020000
# endif
/* Set the range of TCMSRAM */
# define TCMSRAM_START 0x10000000
# define TCMSRAM_END 0x10010000
/* There are 4 possible SRAM configuration case:
*
* Case 0. System SRAM
* CONFIG_MM_REGIONS define as 1
* CONFIG_GD32F4_TCMEXCLUDE defined, not use TCMSRAM
* CONFIG_GD32F4_EXTERNAL_RAM NOT defined
*
* Case 1. System SRAM and TCM SRAM
* CONFIG_MM_REGIONS define as 2
* CONFIG_GD32F4_TCMEXCLUDE NOT defined, use TCMSRAM
* CONFIG_GD32F4_EXTERNAL_RAM NOT defined
*
* Case 2. System SRAM and EXMC SRAM
* CONFIG_MM_REGIONS define as 2
* CONFIG_GD32F4_TCMEXCLUDE defined, not use TCMSRAM
* CONFIG_GD32F4_EXTERNAL_RAM defined
*
* Case 3. System SRAM, CCM SRAM, and EXMC SRAM
* CONFIG_MM_REGIONS define as 3
* CONFIG_GD32F4_TCMEXCLUDE NOT defined, use TCMSRAM
* CONFIG_GD32F4_EXTERNAL_RAM defined
*
* Make sure that all definitions are consistent before doing anything else
*/
# if CONFIG_MM_REGIONS < 1
# error "There is at least one memory region"
# define CONFIG_MM_REGIONS 1
# undef CONFIG_GD32F4_EXTERNAL_RAM
# undef CONFIG_GD32F4_TCMEXCLUDE
# define CONFIG_GD32F4_TCMEXCLUDE 1
# elif CONFIG_MM_REGIONS < 2
/* Only one memory region. Force Case 0 */
# warning "EXMC SRAM (and TCMSRAM) excluded from the heap"
# undef CONFIG_GD32F4_EXTERNAL_RAM
# undef CONFIG_GD32F4_TCMEXCLUDE
# define CONFIG_GD32F4_TCMEXCLUDE 1
# elif CONFIG_MM_REGIONS < 3
/* Two memory regions. Case 1 or 2 */
# if !defined(CONFIG_GD32F4_TCMEXCLUDE) && defined(CONFIG_GD32F4_EXTERNAL_RAM)
# error "Can not support both TCM SRAM and EXMC SRAM, when CONFIG_MM_REGIONS is 2 "
# undef CONFIG_GD32F4_TCMEXCLUDE
# define CONFIG_GD32F4_TCMEXCLUDE 1
# endif
/* Case 1, TCMSRAM is used. In this case, DMA should not be used */
# if !defined(CONFIG_GD32F4_TCMEXCLUDE)
# ifdef CONFIG_ARCH_DMA
# error "TCMSRAM is included in the heap AND DMA is enabled"
# endif
# endif
# elif CONFIG_MM_REGIONS == 3
/* Three memory regions. Case 3 */
# ifdef CONFIG_ARCH_DMA
# error "TCM SRAM is included in the heap AND DMA is enabled"
# endif
# else
# error "CONFIG_MM_REGIONS > 3 but there no more region(s) are other than SRAM, TCMSRAM and EXMC RAM"
# undef CONFIG_MM_REGIONS
# define CONFIG_MM_REGIONS 3
# endif /* CONFIG_MM_REGIONS */
#else
# error "Unsupported GD32 chip"
#endif
/* If EXMC SRAM is going to be used as heap, then verify that the starting
* address and size of the external SRAM region has been provided in the
* configuration (as CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE).
*/
#ifdef CONFIG_GD32F4_EXTERNAL_RAM
# if !defined(CONFIG_HEAP2_BASE) || !defined(CONFIG_HEAP2_SIZE)
# error "When use EXMC RAM CONFIG_HEAP2_BASE and CONFIG_HEAP2_SIZE must be provided"
# undef CONFIG_GD32F4_EXTERNAL_RAM
# endif
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_heap_color
*
* Description:
* Set heap memory to a known, non-zero state to checking heap usage.
*
****************************************************************************/
#ifdef CONFIG_HEAP_COLORATION
static inline void up_heap_color(void *start, size_t size)
{
memset(start, HEAP_COLOR, size);
}
#else
# define up_heap_color(start,size)
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_allocate_heap
*
* Description:
* This function will be called to dynamically set aside the heap region.
*
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function provides the
* size of the unprotected, user-space heap.
*
* If a protected kernel-space heap is provided, the kernel heap must be
* allocated (and protected) by an analogous up_allocate_kheap().
*
* The following memory map is assumed for the flat build:
*
* .data region. Size determined at link time.
* .bss region Size determined at link time.
* IDLE thread stack. Size determined by CONFIG_IDLETHREAD_STACKSIZE.
* Heap. Extends to the end of SRAM.
*
* The following memory map is assumed for the kernel build:
*
* Kernel .data region Size determined at link time
* Kernel .bss region Size determined at link time
* Kernel IDLE thread stack Size determined by
* CONFIG_IDLETHREAD_STACKSIZE
* Padding for alignment
* User .data region Size determined at link time
* User .bss region Size determined at link time
* Kernel heap Size determined by
* CONFIG_MM_KERNEL_HEAPSIZE
* User heap Extends to the end of SRAM
*
****************************************************************************/
void up_allocate_heap(void **heap_start, size_t *heap_size)
{
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
usize = (1 << log2);
ubase = SRAM_END - usize;
/* Return the user-space heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)ubase;
*heap_size = usize;
/* Colorize the heap for debug */
up_heap_color((void *)ubase, usize);
/* Allow user-mode access to the user heap memory */
gd32_mpu_uheap((uintptr_t)ubase, usize);
#else
/* Return the heap settings */
board_autoled_on(LED_HEAPALLOCATE);
*heap_start = (void *)g_idle_topstack;
*heap_size = SRAM_END - g_idle_topstack;
/* Colorize the heap for debug */
up_heap_color(*heap_start, *heap_size);
#endif
}
/****************************************************************************
* Name: up_allocate_kheap
*
* Description:
* For the kernel build (CONFIG_BUILD_PROTECTED=y) with both kernel- and
* user-space heaps (CONFIG_MM_KERNEL_HEAP=y), this function allocates
* (and protects) the kernel-space heap.
*
****************************************************************************/
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
void up_allocate_kheap(void **heap_start, size_t *heap_size)
{
/* Get the unaligned size and position of the user-space heap.
* This heap begins after the user-space .bss section at an offset
* of CONFIG_MM_KERNEL_HEAPSIZE (subject to alignment).
*/
uintptr_t ubase = (uintptr_t)USERSPACE->us_bssend +
CONFIG_MM_KERNEL_HEAPSIZE;
size_t usize = SRAM_END - ubase;
int log2;
DEBUGASSERT(ubase < (uintptr_t)SRAM_END);
/* Adjust that size to account for MPU alignment requirements.
* NOTE that there is an implicit assumption that the SRAM_END
* is aligned to the MPU requirement.
*/
log2 = (int)mpu_log2regionfloor(usize);
usize = (1 << log2);
ubase = SRAM_END - usize;
/* Return the kernel heap settings (i.e., the part of the heap region
* that was not dedicated to the user heap).
*/
*heap_start = (void *)USERSPACE->us_bssend;
*heap_size = ubase - (uintptr_t)USERSPACE->us_bssend;
}
#endif
/****************************************************************************
* Name: arm_addregion
*
* Description:
* Memory may be added in non-contiguous chunks. Additional chunks are
* added by calling this function.
*
****************************************************************************/
#if CONFIG_MM_REGIONS > 1
void arm_addregion(void)
{
#ifndef CONFIG_GD32F4_TCMEXCLUDE
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the TCMSRAM heap */
gd32_mpu_uheap((uintptr_t)TCMSRAM_START, TCMSRAM_END - TCMSRAM_START);
#endif
/* Colorize the heap for debug */
up_heap_color((void *)TCMSRAM_START, TCMSRAM_END - TCMSRAM_START);
/* Add the TCMSRAM user heap region. */
kumm_addregion((void *)TCMSRAM_START, TCMSRAM_END - TCMSRAM_START);
#endif
#ifdef CONFIG_GD32F4_EXTERNAL_RAM
#if defined(CONFIG_BUILD_PROTECTED) && defined(CONFIG_MM_KERNEL_HEAP)
/* Allow user-mode access to the EXMC SRAM user heap memory */
gd32_mpu_uheap((uintptr_t)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
/* Colorize the heap for debug */
up_heap_color((void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
/* Add the external EXMC SRAM user heap region. */
kumm_addregion((void *)CONFIG_HEAP2_BASE, CONFIG_HEAP2_SIZE);
#endif
}
#endif
arch/arm/src/gd32f4/gd32f4xx_dma.c
+1051
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_dma.h
+262
View File
@@ -0,0 +1,262 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_DMA_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_DMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include "chip.h"
#include "hardware/gd32f4xx_dma.h"
/* The DMA transfer status definitions */
#define DMA_STATUS_ERROR (DMA_INTF_FEEIF | DMA_INTF_SDEIF | DMA_INTF_TAEIF)
#define DMA_STATUS_SUCCESS (DMA_INTF_HTFIF | DMA_INTF_FTFIF)
#define DMA_INTF_MASK (0x3f)
#define DMA_INT_MASK (DMA_CHXCTL_SDEIE | DMA_CHXCTL_TAEIE | DMA_CHXCTL_HTFIE | DMA_CHXCTL_FTFIE)
/* The DMA controllers */
#define GD32_DMA0 (GD32_DMA0_BASE)
#define GD32_DMA1 (GD32_DMA1_BASE)
/****************************************************************************
* Public Types
****************************************************************************/
/* DMA_HANDLE provides an opaque reference that can be used to represent a
* DMA channel.
*/
typedef void *DMA_HANDLE;
/* Description:
* This is the type of the callback that is used to inform the user of the
* completion of the DMA.
*
* Input Parameters:
* handle - Refers to the DMA channel or stream
* status - A bit encoded value that provides the completion status. See
* the DMASTATUS_* definitions above.
* arg - A user-provided value that was provided when gd32_dma_start()
* was called.
*/
typedef void (*dma_callback_t)(DMA_HANDLE handle, uint16_t status,
void *arg);
#ifdef CONFIG_DEBUG_DMA_INFO
struct gd32_dmaregs_s
{
uint32_t intf0;
uint32_t intf1;
uint32_t chctl;
uint32_t chcnt;
uint32_t chpaddr;
uint32_t chm0addr;
uint32_t chm1addr;
uint32_t chfctl;
};
#endif
/****************************************************************************
* Public Data
****************************************************************************/
/* DMA singledata mode initialize struct */
typedef struct
{
uint32_t periph_addr; /* Peripheral base address */
uint32_t memory0_addr; /* Memory 0 base address */
uint16_t number; /* Channel transfer number */
uint8_t periph_inc; /* Peripheral increasing mode */
uint8_t memory_inc; /* Memory increasing mode */
uint8_t periph_memory_width; /* Transfer data size of peripheral */
uint8_t circular_mode; /* DMA circular mode */
uint8_t direction; /* Channel data transfer direction */
uint8_t priority; /* Channel priority level */
} dma_single_data_parameter_struct;
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: gd32_dma_channel_alloc
*
* Description:
* Allocate a DMA channel. This function gives the caller mutually
* exclusive access to the DMA channel specified by the 'dmamap' argument.
* Should note that a DMA channel only can be used by on peripheral at the
* time.
*
* If the DMA channel is not available, then gd32_dma_channel_alloc() will
* wait until the holder of the channel relinquishes the channel by calling
* gd32_dma_channel_free().
*
* Input Parameters:
* periph_req - Identifies the DMA channle is request by which peripheral
*
* Returned Value:
* If periph_req is valid, this function ALWAYS returns a non-NULL
* void* DMA channel handle.
*
****************************************************************************/
DMA_HANDLE gd32_dma_channel_alloc(uint8_t periph_req);
/****************************************************************************
* Name: gd32_dma_channel_free
*
* Description:
* Release a DMA channel. If another thread is waiting for this DMA
* channel in a call to gd32_dma_channel_alloc, then this function will
* re-assign the DMA channel to that thread and wake it up.
* NOTE: The 'handle' used in this argument must NEVER be used again
* until gd32_dma_channel_alloc() is called again to re-gain access to
* the channel.
*
* Returned Value:
* None
*
* Assumptions:
* - The caller holds the DMA channel.
* - There is no DMA in progress
*
****************************************************************************/
void gd32_dma_channel_free(DMA_HANDLE handle);
/****************************************************************************
* Name: gd32_dma_setup
*
* Description:
* Configure DMA before using
*
****************************************************************************/
void gd32_dma_setup(DMA_HANDLE handle, void *arg, uint8_t data_mode);
/****************************************************************************
* Name: gd32_dma_start
*
* Description:
* Start the DMA transfer
*
* Assumptions:
* - DMA handle allocated by gd32_dma_channel_alloc()
* - No DMA in progress
*
****************************************************************************/
void gd32_dma_start(DMA_HANDLE handle, dma_callback_t callback, void *arg,
uint32_t interrupt);
/****************************************************************************
* Name: gd32_dma_stop
*
* Description:
* Cancel the DMA. After gd32_dma_stop() is called, the DMA channel is
* reset and gd32_dma_setup() must be called before gd32_dma_start()
* can be called again
*
* Assumptions:
* - DMA handle allocated by gd32_dma_channel_alloc()
*
****************************************************************************/
void gd32_dma_stop(DMA_HANDLE handle);
/****************************************************************************
* Name: gd32_dma_tansnum_get
*
* Description:
* Get the number of remaining data to be transferred by the DMA
*
* Assumptions:
* - DMA handle allocated by gd32_dma_channel_alloc()
*
****************************************************************************/
size_t gd32_dma_tansnum_get(DMA_HANDLE handle);
/****************************************************************************
* Name: gd32_dma_sample
*
* Description:
* Sample DMA register contents
*
* Assumptions:
* - DMA handle allocated by gd32_dma_channel_alloc()
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA_INFO
void gd32_dma_sample(DMA_HANDLE handle, struct gd32_dmaregs_s *regs);
#else
# define gd32_dma_sample(handle,regs)
#endif
/****************************************************************************
* Name: gd32_dma_dump
*
* Description:
* Dump previously sampled DMA register contents
*
* Assumptions:
* - DMA handle allocated by gd32_dma_channel_alloc()
*
****************************************************************************/
#ifdef CONFIG_DEBUG_DMA_INFO
void gd32_dma_dump(DMA_HANDLE handle, const struct gd32_dmaregs_s *regs,
const char *msg);
#else
# define gd32_dma_dump(handle,regs,msg)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_DMA_H */
arch/arm/src/gd32f4/gd32f4xx_enet.c
+3878
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_enet.h
+65
View File
@@ -0,0 +1,65 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_enet.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_ENET_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_ENET_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if GD32_NETHERNET > 0
#include "hardware/gd32f4xx_enet.h"
#ifndef __ASSEMBLY__
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Function: gd32_phy_boardinitialize
*
* Description:
* Some boards require specialized initialization of the PHY before it can
* be used. This may include such things as configuring GPIOs, resetting
* the PHY, etc. If CONFIG_GD32F4_PHYINIT is defined in the
* configuration then the board specific logic must provide
* gd32_phyinitialize(); The GD32F4 Ethernet driver will call this
* function one time before it first uses the PHY.
*
* Input Parameters:
* intf - Always zero for now.
*
* Returned Value:
* OK on success; Negated errno on failure.
*
****************************************************************************/
#ifdef CONFIG_GD32F4_PHY_INIT
int gd32_phy_boardinitialize(int intf);
#endif
#endif /* __ASSEMBLY__ */
#endif /* GD32_NETHERNET > 0 */
#endif /* __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_ENET_H */
arch/arm/src/gd32f4/gd32f4xx_exti.c
+621
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_exti.h
+235
View File
@@ -0,0 +1,235 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_exti.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_EXTI_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_EXTI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "hardware/gd32f4xx_exti.h"
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: gd32_exti_gpioirq_init
*
* Description:
* Initialize the EXTI gpio irq.
*
* Input Parameters:
* - cfgset: GPIO pin
* - exti_mode: interrupt or event mode
* - trig_type: interrupt trigger type
* - irqnum: pointer to GPIO pin irq number
*
****************************************************************************/
int gd32_exti_gpioirq_init(uint32_t cfgset, uint8_t exti_mode,
uint8_t trig_type, uint8_t *irqnum);
/****************************************************************************
* Name: gd32_exti_gpio_irq_attach
*
* Description:
* Attach the EXTI gpio irq handler.
*
* Input Parameters:
* - irqpin: GPIO irq pin
* - irqhandler: irq handler
* - arg: Argument passed to the interrupt callback
*
****************************************************************************/
int gd32_exti_gpio_irq_attach(uint8_t irqpin, xcpt_t irqhandler,
void *arg);
/****************************************************************************
* Name: gd32_exti_init
*
* Description:
* Initialize the EXTI.
*
* Input Parameters:
* - linex: EXTI line number
* - exti_mode: interrupt or event mode
* - trig_type: interrupt trigger type
*
****************************************************************************/
void gd32_exti_init(uint32_t linex, uint8_t exti_mode, uint8_t trig_type);
/****************************************************************************
* Name: gd32_gpio_exti_linex_get
*
* Description:
* Get EXTI GPIO port and linex from GPIO pin.
*
****************************************************************************/
int gd32_gpio_exti_linex_get(uint32_t cfgset, uint32_t *linex);
/****************************************************************************
* Name: gd32_gpio_exti_linex_get
*
* Description:
* Get EXTI GPIO port and linex from GPIO pin.
*
****************************************************************************/
int gd32_gpio_exti_irqnum_get(uint32_t cfgset, uint8_t *irqnum);
/****************************************************************************
* Name: gd32_exti_interrupt_enable
*
* Description:
* Enable the interrupts from EXTI line x.
*
* Input Parameters:
* - linex: EXTI line number
*
****************************************************************************/
void gd32_exti_interrupt_enable(uint32_t linex);
/****************************************************************************
* Name: gd32_exti_interrupt_disable
*
* Description:
* Disable the interrupts from EXTI line x.
*
* Input Parameters:
* - linex: EXTI line number
*
****************************************************************************/
void gd32_exti_interrupt_enable(uint32_t linex);
/****************************************************************************
* Name: gd32_exti_event_enable
*
* Description:
* Enable the events from EXTI line x.
*
* Input Parameters:
* - linex: EXTI line number
*
****************************************************************************/
void gd32_exti_event_enable(uint32_t linex);
/****************************************************************************
* Name: gd32_exti_event_disable
*
* Description:
* Disable the events from EXTI line x.
*
* Input Parameters:
* - linex: EXTI line number
*
****************************************************************************/
void gd32_exti_event_disable(uint32_t linex);
/****************************************************************************
* Name: gd32_exti_software_interrupt_enable
*
* Description:
* Enable EXTI software interrupt event.
*
* Input Parameters:
* - linex: EXTI line number
*
****************************************************************************/
void gd32_exti_software_interrupt_enable(uint32_t linex);
/****************************************************************************
* Name: gd32_exti_software_interrupt_disable
*
* Description:
* Disable EXTI software interrupt event.
*
* Input Parameters:
* - linex: EXTI line number
*
****************************************************************************/
void gd32_exti_software_interrupt_disable(uint32_t linex);
/****************************************************************************
* Name: gd32_exti_interrupt_flag_get
*
* Description:
* Get EXTI lines flag when the interrupt flag is set.
*
* Input Parameters:
* - linex: EXTI line number
*
* Returned Value:
* status of flag (false or true)
*
****************************************************************************/
bool gd32_exti_interrupt_flag_get(uint32_t linex);
/****************************************************************************
* Name: gd32_exti_interrupt_flag_clear
*
* Description:
* Clear EXTI lines pending flag.
*
* Input Parameters:
* - linex: EXTI line number
*
****************************************************************************/
void gd32_exti_interrupt_flag_clear(uint32_t linex);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_EXTI_H */
arch/arm/src/gd32f4/gd32f4xx_fmc.c
+702
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_fmc.h
+253
View File
@@ -0,0 +1,253 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_fmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_FMC_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_FMC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/progmem.h>
#include "chip.h"
#include "hardware/gd32f4xx_fmc.h"
/* FMC state */
typedef enum
{
FMC_READY, /* the operation has been completed */
FMC_BUSY, /* the operation is in progress */
FMC_RDDERR, /* read D-bus protection error */
FMC_PGSERR, /* program sequence error */
FMC_PGMERR, /* program size not match error */
FMC_WPERR, /* erase/program protection error */
FMC_OPERR, /* operation error */
FMC_PGERR, /* program error */
FMC_TOERR /* timeout error */
} gd32_fmc_state_enum;
/****************************************************************************
* Public Functions Prototypes
****************************************************************************/
/****************************************************************************
* Name: gd32_fmc_wscnt_set
*
* Description:
* Set the wait state counter value
*
* Parameters:
* wscnt - Wait state counter value
*
****************************************************************************/
void gd32_fmc_wscnt_set(uint32_t wscnt);
/****************************************************************************
* Name: gd32_fmc_unlock
*
* Description:
* Unlock the main FMC operation
*
****************************************************************************/
int gd32_fmc_unlock(void);
/****************************************************************************
* Name: gd32_fmc_lock
*
* Description:
* Lock the main FMC operation
*
****************************************************************************/
int gd32_fmc_lock(void);
/****************************************************************************
* Name: gd32_fmc_sector_erase
*
* Description:
* Erase sector
*
* Parameters:
* fmc_sector - Select the sector to erase
*
* Return Value:
* State of FMC
*
****************************************************************************/
gd32_fmc_state_enum gd32_fmc_sector_erase(uint32_t fmc_sector);
/****************************************************************************
* Name: gd32_fmc_mass_erase
*
* Description:
* Erase whole chip
*
****************************************************************************/
gd32_fmc_state_enum gd32_fmc_mass_erase(void);
/****************************************************************************
* Name: gd32_fmc_bank0_erase
*
* Description:
* Erase whole bank0
*
****************************************************************************/
gd32_fmc_state_enum gd32_fmc_bank0_erase(void);
/****************************************************************************
* Name: gd32_fmc_bank1_erase
*
* Description:
* Erase whole bank1
*
****************************************************************************/
gd32_fmc_state_enum gd32_fmc_bank1_erase(void);
/****************************************************************************
* Name: gd32_fmc_word_program
*
* Description:
* Program a word at the corresponding address
*
* Parameters:
* address - Address to program
* data - Word to program(0x00000000 - 0xFFFFFFFF)
*
* Return Value:
* State of FMC
*
****************************************************************************/
gd32_fmc_state_enum gd32_fmc_word_program(uint32_t address, uint32_t data);
/****************************************************************************
* Name: gd32_fmc_word_program
*
* Description:
* Program a half word at the corresponding address
*
* Parameters:
* address - Address to program
* data - Word to program(0x0000 - 0xFFFF)
*
* Return Value:
* State of FMC
*
****************************************************************************/
gd32_fmc_state_enum gd32_fmc_halfword_program(uint32_t address,
uint16_t data);
/****************************************************************************
* Name: gd32_fmc_byte_program
*
* Description:
* Program a byte at the corresponding address
*
* Parameters:
* address - Address to program
* data - Byte to program(0x00 - 0xFF)
*
* Return Value:
* State of FMC
*
****************************************************************************/
gd32_fmc_state_enum gd32_fmc_byte_program(uint32_t address, uint8_t data);
/****************************************************************************
* Name: gd32_ob_unlock
*
* Description:
* Unlock the option byte operation
*
****************************************************************************/
void gd32_ob_unlock(void);
/****************************************************************************
* Name: gd32_ob_lock
*
* Description:
* Lock the option byte operation
*
****************************************************************************/
void gd32_ob_lock(void);
/****************************************************************************
* Name: gd32_ob_start
*
* Description:
* Send option byte change command
*
****************************************************************************/
void gd32_ob_start(void);
/****************************************************************************
* Name: gd32_ob_write_protection_enable
*
* Description:
* Enable write protection
*
* Parameters:
* ob_wp - Specify sector to be write protected
*
****************************************************************************/
int gd32_ob_write_protection_enable(uint32_t ob_wp);
/****************************************************************************
* Name: gd32_ob_write_protection_disable
*
* Description:
* Disable write protection
*
* Parameters:
* ob_wp - Specify sector to be write protected
*
****************************************************************************/
int gd32_ob_write_protection_disable(uint32_t ob_wp);
/****************************************************************************
* Name: gd32_fmc_flag_clear
*
* Description:
* Clear the FMC pending flag
*
* Parameters:
* fmc_flag - FMC flag
*
****************************************************************************/
void gd32_fmc_flag_clear(uint32_t fmc_flag);
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_FMC_H */
arch/arm/src/gd32f4/gd32f4xx_gpio.c
+558
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_gpio.h
+312
View File
@@ -0,0 +1,312 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_GPIO_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_GPIO_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#ifndef __ASSEMBLY__
# include <stdint.h>
# include <stdbool.h>
#endif
#include <nuttx/irq.h>
#include "chip.h"
#include "hardware/gd32f4xx_gpio.h"
/****************************************************************************
* Pre-Processor Declarations
****************************************************************************/
/* Bit-encoded input to gd32_configgpio() */
#if defined(CONFIG_GD32F4_GD32F4XX)
/* Each pin of the general-purpose I/O (GPIO) ports can be individually
* configured by software in several modes. The following definitions provide
* the bit encoding that used to define the pin mode.
*
* 20-bit Encoding: 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ENCODING MMUU OVSS AAAA PPPP BBBB
* GPIO_MODE_INPUT: 00UU .X.. .... PPPP BBBB
* GPIO_MODE_OUTPUT: 01UU OVSS .... PPPP BBBB
* GPIO_MODE_AF: 10UU O.SS AAAA PPPP BBBB
* GPIO_MODE_ANALOG: 11UU .... .... PPPP BBBB
*/
/* Mode configuration:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* MM.. .... .... .... ....
*/
#define GPIO_CFG_MODE_SHIFT (18) /* Bits 18-19: GPIO pin mode */
#define GPIO_CFG_MODE_MASK (3 << GPIO_CFG_MODE_SHIFT)
# define GPIO_CFG_MODE_INPUT (0 << GPIO_CFG_MODE_SHIFT) /* Input mode */
# define GPIO_CFG_MODE_OUTPUT (1 << GPIO_CFG_MODE_SHIFT) /* General purpose output mode */
# define GPIO_CFG_MODE_AF (2 << GPIO_CFG_MODE_SHIFT) /* Alternate function mode */
# define GPIO_CFG_MODE_ANALOG (3 << GPIO_CFG_MODE_SHIFT) /* Analog mode */
/* Pull-up/ pull-down definitions:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* ..UU .... .... .... ....
*/
#define GPIO_CFG_PUPD_SHIFT (16) /* Bits 16-17: Pull-up and pull-down resistors */
#define GPIO_CFG_PUPD_MASK (3 << GPIO_CFG_PUPD_SHIFT)
# define GPIO_CFG_PUPD_NONE (0 << GPIO_CFG_PUPD_SHIFT) /* No pull-up, pull-down */
# define GPIO_CFG_PUPD_PULLUP (1 << GPIO_CFG_PUPD_SHIFT) /* With pull-up resistor */
# define GPIO_CFG_PUPD_PULLDOWN (2 << GPIO_CFG_PUPD_SHIFT) /* With pull-down resistor */
/* GPIO output type:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... O... .... .... ....
*/
#define GPIO_CFG_ODPP_SHIFT (15) /* Bit15: Open drain and push pull mode */
#define GPIO_CFG_ODPP_MASK (1 << GPIO_CFG_ODPP_SHIFT)
#define GPIO_CFG_OD (1 << GPIO_CFG_ODPP_SHIFT) /* Open drain mode */
#define GPIO_CFG_PP (0) /* Push pull mode */
/* If the pin is a GPIO digital output, then this identifies the initial
* output value.
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .V.. .... .... ....
*/
#define GPIO_CFG_OUTPUT_SHIFT (14) /* Bit 14: If output, output value */
#define GPIO_CFG_OUTPUT_MASK (1 << GPIO_CFG_OUTPUT_SHIFT)
#define GPIO_CFG_OUTPUT_SET (1 << GPIO_CFG_OUTPUT_SHIFT)
#define GPIO_CFG_OUTPUT_RESET (0)
/* External interrupt selection (GPIO inputs only):
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .X.. .... .... ....
*/
#define GPIO_CFG_EXTI (1 << 14) /* Bit 14: If input, configure as EXTI interrupt */
/* GPIO output max speed value:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... SS.. .... ....
*/
#define GPIO_CFG_SPEED_SHIFT (12) /* Bits 12-13: GPIO speed selection */
#define GPIO_CFG_SPEED_MASK (3 << GPIO_CFG_SPEED_SHIFT)
# define GPIO_CFG_SPEED_2MHZ (0 << GPIO_CFG_SPEED_SHIFT) /* 2 MHZ Low speed output */
# define GPIO_CFG_SPEED_25MHZ (1 << GPIO_CFG_SPEED_SHIFT) /* 25 MHZ Medium speed output */
# define GPIO_CFG_SPEED_50MHZ (2 << GPIO_CFG_SPEED_SHIFT) /* 50 MHZ Fast speed output */
# define GPIO_CFG_SPEED_200MHZ (3 << GPIO_CFG_SPEED_SHIFT) /* 100 MHZ High speed output */
/* GPIO alternate function:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... AAAA .... ....
*/
#define GPIO_CFG_AF_SHIFT (8) /* Bits 8-11: Alternate function */
#define GPIO_CFG_AF_MASK (15 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF(n) ((n) << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_0 (0 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_1 (1 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_2 (2 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_3 (3 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_4 (4 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_5 (5 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_6 (6 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_7 (7 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_8 (8 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_9 (9 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_10 (10 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_11 (11 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_12 (12 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_13 (13 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_14 (14 << GPIO_CFG_AF_SHIFT)
# define GPIO_CFG_AF_15 (15 << GPIO_CFG_AF_SHIFT)
/* This identifies the GPIO port:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... .... PPPP ....
*/
#define GPIO_CFG_PORT_SHIFT (4) /* Bit 4-7: Port number */
#define GPIO_CFG_PORT_MASK (15 << GPIO_CFG_PORT_SHIFT)
# define GPIO_CFG_PORT_A (0 << GPIO_CFG_PORT_SHIFT) /* GPIOA */
# define GPIO_CFG_PORT_B (1 << GPIO_CFG_PORT_SHIFT) /* GPIOB */
# define GPIO_CFG_PORT_C (2 << GPIO_CFG_PORT_SHIFT) /* GPIOC */
# define GPIO_CFG_PORT_D (3 << GPIO_CFG_PORT_SHIFT) /* GPIOD */
# define GPIO_CFG_PORT_E (4 << GPIO_CFG_PORT_SHIFT) /* GPIOE */
# define GPIO_CFG_PORT_F (5 << GPIO_CFG_PORT_SHIFT) /* GPIOF */
# define GPIO_CFG_PORT_G (6 << GPIO_CFG_PORT_SHIFT) /* GPIOG */
# define GPIO_CFG_PORT_H (7 << GPIO_CFG_PORT_SHIFT) /* GPIOH */
# define GPIO_CFG_PORT_I (8 << GPIO_CFG_PORT_SHIFT) /* GPIOI */
/* This identifies the bit in the port:
*
* 1111 1111 1100 0000 0000
* 9876 5432 1098 7654 3210
* ---- ---- ---- ---- ----
* .... .... .... .... BBBB
*/
#define GPIO_CFG_PIN_SHIFT (0) /* Bits 0-3: GPIO number: 0-15 */
#define GPIO_CFG_PIN_MASK (15 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_0 (0 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_1 (1 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_2 (2 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_3 (3 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_4 (4 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_5 (5 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_6 (6 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_7 (7 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_8 (8 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_9 (9 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_10 (10 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_11 (11 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_12 (12 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_13 (13 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_14 (14 << GPIO_CFG_PIN_SHIFT)
# define GPIO_CFG_PIN_15 (15 << GPIO_CFG_PIN_SHIFT)
#else
# error "Unknown GD32 chip"
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/* Base addresses for each GPIO block */
EXTERN const uint32_t g_gpio_base[GD32_NGPIO_PORTS];
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: gd32_gpio_config
*
* Description:
* Configure a GPIO pin based on bit-encoded description of the pin.
*
* Return value:
* OK on success
* A negated errno value on invalid port or mode.
****************************************************************************/
int gd32_gpio_config(uint32_t cfgset);
/****************************************************************************
* Name: gd32_gpio_unconfig
*
* Description:
* Unconfigure a GPIO pin based on bit-encoded description of the pin, set
* it into default HiZ state.
*
* Returned Value:
* OK on success
* A negated errno value on invalid port or mode
****************************************************************************/
int gd32_gpio_unconfig(uint32_t cfgset);
/****************************************************************************
* Name: gd32_gpiowrite
*
* Description:
* Write one or zero to the selected GPIO pin
*
****************************************************************************/
void gd32_gpio_write(uint32_t pinset, bool value);
/****************************************************************************
* Name: gd32_gpio_read
*
* Description:
* Read one or zero from the selected GPIO pin
*
****************************************************************************/
bool gd32_gpio_read(uint32_t pinset);
/****************************************************************************
* Function: gd32_dump_gpio
*
* Description:
* Dump all GPIO registers associated with the base address of the provided
* pinset.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
int gd32_dump_gpio(uint32_t pinset, const char *msg);
#else
# define gd32_dump_gpio(p,m)
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_GPIO_H */
arch/arm/src/gd32f4/gd32f4xx_idle.c
+173
View File
@@ -0,0 +1,173 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_idle.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <arch/board/board.h>
#include <nuttx/config.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/board.h>
#include <nuttx/power/pm.h>
#include <nuttx/irq.h>
#include "chip.h"
#include "gd32f4xx_pmu.h"
#include "arm_internal.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Does the board support an IDLE LED to indicate that the board is in the
* IDLE state?
*/
#if defined(CONFIG_ARCH_LEDS) && defined(LED_IDLE)
# define BEGIN_IDLE() board_autoled_on(LED_IDLE)
# define END_IDLE() board_autoled_off(LED_IDLE)
#else
# define BEGIN_IDLE()
# define END_IDLE()
#endif
#define PM_IDLE_DOMAIN 0 /* Revisit */
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: up_idlepm
*
* Description:
* Perform IDLE state power management.
*
****************************************************************************/
#ifdef CONFIG_PM
static void up_idlepm(void)
{
static enum pm_state_e oldstate = PM_NORMAL;
enum pm_state_e newstate;
irqstate_t flags;
int ret;
/* Decide, which power saving level can be obtained */
newstate = pm_checkstate(PM_IDLE_DOMAIN);
/* Check for state changes */
if (newstate != oldstate)
{
flags = enter_critical_section();
/* Perform board-specific, state-dependent logic here */
_info("newstate= %d oldstate=%d\n", newstate, oldstate);
/* Then force the global state change */
ret = pm_changestate(PM_IDLE_DOMAIN, newstate);
if (ret < 0)
{
/* The new state change failed, revert to the preceding state */
pm_changestate(PM_IDLE_DOMAIN, oldstate);
}
else
{
/* Save the new state */
oldstate = newstate;
}
/* MCU-specific power management logic */
switch (newstate)
{
case PM_NORMAL:
break;
case PM_IDLE:
break;
case PM_STANDBY:
gd32_pmstop(true);
break;
case PM_SLEEP:
gd32_pmstandby();
break;
default:
break;
}
leave_critical_section(flags);
}
}
#else
# define up_idlepm()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: up_idle
*
* Description:
* up_idle() is the logic that will be executed when there is no other
* ready-to-run task. This is processor idle time and will continue until
* some interrupt occurs to cause a context switch from the idle task.
*
* Processing in this state may be processor-specific. e.g., this is where
* power management operations might be performed.
*
****************************************************************************/
void up_idle(void)
{
#if defined(CONFIG_SUPPRESS_INTERRUPTS) || defined(CONFIG_SUPPRESS_TIMER_INTS)
/* If the system is idle and there are no timer interrupts, then process
* "fake" timer interrupts. Hopefully, something will wake up.
*/
nxsched_process_timer();
#else
/* Perform IDLE mode power management */
up_idlepm();
#if !defined(CONFIG_DEBUG_SYMBOLS)
BEGIN_IDLE();
asm("WFI");
END_IDLE();
#endif
#endif
}
arch/arm/src/gd32f4/gd32f4xx_irq.c
+556
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_lowputc.c
+596
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_lowputc.h
+92
View File
@@ -0,0 +1,92 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_lowputc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_LOWPUTC_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_LOWPUTC_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Name: gd32_lowsetup
*
* Description:
* Called at the very beginning of _start.
* Performs low level initialization of serial console.
*
****************************************************************************/
void gd32_lowsetup(void);
/****************************************************************************
* Name: gd32_usart_reset
*
* Description:
* Reset the USART.
*
****************************************************************************/
void gd32_usart_reset(uint32_t usartbase);
/****************************************************************************
* Name: gd32_usart_clock_enable
*
* Description:
* Enable USART clock
****************************************************************************/
void gd32_usart_clock_enable(uint32_t usartbase);
/****************************************************************************
* Name: gd32_usart_clock_disable
*
* Description:
* Dinable USART clock
****************************************************************************/
void gd32_usart_clock_disable(uint32_t usartbase);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_LOWPUTC_H */
arch/arm/src/gd32f4/gd32f4xx_pmu.c
+666
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_pmu.h
+395
View File
@@ -0,0 +1,395 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_pmu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_PMU_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_PMU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdbool.h>
#include "chip.h"
#include "hardware/gd32f4xx_pmu.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: gd32_pmu_lvd_select
*
* Description:
* Select low voltage detector threshold.
*
* Input Parameters:
* lvdt_n - PMU_CTL_LVDT(n), LVD threshold level
*
* Returned Value:
* None
*
****************************************************************************/
void gd32_pmu_lvd_select(uint32_t lvdt_n);
/****************************************************************************
* Name: gd32_pmu_lvd_enable
*
* Description:
* Enable LVD
*
****************************************************************************/
void gd32_pmu_lvd_enable(void);
/****************************************************************************
* Name: gd32_pmu_lvd_disable
*
* Description:
* Disable LVD
*
****************************************************************************/
void gd32_pmu_lvd_disable(void);
/****************************************************************************
* Name: gd32_pmu_ldo_output_select
*
* Description:
* Select the LDO output voltage. Set LDO output when the main PLL closed,
* and it takes effect when the main PLL enabled.
*
* Input Parameters:
* ldo_output - PMU_CTL_LDOVS(n), PMU LDO output voltage select
*
* Returned Value:
* None
*
****************************************************************************/
void gd32_pmu_ldo_output_select(uint32_t ldo_output);
/****************************************************************************
* Name: gd32_pmu_highdriver_mode_enable
*
* Description:
* Enable high-driver mode
*
****************************************************************************/
void gd32_pmu_highdriver_mode_enable(void);
/****************************************************************************
* Name: gd32_pmu_highdriver_mode_disable
*
* Description:
* Disable high-driver mode
*
****************************************************************************/
void gd32_pmu_highdriver_mode_disable(void);
/****************************************************************************
* Name: gd32_pmu_highdriver_switch_select
*
* Description:
* Switch high-driver mode.
*
* Input Parameters:
* highdr_switch - PMU high-driver mode
* - PMU_HIGHDR_SWITCH_NONE
* - PMU_HIGHDR_SWITCH_EN
*
* Returned Value:
* None
*
****************************************************************************/
void gd32_pmu_highdriver_switch_select(uint32_t highdr_switch);
/****************************************************************************
* Name: gd32_pmu_lowdriver_mode_enable
*
* Description:
* Enable low-driver mode in deep-sleep
*
****************************************************************************/
void gd32_pmu_lowdriver_mode_enable(void);
/****************************************************************************
* Name: gd32_pmu_lowdriver_mode_disable
*
* Description:
* Disable low-driver mode in deep-sleep
*
****************************************************************************/
void gd32_pmu_lowdriver_mode_disable(void);
/****************************************************************************
* Name: gd32_pmu_lowpower_driver_config
*
* Description:
* In deep-sleep mode, driver mode when use low power LDO.
*
* Input Parameters:
* mode - PMU low-driver mode
* - PMU_NORMALDR_LOWPWR: normal driver when use low power LDO
* - PMU_LOWDR_LOWPWR: low-driver mode enabled when LDEN is 11 and
* use low power LDO
*
* Returned Value:
* None
*
****************************************************************************/
void gd32_pmu_lowpower_driver_config(uint32_t mode);
/****************************************************************************
* Name: gd32_pmu_normalpower_driver_config
*
* Description:
* In deep-sleep mode, driver mode when use normal power LDO.
*
* Input Parameters:
* mode - PMU low-driver mode
* - PMU_NORMALDR_NORMALPWR: normal driver when use normal power LDO
* - PMU_LOWDR_NORMALPWR: low-driver mode enabled when LDEN is 11 and
* use normal power LDO
*
* Returned Value:
* None
*
****************************************************************************/
void gd32_pmu_normalpower_driver_config(uint32_t mode);
/****************************************************************************
* Name: gd32_pmu_to_sleepmode
*
* Description:
* PMU work in sleep mode.
*
* Input Parameters:
* sleepmodecmd - PMU command constants
* - WFI_CMD: use WFI command
* - WFE_CMD: use WFE command
* sleeponexit
* - true: SLEEPONEXIT bit is set when the WFI instruction is
* executed, the MCU enters Sleep mode as soon as it
* exits the lowest priority ISR.
* - false: SLEEPONEXIT bit is cleared, the MCU enters Sleep
*
* Returned Value:
* None
*
****************************************************************************/
void gd32_pmu_to_sleepmode(uint8_t sleepmodecmd, bool sleeponexit);
/****************************************************************************
* Name: gd32_pmu_to_deepsleepmode
*
* Description:
* PMU work in deep-sleep mode
*
* Input Parameters:
* ldo
* - PMU_LDO_NORMAL: LDO normal work when pmu enter deep-sleep mode
* - PMU_LDO_LOWPOWER: LDO work at low power mode when pmu enter
* deep-sleep mode
* lowdrive
* - PMU_LOWDRIVER_DISABLE: Low-driver mode disable in deep-sleep mode
* - PMU_LOWDRIVER_ENABLE: Low-driver mode enable in deep-sleep mode
*
* deepsleepmodecmdd - PMU command constants
* - WFI_CMD: use WFI command
* - WFE_CMD: use WFE command
*
* Returned Value:
* None
*
****************************************************************************/
void gd32_pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive,
uint8_t deepsleepmodecmd);
/****************************************************************************
* Name: gd32_pmu_to_standbymode
*
* Description:
* PMU work in standby mode
*
* Input Parameters:
* standbymodecmd - PMU command constants
* WFI_CMD: use WFI command
* WFE_CMD: use WFE command
*
* Returned Value:
* None
*
****************************************************************************/
void gd32_pmu_to_standbymode(uint8_t standbymodecmd);
/****************************************************************************
* Name: gd32_pmu_wakeup_pin_enable
*
* Description:
* Enables PMU wakeup pin.
*
****************************************************************************/
void gd32_pmu_wakeup_pin_enable(void);
/****************************************************************************
* Name: gd32_pmu_wakeup_pin_disable
*
* Description:
* Disables PMU wakeup pin.
*
****************************************************************************/
void gd32_pmu_wakeup_pin_disable(void);
/****************************************************************************
* Name: gd32_pmu_backup_ldo_config
*
* Description:
* Enables the backup ldo, to open Backup SRAM LDO for data protection of
* backup SRAM when VDD shut down. When VDD shut down and this bit is
* cleared, the data in Backup SRAM will be lost.
* Once set, the application should wait that the Backup SRAM LDO flag
* (BLDORF) is set to indicate that the data written into the RAM will be
* maintained when VDD shut down.
*
* Input Parameters:
* bkp_ldo - state to set it to
* - PMU_BLDOON_OFF: backup SRAM LDO closed
* - PMU_BLDOON_ON: backup SRAM LDO closed
*
* Returned Value:
* None
*
****************************************************************************/
void gd32_pmu_backup_ldo_config(bool bkp_ldo);
/****************************************************************************
* Name: gd32_pmu_backup_init
*
* Description:
* Insures the referenced count access to the backup domain
* (RTC registers, RTC backup data registers and backup SRAM is consistent
* with the hardware state without relying on a variable.
*
* NOTE: This function should only be called by SoC Start up code.
*
* Input Parameters:
* writable - set the initial state of the enable and the
* bkp_writable_counter
*
* Returned Value:
* None
*
****************************************************************************/
void gd32_pmu_backup_init(bool writable);
/****************************************************************************
* Name: gd32_pmu_backup_write_enable
*
* Description:
* Enableswrite access to the registers in backup domain
*
****************************************************************************/
void gd32_pmu_backup_write_enable(void);
/****************************************************************************
* Name: gd32_pmu_backup_write_disable
*
* Description:
* DIsables write access to the registers in backup domain
*
****************************************************************************/
void gd32_pmu_backup_write_disable(void);
/****************************************************************************
* Name: gd32_pmu_flag_get
*
* Description:
* Get flag state
*
* Input Parameters:
* flag - PMU_CS_WUF: wakeup flag
* - PMU_CS_STBF: standby flag
* - PMU_CS_LVDF: lvd flag
* - PMU_CS_BLDORF: backup SRAM LDO ready flag
* - PMU_CS_LDOVSRF: LDO voltage select ready flag
* - PMU_CS_HDRF: high-driver ready flag
* - PMU_CS_HDSRF: high-driver switch ready flag
* - PMU_CS_LDRF: low-driver mode ready flag
*
****************************************************************************/
bool gd32_pmu_flag_get(uint32_t flag);
/****************************************************************************
* Name: gd32_pmu_backup_write_disable
*
* Description:
* Clear the flag
*
* Input Parameters:
* flag - PMU_FLAG_RESET_WAKEUP: reset wakeup flag
* - PMU_FLAG_RESET_STANDBY: reset standby flag
*
****************************************************************************/
void gd32_pmu_flag_clear(uint32_t flag);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_PMU_H */
arch/arm/src/gd32f4/gd32f4xx_progmem.c
+686
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_progmem.h
+44
View File
@@ -0,0 +1,44 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_progmem.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_PROGMEM_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_PROGMEM_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/progmem.h>
/****************************************************************************
* Refer to GD32F4xx_User_Manual Chapter 2: Flash memory controller to know
* about how program with the flash memory on GD32F450Z.
*
****************************************************************************/
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define FMC_STAT_PERR (FMC_STAT_END | FMC_STAT_OPERR | FMC_STAT_WPERR | FMC_STAT_PGMERR | FMC_STAT_PGSERR)
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_PROGMEM_H */
arch/arm/src/gd32f4/gd32f4xx_rcu.c
+762
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_rcu.h
+180
View File
@@ -0,0 +1,180 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_rcu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_RCU_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_RCU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_GD32F4_GD32F4XX)
# include "hardware/gd32f4xx_rcu.h"
#else
# error "Unknown GD32 chip"
#endif
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
#define RCU_PERI_REG_SHIFT (6)
#define RCU_GPIOA_EN ((GD32_RCU_AHB1EN_OFFSET << RCU_PERI_REG_SHIFT) | 0)
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: gd32_clockconfig
*
* Description:
* Called to initialize the GD32F4. This does whatever setup is needed to
* put the MCU in a usable state. This includes the initialization of
* clocking using the settings in board.h.
*
****************************************************************************/
void gd32_clockconfig(void);
/****************************************************************************
* Name: gd32_rcu_ckout0_config
*
* Description:
* Configure the CK_OUT0 clock source and divider. CK_OUT0 is connected
* to PA8. PA8 should be configured in alternate function mode.
****************************************************************************/
void gd32_rcu_ckout0_config(uint32_t src, uint32_t div);
/****************************************************************************
* Name: gd32_rcu_ckout1_config
*
* Description:
* Configure the CK_OUT0 clock source and divider. CK_OUT0 is connected
* to PC9. PC9 should be configured in alternate function mode.
****************************************************************************/
void gd32_rcu_ckout1_config(uint32_t src, uint32_t div);
/****************************************************************************
* Name: gd32_board_clockconfig
*
* Description:
* Any GD32 board may replace the "standard" board clock configuration
* logic with its own, custom clock configuration logic.
*
****************************************************************************/
#ifdef CONFIG_ARCH_BOARD_GD32F4_CUSTOM_CLOCKCONFIG
void gd32_board_clock_config(void);
#endif
/****************************************************************************
* Name: gd32_clockenable
*
* Description:
* Re-enable the clock and restore the clock settings based on settings in
* board.h.
* This function is only available to support low-power modes of operation:
* When re-awakening from deep-sleep modes, it is necessary to re-enable/
* re-start the PLL
*
* This functional performs a subset of the operations performed by
* gd32_clockconfig(): It does not reset any devices, and it does not
* reset the currently enabled peripheral clocks.
*
* If CONFIG_ARCH_BOARD_GD32F4_CUSTOM_CLOCKCONFIG is defined, then clocking
* will be enabled by an externally provided, board-specific function
* called gd32_board_clockconfig().
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
#ifdef CONFIG_PM
void gd32_clock_enable(void);
#endif
/****************************************************************************
* Name: gd32_rcu_lxtal_enable
*
* Description:
* Enable the External Low Speed crystal oscillator (LXTAL).
*
* Input Parameters:
* None
*
* Returned Value:
* None
*
****************************************************************************/
void gd32_rcu_lxtal_enable(void);
/****************************************************************************
* Name: gd32_rcu_irc16_enable
*
* Description:
* Enable the Internal 16M RC oscillator (IRC16M).
*
****************************************************************************/
void gd32_rcu_irc16m_enable(void);
/****************************************************************************
* Name: gd32_rcu_irc16m_disable
*
* Description:
* Disable the Internal 16M RC oscillator (IRC16M).
*
****************************************************************************/
void gd32_rcu_irc16m_disable(void);
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_RCU_H */
arch/arm/src/gd32f4/gd32f4xx_serial.c
+2984
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_spi.c
+2433
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/gd32f4xx_spi.h
+233
View File
@@ -0,0 +1,233 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_SPI_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <nuttx/spi/spi.h>
#include "chip.h"
#include "hardware/gd32f4xx_spi.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#ifndef __ASSEMBLY__
#undef EXTERN
#if defined(__cplusplus)
#define EXTERN extern "C"
extern "C"
{
#else
#define EXTERN extern
#endif
/****************************************************************************
* Public Data
****************************************************************************/
struct spi_dev_s;
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: gd32_spibus_initialize
*
* Description:
* Initialize the selected SPI bus
*
* Input Parameters:
* bus number (for hardware that has multiple SPI interfaces)
*
* Returned Value:
* Valid SPI device structure reference on success; a NULL on failure
*
****************************************************************************/
struct spi_dev_s *gd32_spibus_initialize(int bus);
/****************************************************************************
* Name: gd32_spibus_deinitialize
*
* Description:
* Deinitialize the selected SPI port
*
* Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
****************************************************************************/
void gd32_spibus_deinitialize(int port);
/****************************************************************************
* Name: gd32_spibus_deinitialize
*
* Description:
* Deinitialize the selected SPI port
*
* Input Parameters:
* Port number (for hardware that has multiple SPI interfaces)
*
****************************************************************************/
void gd32_spibus_deinitialize(int port);
/****************************************************************************
* Name: gd32_spi[n] select and gd32_spi[n] status
*
* Description:
* The external functions, gd32_spi[n]select, gd32_spi[n]status,
* and gd32_spi[n]cmddata must be provided by board-specific logic.
* These are implementations of the select, status, and cmddata methods of
* the SPI interface defined by struct spi_ops_s (see
* include/nuttx/spi/spi.h). All other methods (including
* gd32_spibus_initialize()) are provided by common GD32F4 logic.
* To use this common SPI logic on your board:
*
* 1. Provide logic in gd32_boardinitialize() to configure SPI chip
* select pins.
* 2. Provide gd32_spi[n]select() and gd32_spi[n] status() functions
* in your board-specific logic. These functions will perform chip
* selection and status operations using GPIOs in the way your board
* is configured.
* 3. If CONFIG_SPI_CMDDATA is defined in the NuttX configuration, then
* provide gd32_spi[n]cmddata() functions in your board-specific
* logic. These functions will perform cmd/data selection operations
* using GPIOs in the way your board is configured.
* 4. Add a calls to gd32_spibus_initialize() in your low level
* application initialization logic
* 5. The handle returned by gd32_spibus_initialize() may then be used to
* bind the SPI driver to higher level logic (e.g., calling
* mmcsd_spislotinitialize(), for example, will bind the SPI driver to
* the SPI MMC/SD driver).
*
****************************************************************************/
#ifdef CONFIG_GD32F4_SPI0
void gd32_spi0select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t gd32_spi0status(struct spi_dev_s *dev, uint32_t devid);
int gd32_spi0cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_GD32F4_SPI1
void gd32_spi1select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t gd32_spi1status(struct spi_dev_s *dev, uint32_t devid);
int gd32_spi1cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_GD32F4_SPI2
void gd32_spi2select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t gd32_spi2status(struct spi_dev_s *dev, uint32_t devid);
int gd32_spi2cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_GD32F4_SPI3
void gd32_spi3select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t gd32_spi3status(struct spi_dev_s *dev, uint32_t devid);
int gd32_spi3cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_GD32F4_SPI4
void gd32_spi4select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t gd32_spi4status(struct spi_dev_s *dev, uint32_t devid);
int gd32_spi4cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
#ifdef CONFIG_GD32F4_SPI5
void gd32_spi5select(struct spi_dev_s *dev, uint32_t devid,
bool selected);
uint8_t gd32_spi5status(struct spi_dev_s *dev, uint32_t devid);
int gd32_spi5cmddata(struct spi_dev_s *dev, uint32_t devid, bool cmd);
#endif
/****************************************************************************
* Name: gd32_spi[n]register
*
* Description:
* If the board supports a card detect callback to inform the SPI-based
* MMC/SD driver when an SD card is inserted or removed, then
* CONFIG_SPI_CALLBACK should be defined and the following function(s)
* must be implemented. These functions implements the registercallback
* method of the SPI interface (see include/nuttx/spi/spi.h for details)
*
* Input Parameters:
* dev - Device-specific state data
* callback - The function to call on the media change
* arg - A caller provided value to return with the callback
*
* Returned Value:
* 0 on success; negated errno on failure.
*
****************************************************************************/
#ifdef CONFIG_SPI_CALLBACK
#ifdef CONFIG_GD32F4_SPI0
int gd32_spi0register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_GD32F4_SPI1
int gd32_spi1register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_GD32F4_SPI2
int gd32_spi2register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_GD32F4_SPI3
int gd32_spi3register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_GD32F4_SPI4
int gd32_spi4register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#ifdef CONFIG_GD32F4_SPI5
int gd32_spi5register(struct spi_dev_s *dev, spi_mediachange_t callback,
void *arg);
#endif
#endif
#undef EXTERN
#if defined(__cplusplus)
}
#endif
#endif /* __ASSEMBLY__ */
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_SPI_H */
arch/arm/src/gd32f4/gd32f4xx_start.c
+284
View File
@@ -0,0 +1,284 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_start.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <assert.h>
#include <debug.h>
#include <nuttx/init.h>
#include "arm_internal.h"
#include "nvic.h"
#include "mpu.h"
#include "gd32f4xx.h"
#include "gd32f4xx_gpio.h"
#include "gd32f4xx_start.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* .data is positioned first in the primary RAM followed immediately by .bss.
* The IDLE thread stack lies just after .bss and has size give by
* CONFIG_IDLETHREAD_STACKSIZE; The heap then begins just after the IDLE.
* ARM EABI requires 64 bit stack alignment.
*/
#define HEAP_BASE ((uintptr_t)&_ebss + CONFIG_IDLETHREAD_STACKSIZE)
/****************************************************************************
* Public Data
****************************************************************************/
/* g_idle_topstack: _sbss is the start of the BSS region as defined by the
* linker script. _ebss lies at the end of the BSS region. The idle task
* stack starts at the end of BSS and is of size CONFIG_IDLETHREAD_STACKSIZE.
* The IDLE thread is the thread that the system boots on and, eventually,
* becomes the IDLE, do nothing task that runs only when there is nothing
* else to run. The heap continues from there until the end of memory.
* g_idle_topstack is a read-only variable the provides this computed
* address.
*/
const uintptr_t g_idle_topstack = HEAP_BASE;
/****************************************************************************
* Private Function prototypes
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
static inline void gd32_fpuconfig(void);
#endif
/****************************************************************************
* Public Function prototypes
****************************************************************************/
#ifdef CONFIG_ARMV7M_STACKCHECK
/* we need to get r10 set before we can allow instrumentation calls */
void __start(void) noinstrument_function;
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Name: showprogress
*
* Description:
* Print a character on the UART to show boot status.
*
****************************************************************************/
#ifdef CONFIG_DEBUG_FEATURES
# define showprogress(c) arm_lowputc(c)
#else
# define showprogress(c)
#endif
/****************************************************************************
* Name: gd32_fpuconfig
*
* Description:
* Configure the FPU. Relative bit settings:
*
* CPACR: Enables access to CP10 and CP11
* CONTROL.FPCA: Determines whether the FP extension is active in the
* current context:
* FPCCR.ASPEN: Enables automatic FP state preservation, then the
* processor sets this bit to 1 on successful completion of any FP
* instruction.
* FPCCR.LSPEN: Enables lazy context save of FP state. When this is
* done, the processor reserves space on the stack for the FP state,
* but does not save that state information to the stack.
*
* Software must not change the value of the ASPEN bit or LSPEN bit either:
* - the CPACR permits access to CP10 and CP11, that give access to the FP
* extension, or
* - the CONTROL.FPCA bit is set to 1
*
****************************************************************************/
#ifdef CONFIG_ARCH_FPU
#ifndef CONFIG_ARMV7M_LAZYFPU
static inline void gd32_fpuconfig(void)
{
uint32_t regval;
/* Set CONTROL.FPCA so that we always get the extended context frame
* with the volatile FP registers stacked above the basic context.
*/
regval = getcontrol();
regval |= CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to turn on CONTROL.FPCA for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
static inline void gd32_fpuconfig(void)
{
uint32_t regval;
/* Clear CONTROL.FPCA so that we do not get the extended context frame
* with the volatile FP registers stacked in the saved context.
*/
regval = getcontrol();
regval &= ~CONTROL_FPCA;
setcontrol(regval);
/* Ensure that FPCCR.LSPEN is disabled, so that we don't have to contend
* with the lazy FP context save behaviour. Clear FPCCR.ASPEN since we
* are going to keep CONTROL.FPCA off for all contexts.
*/
regval = getreg32(NVIC_FPCCR);
regval &= ~(NVIC_FPCCR_ASPEN | NVIC_FPCCR_LSPEN);
putreg32(regval, NVIC_FPCCR);
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
#else
# define gd32_fpuconfig()
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: _start
*
* Description:
* This is the reset entry point.
*
****************************************************************************/
void __start(void)
{
const uint32_t *src;
uint32_t *dest;
#ifdef CONFIG_ARMV7M_STACKCHECK
/* Set the stack limit before we attempt to call any functions */
__asm__ volatile("sub r10, sp, %0" : :
"r"(CONFIG_IDLETHREAD_STACKSIZE - 64) :);
#endif
/* Clear .bss. We'll do this inline (vs. calling memset) just to be
* certain that there are no issues with the state of global variables.
*/
for (dest = &_sbss; dest < &_ebss; )
{
*dest++ = 0;
}
/* Move the initialized data section from his temporary holding spot in
* FLASH into the correct place in SRAM. The correct place in SRAM is
* give by _sdata and _edata. The temporary location is in FLASH at the
* end of all of the other read-only data (.text, .rodata) at _eronly.
*/
for (src = &_eronly, dest = &_sdata; dest < &_edata; )
{
*dest++ = *src++;
}
/* Configure the UART so that we can get debug output as soon as possible */
gd32_clockconfig();
gd32_fpuconfig();
gd32_lowsetup();
showprogress('A');
#ifdef CONFIG_ARMV7M_ITMSYSLOG
/* Perform ARMv7-M ITM SYSLOG initialization */
itm_syslog_initialize();
#endif
/* Perform early serial initialization */
#ifdef USE_EARLYSERIALINIT
arm_earlyserialinit();
#endif
showprogress('B');
/* For the case of the separate user-/kernel-space build, perform whatever
* platform specific initialization of the user memory is required.
* Normally this just means initializing the user space .data and .bss
* segments.
*/
#ifdef CONFIG_BUILD_PROTECTED
gd32_userspace();
showprogress('C');
#endif
/* Initialize onboard resources */
gd32_boardinitialize();
showprogress('D');
/* Then start NuttX */
showprogress('\r');
showprogress('\n');
nx_start();
/* Shouldn't get here */
for (; ; );
}
arch/arm/src/gd32f4/gd32f4xx_start.h
+47
View File
@@ -0,0 +1,47 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_start.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_START_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_START_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: gd32_boardinitialize
*
* Description:
* All GD32 architectures must provide the following entry point. This
* entry point is called early in the initialization -- after clocking
* and memory have been configured but before caches have been enabled
* and before any devices have been initialized.
*
****************************************************************************/
void gd32_boardinitialize(void);
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_START_H */
arch/arm/src/gd32f4/gd32f4xx_syscfg.c
+248
View File
@@ -0,0 +1,248 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_syscfg.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <sys/types.h>
#include <stdint.h>
#include <stdbool.h>
#include <errno.h>
#include <debug.h>
#include <nuttx/irq.h>
#include "arm_internal.h"
#include "chip.h"
#include "gd32f4xx_syscfg.h"
#include "gd32f4xx_rcu.h"
#ifdef CONFIG_GD32F4_SYSCFG
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Name: gd32_syscfg_bootmode_config
*
* Description:
* This function configure the boot mode.
*
****************************************************************************/
void gd32_syscfg_bootmode_config(uint8_t syscfg_bootmode)
{
uint32_t regval;
regval = getreg32(GD32_SYSCFG_CFG0);
regval &= ~ SYSCFG_CFG0_BOOT_MODE_MASK;
regval |= (uint32_t)syscfg_bootmode;
putreg32(regval, GD32_SYSCFG_CFG0);
}
/****************************************************************************
* Name: gd32_syscfg_fmc_swap_config
*
* Description:
* This function configure FMC memory mapping swap.
*
****************************************************************************/
void gd32_syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap)
{
uint32_t regval;
regval = getreg32(GD32_SYSCFG_CFG0);
regval &= ~SYSCFG_CFG0_FMC_SWP_MASK;
regval |= syscfg_fmc_swap;
putreg32(regval, GD32_SYSCFG_CFG0);
}
/****************************************************************************
* Name: gd32_syscfg_exmc_swap_config
*
* Description:
* This function configure EXMC memory mapping swap.
*
****************************************************************************/
void gd32_syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap)
{
uint32_t regval;
regval = getreg32(GD32_SYSCFG_CFG0);
regval &= ~SYSCFG_CFG0_EXMC_SWP_MASK;
regval |= syscfg_exmc_swap;
putreg32(regval, GD32_SYSCFG_CFG0);
}
/****************************************************************************
* Name: gd32_syscfg_exti_line_config
*
* Description:
* This function configure the GPIO pin as EXTI Line.
*
****************************************************************************/
void gd32_syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin)
{
uint32_t regval;
uint32_t regaddr;
switch (exti_pin / SYSCFG_EXTI_SS_JSTEP)
{
/* EXTI source line(0..3) */
case SYSCFG_EXTISS0:
regaddr = GD32_SYSCFG_EXTISS0;
break;
/* EXTI source line(4..7) */
case SYSCFG_EXTISS1:
regaddr = GD32_SYSCFG_EXTISS1;
break;
/* EXTI source line(8..11) */
case SYSCFG_EXTISS2:
regaddr = GD32_SYSCFG_EXTISS2;
break;
/* EXTI source line(12..15) */
case SYSCFG_EXTISS3:
regaddr = GD32_SYSCFG_EXTISS3;
break;
default:
break;
}
regval = getreg32(regaddr);
regval &= ~(SYSCFG_EXTI_SS_MASK << (SYSCFG_EXTI_SS_MSTEP(exti_pin)));
regval |= ((exti_port) << (SYSCFG_EXTI_SS_MSTEP(exti_pin)));
putreg32(regval, regaddr);
}
/****************************************************************************
* Name: gd32_syscfg_enet_phy_interface_config
*
* Description:
* This function configure the PHY interface for the ethernet MAC.
*
****************************************************************************/
void
gd32_syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface)
{
uint32_t regval;
regval = getreg32(GD32_SYSCFG_CFG1);
regval &= ~SYSCFG_CFG1_ENET_PHY_SEL_MASK;
regval |= syscfg_enet_phy_interface;
putreg32(regval, GD32_SYSCFG_CFG1);
}
/****************************************************************************
* Name: gd32_syscfg_compensation_config
*
* Description:
* This function configure the I/O compensation cell.
*
****************************************************************************/
void gd32_syscfg_compensation_config(uint32_t syscfg_compensation)
{
uint32_t regval;
regval = getreg32(GD32_SYSCFG_CPSCTL);
regval &= ~SYSCFG_CPSCTL_CPS_EN_MASK;
regval |= syscfg_compensation;
putreg32(regval, GD32_SYSCFG_CPSCTL);
}
/****************************************************************************
* Name: gd32_syscfg_flag_get
*
* Description:
* This function checks whether the I/O compensation cell ready flag
* is set or not.
*
****************************************************************************/
bool gd32_syscfg_flag_get(void)
{
bool regval;
regval = getreg32(GD32_SYSCFG_CPSCTL);
return (bool)(regval & SYSCFG_CPSCTL_CPS_RDY_MASK);
}
/****************************************************************************
* Name: gd32_syscfg_clock_enable
*
* Description:
* Enable SYSCFG clock
****************************************************************************/
void gd32_syscfg_clock_enable(void)
{
uint32_t rcu_en;
uint32_t regaddr;
rcu_en = RCU_APB2EN_SYSCFGEN;
regaddr = GD32_RCU_APB2EN;
/* Check clock if alreay enable. */
if (rcu_en != (rcu_en & getreg32(regaddr)))
{
/* Enable/disable APB2 clock for SYSCFG */
modifyreg32(regaddr, 0, rcu_en);
}
}
/****************************************************************************
* Name: gd32_syscfg_clock_disable
*
* Description:
* Dinable SYSCFG clock
****************************************************************************/
void gd32_syscfg_clock_disable(void)
{
uint32_t rcu_en;
uint32_t regaddr;
rcu_en = RCU_APB2EN_SYSCFGEN;
regaddr = GD32_RCU_APB2EN;
/* Disable APB2 clock for SYSCFG */
modifyreg32(regaddr, rcu_en, 0);
}
#endif /* CONFIG_GD32F4_SYSCFG */
arch/arm/src/gd32f4/gd32f4xx_syscfg.h
+131
View File
@@ -0,0 +1,131 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_syscfg.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_GD32F4XX_SYSCFG_H
#define __ARCH_ARM_SRC_GD32F4_GD32F4XX_SYSCFG_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_GD32F4_GD32F4XX)
# include "hardware/gd32f4xx_syscfg.h"
#else
# error "Unknown GD32 Chip"
#endif
/****************************************************************************
* Public Function Prototypes
****************************************************************************/
/****************************************************************************
* Name: gd32_syscfg_bootmode_config
*
* Description:
* This function configure the boot mode.
*
****************************************************************************/
void gd32_syscfg_bootmode_config(uint8_t syscfg_bootmode);
/****************************************************************************
* Name: gd32_syscfg_fmc_swap_config
*
* Description:
* This function configure FMC memory mapping swap.
*
****************************************************************************/
void gd32_syscfg_fmc_swap_config(uint32_t syscfg_fmc_swap);
/****************************************************************************
* Name: gd32_syscfg_exmc_swap_config
*
* Description:
* This function configure EXMC memory mapping swap.
*
****************************************************************************/
void gd32_syscfg_exmc_swap_config(uint32_t syscfg_exmc_swap);
/****************************************************************************
* Name: gd32_syscfg_exti_line_config
*
* Description:
* This function configure the GPIO pin as EXTI Line.
*
****************************************************************************/
void gd32_syscfg_exti_line_config(uint8_t exti_port, uint8_t exti_pin);
/****************************************************************************
* Name: gd32_syscfg_enet_phy_interface_config
*
* Description:
* This function configure the PHY interface for the ethernet MAC.
*
****************************************************************************/
void
gd32_syscfg_enet_phy_interface_config(uint32_t syscfg_enet_phy_interface);
/****************************************************************************
* Name: gd32_syscfg_compensation_config
*
* Description:
* This function configure the I/O compensation cell.
*
****************************************************************************/
void gd32_syscfg_compensation_config(uint32_t syscfg_compensation);
/****************************************************************************
* Name: gd32_syscfg_flag_get
*
* Description:
* This function checks whether the I/O compensation cell ready flag
* is set or not.
*
****************************************************************************/
bool gd32_syscfg_flag_get(void);
/****************************************************************************
* Name: gd32_syscfg_clock_enable
*
* Description:
* Enable SYSCFG clock
****************************************************************************/
void gd32_syscfg_clock_enable(void);
/****************************************************************************
* Name: gd32_syscfg_clock_disable
*
* Description:
* Dinable SYSCFG clock
****************************************************************************/
void gd32_syscfg_clock_disable(void);
#endif /* __ARCH_ARM_SRC_GD32F4_GD32F4XX_SYSCFG_H */
arch/arm/src/gd32f4/gd32f4xx_timerisr.c
+136
View File
@@ -0,0 +1,136 @@
/****************************************************************************
* arch/arm/src/gd32f4/gd32f4xx_timerisr.c
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include <stdint.h>
#include <time.h>
#include <debug.h>
#include <nuttx/arch.h>
#include <nuttx/timers/arch_timer.h>
#include <arch/board/board.h>
#include "nvic.h"
#include "clock/clock.h"
#include "arm_internal.h"
#include "chip.h"
#include "gd32f4xx.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* The desired timer interrupt frequency is provided by the definition
* CLK_TCK (see include/time.h). CLK_TCK defines the desired number of
* system clock ticks per second. That value is a user configurable setting
* that defaults to 100 (100 ticks per second = 10 MS interval).
*
* The RCU feeds the Cortex System Timer (SysTick) with the AHB clock (HCLK)
* divided by 8. The SysTick can work either with this clock or with the
* Cortex clock (HCLK), configurable in the SysTick Control and Status
* register.
*/
#define SYSTICK_RELOAD ((GD32_SYSCLK_FREQUENCY / CLK_TCK) - 1)
/* The size of the reload field is 24 bits. Verify that the reload value
* will fit in the reload register.
*/
#if SYSTICK_RELOAD > 0x00ffffff
# error SYSTICK_RELOAD exceeds the range of the RELOAD register
#endif
/****************************************************************************
* Private Functions
****************************************************************************/
/****************************************************************************
* Function: gd32_timerisr
*
* Description:
* The timer ISR will perform a variety of services for various portions
* of the systems.
*
****************************************************************************/
#if !defined(CONFIG_ARMV7M_SYSTICK) && !defined(CONFIG_TIMER_ARCH)
static int gd32_timerisr(int irq, uint32_t *regs, void *arg)
{
/* Process timer interrupt */
nxsched_process_timer();
return 0;
}
#endif
/****************************************************************************
* Public Functions
****************************************************************************/
/****************************************************************************
* Function: up_timer_initialize
*
* Description:
* This function is called during start-up to initialize
* the timer interrupt.
*
****************************************************************************/
void up_timer_initialize(void)
{
uint32_t regval;
/* Set the SysTick interrupt to the default priority */
regval = getreg32(NVIC_SYSH12_15_PRIORITY);
regval &= ~NVIC_SYSH_PRIORITY_PR15_MASK;
regval |= (NVIC_SYSH_PRIORITY_DEFAULT << NVIC_SYSH_PRIORITY_PR15_SHIFT);
putreg32(regval, NVIC_SYSH12_15_PRIORITY);
/* Make sure that the SYSTICK clock source is set correctly */
#if defined(CONFIG_ARMV7M_SYSTICK) && defined(CONFIG_TIMER_ARCH)
up_timer_set_lowerhalf(systick_initialize(true, GD32_SYSCLK_FREQUENCY,
-1));
#else
/* Configure SysTick to interrupt at the requested rate */
putreg32(SYSTICK_RELOAD, NVIC_SYSTICK_RELOAD);
/* Attach the timer interrupt vector */
irq_attach(GD32_IRQ_SYSTICK, (xcpt_t)gd32_timerisr, NULL);
/* Enable SysTick interrupts */
putreg32((NVIC_SYSTICK_CTRL_CLKSOURCE | NVIC_SYSTICK_CTRL_TICKINT |
NVIC_SYSTICK_CTRL_ENABLE), NVIC_SYSTICK_CTRL);
/* And enable the timer interrupt */
up_enable_irq(GD32_IRQ_SYSTICK);
#endif
}
arch/arm/src/gd32f4/gd32f4xx_usart.h
+594
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h
+138
View File
@@ -0,0 +1,138 @@
/****************************************************************************
* arch/arm/src/gd32f4/hardware/gd32f450_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F450_MEMORYMAP_H
#define __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F450_MEMORYMAP_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GD32F4XX Address Blocks **************************************************/
#define GD32_CODE_BASE 0x00000000 /* 0x00000000-0x1fffffff: 512Mb code block */
#define GD32_SRAM_BASE 0x20000000 /* 0x20000000-0x3fffffff: 512Mb sram block */
#define GD32_PERIPH_BASE 0x40000000 /* 0x40000000-0x5fffffff: 512Mb peripheral block */
#define GD32_EXMC_REG_BASE 0xa0000000 /* 0xa0000000-0xbfffffff: 512Mb EXMC register block */
#define GD32_EXMC_BASE 0x60000000 /* 0x60000000-0x7fffffff: EXMC base */
#define GD32_EXMC_BANK0 0x60000000 /* 0x60000000-0x6fffffff: 256Mb NOR/PSRAM/SRAM */
#define GD32_EXMC_BANK1 0x70000000 /* 0x70000000-0x7fffffff: 256Mb NAND FLASH */
#define GD32_EXMC_BANK2 0x80000000 /* 0x80000000-0x8fffffff: 256Mb NAND FLASH */
#define GD32_EXMC_BANK3 0x90000000 /* 0x90000000-0x9fffffff: 256Mb PC CARD*/
#define GD32_EXMC_BANK4 0xc0000000 /* 0xc0000000-0xcfffffff: 256Mb SDRAM */
#define GD32_EXMC_BANK5 0xd0000000 /* 0xd0000000-0xdfffffff: 256Mb SDRAM */
#define GD32_CORTEX_BASE 0xe0000000 /* 0xe0000000-0xffffffff: 512Mb Cortex-M4 block */
#define GD32_REGION_MASK 0xf0000000
#define GD32_IS_SRAM(a) ((((uint32_t)(a)) & GD32_REGION_MASK) == GD32_SRAM_BASE)
#define GD32_IS_EXTSRAM(a) ((((uint32_t)(a)) & GD32_REGION_MASK) == GD32_EXMC_BANK0)
/* Code Base Addresses ******************************************************/
#define GD32_BOOT_BASE 0x00000000 /* 0x00000000-0x007ffffff: Aliased to the boot device */
#define GD32_FLASH_BASE 0x08000000 /* 0x08000000-0x082fffff: Main flash */
/* 0x08100000-0x0fffffff: Reserved */
#define GD32_TCMSRAM_BASE 0x10000000 /* 0x10000000-0x1000ffff: 64Kb TCMSRAM */
/* 0x10010000-0x1ffebfff: Reserved */
#define GD32_OPBYTE_BANK1 0x1ffec000 /* 0x1ffec000-0x1ffec00f: 16b Option bytes */
/* 0x1ffec010-0x1ffeffff: Reserved */
#define GD32_BOOTLD_BASE 0x1fff0000 /* 0x1fff0000-0x1fff77ff: 30Kb Boot loader */
#define GD32_OTP_BASE 0x1fff7800 /* 0x1fff7800-0x1fff7a0f: 528b OTP block */
/* 0x1fff7a10-0x1fffbfff: Reserved */
#define GD32_OPBYTE_BANK0 0x1fffc000 /* 0x1fffc000-0x1fffc00f: 16b Option bytes */
/* 0x1fffc010-0x1fffffff: Reserved */
/* System Memory Addresses **************************************************/
#define GD32_UNIQUE_ID 0x1fff7a10 /* The 96-bit unique device ID */
#define GD32_FLASH_DENSITY 0x1fff7a20 /* The memory density information, indicates the size of
* the device Flash or RAM memory expressed in
* Kbytes. Example: 0x020 corresponds
* to 32 Kbytes.
*/
/* SRAM Base Addresses ******************************************************/
/* 0x20000000-0x2001bfff:
* 112Kb aliased by bit-banding
*/
/* 0x2001c000-0x2001ffff:
* 16Kb aliased by bit-banding
*/
#define GD32_SRAMBB_BASE 0x22000000 /* 0x22000000- : SRAM bit-band region */
/* Peripheral Base Addresses ************************************************/
#define GD32_APB1_BUS_BASE 0x40000000 /* APB1 base address */
#define GD32_APB2_BUS_BASE 0x40010000 /* APB2 base address */
#define GD32_AHB1_BUS_BASE 0x40020000 /* AHB1 base address */
#define GD32_AHB2_BUS_BASE 0x50000000 /* AHB2 base address */
/* APB1 Base Addresses ******************************************************/
#define GD32_TIMER_BASE (GD32_APB1_BUS_BASE + 0x00000000U) /* TIMER base address */
#define GD32_RTC_BASE (GD32_APB1_BUS_BASE + 0x00002800U) /* RTC base address */
#define GD32_WWDGT_BASE (GD32_APB1_BUS_BASE + 0x00002C00U) /* WWDGT base address */
#define GD32_FWDGT_BASE (GD32_APB1_BUS_BASE + 0x00003000U) /* FWDGT base address */
#define GD32_I2S_ADD_BASE (GD32_APB1_BUS_BASE + 0x00003400U) /* I2S1_add base address */
#define GD32_SPI_BASE (GD32_APB1_BUS_BASE + 0x00003800U) /* SPI base address */
#define GD32_USART_BASE (GD32_APB1_BUS_BASE + 0x00004400U) /* USART base address */
#define GD32_I2C_BASE (GD32_APB1_BUS_BASE + 0x00005400U) /* I2C base address */
#define GD32_CAN_BASE (GD32_APB1_BUS_BASE + 0x00006400U) /* CAN base address */
#define GD32_CTC_BASE (GD32_APB1_BUS_BASE + 0x00006C00U) /* CTC base address */
#define GD32_PMU_BASE (GD32_APB1_BUS_BASE + 0x00007000U) /* PMU base address */
#define GD32_DAC_BASE (GD32_APB1_BUS_BASE + 0x00007400U) /* DAC base address */
#define GD32_IREF_BASE (GD32_APB1_BUS_BASE + 0x0000C400U) /* IREF base address */
/* APB2 Base Addresses ******************************************************/
#define GD32_TLI_BASE (GD32_APB2_BUS_BASE + 0x00006800U) /* TLI base address */
#define GD32_SYSCFG_BASE (GD32_APB2_BUS_BASE + 0x00003800U) /* SYSCFG base address */
#define GD32_EXTI_BASE (GD32_APB2_BUS_BASE + 0x00003C00U) /* EXTI base address*/
#define GD32_SDIO_BASE (GD32_APB2_BUS_BASE + 0x00002C00U) /* SDIO base address */
#define GD32_ADC_BASE (GD32_APB2_BUS_BASE + 0x00002000U) /* ADC base address */
/* AHB1 Base Addresses ******************************************************/
#define GD32_GPIO_BASE (GD32_AHB1_BUS_BASE + 0x00000000U) /* GPIO base address*/
#define GD32_CRC_BASE (GD32_AHB1_BUS_BASE + 0x00003000U) /* CRC base address */
#define GD32_RCU_BASE (GD32_AHB1_BUS_BASE + 0x00003800U) /* RCU base address */
#define GD32_FMC_BASE (GD32_AHB1_BUS_BASE + 0x00003C00U) /* FMC base address */
#define GD32_BKPSRAM_BASE (GD32_AHB1_BUS_BASE + 0x00004000U) /* BKPSRAM base address */
#define GD32_DMA_BASE (GD32_AHB1_BUS_BASE + 0x00006000U) /* DMA base address */
#define GD32_ENET_BASE (GD32_AHB1_BUS_BASE + 0x00008000U) /* ENET base address */
#define GD32_IPA_BASE (GD32_AHB1_BUS_BASE + 0x0000B000U) /* IPA base address */
#define GD32_USBHS_BASE (GD32_AHB1_BUS_BASE + 0x00020000U) /* USBHS base address */
/* AHB2 Base Addresses ******************************************************/
#define GD32_USBFS_BASE (GD32_AHB2_BUS_BASE + 0x00000000U) /* USBFS base address */
#define GD32_DCI_BASE (GD32_AHB2_BUS_BASE + 0x00050000U) /* DCI base address */
#define GD32_TRNG_BASE (GD32_AHB2_BUS_BASE + 0x00060800U) /* TRNG base address */
/* DBG register Base Addresses **********************************************/
#define GD32_DBG_BASE 0xe0042000
#endif /* __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F450_MEMORYMAP_H */
arch/arm/src/gd32f4/hardware/gd32f450_pinmap.h
+847
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h
+480
View File
@@ -0,0 +1,480 @@
/****************************************************************************
* arch/arm/src/gd32f4/hardware/gd32f4xx_dma.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_DMA_H
#define __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_DMA_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* DMA definitions */
#define GD32_DMA0_BASE (GD32_DMA_BASE+0x00000000) /* DMA0 base address */
#define GD32_DMA1_BASE (GD32_DMA_BASE+0x00000400) /* DMA1 base address */
/* Register Offsets *********************************************************/
#define GD32_DMA_INTF0_OFFSET 0x0000 /* DMA interrupt flag register 0 offset */
#define GD32_DMA_INTF1_OFFSET 0x0004 /* DMA interrupt flag register 1 offset */
#define GD32_DMA_INTC0_OFFSET 0x0008 /* DMA interrupt flag clear register 1 offset */
#define GD32_DMA_INTC1_OFFSET 0x000C /* DMA interrupt flag clear register 1 offset */
#define GD32_DMA_CH0CTL_OFFSET 0x0010 /* DMA channel 0 control register offset */
#define GD32_DMA_CH0CNT_OFFSET 0x0014 /* DMA channel 0 counter register offset */
#define GD32_DMA_CH0PADDR_OFFSET 0x0018 /* DMA channel 0 peripheral base address register offset */
#define GD32_DMA_CH0M0ADDR_OFFSET 0x001C /* DMA channel 0 memory 0 base address register offset */
#define GD32_DMA_CH0M1ADDR_OFFSET 0x0020 /* DMA channel 0 memory 1 base address register offset */
#define GD32_DMA_CH0FCTL_OFFSET 0x0024 /* DMA channel 0 FIFO control register offset */
#define GD32_DMA_CH1CTL_OFFSET 0x0028 /* DMA channel 1 control register offset */
#define GD32_DMA_CH1CNT_OFFSET 0x002C /* DMA channel 1 counter register offset */
#define GD32_DMA_CH1PADDR_OFFSET 0x0030 /* DMA channel 1 peripheral base address register offset */
#define GD32_DMA_CH1M0ADDR_OFFSET 0x0034 /* DMA channel 1 memory 0 base address register offset */
#define GD32_DMA_CH1M1ADDR_OFFSET 0x0038 /* DMA channel 1 memory 1 base address register offset */
#define GD32_DMA_CH1FCTL_OFFSET 0x003C /* DMA channel 1 FIFO control register offset */
#define GD32_DMA_CH2CTL_OFFSET 0x0040 /* DMA channel 2 control register offset */
#define GD32_DMA_CH2CNT_OFFSET 0x0044 /* DMA channel 2 counter register offset */
#define GD32_DMA_CH2PADDR_OFFSET 0x0048 /* DMA channel 2 peripheral base address register offset */
#define GD32_DMA_CH2M0ADDR_OFFSET 0x004C /* DMA channel 2 memory 0 base address register offset */
#define GD32_DMA_CH2M1ADDR_OFFSET 0x0050 /* DMA channel 2 memory 1 base address register offset */
#define GD32_DMA_CH2FCTL_OFFSET 0x0054 /* DMA channel 2 FIFO control register offset */
#define GD32_DMA_CH3CTL_OFFSET 0x0058 /* DMA channel 3 control register offset */
#define GD32_DMA_CH3CNT_OFFSET 0x005C /* DMA channel 3 counter register offset */
#define GD32_DMA_CH3PADDR_OFFSET 0x0060 /* DMA channel 3 peripheral base address register offset */
#define GD32_DMA_CH3M0ADDR_OFFSET 0x0064 /* DMA channel 3 memory 0 base address register offset */
#define GD32_DMA_CH3M1ADDR_OFFSET 0x0068 /* DMA channel 3 memory 1 base address register offset */
#define GD32_DMA_CH3FCTL_OFFSET 0x006C /* DMA channel 3 FIFO control register offset */
#define GD32_DMA_CH4CTL_OFFSET 0x0070 /* DMA channel 4 control register offset */
#define GD32_DMA_CH4CNT_OFFSET 0x0074 /* DMA channel 4 counter register offset */
#define GD32_DMA_CH4PADDR_OFFSET 0x0078 /* DMA channel 4 peripheral base address register offset */
#define GD32_DMA_CH4M0ADDR_OFFSET 0x007C /* DMA channel 4 memory 0 base address register offset */
#define GD32_DMA_CH4M1ADDR_OFFSET 0x0080 /* DMA channel 4 memory 1 base address register offset */
#define GD32_DMA_CH4FCTL_OFFSET 0x0084 /* DMA channel 4 FIFO control register offset */
#define GD32_DMA_CH5CTL_OFFSET 0x0088 /* DMA channel 5 control register offset */
#define GD32_DMA_CH5CNT_OFFSET 0x008C /* DMA channel 5 counter register offset */
#define GD32_DMA_CH5PADDR_OFFSET 0x0090 /* DMA channel 5 peripheral base address register offset */
#define GD32_DMA_CH5M0ADDR_OFFSET 0x0094 /* DMA channel 5 memory 0 base address register offset */
#define GD32_DMA_CH5M1ADDR_OFFSET 0x0098 /* DMA channel 5 memory 1 base address register offset */
#define GD32_DMA_CH5FCTL_OFFSET 0x009C /* DMA channel 5 FIFO control register offset */
#define GD32_DMA_CH6CTL_OFFSET 0x00A0 /* DMA channel 6 control register offset */
#define GD32_DMA_CH6CNT_OFFSET 0x00A4 /* DMA channel 6 counter register offset */
#define GD32_DMA_CH6PADDR_OFFSET 0x00A8 /* DMA channel 6 peripheral base address register offset */
#define GD32_DMA_CH6M0ADDR_OFFSET 0x00AC /* DMA channel 6 memory 0 base address register offset */
#define GD32_DMA_CH6M1ADDR_OFFSET 0x00B0 /* DMA channel 6 memory 1 base address register offset */
#define GD32_DMA_CH6FCTL_OFFSET 0x00B4 /* DMA channel 6 FIFO control register offset */
#define GD32_DMA_CH7CTL_OFFSET 0x00B8 /* DMA channel 7 control register offset */
#define GD32_DMA_CH7CNT_OFFSET 0x00BC /* DMA channel 7 counter register offset */
#define GD32_DMA_CH7PADDR_OFFSET 0x00C0 /* DMA channel 7 peripheral base address register offset */
#define GD32_DMA_CH7M0ADDR_OFFSET 0x00C4 /* DMA channel 7 memory 0 base address register offset */
#define GD32_DMA_CH7M1ADDR_OFFSET 0x00C8 /* DMA channel 7 memory 1 base address register offset */
#define GD32_DMA_CH7FCTL_OFFSET 0x00CC /* DMA channel 7 FIFO control register offset */
/* Register Addresses *******************************************************/
#define GD32_DMA_INTF0(dmax) ((dmax)+GD32_DMA_INTF0_OFFSET) /* DMA interrupt flag register 0 */
#define GD32_DMA_INTF1(dmax) ((dmax)+GD32_DMA_INTF1_OFFSET) /* DMA interrupt flag register 1 */
#define GD32_DMA_INTC0(dmax) ((dmax)+GD32_DMA_INTC0_OFFSET) /* DMA interrupt flag clear register 1 */
#define GD32_DMA_INTC1(dmax) ((dmax)+GD32_DMA_INTC1_OFFSET) /* DMA interrupt flag clear register 1 */
#define GD32_DMA_CH0CTL(dmax) ((dmax)+GD32_DMA_CH0CTL_OFFSET) /* DMA channel 0 control register */
#define GD32_DMA_CH0CNT(dmax) ((dmax)+GD32_DMA_CH0CNT_OFFSET) /* DMA channel 0 counter register */
#define GD32_DMA_CH0PADDR(dmax) ((dmax)+GD32_DMA_CH0PADDR_OFFSET) /* DMA channel 0 peripheral base address register */
#define GD32_DMA_CH0M0ADDR(dmax) ((dmax)+GD32_DMA_CH0M0ADDR_OFFSET) /* DMA channel 0 memory 0 base address register */
#define GD32_DMA_CH0M1ADDR(dmax) ((dmax)+GD32_DMA_CH0M1ADDR_OFFSET) /* DMA channel 0 memory 1 base address register */
#define GD32_DMA_CH0FCTL(dmax) ((dmax)+GD32_DMA_CH0FCTL_OFFSET) /* DMA channel 0 FIFO control register */
#define GD32_DMA_CH1CTL(dmax) ((dmax)+GD32_DMA_CH1CTL_OFFSET) /* DMA channel 1 control register */
#define GD32_DMA_CH1CNT(dmax) ((dmax)+GD32_DMA_CH1CNT_OFFSET) /* DMA channel 1 counter register */
#define GD32_DMA_CH1PADDR(dmax) ((dmax)+GD32_DMA_CH1PADDR_OFFSET) /* DMA channel 1 peripheral base address register */
#define GD32_DMA_CH1M0ADDR(dmax) ((dmax)+GD32_DMA_CH1M0ADDR_OFFSET) /* DMA channel 1 memory 0 base address register */
#define GD32_DMA_CH1M1ADDR(dmax) ((dmax)+GD32_DMA_CH1M1ADDR_OFFSET) /* DMA channel 1 memory 1 base address register */
#define GD32_DMA_CH1FCTL(dmax) ((dmax)+GD32_DMA_CH1FCTL_OFFSET) /* DMA channel 1 FIFO control register */
#define GD32_DMA_CH2CTL(dmax) ((dmax)+GD32_DMA_CH2CTL_OFFSET) /* DMA channel 2 control register */
#define GD32_DMA_CH2CNT(dmax) ((dmax)+GD32_DMA_CH2CNT_OFFSET) /* DMA channel 2 counter register */
#define GD32_DMA_CH2PADDR(dmax) ((dmax)+GD32_DMA_CH2PADDR_OFFSET) /* DMA channel 2 peripheral base address register */
#define GD32_DMA_CH2M0ADDR(dmax) ((dmax)+GD32_DMA_CH2M0ADDR_OFFSET) /* DMA channel 2 memory 0 base address register */
#define GD32_DMA_CH2M1ADDR(dmax) ((dmax)+GD32_DMA_CH2M1ADDR_OFFSET) /* DMA channel 2 memory 1 base address register */
#define GD32_DMA_CH2FCTL(dmax) ((dmax)+GD32_DMA_CH2FCTL_OFFSET) /* DMA channel 2 FIFO control register */
#define GD32_DMA_CH3CTL(dmax) ((dmax)+GD32_DMA_CH3CTL_OFFSET) /* DMA channel 3 control register */
#define GD32_DMA_CH3CNT(dmax) ((dmax)+GD32_DMA_CH3CNT_OFFSET) /* DMA channel 3 counter register */
#define GD32_DMA_CH3PADDR(dmax) ((dmax)+GD32_DMA_CH3PADDR_OFFSET) /* DMA channel 3 peripheral base address register */
#define GD32_DMA_CH3M0ADDR(dmax) ((dmax)+GD32_DMA_CH3M0ADDR_OFFSET) /* DMA channel 3 memory 0 base address register */
#define GD32_DMA_CH3M1ADDR(dmax) ((dmax)+GD32_DMA_CH3M1ADDR_OFFSET) /* DMA channel 3 memory 1 base address register */
#define GD32_DMA_CH3FCTL(dmax) ((dmax)+GD32_DMA_CH3FCTL_OFFSET) /* DMA channel 3 FIFO control register */
#define GD32_DMA_CH4CTL(dmax) ((dmax)+GD32_DMA_CH4CTL_OFFSET) /* DMA channel 4 control register */
#define GD32_DMA_CH4CNT(dmax) ((dmax)+GD32_DMA_CH4CNT_OFFSET) /* DMA channel 4 counter register */
#define GD32_DMA_CH4PADDR(dmax) ((dmax)+GD32_DMA_CH4PADDR_OFFSET) /* DMA channel 4 peripheral base address register */
#define GD32_DMA_CH4M0ADDR(dmax) ((dmax)+GD32_DMA_CH4M0ADDR_OFFSET) /* DMA channel 4 memory 0 base address register */
#define GD32_DMA_CH4M1ADDR(dmax) ((dmax)+GD32_DMA_CH4M1ADDR_OFFSET) /* DMA channel 4 memory 1 base address register */
#define GD32_DMA_CH4FCTL(dmax) ((dmax)+GD32_DMA_CH4FCTL_OFFSET) /* DMA channel 4 FIFO control register */
#define GD32_DMA_CH5CTL(dmax) ((dmax)+GD32_DMA_CH5CTL_OFFSET) /* DMA channel 5 control register */
#define GD32_DMA_CH5CNT(dmax) ((dmax)+GD32_DMA_CH5CNT_OFFSET) /* DMA channel 5 counter register */
#define GD32_DMA_CH5PADDR(dmax) ((dmax)+GD32_DMA_CH5PADDR_OFFSET) /* DMA channel 5 peripheral base address register */
#define GD32_DMA_CH5M0ADDR(dmax) ((dmax)+GD32_DMA_CH5M0ADDR_OFFSET) /* DMA channel 5 memory 0 base address register */
#define GD32_DMA_CH5M1ADDR(dmax) ((dmax)+GD32_DMA_CH5M1ADDR_OFFSET) /* DMA channel 5 memory 1 base address register */
#define GD32_DMA_CH5FCTL(dmax) ((dmax)+GD32_DMA_CH5FCTL_OFFSET) /* DMA channel 5 FIFO control register */
#define GD32_DMA_CH6CTL(dmax) ((dmax)+GD32_DMA_CH6CTL_OFFSET) /* DMA channel 6 control register */
#define GD32_DMA_CH6CNT(dmax) ((dmax)+GD32_DMA_CH6CNT_OFFSET) /* DMA channel 6 counter register */
#define GD32_DMA_CH6PADDR(dmax) ((dmax)+GD32_DMA_CH6PADDR_OFFSET) /* DMA channel 6 peripheral base address register */
#define GD32_DMA_CH6M0ADDR(dmax) ((dmax)+GD32_DMA_CH6M0ADDR_OFFSET) /* DMA channel 6 memory 0 base address register */
#define GD32_DMA_CH6M1ADDR(dmax) ((dmax)+GD32_DMA_CH6M1ADDR_OFFSET) /* DMA channel 6 memory 1 base address register */
#define GD32_DMA_CH6FCTL(dmax) ((dmax)+GD32_DMA_CH6FCTL_OFFSET) /* DMA channel 6 FIFO control register */
#define GD32_DMA_CH7CTL(dmax) ((dmax)+GD32_DMA_CH7CTL_OFFSET) /* DMA channel 7 control register */
#define GD32_DMA_CH7CNT(dmax) ((dmax)+GD32_DMA_CH7CNT_OFFSET) /* DMA channel 7 counter register */
#define GD32_DMA_CH7PADDR(dmax) ((dmax)+GD32_DMA_CH7PADDR_OFFSET) /* DMA channel 7 peripheral base address register */
#define GD32_DMA_CH7M0ADDR(dmax) ((dmax)+GD32_DMA_CH7M0ADDR_OFFSET) /* DMA channel 7 memory 0 base address register */
#define GD32_DMA_CH7M1ADDR(dmax) ((dmax)+GD32_DMA_CH7M1ADDR_OFFSET) /* DMA channel 7 memory 1 base address register */
#define GD32_DMA_CH7FCTL(dmax) ((dmax)+GD32_DMA_CH7FCTL_OFFSET) /* DMA channel 7 FIFO control register */
/* DMA channelx register address */
#define GD32_DMA_CHCTL(dma, channelx) ((dma+0x10) + 0x18*(channelx)) /* The address of DMA channel CHXCTL register */
#define GD32_DMA_CHCNT(dma, channelx) ((dma+0x14) + 0x18*(channelx)) /* The address of DMA channel CHXCNT register */
#define GD32_DMA_CHPADDR(dma, channelx) ((dma+0x18) + 0x18*(channelx)) /* The address of DMA channel CHXPADDR register */
#define GD32_DMA_CHM0ADDR(dma, channelx) ((dma+0x1C) + 0x18*(channelx)) /* The address of DMA channel CHXM0ADDR register */
#define GD32_DMA_CHM1ADDR(dma, channelx) ((dma+0x20) + 0x18*(channelx)) /* The address of DMA channel CHXM1ADDR register */
#define GD32_DMA_CHFCTL(dma, channelx) ((dma+0x24) + 0x18*(channelx)) /* The address of DMA channel CHXMADDR register */
/* bits definitions */
/* DMA_INTF */
#define DMA_INTF_FEEIF (1 << 0) /* Bit 0: FIFO error and exception flag */
#define DMA_INTF_SDEIF (1 << 2) /* Bit 2: single data mode exception flag */
#define DMA_INTF_TAEIF (1 << 3) /* Bit 3: transfer access error flag */
#define DMA_INTF_HTFIF (1 << 4) /* Bit 4: half transfer finish flag */
#define DMA_INTF_FTFIF (1 << 5) /* Bit 5: full transger finish flag */
/* DMA_INTC */
#define DMA_INTC_FEEIFC (1 << 0) /* Bit 0: clear FIFO error and exception flag */
#define DMA_INTC_SDEIFC (1 << 2) /* Bit 2: clear single data mode exception flag */
#define DMA_INTC_TAEIFC (1 << 3) /* Bit 3: clear single data mode exception flag */
#define DMA_INTC_HTFIFC (1 << 4) /* Bit 4: clear half transfer finish flag */
#define DMA_INTC_FTFIFC (1 << 5) /* Bit 5: clear full transger finish flag */
/* DMA_CHxCTL,x=0..7 */
#define DMA_CHXCTL_CHEN (1 << 0) /* Bit 0: channel x enable */
#define DMA_CHXCTL_SDEIE (1 << 1) /* Bit 1: enable bit for channel x single data mode exception interrupt */
#define DMA_CHXCTL_TAEIE (1 << 2) /* Bit 2: enable bit for channel x tranfer access error interrupt */
#define DMA_CHXCTL_HTFIE (1 << 3) /* Bit 3: enable bit for channel x half transfer finish interrupt */
#define DMA_CHXCTL_FTFIE (1 << 4) /* Bit 4: enable bit for channel x full transfer finish interrupt */
#define DMA_CHXCTL_TFCS (1 << 5) /* Bit 5: transfer flow controller select */
#define DMA_CHXCTL_TM_SHIFT (6) /* Bit 6-7: transfer mode */
#define DMA_CHXCTL_TM_MASK (3 << DMA_CHXCTL_TM_SHIFT)
#define DMA_CHXCTL_TM(n) ((n) << DMA_CHXCTL_TM_SHIFT)
# define DMA_PERIPH_TO_MEMORY DMA_CHXCTL_TM(0) /* 00: read from peripheral and write to memory */
# define DMA_MEMORY_TO_PERIPH DMA_CHXCTL_TM(1) /* 01: read from peripheral and write to memory */
# define DMA_MEMORY_TO_MEMORY DMA_CHXCTL_TM(2) /* 02: read from peripheral and write to memory */
#define DMA_CHXCTL_CMEN (1 << 8) /* Bit 8: circulation mode */
#define DMA_CHXCTL_PNAGA (1 << 9) /* Bit 9: next address generation algorithm of peripheral */
#define DMA_CHXCTL_MNAGA (1 << 10) /* Bit 10: next address generation algorithm of memory */
#define DMA_CHXCTL_PWIDTH_SHIFT (11) /* Bit 11-12: transfer width of peipheral */
#define DMA_CHXCTL_PWIDTH_MASK (3 << DMA_CHXCTL_PWIDTH_SHIFT)
#define DMA_CHXCTL_PWIDTH(n) ((n) << DMA_CHXCTL_PWIDTH_SHIFT)
# define DMA_PERIPH_WIDTH_8BIT DMA_CHXCTL_PWIDTH(0) /* 00: transfer data width of peripheral is 8-bit */
# define DMA_PERIPH_WIDTH_16BIT DMA_CHXCTL_PWIDTH(1) /* 01: transfer data width of peripheral is 16-bit */
# define DMA_PERIPH_WIDTH_32BIT DMA_CHXCTL_PWIDTH(2) /* 02: transfer data width of peripheral is 32-bit */
#define DMA_CHXCTL_MWIDTH_SHIFT (13) /* Bit 13-14: transfer width of memory */
#define DMA_CHXCTL_MWIDTH_MASK (3 << DMA_CHXCTL_MWIDTH_SHIFT)
#define DMA_CHXCTL_MWIDTH(n) ((n) << DMA_CHXCTL_MWIDTH_SHIFT)
# define DMA_MEMORY_WIDTH_8BIT DMA_CHXCTL_MWIDTH(0) /* 00: transfer data width of memory is 8-bit */
# define DMA_MEMORY_WIDTH_16BIT DMA_CHXCTL_MWIDTH(1) /* 01: transfer data width of memory is 16-bit */
# define DMA_MEMORY_WIDTH_32BIT DMA_CHXCTL_MWIDTH(2) /* 02: transfer data width of memory is 32-bit */
#define DMA_CHXCTL_PAIF (1 << 15) /* Bit 15: peripheral address increment fixed */
#define DMA_CHXCTL_PRIO_SHIFT (16) /* Bit 16-17: priority level */
#define DMA_CHXCTL_PRIO_MASK (3 << DMA_CHXCTL_PRIO_SHIFT)
#define DMA_CHXCTL_PRIO(n) ((n) << DMA_CHXCTL_PRIO_SHIFT)
# define DMA_PRIORITY_LOW DMA_CHXCTL_PRIO(0) /* 00: low priority */
# define DMA_PRIORITY_MEDIUM DMA_CHXCTL_PRIO(1) /* 01: medium priority */
# define DMA_PRIORITY_HIGH DMA_CHXCTL_PRIO(2) /* 10: high priority */
# define DMA_PRIORITY_ULTRA_HIGH DMA_CHXCTL_PRIO(3) /* 11: ultra high priority */
#define DMA_CHXCTL_SBMEN (1 << 18) /* Bit 18: switch-buffer mode enable */
#define DMA_CHXCTL_MBS (1 << 19) /* Bit19: memory buffer select */
#define DMA_CHXCTL_PBURST_SHIFT (21) /* Bit 21-22: transfer burst type of peripheral */
#define DMA_CHXCTL_PBURST_MASK (3 << DMA_CHXCTL_PBURST_SHIFT)
#define DMA_CHXCTL_PBURST(n) ((n) << DMA_CHXCTL_PBURST_SHIFT)
# define DMA_PERIPH_BURST_SINGLE DMA_CHXCTL_PBURST(0) /* single burst */
# define DMA_PERIPH_BURST_4_BEAT DMA_CHXCTL_PBURST(1) /* 4-beat burst */
# define DMA_PERIPH_BURST_8_BEAT DMA_CHXCTL_PBURST(2) /* 8-beat burst */
# define DMA_PERIPH_BURST_16_BEAT DMA_CHXCTL_PBURST(3) /* 16-beat burst */
#define DMA_CHXCTL_MBURST_SHIFT (23) /* Bit 23-24: transfer burst type of memory */
#define DMA_CHXCTL_MBURST_MASK (3 << DMA_CHXCTL_MBURST_SHIFT)
#define DMA_CHXCTL_MBURST(n) ((n) << DMA_CHXCTL_MBURST_SHIFT)
# define DMA_MEMORY_BURST_SINGLE DMA_CHXCTL_MBURST(0) /* single burst */
# define DMA_MEMORY_BURST_4_BEAT DMA_CHXCTL_MBURST(1) /* 4-beat burst */
# define DMA_MEMORY_BURST_8_BEAT DMA_CHXCTL_MBURST(2) /* 8-beat burst */
# define DMA_MEMORY_BURST_16_BEAT DMA_CHXCTL_MBURST(3) /* 16-beat burst */
#define DMA_CHXCTL_PERIEN_SHIFT (25) /* Bit 25-27: peripheral enable */
#define DMA_CHXCTL_PERIEN_MASK (7 << DMA_CHXCTL_PERIEN_SHIFT)
#define DMA_CHXCTL_PERIEN(n) ((n) << DMA_CHXCTL_PERIEN_SHIFT)
# define DMA_PERIPH_0_SELECT DMA_CHXCTL_PERIEN(0) /* peripheral 0 select */
# define DMA_PERIPH_1_SELECT DMA_CHXCTL_PERIEN(1) /* peripheral 1 select */
# define DMA_PERIPH_2_SELECT DMA_CHXCTL_PERIEN(2) /* peripheral 2 select */
# define DMA_PERIPH_3_SELECT DMA_CHXCTL_PERIEN(3) /* peripheral 3 select */
# define DMA_PERIPH_4_SELECT DMA_CHXCTL_PERIEN(4) /* peripheral 4 select */
# define DMA_PERIPH_5_SELECT DMA_CHXCTL_PERIEN(5) /* peripheral 5 select */
# define DMA_PERIPH_6_SELECT DMA_CHXCTL_PERIEN(6) /* peripheral 6 select */
# define DMA_PERIPH_7_SELECT DMA_CHXCTL_PERIEN(7) /* peripheral 7 select */
/* DMA_CHxCNT, x=0..7 */
#define DMA_CHXCNT_CNT_MASK (0xffff << 0) /* Bit 0-15: transfer counter */
/* DMA_CHxPADDR,x=0..7 */
#define DMA_CHXPADDR_PADDR_MASK (0xffffffff << 0) /* Bit 0-31: peripheral base address */
/* DMA_CHxM0ADDR,x=0..7 */
#define DMA_CHXM0ADDR_M0ADDR_MASK (0xffffffff << 0) /* Bit 0-31: memory 0 base address */
/* DMA_CHxM1ADDR,x=0..7 */
#define DMA_CHXM1ADDR_M0ADDR_MASK (0xffffffff << 0) /* Bit 0-31: memory 1 base address */
/* DMA_CHxFCTL,x=0..7 */
#define DMA_CHXFCTL_FCCV_SHIFT (0) /* Bit 0-1: FIFO counter critical value */
#define DMA_CHXFCTL_FCCV_MASK (3 << DMA_CHXFCTL_FCCV_SHIFT)
#define DMA_CHXFCTL_FCCV(n) ((n) << DMA_CHXFCTL_FCCV_SHIFT)
# define DMA_FIFO_1_WORD DMA_CHXFCTL_FCCV(0) /* critical value 1 word */
# define DMA_FIFO_2_WORD DMA_CHXFCTL_FCCV(1) /* critical value 2 word */
# define DMA_FIFO_3_WORD DMA_CHXFCTL_FCCV(2) /* critical value 3 word */
# define DMA_FIFO_4_WORD DMA_CHXFCTL_FCCV(3) /* critical value 4 word */
#define DMA_CHXFCTL_MDMEN (1 << 2) /* Bit 2: multi-data mode enable */
#define DMA_CHXFCTL_FCNT_SHIFT (3) /* Bit 3-5: FIFO counter */
#define DMA_CHXFCTL_FCNT_MASK (7 << DMA_CHXFCTL_FCNT_SHIFT)
#define DMA_CHXFCTL_FCNT(n) ((n) << DMA_CHXFCTL_FCNT_SHIFT)
#define DMA_CHXFCTL_FEEIE (1 << 7) /* Bit 3: FIFO exception interrupt enable */
#define GD32_DMA_FLAG_ADD(flag,channel) ((uint32_t)((flag)<<((((uint32_t)(channel)*6U))+((uint32_t)(((uint32_t)(channel)) >> 1U)&0x01U)*4U))) /* DMA channel flag shift */
/* peripheral increasing mode */
#define DMA_PERIPH_INCREASE_ENABLE (0x00000000) /* Next address of peripheral is increasing address mode */
#define DMA_PERIPH_INCREASE_DISABLE (0x00000001) /* Next address of peripheral is fixed address mode */
#define DMA_PERIPH_INCREASE_FIX (0x00000002) /* Next address of peripheral is increasing fixed */
/* memory increasing mode */
#define DMA_MEMORY_INCREASE_ENABLE (0x00000000) /* Next address of memory is increasing address mode */
#define DMA_MEMORY_INCREASE_DISABLE (0x00000001) /* Next address of memory is fixed address mode */
/* DMA circular mode */
#define DMA_CIRCULAR_MODE_ENABLE (0x00000000) /* Circular mode enable */
#define DMA_CIRCULAR_MODE_DISABLE (0x00000001) /* Circular mode disable */
/* DMA width selection */
#define DMA_WIDTH_8BITS_SELECT (0x00000000) /* Select 8 bits width */
#define DMA_WIDTH_16BITS_SELECT (0x00000001) /* Select 16 bits width */
#define DMA_WIDTH_32BITS_SELECT (0x00000002) /* Select 16 bits width */
/* DMA priority level selection */
#define DMA_PRIO_LOW_SELECT (0x00000000) /* Select low priority level */
#define DMA_PRIO_MEDIUM_SELECT (0x00000001) /* Select medium priority level */
#define DMA_PRIO_HIGH_SELECT (0x00000002) /* Select high priority level */
#define DMA_PRIO_ULTRA_HIGHSELECT (0x00000003) /* Select ultra high priority level */
/* DMA channel select */
#define GD32_DMA_CH0 (0) /* DMA Channel 0 */
#define GD32_DMA_CH1 (1) /* DMA Channel 1 */
#define GD32_DMA_CH2 (2) /* DMA Channel 2 */
#define GD32_DMA_CH3 (3) /* DMA Channel 3 */
#define GD32_DMA_CH4 (4) /* DMA Channel 4 */
#define GD32_DMA_CH5 (5) /* DMA Channel 5 */
#define GD32_DMA_CH6 (6) /* DMA Channel 6 */
#define GD32_DMA_CH7 (7) /* DMA Channel 7 */
/* DMA peripheral select */
#define GD32_DMA_SUBPERI0 (0) /* DMA Peripheral 0 */
#define GD32_DMA_SUBPERI1 (1) /* DMA Peripheral 1 */
#define GD32_DMA_SUBPERI2 (2) /* DMA Peripheral 2 */
#define GD32_DMA_SUBPERI3 (3) /* DMA Peripheral 3 */
#define GD32_DMA_SUBPERI4 (4) /* DMA Peripheral 4 */
#define GD32_DMA_SUBPERI5 (5) /* DMA Peripheral 5 */
#define GD32_DMA_SUBPERI6 (6) /* DMA Peripheral 6 */
#define GD32_DMA_SUBPERI7 (7) /* DMA Peripheral 7 */
/* DMA peripheral requests mapping */
#define CHANNEL_SHIFT (0)
#define CHANNEL_MASK (0xf)
#define PERIPH_SHIFT (4)
#define PERIPH_MASK (0x7)
/* Peripheral requests to DMA0 */
#define DMA_REQ_SPI2_RX_1 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | (GD32_DMA_CH0 << CHANNEL_SHIFT))
#define DMA_REQ_I2C0_RX_1 ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | (GD32_DMA_CH0 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER3_CH0 ((GD32_DMA_SUBPERI2 << PERIPH_SHIFT) | (GD32_DMA_CH0 << CHANNEL_SHIFT))
#define DMA_REQ_I2S2_ADD_RX_1 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | (GD32_DMA_CH0 << CHANNEL_SHIFT))
#define DMA_REQ_UART4_RX ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | (GD32_DMA_CH0 << CHANNEL_SHIFT))
#define DMA_REQ_UART7_TX ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | (GD32_DMA_CH0 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER4_CH2 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | (GD32_DMA_CH0 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER4_UP_1 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | (GD32_DMA_CH0 << CHANNEL_SHIFT))
#define DMA_REQ_I2S2_ADD_RX ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | (GD32_DMA_CH0 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER1_UP_1 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | (GD32_DMA_CH1 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER1_CH2 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | (GD32_DMA_CH1 << CHANNEL_SHIFT))
#define DMA_REQ_USART2_RX ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | (GD32_DMA_CH1 << CHANNEL_SHIFT))
#define DMA_REQ_UART6_TX ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | (GD32_DMA_CH1 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER4_CH3_1 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | (GD32_DMA_CH1 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER4_TG ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | (GD32_DMA_CH1 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER5_UP ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | (GD32_DMA_CH1 << CHANNEL_SHIFT))
#define DMA_REQ_SPI2_RX_2 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | (GD32_DMA_CH2 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER6_UP_1 ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | (GD32_DMA_CH2 << CHANNEL_SHIFT))
#define DMA_REQ_I2S2_ADD_RX_2 ((GD32_DMA_SUBPERI2 << PERIPH_SHIFT) | (GD32_DMA_CH2 << CHANNEL_SHIFT))
#define DMA_REQ_I2C2_RX ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | (GD32_DMA_CH2 << CHANNEL_SHIFT))
#define DMA_REQ_UART3_RX ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | (GD32_DMA_CH2 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER2_CH3 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | (GD32_DMA_CH2 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER2_UP_1 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | (GD32_DMA_CH2 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER4_CH0 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | (GD32_DMA_CH2 << CHANNEL_SHIFT))
#define DMA_REQ_I2C1_RX_1 ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | (GD32_DMA_CH2 << CHANNEL_SHIFT))
#define DMA_REQ_SPI1_RX ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | (GD32_DMA_CH3 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER3_CH1 ((GD32_DMA_SUBPERI2 << PERIPH_SHIFT) | (GD32_DMA_CH3 << CHANNEL_SHIFT))
#define DMA_REQ_I2S1_ADD_RX ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | (GD32_DMA_CH3 << CHANNEL_SHIFT))
#define DMA_REQ_USART2_TX_1 ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | (GD32_DMA_CH3 << CHANNEL_SHIFT))
#define DMA_REQ_UART6_RX ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | (GD32_DMA_CH3 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER4_CH3_2 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | (GD32_DMA_CH3 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER4_UP_2 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | (GD32_DMA_CH3 << CHANNEL_SHIFT))
#define DMA_REQ_I2C1_RX_2 ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | (GD32_DMA_CH3 << CHANNEL_SHIFT))
#define DMA_REQ_SPI1_TX ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | (GD32_DMA_CH4 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER6_UP_2 ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | (GD32_DMA_CH4 << CHANNEL_SHIFT))
#define DMA_REQ_I2S1_ADD_TX ((GD32_DMA_SUBPERI2 << PERIPH_SHIFT) | (GD32_DMA_CH4 << CHANNEL_SHIFT))
#define DMA_REQ_I2C2_TX ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | (GD32_DMA_CH4 << CHANNEL_SHIFT))
#define DMA_REQ_UART3_TX ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | (GD32_DMA_CH4 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER2_CH0 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | (GD32_DMA_CH4 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER2_UP_2 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | (GD32_DMA_CH4 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER4_CH1 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | (GD32_DMA_CH4 << CHANNEL_SHIFT))
#define DMA_REQ_USART2_TX_2 ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | (GD32_DMA_CH4 << CHANNEL_SHIFT))
#define DMA_REQ_SPI2_TX_1 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | (GD32_DMA_CH5 << CHANNEL_SHIFT))
#define DMA_REQ_I2C0_RX ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | (GD32_DMA_CH5 << CHANNEL_SHIFT))
#define DMA_REQ_I2S2_ADD_TX ((GD32_DMA_SUBPERI2 << PERIPH_SHIFT) | (GD32_DMA_CH5 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER1_CH0 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | (GD32_DMA_CH5 << CHANNEL_SHIFT))
#define DMA_REQ_USART1_RX ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | (GD32_DMA_CH5 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER2_CH1 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | (GD32_DMA_CH5 << CHANNEL_SHIFT))
#define DMA_REQ_DAC0 ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | (GD32_DMA_CH5 << CHANNEL_SHIFT))
#define DMA_REQ_I2C0_TX_1 ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | (GD32_DMA_CH6 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER3_UP ((GD32_DMA_SUBPERI2 << PERIPH_SHIFT) | (GD32_DMA_CH6 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER1_CH1 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | (GD32_DMA_CH6 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER1_CH3_1 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | (GD32_DMA_CH6 << CHANNEL_SHIFT))
#define DMA_REQ_USART1_TX ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | (GD32_DMA_CH6 << CHANNEL_SHIFT))
#define DMA_REQ_UART7_RX ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | (GD32_DMA_CH6 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER4_UP ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | (GD32_DMA_CH6 << CHANNEL_SHIFT))
#define DMA_REQ_DAC1 ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | (GD32_DMA_CH6 << CHANNEL_SHIFT))
#define DMA_REQ_SPI2_TX_2 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | (GD32_DMA_CH7 << CHANNEL_SHIFT))
#define DMA_REQ_I2C0_TX_2 ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | (GD32_DMA_CH7 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER3_CH2 ((GD32_DMA_SUBPERI2 << PERIPH_SHIFT) | (GD32_DMA_CH7 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER1_UP_2 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | (GD32_DMA_CH7 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER1_CH3_2 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | (GD32_DMA_CH7 << CHANNEL_SHIFT))
#define DMA_REQ_UART4_TX ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | (GD32_DMA_CH7 << CHANNEL_SHIFT))
#define DMA_REQ_TIMER2_CH2 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | (GD32_DMA_CH7 << CHANNEL_SHIFT))
#define DMA_REQ_I2C1_TX ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | (GD32_DMA_CH7 << CHANNEL_SHIFT))
/* Peripheral requests to DMA1 */
#define DMA_REQ_ADC0_1 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | ((GD32_DMA_CH0 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_ADC2_1 ((GD32_DMA_SUBPERI2 << PERIPH_SHIFT) | ((GD32_DMA_CH0 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI0_RX_1 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | ((GD32_DMA_CH0 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI3_RX_1 ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | ((GD32_DMA_CH0 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_TG_1 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | ((GD32_DMA_CH0 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_DCI_1 ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | ((GD32_DMA_CH1 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_ADC2_2 ((GD32_DMA_SUBPERI2 << PERIPH_SHIFT) | ((GD32_DMA_CH1 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI3_TX_1 ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | ((GD32_DMA_CH1 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_USART5_RX_1 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | ((GD32_DMA_CH1 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_CH0_1 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | ((GD32_DMA_CH1 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER7_UP ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | ((GD32_DMA_CH1 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER7_CH0_1 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | ((GD32_DMA_CH2 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER7_CH1_1 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | ((GD32_DMA_CH2 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER7_CH2_1 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | ((GD32_DMA_CH2 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_ADC1_1 ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | ((GD32_DMA_CH2 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI0_RX_2 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | ((GD32_DMA_CH2 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_USART0_RX_1 ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | ((GD32_DMA_CH2 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_USART5_RX_2 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | ((GD32_DMA_CH2 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_CH1_1 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | ((GD32_DMA_CH2 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER7_CH0_2 ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | ((GD32_DMA_CH2 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_ADC1_2 ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | ((GD32_DMA_CH3 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI4_RX_1 ((GD32_DMA_SUBPERI2 << PERIPH_SHIFT) | ((GD32_DMA_CH3 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI0_TX_1 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | ((GD32_DMA_CH3 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SDIO_1 ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | ((GD32_DMA_CH3 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI3_RX_2 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | ((GD32_DMA_CH3 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_CH0_2 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | ((GD32_DMA_CH3 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER7_CH1_2 ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | ((GD32_DMA_CH3 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_ADC0_2 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | ((GD32_DMA_CH4 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI4_TX_1 ((GD32_DMA_SUBPERI2 << PERIPH_SHIFT) | ((GD32_DMA_CH4 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI3_TX_2 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | ((GD32_DMA_CH4 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_CH3 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | ((GD32_DMA_CH4 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_TG_2 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | ((GD32_DMA_CH4 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_CMT ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | ((GD32_DMA_CH4 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER7_CH2_2 ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | ((GD32_DMA_CH4 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI5_TX ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | ((GD32_DMA_CH5 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI0_TX_2 ((GD32_DMA_SUBPERI3 << PERIPH_SHIFT) | ((GD32_DMA_CH5 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_USART0_RX_2 ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | ((GD32_DMA_CH5 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_UP ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | ((GD32_DMA_CH5 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI4_RX_2 ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | ((GD32_DMA_CH5 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_CH0_3 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | ((GD32_DMA_CH6 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_CH1_2 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | ((GD32_DMA_CH6 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_CH2_1 ((GD32_DMA_SUBPERI0 << PERIPH_SHIFT) | ((GD32_DMA_CH6 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI5_RX ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | ((GD32_DMA_CH6 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SDIO_2 ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | ((GD32_DMA_CH6 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_USART5_TX_1 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | ((GD32_DMA_CH6 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER0_CH2_2 ((GD32_DMA_SUBPERI6 << PERIPH_SHIFT) | ((GD32_DMA_CH6 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_SPI4_TX_2 ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | ((GD32_DMA_CH6 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_DCI_2 ((GD32_DMA_SUBPERI1 << PERIPH_SHIFT) | ((GD32_DMA_CH7 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_USART0_TX ((GD32_DMA_SUBPERI4 << PERIPH_SHIFT) | ((GD32_DMA_CH7 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_USART5_TX_2 ((GD32_DMA_SUBPERI5 << PERIPH_SHIFT) | ((GD32_DMA_CH7 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER7_CH3 ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | ((GD32_DMA_CH7 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER7_TG ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | ((GD32_DMA_CH7 + 8) << CHANNEL_SHIFT))
#define DMA_REQ_TIMER7_CMT ((GD32_DMA_SUBPERI7 << PERIPH_SHIFT) | ((GD32_DMA_CH7 + 8) << CHANNEL_SHIFT))
#endif /* __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_DMA_H */
arch/arm/src/gd32f4/hardware/gd32f4xx_enet.h
+924
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/hardware/gd32f4xx_exti.h
+143
View File
@@ -0,0 +1,143 @@
/****************************************************************************
* arch/arm/src/gd32f4/hardware/gd32f4xx_exti.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_EXTI_H
#define __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_EXTI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define GD32_NEXTI 23
#define GD32_EXTI_MASK 0x007fffff
#define GD32_EXTI_BIT(n) (1 << (n))
/* Register Offsets *********************************************************/
#define GD32_EXTI_INTEN_OFFSET 0x0000 /* interrupt enable register offset */
#define GD32_EXTI_EVEN_OFFSET 0x0004 /* event enable register offset */
#define GD32_EXTI_RTEN_OFFSET 0x0008 /* rising edge trigger enable register offset */
#define GD32_EXTI_FTEN_OFFSET 0x000c /* falling trigger enable register offset */
#define GD32_EXTI_SWIEV_OFFSET 0x0010 /* software interrupt event register offset */
#define GD32_EXTI_PD_OFFSET 0x0014 /* pending register offset */
/* Register Addresses *******************************************************/
#define GD32_EXTI_INTEN (GD32_EXTI_BASE+GD32_EXTI_INTEN_OFFSET) /* interrupt enable register */
#define GD32_EXTI_EVEN (GD32_EXTI_BASE+GD32_EXTI_EVEN_OFFSET) /* event enable register */
#define GD32_EXTI_RTEN (GD32_EXTI_BASE+GD32_EXTI_RTEN_OFFSET) /* rising edge trigger enable register */
#define GD32_EXTI_FTEN (GD32_EXTI_BASE+GD32_EXTI_FTEN_OFFSET) /* falling trigger enable register */
#define GD32_EXTI_SWIEV (GD32_EXTI_BASE+GD32_EXTI_SWIEV_OFFSET) /* software interrupt event register */
#define GD32_EXTI_PD (GD32_EXTI_BASE+GD32_EXTI_PD_OFFSET) /* pending register */
/* Register Bitfield Definitions ********************************************/
/* EXTI lines > 15 are associated with internal devices: */
# define EXTI_PVD_LINE (1 << 16) /* EXTI line 16 is connected to the PVD output */
# define EXTI_RTC_ALARM (1 << 17) /* EXTI line 17 is connected to the RTC Alarm event */
# define EXTI_OTGFS_WAKEUP (1 << 18) /* EXTI line 18 is connected to the USB OTG FS Wakeup event */
# define EXTI_ETH_WAKEUP (1 << 19) /* EXTI line 19 is connected to the Ethernet Wakeup event */
# define EXTI_OTGHS_WAKEUP (1 << 20) /* EXTI line 20 is connected to the USB OTG HS Wakeup event */
# define EXTI_RTC_TAMPER (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */
# define EXTI_RTC_TIMESTAMP (1 << 21) /* EXTI line 21 is connected to the RTC Tamper and TimeStamp events */
# define EXTI_RTC_WAKEUP (1 << 22) /* EXTI line 22 is connected to the RTC Wakeup event */
/* Interrupt mask register */
#define EXTI_INTEN_BIT(n) GD32_EXTI_BIT(n) /* 1=Interrupt request from line x is not masked */
#define EXTI_INTEN_SHIFT (0) /* Bits 0-X: Interrupt Mask for all lines */
#define EXTI_INTEN_MASK GD32_EXTI_MASK
/* Event mask register */
#define EXTI_EVEN_BIT(n) GD32_EXTI_BIT(n) /* 1=Event request from line x is not mask */
#define EXTI_EVEN_SHIFT (0) /* Bits Bits 0-X: Event Mask for all lines */
#define EXTI_EVEN_MASK GD32_EXTI_MASK
/* Rising Trigger selection register */
#define EXTI_RTEN_BIT(n) GD32_EXTI_BIT(n) /* 1=Rising trigger enabled (for Event and Interrupt) for input line */
#define EXTI_RTEN_SHIFT (0) /* Bits 0-X: Rising trigger event configuration bit for all lines */
#define EXTI_RTEN_MASK GD32_EXTI_MASK
/* Falling Trigger selection register */
#define EXTI_FTEN_BIT(n) GD32_EXTI_BIT(n) /* 1=Falling trigger enabled (for Event and Interrupt) for input line */
#define EXTI_FTEN_SHIFT (0) /* Bits 0-X: Falling trigger event configuration bitfor all lines */
#define EXTI_FTEN_MASK GD32_EXTI_MASK
/* Software interrupt event register */
#define EXTI_SWIEV_BIT(n) GD32_EXTI_BIT(n) /* 1=Sets the corresponding pending bit in EXTI_PR */
#define EXTI_SWIEV_SHIFT (0) /* Bits 0-X: Software Interrupt for all lines */
#define EXTI_SWIEV_MASK GD32_EXTI_MASK
/* Pending register */
#define EXTI_PD_BIT(n) GD32_EXTI_BIT(n) /* 1=Selected trigger request occurred */
#define EXTI_PD_SHIFT (0) /* Bits 0-X: Pending bit for all lines */
#define EXTI_PD_MASK GD32_EXTI_MASK
/* EXTI line number */
#define EXTI_0 GD32_EXTI_BIT(0) /* EXTI line 0 */
#define EXTI_1 GD32_EXTI_BIT(1) /* EXTI line 1 */
#define EXTI_2 GD32_EXTI_BIT(2) /* EXTI line 2 */
#define EXTI_3 GD32_EXTI_BIT(3) /* EXTI line 3 */
#define EXTI_4 GD32_EXTI_BIT(4) /* EXTI line 4 */
#define EXTI_5 GD32_EXTI_BIT(5) /* EXTI line 5 */
#define EXTI_6 GD32_EXTI_BIT(6) /* EXTI line 6 */
#define EXTI_7 GD32_EXTI_BIT(7) /* EXTI line 7 */
#define EXTI_8 GD32_EXTI_BIT(8) /* EXTI line 8 */
#define EXTI_9 GD32_EXTI_BIT(9) /* EXTI line 9 */
#define EXTI_10 GD32_EXTI_BIT(10) /* EXTI line 10 */
#define EXTI_11 GD32_EXTI_BIT(11) /* EXTI line 11 */
#define EXTI_12 GD32_EXTI_BIT(12) /* EXTI line 12 */
#define EXTI_13 GD32_EXTI_BIT(13) /* EXTI line 13 */
#define EXTI_14 GD32_EXTI_BIT(14) /* EXTI line 14 */
#define EXTI_15 GD32_EXTI_BIT(15) /* EXTI line 15 */
#define EXTI_16 GD32_EXTI_BIT(16) /* EXTI line 16 */
#define EXTI_17 GD32_EXTI_BIT(17) /* EXTI line 17 */
#define EXTI_18 GD32_EXTI_BIT(18) /* EXTI line 18 */
#define EXTI_19 GD32_EXTI_BIT(19) /* EXTI line 19 */
#define EXTI_20 GD32_EXTI_BIT(20) /* EXTI line 20 */
#define EXTI_21 GD32_EXTI_BIT(21) /* EXTI line 21 */
#define EXTI_22 GD32_EXTI_BIT(22) /* EXTI line 22 */
/* External interrupt and event */
#define EXTI_INTERRUPT 0 /* EXTI interrupt mode */
#define EXTI_EVENT 1 /* EXTI event mode */
/* Interrupt trigger mode */
#define EXTI_TRIG_RISING 0 /* EXTI rising edge trigger */
#define EXTI_TRIG_FALLING 1 /* EXTI falling edge trigger */
#define EXTI_TRIG_BOTH 2 /* EXTI rising and falling edge trigger */
#define EXTI_TRIG_NONE 3 /* None EXTI edge trigger */
#endif /* __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_EXTI_H */
arch/arm/src/gd32f4/hardware/gd32f4xx_fmc.h
+297
View File
@@ -0,0 +1,297 @@
/****************************************************************************
* arch/arm/src/gd32f4/hardware/gd32f4xx_fmc.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_FMC_H
#define __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_FMC_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
#define _K(x) ((x)*1024)
#if !defined(CONFIG_GD32F4_FLASH_CONFIG_DEFAULT) && \
!defined(CONFIG_GD32F4_FLASH_CONFIG_E) && \
!defined(CONFIG_GD32F4_FLASH_CONFIG_F) && \
!defined(CONFIG_GD32F4_FLASH_CONFIG_I) && \
!defined(CONFIG_GD32F4_FLASH_CONFIG_K)
# define CONFIG_GD32F4_FLASH_CONFIG_DEFAULT
#endif
/* Flash default size is 512K */
#if defined(CONFIG_GD32F4_FLASH_CONFIG_DEFAULT)
# define GD32_FMC_NSECTORS 8
# define GD32_FMC_SIZE _K((4 * 16) + (1 * 64) + (3 * 128))
# define GD32_FMC_SIZES {_K(16), _K(16), _K(16), _K(16), \
_K(64),_K(128), _K(128), _K(128)}
/* Override of the FLASH Has been Chosen */
#elif !defined(CONFIG_GD32F4_FLASH_CONFIG_DEFAULT)
# if defined(CONFIG_GD32F4_FLASH_CONFIG_E)
# define GD32_FMC_NSECTORS 8
# define GD32_FMC_SIZE _K((4 * 16) + (1 * 64) + (3 * 128))
# define GD32_FMC_SIZES {_K(16), _K(16), _K(16), _K(16), \
_K(64), _K(128), _K(128), _K(128)}
# elif defined(CONFIG_GD32F4_FLASH_CONFIG_G)
# define GD32_FMC_NSECTORS 12
# define GD32_FMC_SIZE _K((4 * 16) + (1 * 64) + (7 * 128))
# define GD32_FMC_SIZES {_K(16), _K(16), _K(16), _K(16), \
_K(64), _K(128), _K(128), _K(128), \
_K(128), _K(128), _K(128), _K(128)}
# elif defined(CONFIG_GD32F4_FLASH_CONFIG_I)
# define GD32_FMC_NSECTORS 24
# define GD32_FMC_SIZE _K((4 * 16) + (1 * 64) + (7 * 128)) + \
_K((4 * 16) + (1 * 64) + (7 * 128))
# define GD32_FMC_SIZES {_K(16), _K(16), _K(16), _K(16), \
_K(64), _K(128), _K(128), _K(128), \
_K(128), _K(128), _K(128), _K(128), \
_K(16), _K(16), _K(16), _K(16), \
_K(64), _K(128), _K(128), _K(128), \
_K(128), _K(128), _K(128), _K(128)}
# elif defined(CONFIG_GD32F4_FLASH_CONFIG_K)
# define GD32_FMC_NSECTORS 28
# define GD32_FMC_SIZE _K((4 * 16) + (1 * 64) + (7 * 128)) + \
_K((4 * 16) + (1 * 64) + (7 * 128))
# define GD32_FMC_SIZES {_K(16), _K(16), _K(16), _K(16), \
_K(64), _K(128), _K(128), _K(128), \
_K(128), _K(128), _K(128), _K(128), \
_K(16), _K(16), _K(16), _K(16), \
_K(64), _K(128), _K(128), _K(128), \
_K(128), _K(128), _K(128), _K(128)}, \
_K(256), _K(256), _K(256), _K(256)}
# endif
#endif /* !defined(CONFIG_GD32F4_FLASH_CONFIG_DEFAULT) */
/* Register Offsets *********************************************************/
#define GD32_FMC_WS_OFFSET 0x0000 /* FMC wait state register offset */
#define GD32_FMC_KEY_OFFSET 0x0004 /* FMC unlock key register offset */
#define GD32_FMC_OBKEY_OFFSET 0x0008 /* FMC option byte register offset */
#define GD32_FMC_STAT_OFFSET 0x000C /* FMC status register offset */
#define GD32_FMC_CTL_OFFSET 0x0010 /* FMC control register offset */
#define GD32_FMC_OBCTL0_OFFSET 0x0014 /* FMC option byte control register 0 offset */
#define GD32_FMC_OBCTL1_OFFSET 0x0018 /* FMC option byte control register 1 offset */
#define GD32_FMC_WSEN_OFFSET 0x00FC /* FMC wait state enable register offset */
#define GD32_FMC_PID_OFFSET 0x0100 /* FMC product ID register offset */
/* Register Addresses *******************************************************/
#define GD32_FMC_WS (GD32_FMC_BASE+GD32_FMC_WS_OFFSET) /* FMC wait state register */
#define GD32_FMC_KEY (GD32_FMC_BASE+GD32_FMC_KEY_OFFSET) /* FMC unlock key register */
#define GD32_FMC_OBKEY (GD32_FMC_BASE+GD32_FMC_OBKEY_OFFSET) /* FMC option byte register */
#define GD32_FMC_STAT (GD32_FMC_BASE+GD32_FMC_STAT_OFFSET) /* FMC status register */
#define GD32_FMC_CTL (GD32_FMC_BASE+GD32_FMC_CTL_OFFSET) /* FMC control register */
#define GD32_FMC_OBCTL0 (GD32_FMC_BASE+GD32_FMC_OBCTL0_OFFSET) /* FMC option byte control register 0 */
#define GD32_FMC_OBCTL1 (GD32_FMC_BASE+GD32_FMC_OBCTL1_OFFSET) /* FMC option byte control register 1 */
#define GD32_FMC_WSEN (GD32_FMC_BASE+GD32_FMC_WSEN_OFFSET) /* FMC wait state enable register */
#define GD32_FMC_PID (GD32_FMC_BASE+GD32_FMC_PID_OFFSET) /* FMC product ID register */
/* Register Bitfield Definitions ********************************************/
/* FMC wait state register */
#define FMC_WS_WSCNT_SHIFT (0)
#define FMC_WS_WSCNT_MASK (15 << FMC_WS_WSCNT_SHIFT)
#define FMC_WC_WSCNT(n) ((n) << FMC_WS_WSCNT_SHIFT)
#define FMC_WS_WSCNT_0 WC_WSCNT(0) /* FMC 0 wait */
#define FMC_WS_WSCNT_1 WC_WSCNT(1) /* FMC 1 wait */
#define FMC_WS_WSCNT_2 WC_WSCNT(2) /* FMC 2 wait */
#define FMC_WS_WSCNT_3 WC_WSCNT(3) /* FMC 3 wait */
#define FMC_WS_WSCNT_4 WC_WSCNT(4) /* FMC 4 wait */
#define FMC_WS_WSCNT_5 WC_WSCNT(5) /* FMC 5 wait */
#define FMC_WS_WSCNT_6 WC_WSCNT(6) /* FMC 6 wait */
#define FMC_WS_WSCNT_7 WC_WSCNT(7) /* FMC 7 wait */
#define FMC_WS_WSCNT_8 WC_WSCNT(8) /* FMC 8 wait */
#define FMC_WS_WSCNT_9 WC_WSCNT(9) /* FMC 9 wait */
#define FMC_WS_WSCNT_10 WC_WSCNT(10) /* FMC 10 wait */
#define FMC_WS_WSCNT_11 WC_WSCNT(11) /* FMC 11 wait */
#define FMC_WS_WSCNT_12 WC_WSCNT(12) /* FMC 12 wait */
#define FMC_WS_WSCNT_13 WC_WSCNT(13) /* FMC 13 wait */
#define FMC_WS_WSCNT_14 WC_WSCNT(14) /* FMC 14 wait */
#define FMC_WS_WSCNT_15 WC_WSCNT(15) /* FMC 15 wait */
/* FMC status register */
#define FMC_STAT_END (1 << 0) /* Bit 0: end of operation flag bit */
#define FMC_STAT_OPERR (1 << 1) /* Bit 1: flash operation error flag bit */
#define FMC_STAT_WPERR (1 << 4) /* Bit 4: erase/Program protection error flag bit */
#define FMC_STAT_PGMERR (1 << 5) /* Bit 5: program size not match error flag bit */
#define FMC_STAT_PGSERR (1 << 6) /* Bit 6: program sequence error flag bit */
#define FMC_STAT_RDDERR (1 << 7) /* Bit 7: read D-bus protection error flag bit */
#define FMC_STAT_BUSY (1 << 16) /* Bit 16: flash busy flag bit */
/* FMC control register */
#define FMC_CTL_PG (1 << 0) /* Bit 0: main flash program command bit */
#define FMC_CTL_SER (1 << 1) /* Bit 1: main flash sector erase command bit */
#define FMC_CTL_MER0 (1 << 2) /* Bit 2: main flash mass erase for bank0 command bit */
#define FMC_CTL_SN_SHIFT (3) /* Bits 3-7: select which sector number to be erased */
#define FMC_CTL_SN_MASK (31 << FMC_CTL_SN_SHIFT)
#define FMC_CTL_SN(n) ((n) << FMC_CTL_SN_SHIFT) /* Sector n, n=0..11 */
#define FMC_CTL_SN_0_11(n) ((n) << FMC_CTL_SN_SHIFT) /* Sector n, n=0..11 */
#define FMC_CTL_SN_12_23(n) ((n+4) << FMC_CTL_SN_SHIFT)) /* Sector n, n=12..23 */
#define FMC_CTL_SN_24_27(n) ((n-12) << FMC_CTL_SN_SHIFT)) /* Sector n, n=24..27 */
#define FMC_CTL_SN_0 (0 << FMC_CTL_SN_SHIFT) /* sector 0 */
#define FMC_CTL_SN_1 (1 << FMC_CTL_SN_SHIFT) /* sector 1 */
#define FMC_CTL_SN_2 (2 << FMC_CTL_SN_SHIFT) /* sector 2 */
#define FMC_CTL_SN_3 (3 << FMC_CTL_SN_SHIFT) /* sector 3 */
#define FMC_CTL_SN_4 (4 << FMC_CTL_SN_SHIFT) /* sector 4 */
#define FMC_CTL_SN_5 (5 << FMC_CTL_SN_SHIFT) /* sector 5 */
#define FMC_CTL_SN_6 (6 << FMC_CTL_SN_SHIFT) /* sector 6 */
#define FMC_CTL_SN_7 (7 << FMC_CTL_SN_SHIFT) /* sector 7 */
#define FMC_CTL_SN_8 (8 << FMC_CTL_SN_SHIFT) /* sector 8 */
#define FMC_CTL_SN_9 (9 << FMC_CTL_SN_SHIFT) /* sector 9 */
#define FMC_CTL_SN_10 (10 << FMC_CTL_SN_SHIFT) /* sector 10 */
#define FMC_CTL_SN_11 (11 << FMC_CTL_SN_SHIFT) /* sector 11 */
#define FMC_CTL_SN_12 (16 << FMC_CTL_SN_SHIFT) /* sector 12 */
#define FMC_CTL_SN_13 (17 << FMC_CTL_SN_SHIFT) /* sector 13 */
#define FMC_CTL_SN_14 (18 << FMC_CTL_SN_SHIFT) /* sector 14 */
#define FMC_CTL_SN_15 (19 << FMC_CTL_SN_SHIFT) /* sector 15 */
#define FMC_CTL_SN_16 (20 << FMC_CTL_SN_SHIFT) /* sector 16 */
#define FMC_CTL_SN_17 (21 << FMC_CTL_SN_SHIFT) /* sector 17 */
#define FMC_CTL_SN_18 (22 << FMC_CTL_SN_SHIFT) /* sector 18 */
#define FMC_CTL_SN_19 (23 << FMC_CTL_SN_SHIFT) /* sector 19 */
#define FMC_CTL_SN_20 (24 << FMC_CTL_SN_SHIFT) /* sector 20 */
#define FMC_CTL_SN_21 (25 << FMC_CTL_SN_SHIFT) /* sector 21 */
#define FMC_CTL_SN_22 (26 << FMC_CTL_SN_SHIFT) /* sector 22 */
#define FMC_CTL_SN_23 (27 << FMC_CTL_SN_SHIFT) /* sector 23 */
#define FMC_CTL_SN_24 (12 << FMC_CTL_SN_SHIFT) /* sector 24 */
#define FMC_CTL_SN_25 (13 << FMC_CTL_SN_SHIFT) /* sector 25 */
#define FMC_CTL_SN_26 (14 << FMC_CTL_SN_SHIFT) /* sector 26 */
#define FMC_CTL_SN_27 (15 << FMC_CTL_SN_SHIFT) /* sector 27 */
#define FMC_CTL_PSZ_SHIFT (8) /* Bits 8-9: Program size */
#define FMC_CTL_PSZ_MASK (3 << FMC_CTL_PSZ_SHIFT)
#define FMC_CTL_PSZ_BYTE (0 << FMC_CTL_PSZ_SHIFT) /* FMC program by byte access */
#define FMC_CTL_PSZ_HALF_WORD (1 << FMC_CTL_PSZ_SHIFT) /* FMC program by half-word access */
#define FMC_CTL_PSZ_WORD (2 << FMC_CTL_PSZ_SHIFT) /* FMC program by word access */
#define FMC_CTL_MER1 (1 << 15) /* Bit 15: main flash mass erase for bank1 command bit */
#define FMC_CTL_START (1 << 16) /* Bit 16: send erase command to FMC bit */
#define FMC_CTL_ENDIE (1 << 24) /* Bit 24: end of operation interrupt enable bit */
#define FMC_CTL_ERRIE (1 << 25) /* Bit 25: error interrupt enable bit */
#define FMC_CTL_LK (1 << 31) /* Bit 31: FMC_CTL lock bit */
/* FMC option byte control register 0 */
#define FMC_OBCTL0_OB_LK (1 << 0) /* Bit 0: FMC_OBCTL0 lock bit */
#define FMC_OBCTL0_OB_START (1 << 1) /* Bit 1: send option byte change command to FMC bit */
#define FMC_OBCTL0_BOR_TH_SHIFT (2) /* Bits 2-3: Boption byte BOR threshold value */
#define FMC_OBCTL0_BOR_TH_MASK (3 << FLASH_OPTCR_BORLEV_SHIFT)
#define FMC_OB_BOR_TH_VALUE3 (0 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR threshold value 3 */
#define FMC_OB_BOR_TH_VALUE2 (1 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR threshold value 2 */
#define FMC_OB_BOR_TH_VALUE1 (2 << FLASH_OPTCR_BORLEV_SHIFT) /* BOR threshold value 1 */
#define FMC_OB_BOR_TH_VALUE0 (3 << FLASH_OPTCR_BORLEV_SHIFT) /* no BOR function */
#define FMC_OBCTL0_BB (1 << 4) /* Bit 4: option byte boot bank value */
#define FMC_OBCTL0_NWDG_HW (1 << 5) /* Bit 5: option byte watchdog value */
#define FMC_OBCTL0_NRST_DPSLP (1 << 5) /* Bit 6: option byte deepsleep value */
#define FMC_OBCTL0_NRST_STDBY (1 << 7) /* Bit 7: option byte standby value */
#define FMC_OBCTL0_SPC_SHIFT (8) /* Bits 8-15: option byte Security Protection code */
#define FMC_OBCTL0_SPC_MASK (0xff << FMC_OBCTL0_SPC_SHIFT)
#define FMC_OBCTL0_WP0_SHIFT (16) /* Bits 16-27: erase/program protection of each sector when DRP is 0 */
#define FMC_OBCTL0_WP0_MASK (0xfff << FMC_OBCTL0_WP0_SHIFT)
#define FMC_OBCTL0_DBS (1 << 30) /* Bit 30: double banks or single bank selection when flash size is 1M bytes */
#define FMC_OBCTL0_DRP (1 << 31) /* Bit 31: D-bus read protection bit */
/* FMC option byte control register 1 */
#define FMC_OBCTL1_WP1_SHIFT (16) /* Bits 16-27: erase/program protection of each sector when DRP is 0 */
#define FMC_OBCTL1_WP1_MASK (0xfff << FMC_OBCTL1_WP1_SHIFT)
/* FMC wait state enable register */
#define FMC_WSEN_WSEN (1 << 0) /* FMC wait state enable bit */
/* FMC unlock key */
#define FMC_UNLOCK_KEY0 (0x45670123) /* Unlock key 0 */
#define FMC_UNLOCK_KEY1 (0xCDEF89AB) /* Unlock key 1 */
#define FMC_OB_UNLOCK_KEY0 (0x08192A3B) /* ob unlock key 0 */
#define FMC_OB_UNLOCK_KEY1 (0x4C5D6E7F) /* ob unlock key 1 */
/* option bytes write protection */
#define FMC_OB_WP_0 (0x00000001) /* erase/program protection of sector 0 */
#define FMC_OB_WP_1 (0x00000002) /* erase/program protection of sector 1 */
#define FMC_OB_WP_2 (0x00000004) /* erase/program protection of sector 2 */
#define FMC_OB_WP_3 (0x00000008) /* erase/program protection of sector 3 */
#define FMC_OB_WP_4 (0x00000010) /* erase/program protection of sector 4 */
#define FMC_OB_WP_5 (0x00000020) /* erase/program protection of sector 5 */
#define FMC_OB_WP_6 (0x00000040) /* erase/program protection of sector 6 */
#define FMC_OB_WP_7 (0x00000080) /* erase/program protection of sector 7 */
#define FMC_OB_WP_8 (0x00000100) /* erase/program protection of sector 8 */
#define FMC_OB_WP_9 (0x00000200) /* erase/program protection of sector 9 */
#define FMC_OB_WP_10 (0x00000400) /* erase/program protection of sector 10 */
#define FMC_OB_WP_11 (0x00000800) /* erase/program protection of sector 11 */
#define FMC_OB_WP_12 (0x00010000) /* erase/program protection of sector 12 */
#define FMC_OB_WP_13 (0x00020000) /* erase/program protection of sector 13 */
#define FMC_OB_WP_14 (0x00040000) /* erase/program protection of sector 14 */
#define FMC_OB_WP_15 (0x00080000) /* erase/program protection of sector 15 */
#define FMC_OB_WP_16 (0x00100000) /* erase/program protection of sector 16 */
#define FMC_OB_WP_17 (0x00200000) /* erase/program protection of sector 17 */
#define FMC_OB_WP_18 (0x00400000) /* erase/program protection of sector 18 */
#define FMC_OB_WP_19 (0x00800000) /* erase/program protection of sector 19 */
#define FMC_OB_WP_20 (0x01000000) /* erase/program protection of sector 20 */
#define FMC_OB_WP_21 (0x02000000) /* erase/program protection of sector 21 */
#define FMC_OB_WP_22 (0x04000000) /* erase/program protection of sector 22 */
#define FMC_OB_WP_23_27 (0x08000000) /* erase/program protection of sector 23~27 */
#define FMC_OB_WP_ALL (0x0FFF0FFF) /* erase/program protection of all sectors */
/* option bytes D-bus read protection */
#define FMC_OB_DRP_0 (0x00000001) /* D-bus read protection protection of sector 0 */
#define FMC_OB_DRP_1 (0x00000002) /* D-bus read protection protection of sector 1 */
#define FMC_OB_DRP_2 (0x00000004) /* D-bus read protection protection of sector 2 */
#define FMC_OB_DRP_3 (0x00000008) /* D-bus read protection protection of sector 3 */
#define FMC_OB_DRP_4 (0x00000010) /* D-bus read protection protection of sector 4 */
#define FMC_OB_DRP_5 (0x00000020) /* D-bus read protection protection of sector 5 */
#define FMC_OB_DRP_6 (0x00000040) /* D-bus read protection protection of sector 6 */
#define FMC_OB_DRP_7 (0x00000080) /* D-bus read protection protection of sector 7 */
#define FMC_OB_DRP_8 (0x00000100) /* D-bus read protection protection of sector 8 */
#define FMC_OB_DRP_9 (0x00000200) /* D-bus read protection protection of sector 9 */
#define FMC_OB_DRP_10 (0x00000400) /* D-bus read protection protection of sector 10 */
#define FMC_OB_DRP_11 (0x00000800) /* D-bus read protection protection of sector 11 */
#define FMC_OB_DRP_12 (0x00010000) /* D-bus read protection protection of sector 12 */
#define FMC_OB_DRP_13 (0x00020000) /* D-bus read protection protection of sector 13 */
#define FMC_OB_DRP_14 (0x00040000) /* D-bus read protection protection of sector 14 */
#define FMC_OB_DRP_15 (0x00080000) /* D-bus read protection protection of sector 15 */
#define FMC_OB_DRP_16 (0x00100000) /* D-bus read protection protection of sector 16 */
#define FMC_OB_DRP_17 (0x00200000) /* D-bus read protection protection of sector 17 */
#define FMC_OB_DRP_18 (0x00400000) /* D-bus read protection protection of sector 18 */
#define FMC_OB_DRP_19 (0x00800000) /* D-bus read protection protection of sector 19 */
#define FMC_OB_DRP_20 (0x01000000) /* D-bus read protection protection of sector 20 */
#define FMC_OB_DRP_21 (0x02000000) /* D-bus read protection protection of sector 21 */
#define FMC_OB_DRP_22 (0x04000000) /* D-bus read protection protection of sector 22 */
#define FMC_OB_DRP_23_27 (0x08000000) /* D-bus read protection protection of sector 23~27 */
#define FMC_OB_DRP_ALL (0x0FFF0FFF) /* D-bus read protection protection of all sectors */
/* FMC time out */
#define FMC_TIMEOUT_COUNT (0x4FFFFFFF) /* count to judge of FMC timeout */
#endif /* __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_FMC_H */
arch/arm/src/gd32f4/hardware/gd32f4xx_gpio.h
+217
View File
@@ -0,0 +1,217 @@
/****************************************************************************
* arch/arm/src/gd32f4/hardware/gd32f4xx_gpio.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32_HARDWARE_GD32F4XX_GPIO_H
#define __ARCH_ARM_SRC_GD32_HARDWARE_GD32F4XX_GPIO_H
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* GPIOx(x=A,B,C,D,E,F,G,H,I) definitions ***********************************/
#define GD32_GPIOA_BASE (GD32_GPIO_BASE + 0x00000000)
#define GD32_GPIOB_BASE (GD32_GPIO_BASE + 0x00000400)
#define GD32_GPIOC_BASE (GD32_GPIO_BASE + 0x00000800)
#define GD32_GPIOD_BASE (GD32_GPIO_BASE + 0x00000c00)
#define GD32_GPIOE_BASE (GD32_GPIO_BASE + 0x00001000)
#define GD32_GPIOF_BASE (GD32_GPIO_BASE + 0x00001400)
#define GD32_GPIOG_BASE (GD32_GPIO_BASE + 0x00001800)
#define GD32_GPIOH_BASE (GD32_GPIO_BASE + 0x00001c00)
#define GD32_GPIOI_BASE (GD32_GPIO_BASE + 0x00002000)
/* Register Offsets *********************************************************/
#define GD32_GPIO_CTL_OFFSET 0x0000 /* GPIO port control register offfset */
#define GD32_GPIO_OMODE_OFFSET 0x0004 /* GPIO port output mode register offfset */
#define GD32_GGPIO_OSPD_OFFSET 0x0008 /* GPIO port output speed register offfset */
#define GD32_GPIO_PUD_OFFSET 0x000c /* GPIO port pull-up/pull-down register offfset */
#define GD32_GPIO_ISTAT_OFFSET 0x0010 /* GPIO port input status register offfset */
#define GD32_GPIO_OCTL_OFFSET 0x0014 /* GPIO port output control register offfset */
#define GD32_GPIO_BOP_OFFSET 0x0018 /* GPIO port bit operation register offfset */
#define GD32_GPIO_LOCK_OFFSET 0x001c /* GPIO port configuration lock register offfset */
#define GD32_GPIO_AFSEL0_OFFSET 0x0020 /* GPIO alternate function selected register 0 offfset */
#define GD32_GPIO_AFSEL1_OFFSET 0x0024 /* GPIO alternate function selected register 1 offfset */
#define GD32_GPIO_BC_OFFSET 0x0028 /* GPIO bit clear register offfset */
#define GD32_GPIO_TG_OFFSET 0x002c /* GPIO port bit toggle register offfset */
/* Register Addresses *******************************************************/
#define GD32_GPIOA GD32_GPIOA_BASE
#define GD32_GPIOB GD32_GPIOB_BASE
#define GD32_GPIOC GD32_GPIOC_BASE
#define GD32_GPIOD GD32_GPIOD_BASE
#define GD32_GPIOE GD32_GPIOE_BASE
#define GD32_GPIOF GD32_GPIOF_BASE
#define GD32_GPIOG GD32_GPIOG_BASE
#define GD32_GPIOH GD32_GPIOH_BASE
#define GD32_GPIOI GD32_GPIOI_BASE
#define GD32_GPIO_CTL(gpiox) ((gpiox)+GD32_GPIO_CTL_OFFSET) /* GPIO port control register */
#define GD32_GPIO_OMODE(gpiox) ((gpiox)+GD32_GPIO_OMODE_OFFSET) /* GPIO port output mode register */
#define GD32_GPIO_OSPD(gpiox) ((gpiox)+GD32_GGPIO_OSPD_OFFSET) /* GPIO port output speed register */
#define GD32_GPIO_PUD(gpiox) ((gpiox)+GD32_GPIO_PUD_OFFSET) /* GPIO port pull-up/pull-down register */
#define GD32_GPIO_ISTAT(gpiox) ((gpiox)+GD32_GPIO_ISTAT_OFFSET) /* GPIO port input status register */
#define GD32_GPIO_OCTL(gpiox) ((gpiox)+GD32_GPIO_OCTL_OFFSET) /* GPIO port output control register */
#define GD32_GPIO_BOP(gpiox) ((gpiox)+GD32_GPIO_BOP_OFFSET) /* GPIO port bit operation register */
#define GD32_GPIO_LOCK(gpiox) ((gpiox)+GD32_GPIO_LOCK_OFFSET) /* GPIO port configuration lock register */
#define GD32_GPIO_AFSEL0(gpiox) ((gpiox)+GD32_GPIO_AFSEL0_OFFSET) /* GPIO alternate function selected register 0 */
#define GD32_GPIO_AFSEL1(gpiox) ((gpiox)+GD32_GPIO_AFSEL1_OFFSET) /* GPIO alternate function selected register 1 */
#define GD32_GPIO_BC(gpiox) ((gpiox)+GD32_GPIO_BC_OFFSET) /* GPIO bit clear register */
#define GD32_GPIO_TG(gpiox) ((gpiox)+GD32_GPIO_TG_OFFSET) /* GPIO port bit toggle register */
/* Register Bitfield Definitions ********************************************/
/* GPIO port control register */
#define GPIO_MODE_INPUT (0) /* Input mode */
#define GPIO_MODE_OUTPUT (1) /* Output mode */
#define GPIO_MODE_AF (2) /* Alternate function mode */
#define GPIO_MODE_ANALOG (3) /* Analog mode */
#define GPIO_MODE_SHIFT(n) ((n) << 1)
#define GPIO_MODE_MASK(n) (3 << GPIO_MODE_SHIFT(n))
#define GPIO_MODE0_MASK (3 << GPIO_MODE_SHIFT(0))
#define GPIO_MODE1_MASK (3 << GPIO_MODE_SHIFT(1))
#define GPIO_MODE2_MASK (3 << GPIO_MODE_SHIFT(2))
#define GPIO_MODE3_MASK (3 << GPIO_MODE_SHIFT(3))
#define GPIO_MODE4_MASK (3 << GPIO_MODE_SHIFT(4))
#define GPIO_MODE5_MASK (3 << GPIO_MODE_SHIFT(5))
#define GPIO_MODE6_MASK (3 << GPIO_MODE_SHIFT(6))
#define GPIO_MODE7_MASK (3 << GPIO_MODE_SHIFT(7))
#define GPIO_MODE8_MASK (3 << GPIO_MODE_SHIFT(8))
#define GPIO_MODE9_MASK (3 << GPIO_MODE_SHIFT(9))
#define GPIO_MODE10_MASK (3 << GPIO_MODE_SHIFT(10))
#define GPIO_MODE11_MASK (3 << GPIO_MODE_SHIFT(11))
#define GPIO_MODE12_MASK (3 << GPIO_MODE_SHIFT(12))
#define GPIO_MODE13_MASK (3 << GPIO_MODE_SHIFT(13))
#define GPIO_MODE14_MASK (3 << GPIO_MODE_SHIFT(14))
#define GPIO_MODE15_MASK (3 << GPIO_MODE_SHIFT(15))
/* GPIO port output mode register */
#define GPIO_OTYPE_OD(n) (1 << (n)) /* 1=Output open drain mode */
#define GPIO_OTYPE_PP(n) (0) /* 0=Output push pull mode */
/* GPIO port output speed register */
#define GPIO_OSPEED_2MHZ (0) /* Output max speed 2MHz */
#define GPIO_OSPEED_25MHZ (1) /* Output max speed 25MHz */
#define GPIO_OSPEED_50MHZ (2) /* Output max speed 50MHz */
#define GPIO_OSPEED_200MHZ (3) /* Output max speed 200MHz */
#define GPIO_OSPEED_SHIFT(n) ((n) << 1)
#define GPIO_OSPEED_MASK(n) (3 << GPIO_OSPEED_SHIFT(n))
#define GPIO_OSPEED0_MASK (3 << GPIO_OSPEED_SHIFT(0))
#define GPIO_OSPEED1_MASK (3 << GPIO_OSPEED_SHIFT(1))
#define GPIO_OSPEED2_MASK (3 << GPIO_OSPEED_SHIFT(2))
#define GPIO_OSPEED3_MASK (3 << GPIO_OSPEED_SHIFT(3))
#define GPIO_OSPEED4_MASK (3 << GPIO_OSPEED_SHIFT(4))
#define GPIO_OSPEED5_MASK (3 << GPIO_OSPEED_SHIFT(5))
#define GPIO_OSPEED6_MASK (3 << GPIO_OSPEED_SHIFT(6))
#define GPIO_OSPEED7_MASK (3 << GPIO_OSPEED_SHIFT(7))
#define GPIO_OSPEED8_MASK (3 << GPIO_OSPEED_SHIFT(8))
#define GPIO_OSPEED9_MASK (3 << GPIO_OSPEED_SHIFT(9))
#define GPIO_OSPEED10_MASK (3 << GPIO_OSPEED_SHIFT(10))
#define GPIO_OSPEED11_MASK (3 << GPIO_OSPEED_SHIFT(11))
#define GPIO_OSPEED12_MASK (3 << GPIO_OSPEED_SHIFT(12))
#define GPIO_OSPEED13_MASK (3 << GPIO_OSPEED_SHIFT(13))
#define GPIO_OSPEED14_MASK (3 << GPIO_OSPEED_SHIFT(14))
#define GPIO_OSPEED15_MASK (3 << GPIO_OSPEED_SHIFT(15))
/* GPIO port pull-up/pull-down register */
#define GPIO_PUPD_NONE (0) /* Floating mode, no pull-up and pull-down resistors */
#define GPIO_PUPD_PULLUP (1) /* With pull-up resistor */
#define GPIO_PUPD_PULLDOWN (2) /* With pull-up resistor */
#define GPIO_PUPD_SHIFT(n) ((n) << 1)
#define GPIO_PUPD_MASK(n) (3 << GPIO_PUPD_SHIFT(n))
#define GPIO_PUPD0_MASK (3 << GPIO_PUPD_SHIFT(0))
#define GPIO_PUPD1_MASK (3 << GPIO_PUPD_SHIFT(1))
#define GPIO_PUPD2_MASK (3 << GPIO_PUPD_SHIFT(2))
#define GPIO_PUPD3_MASK (3 << GPIO_PUPD_SHIFT(3))
#define GPIO_PUPD4_MASK (3 << GPIO_PUPD_SHIFT(4))
#define GPIO_PUPD5_MASK (3 << GPIO_PUPD_SHIFT(5))
#define GPIO_PUPD6_MASK (3 << GPIO_PUPD_SHIFT(6))
#define GPIO_PUPD7_MASK (3 << GPIO_PUPD_SHIFT(7))
#define GPIO_PUPD8_MASK (3 << GPIO_PUPD_SHIFT(8))
#define GPIO_PUPD9_MASK (3 << GPIO_PUPD_SHIFT(9))
#define GPIO_PUPD10_MASK (3 << GPIO_PUPD_SHIFT(10))
#define GPIO_PUPD11_MASK (3 << GPIO_PUPD_SHIFT(11))
#define GPIO_PUPD12_MASK (3 << GPIO_PUPD_SHIFT(12))
#define GPIO_PUPD13_MASK (3 << GPIO_PUPD_SHIFT(13))
#define GPIO_PUPD14_MASK (3 << GPIO_PUPD_SHIFT(14))
#define GPIO_PUPD15_MASK (3 << GPIO_PUPD_SHIFT(15))
/* GPIO port input status register */
#define GPIO_ISTAT(n) (1 << (n))
/* GPIO port output control register */
#define GPIO_OCTL(n) (1 << (n))
/* GPIO port bit operation register */
#define GPIO_BOP_SET(n) (1 << (n))
#define GPIO_BOP_CLEAR(n) (1 << ((n)+16))
/* GPIO port configuration lock register */
#define GPIO_LOCK(n) (1 << (n))
#define GPIO_LOCK_LKK (1 << 16) /* Lock key */
/* GPIO alternate function selected register 0/1 */
#define GPIO_AF_SHIFT(n) ((n) << 2)
#define GPIO_AF_MASK(n) (15 << GPIO_AF_SHIFT(n))
#define GPIO_AFSEL0_SEL0_MASK (15 << GPIO_AF_SHIFT(0))
#define GPIO_AFSEL0_SEL1_MASK (15 << GPIO_AF_SHIFT(1))
#define GPIO_AFSEL0_SEL2_MASK (15 << GPIO_AF_SHIFT(2))
#define GPIO_AFSEL0_SEL3_MASK (15 << GPIO_AF_SHIFT(3))
#define GPIO_AFSEL0_SEL4_MASK (15 << GPIO_AF_SHIFT(4))
#define GPIO_AFSEL0_SEL5_MASK (15 << GPIO_AF_SHIFT(5))
#define GPIO_AFSEL0_SEL6_MASK (15 << GPIO_AF_SHIFT(6))
#define GPIO_AFSEL0_SEL7_MASK (15 << GPIO_AF_SHIFT(7))
#define GPIO_AFSEL1_SEL8_MASK (15 << GPIO_AF_SHIFT(0))
#define GPIO_AFSEL1_SEL9_MASK (15 << GPIO_AF_SHIFT(1))
#define GPIO_AFSEL1_SEL10_MASK (15 << GPIO_AF_SHIFT(2))
#define GPIO_AFSEL1_SEL11_MASK (15 << GPIO_AF_SHIFT(3))
#define GPIO_AFSEL1_SEL12_MASK (15 << GPIO_AF_SHIFT(4))
#define GPIO_AFSEL1_SEL13_MASK (15 << GPIO_AF_SHIFT(5))
#define GPIO_AFSEL1_SEL14_MASK (15 << GPIO_AF_SHIFT(6))
#define GPIO_AFSEL1_SEL15_MASK (15 << GPIO_AF_SHIFT(7))
/* GPIO bit clear register */
#define GPIO_BC_SET(n) (1 << (n))
/* GPIO port bit toggle register */
#define GPIO_TG_SET(n) (1 << (n))
/* GPIO pin definitions */
#define GPIO_PIN(n) (1 << (n)) /* Bit n: Pin n, n=0-15 */
#endif /* __ARCH_ARM_SRC_GD32_HARDWARE_GD32F4XX_GPIO_H */
arch/arm/src/gd32f4/hardware/gd32f4xx_memorymap.h
+38
View File
@@ -0,0 +1,38 @@
/****************************************************************************
* arch/arm/src/gd32f4/hardware/gd32f4xx_memorymap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_MEMORYMAP_H
#define __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_MEMORYMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
#if defined(CONFIG_GD32F4_GD32F450)
# include "hardware/gd32f450_memorymap.h"
#else
# error "Unsupported GD32F4 memory map"
#endif
#endif /* __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_MEMORYMAP_H */
arch/arm/src/gd32f4/hardware/gd32f4xx_pinmap.h
+39
View File
@@ -0,0 +1,39 @@
/****************************************************************************
* arch/arm/src/gd32f4/hardware/gd32f4xx_pinmap.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_PINMAP_H
#define __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_PINMAP_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
/* GD32 F4 Family ***********************************************************/
#if defined(CONFIG_GD32F4_GD32F450)
# include "hardware/gd32f450_pinmap.h"
#else
# error "No pinmap file for this GD32 chip"
#endif
#endif /* __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_PINMAP_H */
arch/arm/src/gd32f4/hardware/gd32f4xx_pmu.h
+133
View File
@@ -0,0 +1,133 @@
/****************************************************************************
* arch/arm/src/gd32f4/hardware/gd32f4xx_pmu.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_PMU_H
#define __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_PMU_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* Register Offsets *********************************************************/
#define GD32_PMU_CTL_OFFSET 0x0000 /* Power control register offset */
#define GD32_PMU_CS_OFFSET 0x0004 /* Power control and status register offset */
/* Register Addresses *******************************************************/
#define GD32_PMU_CTL (GD32_PMU_BASE+GD32_PMU_CTL_OFFSET) /* Power control register */
#define GD32_PMU_CS (GD32_PMU_BASE+GD32_PMU_CS_OFFSET) /* Power control and status register */
/* Register Bitfield Definitions ********************************************/
/* Power control register */
#define PMU_CTL_LDOLP (1 << 0) /* Bit 0: LDO low power mode */
#define PMU_CTL_STBMOD (1 << 1) /* Bit 1: Standby mode */
#define PMU_CTL_WURST (1 << 2) /* Bit 2: wakeup flag reset */
#define PMU_CTL_STBRST (1 << 3) /* Bit 3: Standby flag reset */
#define PMU_CTL_LVDEN (1 << 4) /* Bit 4: Low voltage detector enable */
#define PMU_CTL_LVDT_SHIFT (5) /* Bits 5-7: Low voltage detector threshold */
#define PMU_CTL_LVDT_MASK (7 << PMU_CTL_LVDT_SHIFT)
# define PMU_CTL_LVDT(n) ((n) << PMU_CTL_LVDT_SHIFT)
# define PMU_LVDT_0 PMU_CTL_LVDT(0) /* Voltage threshold is 2.1V */
# define PMU_LVDT_1 PMU_CTL_LVDT(1) /* Voltage threshold is 2.3V */
# define PMU_LVDT_2 PMU_CTL_LVDT(2) /* Voltage threshold is 2.4V */
# define PMU_LVDT_3 PMU_CTL_LVDT(3) /* Voltage threshold is 2.6V */
# define PMU_LVDT_4 PMU_CTL_LVDT(4) /* Voltage threshold is 2.7V */
# define PMU_LVDT_5 PMU_CTL_LVDT(5) /* Voltage threshold is 2.9V */
# define PMU_LVDT_6 PMU_CTL_LVDT(6) /* Voltage threshold is 3.0V */
# define PMU_LVDT_7 PMU_CTL_LVDT(7) /* Voltage threshold is 3.1V */
#define PMU_CTL_BKPWEN (1 << 8) /* Bit 8: Backup domain write enable */
#define PMU_CTL_LDLP (1 << 10) /* Bit 10: Low-driver mode when use low power LDO */
#define PMU_CTL_LDNP (1 << 11) /* Bit 11: Low-driver mode when use normal power LDO */
#define PMU_CTL_LDOVS_SHIFT (14) /* Bit 14-15: LDO output voltage select */
#define PMU_CTL_LDOVS_MASK (3 << PMU_CTL_LDOVS_SHIFT)
# define PMU_CTL_LDOVS(n) ((n) << PMU_CTL_LDOVS_SHIFT)
# define PMU_LDOVS_LOW PMU_CTL_LDOVS(1) /* LDO output voltage low mode */
# define PMU_LDOVS_MID PMU_CTL_LDOVS(2) /* LDO output voltage mid mode */
# define PMU_LDOVS_HIGH PMU_CTL_LDOVS(3) /* LDO output voltage high mode */
#define PMU_CTL_HDEN (1 << 16) /* Bit 16: High-driver mode enable */
#define PMU_CTL_HDS (1 << 17) /* Bit 17: High-driver mode switch */
#define PMU_CTL_LDEN_SHIFT (18) /* Bit 18-19: LDO output voltage select */
#define PMU_CTL_LDEN_MASK (3 << PMU_CTL_LDEN_SHIFT)
# define PMU_CTL_LDEN(n) ((n) << PMU_CTL_LDEN_SHIFT)
# define PMU_LOWDRIVER_DISABLE PMU_CTL_LDEN(0) /* Low-driver mode disable in deep-sleep mode */
# define PMU_LOWDRIVER_ENABLE PMU_CTL_LDEN(3) /* Low-driver mode enable in deep-sleep mode */
/* Power control and status register */
#define PMU_CS_WUF (1 << 0) /* Bit 0: Wakeup Flag */
#define PMU_CS_STBF (1 << 1) /* Bit 1: Standby Flag */
#define PMU_CS_LVDF (1 << 2) /* Bit 2: Low voltage detector status flag */
#define PMU_CS_BLDORF (1 << 3) /* Bit 3: Backup SRAM LDO ready flag */
#define PMU_CS_WUPEN (1 << 8) /* Bit 8: Wakeup pin enable */
#define PMU_CS_BLDOON (1 << 9) /* Bit 9: Backup SRAM LDO on */
#define PMU_CS_LDOVSRF (1 << 14) /* Bit 14: LDO voltage select ready flag */
#define PMU_CS_HDRF (1 << 16) /* Bit 16: High-driver ready flag */
#define PMU_CS_HDSRF (1 << 17) /* Bit 17: High-driver switch ready flag */
#define PMU_CS_LDRF_SHIFT (18) /* Bit 18-19: Low-driver mode ready flag */
#define PMU_CS_LDRF_MASK (3 << PMU_CS_LDRF_SHIFT)
# define PMU_CS_LDRF(n) ((n) << PMU_CS_LDRF_SHIFT)
# define PMU_LDRF_NORMAL PMU_CS_LDRF(0) /* Normal driver in deep-sleep mode */
# define PMU_LDRF_LOWDRIVER PMU_CS_LDRF(3) /* Low-driver mode in deep-sleep mode */
/* PMU low-driver mode when use low power LDO */
#define PMU_NORMALDR_LOWPWR (0) /* Normal driver when use low power LDO */
#define PMU_LOWDR_LOWPWR PMU_CTL_LDLP /* Low-driver mode enabled when LDEN is 11 and use low power LDO */
/* PMU low-driver mode when use normal power LDO */
#define PMU_NORMALDR_NORMALPWR (0) /* Normal driver when use normal power LDO */
#define PMU_LOWDR_NORMALPWR PMU_CTL_LDNP /* Low-driver mode enabled when LDEN is 11 and use normal power LDO */
/* PMU ldo definitions */
#define PMU_LDO_NORMAL (0) /* LDO normal work when PMU enter deep-sleep mode */
#define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /* LDO work at low power status when PMU enter deep-sleep mode */
/* PMU flag reset definitions */
#define PMU_FLAG_RESET_WAKEUP (0x00) /* Wakeup flag reset */
#define PMU_FLAG_RESET_STANDBY (0x01) /* Standby flag reset */
/* PMU high-driver mode switch */
#define PMU_HIGHDR_SWITCH_NONE (0) /* No high-driver mode switch */
#define PMU_HIGHDR_SWITCH_EN PMU_CTL_HDS /* High-driver mode switch */
/* PMU command constants definitions */
#define WFI_CMD (0x00) /* Use WFI command */
#define WFE_CMD (0x01) /* Use WFE command */
/* PMU backup SRAM LDO on or off */
#define PMU_BLDOON_OFF (0) /* Backup SRAM LDO off */
#define PMU_BLDOON_ON PMU_CS_BLDOON /* The backup SRAM LDO on */
#endif /* __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_PMU_H */
arch/arm/src/gd32f4/hardware/gd32f4xx_rcu.h
+668
View File
File diff suppressed because it is too large Load Diff
arch/arm/src/gd32f4/hardware/gd32f4xx_spi.h
+222
View File
@@ -0,0 +1,222 @@
/****************************************************************************
* arch/arm/src/gd32f4/hardware/gd32f4xx_spi.h
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
****************************************************************************/
#ifndef __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_SPI_H
#define __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_SPI_H
/****************************************************************************
* Included Files
****************************************************************************/
#include <nuttx/config.h>
#include "chip.h"
/****************************************************************************
* Pre-processor Definitions
****************************************************************************/
/* SPIx(x=0,1,2,3,4,5) definitions */
#define GD32_SPI0_BASE (GD32_SPI_BASE+0x0000F800) /* SPI0 base address */
#define GD32_SPI1_BASE (GD32_SPI_BASE+0x00000000) /* SPI1 base address */
#define GD32_SPI2_BASE (GD32_SPI_BASE+0x00000400) /* SPI2 base address */
#define GD32_SPI3_BASE (GD32_SPI_BASE+0x0000FC00) /* SPI3 base address */
#define GD32_SPI4_BASE (GD32_SPI_BASE+0x00011800) /* SPI4 base address */
#define GD32_SPI5_BASE (GD32_SPI_BASE+0x00011C00) /* SPI5 base address */
/* I2Sx_ADD(x=1,2) definitions */
#define GD32_I2S1_ADD_BASE (GD32_I2S_ADD_BASE+0x00000000) /* I2S1_ADD base address */
#define GD32_I2S2_ADD_BASE (GD32_I2S_ADD_BASE+0x00000C00) /* I2S2_ADD base address */
/* Register Offsets *********************************************************/
#define GD32_SPI_CTL0_OFFSET 0x0000 /* SPI control register 0 offset */
#define GD32_SPI_CTL1_OFFSET 0x0004 /* SPI control register 1 offset */
#define GD32_SPI_STAT_OFFSET 0x0008 /* SPI status register offset */
#define GD32_SPI_DATA_OFFSET 0x000C /* SPI data register offset */
#define GD32_SPI_CRCPOLY_OFFSET 0x0010 /* SPI CRC polynomial register offset */
#define GD32_SPI_RCRC_OFFSET 0x0014 /* SPI receive CRC register offset */
#define GD32_SPI_TCRC_OFFSET 0x0018 /* SPI transmit CRC register offset */
#define GD32_SPI_I2SCTL_OFFSET 0x001C /* SPI I2S control register offset */
#define GD32_SPI_I2SPSC_OFFSET 0x0020 /* SPI I2S clock prescaler register offset */
#define GD32_SPI_QCTL_OFFSET 0x0080 /* SPI quad mode control register offset */
/* Register Addresses *******************************************************/
#define GD32_SPI0 GD32_SPI0_BASE
#define GD32_SPI1 GD32_SPI1_BASE
#define GD32_SPI2 GD32_SPI2_BASE
#define GD32_SPI3 GD32_SPI3_BASE
#define GD32_SPI4 GD32_SPI4_BASE
#define GD32_SPI5 GD32_SPI5_BASE
#define GD32_I2S1_ADD GD32_I2S1_ADD_BASE
#define GD32_I2S2_ADD GD32_I2S2_ADD_BASE
/* SPI registers definitions */
#define GD32_SPI_CTL0(spix) ((spix)+GD32_SPI_CTL0_OFFSET) /* SPI control register 0 */
#define GD32_SPI_CTL1(spix) ((spix)+GD32_SPI_CTL1_OFFSET) /* SPI control register 1*/
#define GD32_SPI_STAT(spix) ((spix)+GD32_SPI_STAT_OFFSET) /* SPI status register */
#define GD32_SPI_DATA(spix) ((spix)+GD32_SPI_DATA_OFFSET) /* SPI data register */
#define GD32_SPI_CRCPOLY(spix) ((spix)+GD32_SPI_CRCPOLY_OFFSET) /* SPI CRC polynomial register */
#define GD32_SPI_RCRC(spix) ((spix)+GD32_SPI_RCRC_OFFSET) /* SPI receive CRC register */
#define GD32_SPI_TCRC(spix) ((spix)+GD32_SPI_TCRC_OFFSET) /* SPI transmit CRC register */
#define GD32_SPI_I2SCTL(spix) ((spix)+GD32_SPI_I2SCTL_OFFSET) /* SPI I2S control register */
#define GD32_SPI_I2SPSC(spix) ((spix)+GD32_SPI_I2SPSC_OFFSET) /* SPI I2S clock prescaler register */
#define GD32_SPI_QCTL(spix) ((spix)+GD32_SPI_QCTL_OFFSET) /* SPI quad mode control register */
/* I2S_ADD registers definitions */
#define I2S_ADD_CTL0(i2sx_add) ((i2sx_add)+GD32_SPI_CTL0_OFFSET) /* I2S_ADD control register 0 */
#define I2S_ADD_CTL1(i2sx_add) ((i2sx_add)+GD32_SPI_CTL1_OFFSET) /* I2S_ADD control register 1*/
#define I2S_ADD_STAT(i2sx_add) ((i2sx_add)+GD32_SPI_STAT_OFFSET) /* I2S_ADD status register */
#define I2S_ADD_DATA(i2sx_add) ((i2sx_add)+GD32_SPI_DATA_OFFSET) /* I2S_ADD data register */
#define I2S_ADD_CRCPOLY(i2sx_add) ((i2sx_add)+GD32_SPI_CRCPOLY_OFFSET) /* I2S_ADD CRC polynomial register */
#define I2S_ADD_RCRC(i2sx_add) ((i2sx_add)+GD32_SPI_RCRC_OFFSET) /* I2S_ADD receive CRC register */
#define I2S_ADD_TCRC(i2sx_add) ((i2sx_add)+GD32_SPI_TCRC_OFFSET) /* I2S_ADD transmit CRC register */
#define I2S_ADD_I2SCTL(i2sx_add) ((i2sx_add)+GD32_SPI_I2SCTL_OFFSET) /* I2S_ADD I2S control register */
#define I2S_ADD_I2SPSC(i2sx_add) ((i2sx_add)+GD32_SPI_I2SPSC_OFFSET) /* I2S_ADD I2S clock prescaler register */
/* Register Bitfield Definitions ********************************************/
/* Control register 0 */
#define SPI_CTL0_CKPH (1 << 0) /* Bit 0: clock phase selection*/
#define SPI_CTL0_CKPL (1 << 1) /* Bit 1: clock polarity selection */
#define SPI_CTL0_MSTMOD (1 << 2) /* Bit 2: master mode enable */
#define SPI_CTL0_PSC_SHIFT (3) /* Bit 3-5: master clock prescaler selection */
#define SPI_CTL0_PSC_MASK (7 << SPI_CTL0_PSC_SHIFT)
#define SPI_CTL0_PSC(n) ((n) << SPI_CTL0_PSC_SHIFT)
# define SPI_CTL0_PSC_2 SPI_CTL0_PSC(0) /* 000: SPI clock prescale factor is 2 */
# define SPI_CTL0_PSC_4 SPI_CTL0_PSC(1) /* 001: SPI clock prescale factor is 4 */
# define SPI_CTL0_PSC_8 SPI_CTL0_PSC(2) /* 010: SPI clock prescale factor is 8 */
# define SPI_CTL0_PSC_16 SPI_CTL0_PSC(3) /* 011: SPI clock prescale factor is 16 */
# define SPI_CTL0_PSC_32 SPI_CTL0_PSC(4) /* 100: SPI clock prescale factor is 32 */
# define SPI_CTL0_PSC_64 SPI_CTL0_PSC(5) /* 101: SPI clock prescale factor is 64 */
# define SPI_CTL0_PSC_128 SPI_CTL0_PSC(6) /* 110: SPI clock prescale factor is 128 */
# define SPI_CTL0_PSC_256 SPI_CTL0_PSC(7) /* 111: SPI clock prescale factor is 256 */
#define SPI_CTL0_SPIEN (1 << 6) /* Bit 6: SPI enable*/
#define SPI_CTL0_LF (1 << 7) /* Bit 7: lsb first mode */
#define SPI_CTL0_SWNSS (1 << 8) /* Bit 8: nss pin selection in nss software mode */
#define SPI_CTL0_SWNSSEN (1 << 9) /* Bit 9: nss software mode selection */
#define SPI_CTL0_RO (1 << 10) /* Bit 10: receive only */
#define SPI_CTL0_FF16 (1 << 11) /* Bit 11: data frame size */
#define SPI_CTL0_CRCNT (1 << 12) /* Bit 12: CRC next transfer */
#define SPI_CTL0_CRCEN (1 << 13) /* Bit 13: CRC calculation enable */
#define SPI_CTL0_BDOEN (1 << 14) /* Bit 14: bidirectional transmit output enable*/
#define SPI_CTL0_BDEN (1 << 15) /* Bit 15: bidirectional enable */
/* SPI_CTL1 */
#define SPI_CTL1_DMAREN (1 << 0) /* Bit 0: receive buffer dma enable */
#define SPI_CTL1_DMATEN (1 << 1) /* Bit 1: transmit buffer dma enable */
#define SPI_CTL1_NSSDRV (1 << 2) /* Bit 2: drive nss output */
#define SPI_CTL1_TMOD (1 << 4) /* Bit 4: SPI TI mode enable */
#define SPI_CTL1_ERRIE (1 << 5) /* Bit 5: errors interrupt enable */
#define SPI_CTL1_RBNEIE (1 << 6) /* Bit 6: receive buffer not empty interrupt enable */
#define SPI_CTL1_TBEIE (1 << 7) /* Bit 7: transmit buffer empty interrupt enable */
/* SPI_STAT */
#define SPI_STAT_RBNE (1 << 0) /* Bit 0: receive buffer not empty */
#define SPI_STAT_TBE (1 << 1) /* Bit 1: transmit buffer empty */
#define SPI_STAT_I2SCH (1 << 2) /* Bit 2: I2S channel side */
#define SPI_STAT_TXURERR (1 << 3) /* Bit 3: I2S transmission underrun error bit */
#define SPI_STAT_CRCERR (1 << 4) /* Bit 4: SPI CRC error bit */
#define SPI_STAT_CONFERR (1 << 5) /* Bit 5: SPI configuration error bit */
#define SPI_STAT_RXORERR (1 << 6) /* Bit 6: SPI reception overrun error bit */
#define SPI_STAT_TRANS (1 << 7) /* Bit 7: transmitting on-going bit */
#define SPI_STAT_FERR (1 << 8) /* Bit 8: format error bit */
/* SPI_DATA */
#define SPI_DATA_SHIFT (0) /* Bits 0-15: data transfer register */
#define SPI_DATA_MASK (0xffff << SPI_DATA_SHIFT)
/* SPI_CRCPOLY */
#define SPI_CRCPOLY_CPR_SHIFT (0) /* Bits 0-15: CRC polynomial register */
#define SPI_CRCPOLY_CPR__MASK (0xffff << SPI_CRCPOLY_CPR_SHIFT)
/* SPI_RCRC */
#define SPI_RCRC_RCR_SHIFT (0) /* Bits 0-15: CRX CRC register */
#define SPI_RCRC_RCR_MASK (0xffff << SPI_RCRC_RCR_SHIFT)
/* SPI_TCRC */
#define SPI_TCRC_TCR_SHIFT (0) /* Bits 0-15: TX CRC register */
#define SPI_TCRC_TCR_MASK (0xffff << SPI_TCRC_TCR_SHIFT)
/* SPI_I2SCTL */
#define SPI_I2SCTL_CHLEN (1 << 0) /* Bit 0: channel length */
#define SPI_I2SCTL_DTLEN_SHIFT (1) /* Bit 1-2: data length */
#define SPI_I2SCTL_DTLEN_MASK (3 << SPI_I2SCTL_DTLEN_SHIFT)
#define SPI_I2SCTL_DTLEN(n) ((n) << SPI_I2SCTL_DTLEN_SHIFT)
# define SPI_I2SCTL_DTLEN_DT16B SPI_I2SCTL_DTLEN(0) /* 00: 16 bits */
# define SPI_I2SCTL_DTLEN_DT24B SPI_I2SCTL_DTLEN(1) /* 00: 24 bits */
# define SPI_I2SCTL_DTLEN_DT32B SPI_I2SCTL_DTLEN(2) /* 00: 32 bits */
#define SPI_I2SCTL_CKPL (1 << 3) /* Bit 3: idle state clock polarity */
#define SPI_I2SCTL_I2SSTD_SHIFT (4) /* Bit 4-5: I2S standard selection */
#define SPI_I2SCTL_I2SSTD_MASK (3 << SPI_I2SCTL_I2SSTD_SHIFT)
#define SPI_I2SCTL_I2SSTD(n) ((n) << SPI_I2SCTL_I2SSTD_SHIFT)
# define SPI_I2SSTD_PHILLIPS SPI_I2SCTL_I2SSTD(0) /* 00: I2S Phillips standard */
# define SPI_I2SSTD_MSB SPI_I2SCTL_I2SSTD(0) /* 01: MSB justified standard */
# define SPI_I2SSTD_LSB SPI_I2SCTL_I2SSTD(0) /* 10: LSB justified standard */
# define SPI_I2SSTD_PCM SPI_I2SCTL_I2SSTD(0) /* 11: PCM standard*/
#define SPI_I2SCTL_PCMSMOD (1 << 7) /* Bit 7: PCM frame synchronization mode */
#define SPI_I2SCTL_I2SOPMOD_SHIIFT (8) /* Bit 8-9: I2S operation mode */
#define SPI_I2SCTL_I2SOPMOD_MASK (3 << SPI_I2SCTL_I2SOPMOD_SHIIFT)
#define SPI_I2SCTL_I2SOPMOD(n) ((n) << SPI_I2SCTL_I2SOPMOD_SHIIFT)
# define SPI_I2SCTL_I2SOPMSTRAN SPI_I2SCTL_I2SOPMOD(0) /* 00: Slave transmission mode */
# define SPI_I2SCTL_I2SOPMSRECV SPI_I2SCTL_I2SOPMOD(1) /* 01: Slave reception mode */
# define SPI_I2SCTL_I2SOPMMTRAN SPI_I2SCTL_I2SOPMOD(2) /* 10: Master transmission mode */
# define SPI_I2SCTL_I2SOPMMRECV SPI_I2SCTL_I2SOPMOD(3) /* 11: Master reception mode */
#define SPI_I2SCTL_I2SEN (1 << 10) /* Bit 10: I2S enable */
#define SPI_I2SCTL_I2SSEL (1 << 11) /* Bit 11: I2S mode selection */
/* SPI_I2S_PSC */
#define SPI_I2SPSC_DIV_SHIFT (0) /* Bit0-7: dividing factor for the prescaler */
#define SPI_I2SPSC_DIV_MASK (0xff << SPI_I2SPSC_DIV_SHIFT)
#define SPI_I2SPSC_DIV(n) ((n) << SPI_I2SPSC_DIV_SHIFT) /* Real divider value is DIV * 2 + OF. */
#define SPI_I2SPSC_OF (1 << 8) /* Bit8: odd factor for the prescaler */
#define SPI_I2SPSC_MCKOEN (1 << 9) /* Bit9: I2S MCK output enable */
/* SPI_SPI_QCTL(only SPI5) */
#define SPI_QCTL_QMOD (1 << 0) /* Bit0: quad-SPI mode enable */
#define SPI_QCTL_QRD (1 << 1) /* Bit1: quad-SPI mode read select */
#define SPI_QCTL_IO23_DRV (1 << 2) /* Bit2: drive SPI_IO2 and SPI_IO3 enable */
/* SPI DMA enable */
#define SPI_CTL1_DMAEN (SPI_CTL1_DMAREN | SPI_CTL1_DMATEN) /* SPI RX/TX DMA enable */
/* SPI mode definitions */
#define SPI_MASTER (SPI_CTL0_MSTMOD | SPI_CTL0_SWNSS) /* SPI as master, SWNSS=1 to prevent CONFERR */
#define SPI_SLAVE (0x00000000) /* SPI as slave */
/* SPI bidirectional transfer direction */
#define SPI_BIDIRECTIONAL_TRANSMIT SPI_CTL0_BDOEN /* SPI work in transmit-only mode */
#define SPI_BIDIRECTIONAL_RECEIVE SPI_CTL0_BDOEN) /* SPI work in receive-only mode */
/* SPI transmit type */
#define SPI_TRANSMODE_FULLDUPLEX (00000000) /* SPI receive and send data at fullduplex communication */
#define SPI_TRANSMODE_RECEIVEONLY SPI_CTL0_RO /* SPI only receive data */
#define SPI_TRANSMODE_BDRECEIVE SPI_CTL0_BDEN /* bidirectional receive data */
#define SPI_TRANSMODE_BDTRANSMIT (SPI_CTL0_BDEN | SPI_CTL0_BDOEN) /* bidirectional transmit data*/
#endif /* __ARCH_ARM_SRC_GD32F4_HARDWARE_GD32F4XX_SPI_H */

Some files were not shown because too many files have changed in this diff Show More